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|  <span id="projectnumber">Version 5.3.0</span> |
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| <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> |
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| <div class="title">Startup File startup_<device>.s (deprecated) </div> </div> |
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| <div class="contents"> |
| <div class="textblock"><p>The <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s (deprecated)</a> contains:</p> |
| <ul> |
| <li>The reset handler which is executed after CPU reset and typically calls the <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> function.</li> |
| <li>The setup values for the Main Stack Pointer (MSP).</li> |
| <li>Exception vectors of the Cortex-M Processor with weak functions that implement default routines.</li> |
| <li>Interrupt vectors that are device specific with weak functions that implement default routines.</li> |
| </ul> |
| <p>The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.</p> |
| <p>To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all the IRQ numbers for each interrupt.</p> |
| <p><b>Example:</b> </p> |
| <p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p> |
| <div class="fragment"><div class="line"> ; External Interrupts</div> |
| <div class="line"> DCD WAKEUP0_IRQHandler ; 16+ 0: Wakeup PIO0.0</div> |
| <div class="line"> DCD WAKEUP1_IRQHandler ; 16+ 1: Wakeup PIO0.1</div> |
| <div class="line"> DCD WAKEUP2_IRQHandler ; 16+ 2: Wakeup PIO0.2</div> |
| <div class="line"> : :</div> |
| <div class="line"> : :</div> |
| <div class="line"> DCD EINT1_IRQHandler ; 16+30: PIO INT1</div> |
| <div class="line"> DCD EINT0_IRQHandler ; 16+31: PIO INT0</div> |
| <div class="line"> :</div> |
| <div class="line"> :</div> |
| <div class="line"> EXPORT WAKEUP0_IRQHandler [WEAK]</div> |
| <div class="line"> EXPORT WAKEUP1_IRQHandler [WEAK]</div> |
| <div class="line"> EXPORT WAKEUP2_IRQHandler [WEAK]</div> |
| <div class="line"> : :</div> |
| <div class="line"> : :</div> |
| <div class="line"> EXPORT EINT1_IRQHandler [WEAK]</div> |
| <div class="line"> EXPORT EINT0_IRQHandler [WEAK]</div> |
| <div class="line"></div> |
| <div class="line">WAKEUP0_IRQHandler</div> |
| <div class="line">WAKEUP1_IRQHandler</div> |
| <div class="line">WAKEUP1_IRQHandler</div> |
| <div class="line"> :</div> |
| <div class="line"> :</div> |
| <div class="line">EINT1_IRQHandler</div> |
| <div class="line">EINT0_IRQHandler</div> |
| <div class="line"> B .</div> |
| </div><!-- fragment --><h1><a class="anchor" id="startup_s_sec"></a> |
| startup_Device.s Template File</h1> |
| <p>An Arm Compiler <a class="el" href="startup_s_pg.html#startup_s_sec">startup_Device.s Template File</a> for an Armv7-M processor like Cortex-M3 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.</p> |
| <pre class="fragment">;/**************************************************************************//** |
| ; * @file startup_<Device>.s |
| ; * @brief CMSIS Cortex-M ARMv7-M based Core Device Startup File for |
| ; * Device <Device> |
| ; * @version V5.4.0 |
| ; * @date 12. December 2018 |
| ; ******************************************************************************/ |
| ;/* |
| ; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
| ; * |
| ; * SPDX-License-Identifier: Apache-2.0 |
| ; * |
| ; * Licensed under the Apache License, Version 2.0 (the License); you may |
| ; * not use this file except in compliance with the License. |
| ; * You may obtain a copy of the License at |
| ; * |
| ; * www.apache.org/licenses/LICENSE-2.0 |
| ; * |
| ; * Unless required by applicable law or agreed to in writing, software |
| ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| ; * See the License for the specific language governing permissions and |
| ; * limitations under the License. |
| ; */ |
| |
| ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| |
| |
| ;<h> Stack Configuration |
| ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| ;</h> |
| |
| Stack_Size EQU 0x00000400 |
| |
| AREA STACK, NOINIT, READWRITE, ALIGN=3 |
| __stack_limit |
| Stack_Mem SPACE Stack_Size |
| __initial_sp |
| |
| |
| ;<h> Heap Configuration |
| ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> |
| ;</h> |
| |
| Heap_Size EQU 0x00000C00 |
| |
| IF Heap_Size != 0 ; Heap is provided |
| AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
| __heap_base |
| Heap_Mem SPACE Heap_Size |
| __heap_limit |
| ENDIF |
| |
| |
| PRESERVE8 |
| THUMB |
| |
| |
| ; Vector Table Mapped to Address 0 at Reset |
| |
| AREA RESET, DATA, READONLY |
| EXPORT __Vectors |
| EXPORT __Vectors_End |
| EXPORT __Vectors_Size |
| |
| __Vectors DCD __initial_sp ; Top of Stack |
| DCD Reset_Handler ; Reset Handler |
| DCD NMI_Handler ; -14 NMI Handler |
| DCD HardFault_Handler ; -13 Hard Fault Handler |
| DCD MemManage_Handler ; -12 MPU Fault Handler |
| DCD BusFault_Handler ; -11 Bus Fault Handler |
| DCD UsageFault_Handler ; -10 Usage Fault Handler |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD 0 ; Reserved |
| DCD SVC_Handler ; -5 SVCall Handler |
| DCD DebugMon_Handler ; -4 Debug Monitor Handler |
| DCD 0 ; Reserved |
| DCD PendSV_Handler ; -2 PendSV Handler |
| DCD SysTick_Handler ; -1 SysTick Handler |
| |
| ; Interrupts |
| ; ToDo: Add here the vectors for the device specific external interrupts handler |
| DCD Interrupt0_Handler ; 0 Interrupt 0 |
| DCD Interrupt1_Handler ; 1 Interrupt 1 |
| DCD Interrupt2_Handler ; 2 Interrupt 2 |
| DCD Interrupt3_Handler ; 3 Interrupt 3 |
| DCD Interrupt4_Handler ; 4 Interrupt 4 |
| DCD Interrupt5_Handler ; 5 Interrupt 5 |
| DCD Interrupt6_Handler ; 6 Interrupt 6 |
| DCD Interrupt7_Handler ; 7 Interrupt 7 |
| DCD Interrupt8_Handler ; 8 Interrupt 8 |
| DCD Interrupt9_Handler ; 9 Interrupt 9 |
| |
| SPACE (214 * 4) ; Interrupts 10 .. 224 are left out |
| __Vectors_End |
| __Vectors_Size EQU __Vectors_End - __Vectors |
| |
| |
| AREA |.text|, CODE, READONLY |
| |
| ; Reset Handler |
| |
| Reset_Handler PROC |
| EXPORT Reset_Handler [WEAK] |
| IMPORT SystemInit |
| IMPORT __main |
| |
| LDR R0, =SystemInit |
| BLX R0 |
| LDR R0, =__main |
| BX R0 |
| ENDP |
| |
| |
| ; Macro to define default exception/interrupt handlers. |
| ; Default handler are weak symbols with an endless loop. |
| ; They can be overwritten by real handlers. |
| MACRO |
| Set_Default_Handler $Handler_Name |
| $Handler_Name PROC |
| EXPORT $Handler_Name [WEAK] |
| B . |
| ENDP |
| MEND |
| |
| |
| ; Default exception/interrupt handler |
| |
| Set_Default_Handler NMI_Handler |
| Set_Default_Handler HardFault_Handler |
| Set_Default_Handler MemManage_Handler |
| Set_Default_Handler BusFault_Handler |
| Set_Default_Handler UsageFault_Handler |
| Set_Default_Handler SVC_Handler |
| Set_Default_Handler DebugMon_Handler |
| Set_Default_Handler PendSV_Handler |
| Set_Default_Handler SysTick_Handler |
| |
| Set_Default_Handler Interrupt0_Handler |
| Set_Default_Handler Interrupt1_Handler |
| Set_Default_Handler Interrupt2_Handler |
| Set_Default_Handler Interrupt3_Handler |
| Set_Default_Handler Interrupt4_Handler |
| Set_Default_Handler Interrupt5_Handler |
| Set_Default_Handler Interrupt6_Handler |
| Set_Default_Handler Interrupt7_Handler |
| Set_Default_Handler Interrupt8_Handler |
| Set_Default_Handler Interrupt9_Handler |
| |
| ALIGN |
| |
| |
| ; User setup Stack & Heap |
| |
| IF :LNOT::DEF:__MICROLIB |
| IMPORT __use_two_region_memory |
| ENDIF |
| |
| EXPORT __stack_limit |
| EXPORT __initial_sp |
| IF Heap_Size != 0 ; Heap is provided |
| EXPORT __heap_base |
| EXPORT __heap_limit |
| ENDIF |
| |
| END |
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