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<div id="projectname">CMSIS-Core (Cortex-M)
&#160;<span id="projectnumber">Version 5.3.0</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="title">CoreDebug_Type Struct Reference</div> </div>
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<p>Structure type to access the Core Debug Register (CoreDebug).
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Data Fields</h2></td></tr>
<tr class="memitem:ad63554e4650da91a8e79929cbb63db66"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66">DHCSR</a></td></tr>
<tr class="memdesc:ad63554e4650da91a8e79929cbb63db66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Debug Halting Control and Status Register. <a href="#ad63554e4650da91a8e79929cbb63db66">More...</a><br/></td></tr>
<tr class="separator:ad63554e4650da91a8e79929cbb63db66"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af907cf64577eaf927dac6787df6dd98b"><td class="memItemLeft" align="right" valign="top">__OM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b">DCRSR</a></td></tr>
<tr class="memdesc:af907cf64577eaf927dac6787df6dd98b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 ( /W) Debug Core Register Selector Register. <a href="#af907cf64577eaf927dac6787df6dd98b">More...</a><br/></td></tr>
<tr class="separator:af907cf64577eaf927dac6787df6dd98b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">DCRDR</a></td></tr>
<tr class="memdesc:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) Debug Core Register Data Register. <a href="#aab3cc92ef07bc1f04b3a3aa6db2c2d55">More...</a><br/></td></tr>
<tr class="separator:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeb3126abc4c258a858f21f356c0df6ee"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee">DEMCR</a></td></tr>
<tr class="memdesc:aeb3126abc4c258a858f21f356c0df6ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. <a href="#aeb3126abc4c258a858f21f356c0df6ee">More...</a><br/></td></tr>
<tr class="separator:aeb3126abc4c258a858f21f356c0df6ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<td class="memname">__IOM uint32_t CoreDebug_Type::DCRDR</td>
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<td class="memname">__OM uint32_t CoreDebug_Type::DCRSR</td>
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<td class="memname">__IOM uint32_t CoreDebug_Type::DEMCR</td>
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