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<div id="projectname">CMSIS-Core (Cortex-M)
&#160;<span id="projectnumber">Version 5.3.0</span>
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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div>
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<div class="title">MPU_Type Struct Reference<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv6-M/v7-M</a></div></div> </div>
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<p>Structure type to access the Memory Protection Unit (MPU).
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:aba02af87f77577c725cf73879cabb609"><td class="memItemLeft" align="right" valign="top">__IM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">TYPE</a></td></tr>
<tr class="memdesc:aba02af87f77577c725cf73879cabb609"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) MPU Type Register. <a href="#aba02af87f77577c725cf73879cabb609">More...</a><br/></td></tr>
<tr class="separator:aba02af87f77577c725cf73879cabb609"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">CTRL</a></td></tr>
<tr class="memdesc:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) MPU Control Register. <a href="#a769178ef949f0d5d8f18ddbd9e4e926f">More...</a><br/></td></tr>
<tr class="separator:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f7a117a12cb661c76edc4765453f05c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">RNR</a></td></tr>
<tr class="memdesc:a2f7a117a12cb661c76edc4765453f05c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) MPU Region RNRber Register. <a href="#a2f7a117a12cb661c76edc4765453f05c">More...</a><br/></td></tr>
<tr class="separator:a2f7a117a12cb661c76edc4765453f05c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a990c609b26d990b8ba832b110adfd353"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a></td></tr>
<tr class="memdesc:a990c609b26d990b8ba832b110adfd353"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) MPU Region Base Address Register. <a href="#a990c609b26d990b8ba832b110adfd353">More...</a><br/></td></tr>
<tr class="separator:a990c609b26d990b8ba832b110adfd353"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a></td></tr>
<tr class="memdesc:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) MPU Region Attribute and Size Register. <a href="#a8f00c4a5e31b0a8d103ed3b0732c17a3">More...</a><br/></td></tr>
<tr class="separator:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af8b510a85b175edfd8dd8cc93e967066"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066">RBAR_A1</a></td></tr>
<tr class="memdesc:af8b510a85b175edfd8dd8cc93e967066"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. <a href="#af8b510a85b175edfd8dd8cc93e967066">More...</a><br/></td></tr>
<tr class="separator:af8b510a85b175edfd8dd8cc93e967066"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1658326c6762637eeef8a79bb467445e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a1658326c6762637eeef8a79bb467445e">RASR_A1</a></td></tr>
<tr class="memdesc:a1658326c6762637eeef8a79bb467445e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. <a href="#a1658326c6762637eeef8a79bb467445e">More...</a><br/></td></tr>
<tr class="separator:a1658326c6762637eeef8a79bb467445e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a80d534f0dfc080c841e1772c7a68e1a2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2">RBAR_A2</a></td></tr>
<tr class="memdesc:a80d534f0dfc080c841e1772c7a68e1a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. <a href="#a80d534f0dfc080c841e1772c7a68e1a2">More...</a><br/></td></tr>
<tr class="separator:a80d534f0dfc080c841e1772c7a68e1a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a37131c513d8a8d211b402e5dfda97205"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205">RASR_A2</a></td></tr>
<tr class="memdesc:a37131c513d8a8d211b402e5dfda97205"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. <a href="#a37131c513d8a8d211b402e5dfda97205">More...</a><br/></td></tr>
<tr class="separator:a37131c513d8a8d211b402e5dfda97205"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a207f6e9c3af753367554cc06df300a55"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a207f6e9c3af753367554cc06df300a55">RBAR_A3</a></td></tr>
<tr class="memdesc:a207f6e9c3af753367554cc06df300a55"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. <a href="#a207f6e9c3af753367554cc06df300a55">More...</a><br/></td></tr>
<tr class="separator:a207f6e9c3af753367554cc06df300a55"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd">RASR_A3</a></td></tr>
<tr class="memdesc:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. <a href="#a7d15172b163797736a6c6b4dcc0fa3dd">More...</a><br/></td></tr>
<tr class="separator:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a class="anchor" id="a769178ef949f0d5d8f18ddbd9e4e926f"></a>
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<p>Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
<tr>
<td align="left">[31:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">PRIVDEFENA </td><td align="left">0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">HFNMIENA </td><td align="left">0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">ENABLE </td><td align="left">0 - The MPU is disabled. 1 - The MPU is enabled. </td></tr>
</table>
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<p>Defines the size and access behavior of the region identified by MPU_RNR, and enables that region.</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:29] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[28] </td><td align="left">XN </td><td align="left">Execute Never. </td></tr>
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<td align="left">[27] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[26:24] </td><td align="left">AP </td><td align="left">Access Permissions, see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr>
<tr>
<td align="left">[23:22] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[21:19] </td><td align="left">TEX </td><td align="left">Type Extension. </td></tr>
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<td align="left">[18] </td><td align="left">S </td><td align="left">Shareable. </td></tr>
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<td align="left">[17] </td><td align="left">C </td><td align="left">Cacheable. </td></tr>
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<td align="left">[16] </td><td align="left">B </td><td align="left">Bufferable. </td></tr>
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<td align="left">[15:8] </td><td align="left">SRD </td><td align="left">Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1). </td></tr>
<tr>
<td align="left">[7:6] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[5:1] </td><td align="left">SIZE </td><td align="left">Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">ENABLE </td><td align="left">0 - This region is disabled. 1 - This region is enabled. </td></tr>
</table>
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<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p>
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<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p>
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<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p>
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<p>Holds the base address of the region identified by MPU_RNR. On a write, can also be used to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with the new region number.</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:5] </td><td align="left">ADDR </td><td align="left">Base address of the region. </td></tr>
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<td align="left">[4] </td><td align="left">VALID </td><td align="left">1 - Update <a class="el" href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">MPU_Type::RNR</a> to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region. </td></tr>
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<td align="left">[3:0] </td><td align="left">REGION </td><td align="left">On writes, can specify the number of the region to update, see VALID field description. </td></tr>
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<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p>
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<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p>
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<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p>
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<p>Selects the region currently accessed by <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a> and <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>.</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7:0] </td><td align="left">REGION </td><td align="left">Indicates the memory region accessed. </td></tr>
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<td class="memname">MPU_Type::TYPE</td>
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<p>The MPU Type Register indicates how many regions the MPU support. Software can use it to determine if the processor implements an MPU.</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:16] </td><td align="left">IREGION </td><td align="left">Instruction region. RAZ. Armv7-M only supports a unified MPU. </td></tr>
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<td align="left">[15:8] </td><td align="left">DREGION </td><td align="left">Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. </td></tr>
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<td align="left">[7:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[0] </td><td align="left">SEPARATE </td><td align="left">Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU. </td></tr>
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