blob: 1b1c15fb4e37914bb287657443b1aac5f587faec [file] [log] [blame]
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<title>Reference</title>
<title>CMSIS-Core (Cortex-A): Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<link href="cmsis.css" rel="stylesheet" type="text/css" />
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<script type="text/javascript" src="printComponentTabs.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
$(document).ready(initResizable);
$(window).load(resizeHeight);
</script>
<link href="search/search.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="search/search.js"></script>
<script type="text/javascript">
$(document).ready(function() { searchBox.OnSelectItem(0); });
</script>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
<tbody>
<tr style="height: 46px;">
<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
<td style="padding-left: 0.5em;">
<div id="projectname">CMSIS-Core (Cortex-A)
&#160;<span id="projectnumber">Version 1.1.4</span>
</div>
<div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
</td>
</tr>
</tbody>
</table>
</div>
<!-- end header part -->
<div id="CMSISnav" class="tabs1">
<ul class="tablist">
<script type="text/javascript">
<!--
writeComponentTabs.call(this);
//-->
</script>
</ul>
</div>
<!-- Generated by Doxygen 1.8.6 -->
<script type="text/javascript">
var searchBox = new SearchBox("searchBox", "search",false,'Search');
</script>
<div id="navrow1" class="tabs">
<ul class="tablist">
<li><a href="index.html"><span>Main&#160;Page</span></a></li>
<li><a href="pages.html"><span>Usage&#160;and&#160;Description</span></a></li>
<li class="current"><a href="modules.html"><span>Reference</span></a></li>
<li>
<div id="MSearchBox" class="MSearchBoxInactive">
<span class="left">
<img id="MSearchSelect" src="search/mag_sel.png"
onmouseover="return searchBox.OnSearchSelectShow()"
onmouseout="return searchBox.OnSearchSelectHide()"
alt=""/>
<input type="text" id="MSearchField" value="Search" accesskey="S"
onfocus="searchBox.OnSearchFieldFocus(true)"
onblur="searchBox.OnSearchFieldFocus(false)"
onkeyup="searchBox.OnSearchFieldChange(event)"/>
</span><span class="right">
<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
</span>
</div>
</li>
</ul>
</div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
<div id="nav-tree">
<div id="nav-tree-contents">
<div id="nav-sync" class="sync"></div>
</div>
</div>
<div id="splitbar" style="-moz-user-select:none;"
class="ui-resizable-handle">
</div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('modules.html','');});
</script>
<div id="doc-content">
<!-- window showing the filter options -->
<div id="MSearchSelectWindow"
onmouseover="return searchBox.OnSearchSelectShow()"
onmouseout="return searchBox.OnSearchSelectHide()"
onkeydown="return searchBox.OnSearchSelectKey(event)">
<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark">&#160;</span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark">&#160;</span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark">&#160;</span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark">&#160;</span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark">&#160;</span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark">&#160;</span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark">&#160;</span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark">&#160;</span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark">&#160;</span>Macros</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(9)"><span class="SelectionMark">&#160;</span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(10)"><span class="SelectionMark">&#160;</span>Pages</a></div>
<!-- iframe showing the search results (closed by default) -->
<div id="MSearchResultsWindow">
<iframe src="javascript:void(0)" frameborder="0"
name="MSearchResults" id="MSearchResults">
</iframe>
</div>
<div class="header">
<div class="headertitle">
<div class="title">Reference</div> </div>
</div><!--header-->
<div class="contents">
<div class="textblock">Here is a list of all modules:</div><div class="directory">
<div class="levels">[detail level <span onclick="javascript:toggleLevel(1);">1</span><span onclick="javascript:toggleLevel(2);">2</span><span onclick="javascript:toggleLevel(3);">3</span>]</div><table class="directory">
<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Functions for system and clock setup available in system_<em>device</em>.c </td></tr>
<tr id="row_1_"><td class="entry"><img id="arr_1_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_')"/><a class="el" href="group__CMSIS__core__register.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-A core registers </td></tr>
<tr id="row_1_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_0_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_0_')"/><a class="el" href="group__CMSIS__ACTLR.html" target="_self">Auxiliary Control Register (ACTLR)</a></td><td class="desc">The ACTLR provides IMPLEMENTATION DEFINED configuration and control options </td></tr>
<tr id="row_1_0_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__ACTLR__BITS.html" target="_self">ACTLR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CBPM.html" target="_self">Cache and branch predictor maintenance operations</a></td><td class="desc">This section describes the cache and branch predictor maintenance operations </td></tr>
<tr id="row_1_2_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_2_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_2_')"/><a class="el" href="group__CMSIS__CBAR.html" target="_self">Configuration Base Address Register (CBAR)</a></td><td class="desc">Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13] </td></tr>
<tr id="row_1_2_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__CBAR__BITS.html" target="_self">CBAR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_3_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_3_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_3_')"/><a class="el" href="group__CMSIS__CPACR.html" target="_self">Coprocessor Access Control Register (CPACR)</a></td><td class="desc">The CPACR controls access to coprocessors CP0 to CP13 </td></tr>
<tr id="row_1_3_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CPACR__BITS.html" target="_self">CPACR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_3_1_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__CPACR__CP.html" target="_self">CPACR CP field values</a></td><td class="desc">Valid values for CPACR CP field </td></tr>
<tr id="row_1_4_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_4_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_4_')"/><a class="el" href="group__CMSIS__CPSR.html" target="_self">Current Program Status Register (CPSR)</a></td><td class="desc">The Current Program Status Register (CPSR) holds processor status and control information </td></tr>
<tr id="row_1_4_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CPSR__BITS.html" target="_self">CPSR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_4_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__CPSR__M.html" target="_self">CPSR M field values</a></td><td class="desc">Valid values for CPSR M field </td></tr>
<tr id="row_1_5_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_5_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_5_')"/><a class="el" href="group__CMSIS__DFSR.html" target="_self">Data Fault Status Register (DFSR)</a></td><td class="desc">The DFSR holds status information about the last data fault </td></tr>
<tr id="row_1_5_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__DFSR__BITS.html" target="_self">ACTLR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_6_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_6_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_6_')"/><a class="el" href="group__CMSIS__DACR.html" target="_self">Domain Access Control Register (DACR)</a></td><td class="desc">DACR defines the access permission for each of the sixteen memory domains </td></tr>
<tr id="row_1_6_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__DACR__BITS.html" target="_self">DACR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_6_1_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__DACR__Dn.html" target="_self">DACR Dn field values</a></td><td class="desc">Valid values for DACR Dn field </td></tr>
<tr id="row_1_7_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__FPEXC.html" target="_self">Floating-Point Exception Control register (FPEXC)</a></td><td class="desc">Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded </td></tr>
<tr id="row_1_8_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_8_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_8_')"/><a class="el" href="group__CMSIS__FPSCR.html" target="_self">Floating-point Status and Control Register (FPSCR)</a></td><td class="desc">Provides floating-point system status information and control </td></tr>
<tr id="row_1_8_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__FPSCR__BITS.html" target="_self">FPSCR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_9_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_9_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_9_')"/><a class="el" href="group__CMSIS__IFSR.html" target="_self">Instruction Fault Status Register (IFSR)</a></td><td class="desc">The IFSR holds status information about the last instruction fault </td></tr>
<tr id="row_1_9_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__IFSR__BITS.html" target="_self">IFSR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_10_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_10_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_10_')"/><a class="el" href="group__CMSIS__ISR.html" target="_self">Interrupt Status Register (ISR)</a></td><td class="desc">The ISR shows whether an IRQ, FIQ, or external abort is pending </td></tr>
<tr id="row_1_10_0_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__ISR__BITS.html" target="_self">ISR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_11_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__MPIDR.html" target="_self">Multiprocessor Affinity Register (MPIDR)</a></td><td class="desc">In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions </td></tr>
<tr id="row_1_12_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CNTFRQ.html" target="_self">Counter Frequency register (CNTFRQ)</a></td><td class="desc">Indicates the clock frequency of the system counter </td></tr>
<tr id="row_1_13_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CNTP__CTL.html" target="_self">PL1 Physical Timer Control register (CNTP_CTL)</a></td><td class="desc">The control register for the physical timer </td></tr>
<tr id="row_1_14_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CNTP__CVAL.html" target="_self">PL1 Physical Timer Compare Value register (CNTP_CVAL)</a></td><td class="desc">Holds the 64-bit compare value for the PL1 physical timer </td></tr>
<tr id="row_1_15_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CNTP__TVAL.html" target="_self">PL1 Physical Timer Value register (CNTP_TVAL)</a></td><td class="desc">Holds the timer value for the PL1 physical timer </td></tr>
<tr id="row_1_16_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__CNTPCT.html" target="_self">PL1 Physical Count register (CNTPCT)</a></td><td class="desc">Holds the 64-bit physical count value </td></tr>
<tr id="row_1_17_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__SP.html" target="_self">Stack Pointer (SP/R13)</a></td><td class="desc">The processor uses SP as a pointer to the active stack </td></tr>
<tr id="row_1_18_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_1_18_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('1_18_')"/><a class="el" href="group__CMSIS__SCTLR.html" target="_self">System Control Register (SCTLR)</a></td><td class="desc">The SCTLR provides the top level control of the system, including its memory system </td></tr>
<tr id="row_1_18_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__SCTLR__BITS.html" target="_self">SCTLR Bits</a></td><td class="desc">Bit position and mask macros </td></tr>
<tr id="row_1_19_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__TLB.html" target="_self">TLB maintenance operations</a></td><td class="desc">This section describes the TLB operations that are implemented on all Armv7-A implementations </td></tr>
<tr id="row_1_20_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__TTBR.html" target="_self">Translation Table Base Registers (TTBR0/TTBR1)</a></td><td class="desc">TTBRn holds the base address of translation table n, and information about the memory it occupies </td></tr>
<tr id="row_1_21_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__VBAR.html" target="_self">Vector Base Address Register (VBAR)</a></td><td class="desc">When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode </td></tr>
<tr id="row_1_22_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__CMSIS__MVBAR.html" target="_self">Monitor Vector Base Address Register (MVBAR)</a></td><td class="desc">The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode </td></tr>
<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Naming conventions and optional features for accessing peripherals </td></tr>
<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__version__ctrl.html" target="_self">Version Control</a></td><td class="desc">Version symbols for CMSIS release specific C/C++ source code </td></tr>
<tr id="row_4_" class="even"><td class="entry"><img id="arr_4_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('4_')"/><a class="el" href="group__CMSIS__Core__FunctionInterface.html" target="_self">Core Peripherals</a></td><td class="desc"></td></tr>
<tr id="row_4_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__GIC__functions.html" target="_self">Generic Interrupt Controller Functions</a></td><td class="desc">The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC) </td></tr>
<tr id="row_4_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__L1__cache__functions.html" target="_self">L1 Cache Functions</a></td><td class="desc">L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache </td></tr>
<tr id="row_4_2_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__L2__cache__functions.html" target="_self">L2C-310 Cache Controller Functions</a></td><td class="desc">L2C-310 Cache Controller gives access to functions for level 2 cache maintenance.<br/>
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/index.html">Level 2 Cache Controller L2C-310 Technical Reference Manual</a> </td></tr>
<tr id="row_4_3_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__PL1__timer__functions.html" target="_self">Generic Physical Timer Functions</a></td><td class="desc">Generic Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.<br/>
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464f/index.html">Cortex-A7 MPCore Technical Reference Manual</a> </td></tr>
<tr id="row_4_4_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__PTM__timer__functions.html" target="_self">Private Timer Functions</a></td><td class="desc">Private Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.<br/>
References: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0434c/index.html">Cortex-A5 MPCore Technical Reference Manual</a>, <a href="http://infocenter.arm.com/help/topic/com.arm.doc.100486_0401_10_en/index.html">Cortex-A9 MPCore Technical Reference Manual</a> </td></tr>
<tr id="row_4_5_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img id="arr_4_5_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('4_5_')"/><a class="el" href="group__MMU__functions.html" target="_self">Memory Management Unit Functions</a></td><td class="desc">MMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.<br/>
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a> </td></tr>
<tr id="row_4_5_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__MMU__defs__gr.html" target="_self">MMU Defines and Structs</a></td><td class="desc">Defines and structures that relate to the Memory Management Unit </td></tr>
<tr id="row_4_6_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__FPU__functions.html" target="_self">Floating Point Unit Functions</a></td><td class="desc">FPU Functions enable the use of Floating Point instructions and extensions.<br/>
Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html">Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition</a> </td></tr>
<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__comp__cntrl__gr.html" target="_self">Compiler Control</a></td><td class="desc">Compiler agnostic #define symbols for generic C/C++ source code </td></tr>
<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__CMSIS__Core__InstructionInterface.html" target="_self">Intrinsic Functions</a></td><td class="desc">Functions that generate specific Cortex-A CPU Instructions </td></tr>
<tr id="row_7_"><td class="entry"><img id="arr_7_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('7_')"/><a class="el" href="group__irq__ctrl__gr.html" target="_self">Interrupts and Exceptions</a></td><td class="desc">Generic functions to access the Interrupt Controller </td></tr>
<tr id="row_7_0_" class="even"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__irq__mode__defs.html" target="_self">IRQ Mode Bit-Masks</a></td><td class="desc">Configure interrupt line mode </td></tr>
<tr id="row_7_1_"><td class="entry"><img src="ftv2blank.png" alt="&#160;" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__irq__priority__defs.html" target="_self">IRQ Priority Bit-Masks</a></td><td class="desc">Definitions used by interrupt priority functions </td></tr>
</table>
</div><!-- directory -->
</div><!-- contents -->
</div><!-- doc-content -->
<!-- start footer part -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
<ul>
<li class="footer">Generated on Wed Jul 10 2019 15:20:27 for CMSIS-Core (Cortex-A) Version 1.1.4 by Arm Ltd. All rights reserved.
<!--
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6
-->
</li>
</ul>
</div>
</body>
</html>