Release v2.3.6
diff --git a/Include/stm32f301x8.h b/Include/stm32f301x8.h index 52a0aad..2b5a6c2 100644 --- a/Include/stm32f301x8.h +++ b/Include/stm32f301x8.h
@@ -720,6 +720,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -8566,8 +8575,8 @@ /* Aliases for __IRQn */ #define ADC1_2_IRQn ADC1_IRQn #define COMP1_2_IRQn COMP2_IRQn -#define COMP1_2_3_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_3_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -8581,8 +8590,8 @@ /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler #define COMP1_2_IRQHandler COMP2_IRQHandler -#define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
diff --git a/Include/stm32f302x8.h b/Include/stm32f302x8.h index 0a155f8..ecd2947 100644 --- a/Include/stm32f302x8.h +++ b/Include/stm32f302x8.h
@@ -829,6 +829,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -12331,8 +12340,8 @@ /* Aliases for __IRQn */ #define ADC1_2_IRQn ADC1_IRQn #define COMP1_2_3_IRQn COMP2_IRQn -#define COMP1_2_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -12350,8 +12359,8 @@ /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler #define COMP1_2_3_IRQHandler COMP2_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
diff --git a/Include/stm32f302xc.h b/Include/stm32f302xc.h index 658b362..c58c15c 100644 --- a/Include/stm32f302xc.h +++ b/Include/stm32f302xc.h
@@ -864,6 +864,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -12677,9 +12686,9 @@ /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn -#define COMP2_IRQn COMP1_2_IRQn #define COMP_IRQn COMP1_2_IRQn #define COMP1_2_3_IRQn COMP1_2_IRQn +#define COMP2_IRQn COMP1_2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM18_DAC2_IRQn TIM1_CC_IRQn @@ -12694,9 +12703,9 @@ /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler -#define COMP2_IRQHandler COMP1_2_IRQHandler #define COMP_IRQHandler COMP1_2_IRQHandler #define COMP1_2_3_IRQHandler COMP1_2_IRQHandler +#define COMP2_IRQHandler COMP1_2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
diff --git a/Include/stm32f302xe.h b/Include/stm32f302xe.h index 9be4d11..f9e255b 100644 --- a/Include/stm32f302xe.h +++ b/Include/stm32f302xe.h
@@ -955,6 +955,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -14417,8 +14426,8 @@ /* Aliases for __IRQn */ #define ADC1_IRQn ADC1_2_IRQn -#define COMP1_2_3_IRQn COMP1_2_IRQn #define COMP_IRQn COMP1_2_IRQn +#define COMP1_2_3_IRQn COMP1_2_IRQn #define COMP2_IRQn COMP1_2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn @@ -14436,8 +14445,8 @@ /* Aliases for __IRQHandler */ #define ADC1_IRQHandler ADC1_2_IRQHandler -#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler #define COMP_IRQHandler COMP1_2_IRQHandler +#define COMP1_2_3_IRQHandler COMP1_2_IRQHandler #define COMP2_IRQHandler COMP1_2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler
diff --git a/Include/stm32f303x8.h b/Include/stm32f303x8.h index c905f77..668c1b4 100644 --- a/Include/stm32f303x8.h +++ b/Include/stm32f303x8.h
@@ -781,6 +781,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -12092,8 +12101,8 @@ #define ADC1_IRQn ADC1_2_IRQn #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn -#define COMP_IRQn COMP2_IRQn #define COMP1_2_IRQn COMP2_IRQn +#define COMP_IRQn COMP2_IRQn #define COMP1_2_3_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn @@ -12108,8 +12117,8 @@ #define ADC1_IRQHandler ADC1_2_IRQHandler #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler -#define COMP_IRQHandler COMP2_IRQHandler #define COMP1_2_IRQHandler COMP2_IRQHandler +#define COMP_IRQHandler COMP2_IRQHandler #define COMP1_2_3_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
diff --git a/Include/stm32f303xc.h b/Include/stm32f303xc.h index 3376597..bc07c06 100644 --- a/Include/stm32f303xc.h +++ b/Include/stm32f303xc.h
@@ -896,6 +896,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */
diff --git a/Include/stm32f303xe.h b/Include/stm32f303xe.h index 50acebc..cfb8aa8 100644 --- a/Include/stm32f303xe.h +++ b/Include/stm32f303xe.h
@@ -1007,6 +1007,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */
diff --git a/Include/stm32f318xx.h b/Include/stm32f318xx.h index 120871e..c441955 100644 --- a/Include/stm32f318xx.h +++ b/Include/stm32f318xx.h
@@ -721,6 +721,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -8553,8 +8562,8 @@ /* Aliases for __IRQn */ #define ADC1_2_IRQn ADC1_IRQn #define COMP_IRQn COMP2_IRQn -#define COMP1_2_IRQn COMP2_IRQn #define COMP1_2_3_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -8568,8 +8577,8 @@ /* Aliases for __IRQHandler */ #define ADC1_2_IRQHandler ADC1_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP1_2_3_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
diff --git a/Include/stm32f328xx.h b/Include/stm32f328xx.h index fb6b3f4..a78d828 100644 --- a/Include/stm32f328xx.h +++ b/Include/stm32f328xx.h
@@ -780,6 +780,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -12062,9 +12071,9 @@ #define ADC1_IRQn ADC1_2_IRQn #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP_IRQn COMP2_IRQn #define COMP1_2_3_IRQn COMP2_IRQn -#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM18_DAC2_IRQn TIM1_CC_IRQn @@ -12078,9 +12087,9 @@ #define ADC1_IRQHandler ADC1_2_IRQHandler #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler #define COMP1_2_3_IRQHandler COMP2_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
diff --git a/Include/stm32f334x8.h b/Include/stm32f334x8.h index 7831638..7ca2a90 100644 --- a/Include/stm32f334x8.h +++ b/Include/stm32f334x8.h
@@ -898,6 +898,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -9260,6 +9269,7 @@ #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */ #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */ +/* Slave Timer A reset enable bits upon other slave timers events */ #define HRTIM_RSTR_TIMBCMP1_Pos (19U) #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */ #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */ @@ -9300,6 +9310,169 @@ #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */ #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */ +/* Slave Timer B reset enable bits upon other slave timers events */ +#define HRTIM_RSTBR_TIMACMP1_Pos (19U) +#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */ +#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RSTBR_TIMACMP2_Pos (20U) +#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */ +#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RSTBR_TIMACMP4_Pos (21U) +#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */ +#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_RSTBR_TIMCCMP1_Pos (22U) +#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_RSTBR_TIMCCMP2_Pos (23U) +#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */ +#define HRTIM_RSTBR_TIMCCMP4_Pos (24U) +#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */ +#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */ + +#define HRTIM_RSTBR_TIMDCMP1_Pos (25U) +#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_RSTBR_TIMDCMP2_Pos (26U) +#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */ +#define HRTIM_RSTBR_TIMDCMP4_Pos (27U) +#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */ +#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */ + +#define HRTIM_RSTBR_TIMECMP1_Pos (28U) +#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */ +#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_RSTBR_TIMECMP2_Pos (29U) +#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */ +#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */ +#define HRTIM_RSTBR_TIMECMP4_Pos (30U) +#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */ +#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */ + +/* Slave Timer C reset enable bits upon other slave timers events */ +#define HRTIM_RSTCR_TIMACMP1_Pos (19U) +#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */ +#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RSTCR_TIMACMP2_Pos (20U) +#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */ +#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RSTCR_TIMACMP4_Pos (21U) +#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */ +#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_RSTCR_TIMBCMP1_Pos (22U) +#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_RSTCR_TIMBCMP2_Pos (23U) +#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */ +#define HRTIM_RSTCR_TIMBCMP4_Pos (24U) +#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */ +#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */ + +#define HRTIM_RSTCR_TIMDCMP1_Pos (25U) +#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_RSTCR_TIMDCMP2_Pos (26U) +#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */ +#define HRTIM_RSTCR_TIMDCMP4_Pos (27U) +#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */ +#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */ + +#define HRTIM_RSTCR_TIMECMP1_Pos (28U) +#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */ +#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_RSTCR_TIMECMP2_Pos (29U) +#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */ +#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */ +#define HRTIM_RSTCR_TIMECMP4_Pos (30U) +#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */ +#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */ + +/* Slave Timer D reset enable bits upon other slave timers events */ +#define HRTIM_RSTDR_TIMACMP1_Pos (19U) +#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */ +#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RSTDR_TIMACMP2_Pos (20U) +#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */ +#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RSTDR_TIMACMP4_Pos (21U) +#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */ +#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_RSTDR_TIMBCMP1_Pos (22U) +#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_RSTDR_TIMBCMP2_Pos (23U) +#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */ +#define HRTIM_RSTDR_TIMBCMP4_Pos (24U) +#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */ +#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */ + +#define HRTIM_RSTDR_TIMCCMP1_Pos (25U) +#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_RSTDR_TIMCCMP2_Pos (26U) +#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */ +#define HRTIM_RSTDR_TIMCCMP4_Pos (27U) +#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */ +#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */ + +#define HRTIM_RSTDR_TIMECMP1_Pos (28U) +#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */ +#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */ +#define HRTIM_RSTDR_TIMECMP2_Pos (29U) +#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */ +#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */ +#define HRTIM_RSTDR_TIMECMP4_Pos (30U) +#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */ +#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */ + +#define HRTIM_RSTER_TIMACMP1_Pos (19U) +#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */ +#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */ +#define HRTIM_RSTER_TIMACMP2_Pos (20U) +#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */ +#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */ +#define HRTIM_RSTER_TIMACMP4_Pos (21U) +#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */ +#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */ + +#define HRTIM_RSTER_TIMBCMP1_Pos (22U) +#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */ +#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */ +#define HRTIM_RSTER_TIMBCMP2_Pos (23U) +#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */ +#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */ +#define HRTIM_RSTER_TIMBCMP4_Pos (24U) +#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */ +#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */ + +#define HRTIM_RSTER_TIMCCMP1_Pos (25U) +#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */ +#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */ +#define HRTIM_RSTER_TIMCCMP2_Pos (26U) +#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */ +#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */ +#define HRTIM_RSTER_TIMCCMP4_Pos (27U) +#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */ +#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */ + +#define HRTIM_RSTER_TIMDCMP1_Pos (28U) +#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */ +#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */ +#define HRTIM_RSTER_TIMDCMP2_Pos (29U) +#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */ +#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */ +#define HRTIM_RSTER_TIMDCMP4_Pos (30U) +#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */ +#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */ + /**** Bit definition for Slave Timer Chopper register *************************/ #define HRTIM_CHPR_CARFRQ_Pos (0U) #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */ @@ -15056,8 +15229,8 @@ #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn #define COMP_IRQn COMP2_IRQn -#define COMP1_2_IRQn COMP2_IRQn #define COMP1_2_3_IRQn COMP2_IRQn +#define COMP1_2_IRQn COMP2_IRQn #define COMP4_5_6_IRQn COMP4_6_IRQn #define I2C3_ER_IRQn HRTIM1_FLT_IRQn #define I2C3_EV_IRQn HRTIM1_TIME_IRQn @@ -15074,8 +15247,8 @@ #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler #define COMP_IRQHandler COMP2_IRQHandler -#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP1_2_3_IRQHandler COMP2_IRQHandler +#define COMP1_2_IRQHandler COMP2_IRQHandler #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler #define I2C3_ER_IRQHandler HRTIM1_FLT_IRQHandler #define I2C3_EV_IRQHandler HRTIM1_TIME_IRQHandler
diff --git a/Include/stm32f358xx.h b/Include/stm32f358xx.h index 999f888..13f503e 100644 --- a/Include/stm32f358xx.h +++ b/Include/stm32f358xx.h
@@ -854,6 +854,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -13191,8 +13200,8 @@ #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn #define COMP1_2_IRQn COMP1_2_3_IRQn -#define COMP_IRQn COMP1_2_3_IRQn #define COMP2_IRQn COMP1_2_3_IRQn +#define COMP_IRQn COMP1_2_3_IRQn #define COMP4_6_IRQn COMP4_5_6_IRQn #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM18_DAC2_IRQn TIM1_CC_IRQn @@ -13211,8 +13220,8 @@ #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler -#define COMP_IRQHandler COMP1_2_3_IRQHandler #define COMP2_IRQHandler COMP1_2_3_IRQHandler +#define COMP_IRQHandler COMP1_2_3_IRQHandler #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #define TIM18_DAC2_IRQHandler TIM1_CC_IRQHandler
diff --git a/Include/stm32f373xc.h b/Include/stm32f373xc.h index 22e8f69..4a95fb5 100644 --- a/Include/stm32f373xc.h +++ b/Include/stm32f373xc.h
@@ -892,6 +892,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */
diff --git a/Include/stm32f378xx.h b/Include/stm32f378xx.h index 2f50681..0dbb462 100644 --- a/Include/stm32f378xx.h +++ b/Include/stm32f378xx.h
@@ -851,6 +851,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -11743,9 +11752,9 @@ #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn #define USBWakeUp_IRQn CEC_IRQn +#define COMP2_IRQn COMP_IRQn #define COMP1_2_3_IRQn COMP_IRQn #define COMP1_2_IRQn COMP_IRQn -#define COMP2_IRQn COMP_IRQn #define ADC4_IRQn SDADC1_IRQn #define TIM8_BRK_IRQn TIM12_IRQn #define TIM8_UP_IRQn TIM13_IRQn @@ -11764,9 +11773,9 @@ #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler #define USBWakeUp_IRQHandler CEC_IRQHandler +#define COMP2_IRQHandler COMP_IRQHandler #define COMP1_2_3_IRQHandler COMP_IRQHandler #define COMP1_2_IRQHandler COMP_IRQHandler -#define COMP2_IRQHandler COMP_IRQHandler #define ADC4_IRQHandler SDADC1_IRQHandler #define TIM8_BRK_IRQHandler TIM12_IRQHandler #define TIM8_UP_IRQHandler TIM13_IRQHandler
diff --git a/Include/stm32f398xx.h b/Include/stm32f398xx.h index 060a7e4..dc90a89 100644 --- a/Include/stm32f398xx.h +++ b/Include/stm32f398xx.h
@@ -963,6 +963,15 @@ * @{ */ + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -15027,9 +15036,9 @@ #define SDADC1_IRQn ADC4_IRQn #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn -#define COMP1_2_IRQn COMP1_2_3_IRQn #define COMP_IRQn COMP1_2_3_IRQn #define COMP2_IRQn COMP1_2_3_IRQn +#define COMP1_2_IRQn COMP1_2_3_IRQn #define COMP4_6_IRQn COMP4_5_6_IRQn #define HRTIM1_FLT_IRQn I2C3_ER_IRQn #define HRTIM1_TIME_IRQn I2C3_EV_IRQn @@ -15050,9 +15059,9 @@ #define SDADC1_IRQHandler ADC4_IRQHandler #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler -#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler #define COMP_IRQHandler COMP1_2_3_IRQHandler #define COMP2_IRQHandler COMP1_2_3_IRQHandler +#define COMP1_2_IRQHandler COMP1_2_3_IRQHandler #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler #define HRTIM1_FLT_IRQHandler I2C3_ER_IRQHandler #define HRTIM1_TIME_IRQHandler I2C3_EV_IRQHandler
diff --git a/Include/stm32f3xx.h b/Include/stm32f3xx.h index feef6ec..ec4dca5 100644 --- a/Include/stm32f3xx.h +++ b/Include/stm32f3xx.h
@@ -103,11 +103,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V2.3.5 + * @brief CMSIS Device version number V2.3.6 */ #define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ #define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F3_CMSIS_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F3_CMSIS_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ #define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\ |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\ @@ -204,6 +204,60 @@ #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) /** * @}