Release v1.4.2
diff --git a/Include/stm32g030xx.h b/Include/stm32g030xx.h
index f11fb83..af20715 100644
--- a/Include/stm32g030xx.h
+++ b/Include/stm32g030xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -513,6 +514,9 @@
} WWDG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -2395,7 +2399,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -7398,6 +7402,16 @@
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -7423,5 +7437,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g031xx.h b/Include/stm32g031xx.h
index 46ee306..62f929b 100644
--- a/Include/stm32g031xx.h
+++ b/Include/stm32g031xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -546,6 +547,9 @@
} WWDG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -2485,7 +2489,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -7939,6 +7943,16 @@
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -7964,5 +7978,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g041xx.h b/Include/stm32g041xx.h
index 4f375b2..d8ede70 100644
--- a/Include/stm32g041xx.h
+++ b/Include/stm32g041xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -588,6 +589,9 @@
} RNG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -2721,7 +2725,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -8247,6 +8251,16 @@
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -8272,5 +8286,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g050xx.h b/Include/stm32g050xx.h
index 9916637..53490b7 100644
--- a/Include/stm32g050xx.h
+++ b/Include/stm32g050xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -518,6 +519,9 @@
} WWDG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -2414,7 +2418,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -7522,6 +7526,16 @@
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -7547,5 +7561,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g051xx.h b/Include/stm32g051xx.h
index 1bfaa71..dd3e7c9 100644
--- a/Include/stm32g051xx.h
+++ b/Include/stm32g051xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -586,6 +587,9 @@
} WWDG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -2821,7 +2825,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -8474,6 +8478,16 @@
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -8499,5 +8513,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g061xx.h b/Include/stm32g061xx.h
index f480ce1..4738a94 100644
--- a/Include/stm32g061xx.h
+++ b/Include/stm32g061xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -628,6 +629,9 @@
} RNG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -3057,7 +3061,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x1FUL << FLASH_CR_PNB_Pos) /*!< 0x000000F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -8782,6 +8786,16 @@
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -8807,5 +8821,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g070xx.h b/Include/stm32g070xx.h
index bf82a89..702c42a 100644
--- a/Include/stm32g070xx.h
+++ b/Include/stm32g070xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -517,6 +518,9 @@
} WWDG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -2423,7 +2427,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -7684,6 +7688,16 @@
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -7709,5 +7723,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g071xx.h b/Include/stm32g071xx.h
index 82d78b8..b8b11b3 100644
--- a/Include/stm32g071xx.h
+++ b/Include/stm32g071xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -625,7 +626,6 @@
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
-
/**
* @}
*/
@@ -3040,7 +3040,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -9212,6 +9212,16 @@
#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1) || \
((INSTANCE) == UCPD2))
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -9237,5 +9247,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g081xx.h b/Include/stm32g081xx.h
index a35ffad..d6ebdd4 100644
--- a/Include/stm32g081xx.h
+++ b/Include/stm32g081xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -667,7 +668,6 @@
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
-
/**
* @}
*/
@@ -3276,7 +3276,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -9520,6 +9520,16 @@
#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1) || \
((INSTANCE) == UCPD2))
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -9545,5 +9555,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g0b0xx.h b/Include/stm32g0b0xx.h
index fd3acb4..6c54693 100644
--- a/Include/stm32g0b0xx.h
+++ b/Include/stm32g0b0xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -547,10 +548,6 @@
} USB_DRD_PMABuffDescTypeDef;
/**
- * @}
- */
-
-/**
* @brief Window WATCHDOG
*/
typedef struct
@@ -561,6 +558,9 @@
} WWDG_TypeDef;
+/**
+ * @}
+ */
/** @addtogroup Peripheral_memory_map
* @{
@@ -3148,7 +3148,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_BKER_Pos (13U)
#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00002000 */
@@ -8794,7 +8794,8 @@
/* EndPoint Register MASK (no toggle fields) */
#define USB_CHEP_REG_MASK (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
- USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR) /* =8f8f */
+ USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR |\
+ USB_CHEP_NAK) /* 0x07FF8F8F */
#define USB_CHEP_TX_DTOGMASK (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
#define USB_CHEP_RX_DTOGMASK (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)
@@ -9303,6 +9304,16 @@
/*********************** USB OTG HCD Instances ********************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS))
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -9328,5 +9339,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g0b1xx.h b/Include/stm32g0b1xx.h
index 5d81052..36e2cba 100644
--- a/Include/stm32g0b1xx.h
+++ b/Include/stm32g0b1xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -694,10 +695,6 @@
__IO uint32_t TXBD; /*!<Transmission buffer address*/
__IO uint32_t RXBD; /*!<Reception buffer address */
} USB_DRD_PMABuffDescTypeDef;
-
-/**
- * @}
- */
/**
* @brief VREFBUF
*/
@@ -740,7 +737,6 @@
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
-
/**
* @}
*/
@@ -4001,7 +3997,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_BKER_Pos (13U)
#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00002000 */
@@ -10651,7 +10647,8 @@
/* EndPoint Register MASK (no toggle fields) */
#define USB_CHEP_REG_MASK (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
- USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR) /* =8f8f */
+ USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR |\
+ USB_CHEP_NAK) /* 0x07FF8F8F */
#define USB_CHEP_TX_DTOGMASK (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
#define USB_CHEP_RX_DTOGMASK (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)
@@ -11233,6 +11230,16 @@
/*********************** USB OTG HCD Instances ********************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS))
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -11258,5 +11265,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g0c1xx.h b/Include/stm32g0c1xx.h
index 4ad694c..8ebf0a7 100644
--- a/Include/stm32g0c1xx.h
+++ b/Include/stm32g0c1xx.h
@@ -23,6 +23,7 @@
*
******************************************************************************
*/
+
/** @addtogroup CMSIS_Device
* @{
*/
@@ -70,7 +71,7 @@
/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
@@ -695,10 +696,6 @@
__IO uint32_t TXBD; /*!<Transmission buffer address*/
__IO uint32_t RXBD; /*!<Reception buffer address */
} USB_DRD_PMABuffDescTypeDef;
-
-/**
- * @}
- */
/**
* @brief VREFBUF
*/
@@ -782,7 +779,6 @@
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
-
/**
* @}
*/
@@ -4237,7 +4233,7 @@
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
-#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
+#define FLASH_CR_PNB_Msk (0x3FFUL << FLASH_CR_PNB_Pos) /*!< 0x00001FF8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_BKER_Pos (13U)
#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00002000 */
@@ -10955,7 +10951,8 @@
/* EndPoint Register MASK (no toggle fields) */
#define USB_CHEP_REG_MASK (USB_CHEP_ERRRX | USB_CHEP_ERRTX | USB_CHEP_LSEP | \
USB_CHEP_DEVADDR | USB_CHEP_VTRX | USB_CHEP_SETUP | \
- USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR) /* =8f8f */
+ USB_CHEP_UTYPE | USB_CHEP_KIND | USB_CHEP_VTTX | USB_CHEP_ADDR |\
+ USB_CHEP_NAK) /* 0x07FF8F8F */
#define USB_CHEP_TX_DTOGMASK (USB_CHEP_TX_STTX | USB_CHEP_REG_MASK)
#define USB_CHEP_RX_DTOGMASK (USB_CHEP_RX_STRX | USB_CHEP_REG_MASK)
@@ -11541,6 +11538,16 @@
/*********************** USB OTG HCD Instances ********************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS))
+/******************************************************************************/
+/* For a painless codes migration between the STM32G0xx device product */
+/* lines, the aliases defined below are put in place to overcome the */
+/* differences in the interrupt handlers and IRQn definitions. */
+/* No need to update developed interrupt code when moving across */
+/* product lines within the same STM32G0 Family */
+/******************************************************************************/
+/* Aliases for IRQn_Type */
+#define SVC_IRQn SVCall_IRQn
+
/**
* @}
*/
@@ -11566,5 +11573,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g0xx.h b/Include/stm32g0xx.h
index bd1302d..6ac4107 100644
--- a/Include/stm32g0xx.h
+++ b/Include/stm32g0xx.h
@@ -90,7 +90,7 @@
*/
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
-#define __STM32G0_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32G0_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
@@ -242,8 +242,3 @@
/**
* @}
*/
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/system_stm32g0xx.h b/Include/system_stm32g0xx.h
index 0d2dad6..a1b094c 100644
--- a/Include/system_stm32g0xx.h
+++ b/Include/system_stm32g0xx.h
@@ -101,4 +101,3 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/README.md b/README.md
index c260b8f..6dac671 100644
--- a/README.md
+++ b/README.md
@@ -16,7 +16,7 @@
Two models of publication are proposed for the STM32Cube embedded software:
* The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
* The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
-
+
## Description
This **cmsis_device_g0** MCU component repo is one element of the STM32CubeG0 MCU embedded software package, providing the **cmsis device** part.
@@ -27,14 +27,7 @@
## Compatibility information
-In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package:
-
-CMSIS Device G0 | CMSIS Core | Was delivered in the full MCU package
---------------- | -------------- | -------------------------------------
-Tag v1.2.0 | Tag v4.5_cm0 | Tag v1.2.0
-Tag v1.3.0 | Tag v5.4.0_cm0 | Tag v1.3.0
-Tag v1.4.0 | Tag v5.6.0_cm0 | Tag v1.4.0
-Tag v1.4.1 | Tag v5.6.0_cm0 | Tag v1.5.0
+It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeG0/blob/master/Release_Notes.html) release note.
The full **STM32CubeG0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG0).
diff --git a/Release_Notes.html b/Release_Notes.html
index 68a0bb5..35c0be0 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -45,19 +45,19 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section6" checked aria-hidden="true"> <label for="collapse-section6" area-hidden="true">V1.4.1 / 17-June-2021 </label>
+<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" area-hidden="true">V1.4.2 / 01-April-2022 </label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
-<li>Update to remove wrong bits defined for DMAMUX Req ID.</li>
-<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li>
-<li>Add new atomic register access macros in stm32g0xx.h file.</li>
-<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
-<li>Update Licensing information and format
+<li>Rename ADC TRx registers AWDxTR to be compliant with the reference manual.</li>
+<li>Fix Doxygen grouping issues.</li>
+<li>Update IRQ handler enumeration structure to be aligned with template CMSIS device.h file defined by ARM.
<ul>
-<li>Add LICENSE.txt file</li>
-<li>Remove License message from Release_Notes.html</li>
-<li>Update header files with new license format</li>
+<li>Rename SVC_IRQn to SVCall_IRQn:</li>
+</ul></li>
+<li>Add the following aliases for IRQ number definition to ensure compatibility across STM32 Series;
+<ul>
+<li>#define SVC_IRQn SVCall_IRQn</li>
</ul></li>
</ul>
<h2 id="contents">Contents</h2>
@@ -74,9 +74,38 @@
</div>
</div>
<div class="collapse">
-<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" area-hidden="true">V1.4.0 / 29-October-2020 </label>
+<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" area-hidden="true">V1.4.1 / 17-June-2021 </label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Update to remove wrong bits defined for DMAMUX Req ID.</li>
+<li>Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive : USER_VECT_TAB_ADDRESS.</li>
+<li>Add new atomic register access macros in stm32g0xx.h file.</li>
+<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
+<li>Update Licensing information and format
+<ul>
+<li>Add LICENSE.txt file</li>
+<li>Remove License message from Release_Notes.html</li>
+<li>Update header files with new license format</li>
+</ul></li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<ul>
+<li>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</li>
+<li>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</li>
+<li>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</li>
+<li>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</li>
+</ul>
+<h2 id="known-limitations-1">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" area-hidden="true">V1.4.0 / 29-October-2020 </label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
<h3 id="maintenance-release-and-product-update">Maintenance release and Product Update</h3>
<p>Official release for STM32G0xx CMSIS introducing <strong>stm32g0b0xx, stm32g0b1xx, stm32g0c1xx devices</strong> and <strong>stm32g050xx, stm32g051xx, stm32g061xx devices.</strong></p>
<p>Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
@@ -157,19 +186,19 @@
</tr>
</tbody>
</table>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<p>-<strong>CMSIS devices files for stm32g0B0xx, stm32g0B1xx, stm32g0C1xx devices.</strong></p>
<p>-<strong>CMSIS devices files for stm32g050xx, stm32g051xx, stm32g061xx devices.</strong></p>
<p>-CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p>
<p>-CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
<p>None</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.3.0 / 25-June-2019 </label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release for STM32G0xx CMSIS supporting stm32g030xx, stm32g031xx, stm32g041xx, stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
<p><strong>Fixed bugs list</strong></p>
@@ -185,10 +214,10 @@
</tr>
</tbody>
</table>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<p>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p>
<p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
<p><strong>Requirements not met or planned in a forthcoming release</strong></p>
<table>
<thead>
@@ -218,7 +247,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 05-April-2019 </label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<h3 id="maintenance-release-and-product-update-1">Maintenance release and Product Update</h3>
<p>First release for STM32G0xx CMSIS introducing <strong>stm32g030xx, stm32g031xx, stm32g041xx</strong> devices.</p>
<p><strong>Additional features</strong></p>
@@ -250,10 +279,10 @@
</tr>
</tbody>
</table>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-4">Contents</h2>
<p>CMSIS devices files for stm32g030xx, stm32g031xx, stm32g041xx devices.</p>
<p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
<p><strong>Requirements not met or planned in a forthcoming release</strong></p>
<table>
<thead>
@@ -286,7 +315,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 06-February-2019 </label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="maintenance-release-1">Maintenance release</h3>
<p>Maintenance release for <strong>STM32G0xx</strong> devices (stm32g070xx, stm32g071xx, stm32g081xx devices)</p>
<p><strong>Fixed bugs list</strong></p>
@@ -311,17 +340,17 @@
</tr>
</tbody>
</table>
-<h2 id="contents-4">Contents</h2>
+<h2 id="contents-5">Contents</h2>
<p>CMSIS devices files for stm32g070xx, stm32g071xx, stm32g081xx devices.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"> V1.0.0 / 26-October-2018 </label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release for <strong>STM32G0xx</strong> devices</p>
-<h2 id="contents-5">Contents</h2>
+<h2 id="contents-6">Contents</h2>
<ul>
<li>CMSIS devices files for STM32G070xx, STM32G071xx and STM32G081xx</li>
</ul>
diff --git a/Source/Templates/arm/startup_stm32g030xx.s b/Source/Templates/arm/startup_stm32g030xx.s
index fa700b8..7817481 100644
--- a/Source/Templates/arm/startup_stm32g030xx.s
+++ b/Source/Templates/arm/startup_stm32g030xx.s
@@ -232,5 +232,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g031xx.s b/Source/Templates/arm/startup_stm32g031xx.s
index db2d223..a06c762 100644
--- a/Source/Templates/arm/startup_stm32g031xx.s
+++ b/Source/Templates/arm/startup_stm32g031xx.s
@@ -242,5 +242,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g041xx.s b/Source/Templates/arm/startup_stm32g041xx.s
index 6c02ca0..9f4e4b7 100644
--- a/Source/Templates/arm/startup_stm32g041xx.s
+++ b/Source/Templates/arm/startup_stm32g041xx.s
@@ -244,5 +244,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g050xx.s b/Source/Templates/arm/startup_stm32g050xx.s
index 4e98da2..e05c133 100644
--- a/Source/Templates/arm/startup_stm32g050xx.s
+++ b/Source/Templates/arm/startup_stm32g050xx.s
@@ -235,5 +235,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32g051xx.s b/Source/Templates/arm/startup_stm32g051xx.s
index 19c7dbe..e0c097c 100644
--- a/Source/Templates/arm/startup_stm32g051xx.s
+++ b/Source/Templates/arm/startup_stm32g051xx.s
@@ -244,5 +244,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32g061xx.s b/Source/Templates/arm/startup_stm32g061xx.s
index a22e335..192b7c5 100644
--- a/Source/Templates/arm/startup_stm32g061xx.s
+++ b/Source/Templates/arm/startup_stm32g061xx.s
@@ -246,5 +246,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
\ No newline at end of file
diff --git a/Source/Templates/arm/startup_stm32g070xx.s b/Source/Templates/arm/startup_stm32g070xx.s
index b93a65b..33c8d63 100644
--- a/Source/Templates/arm/startup_stm32g070xx.s
+++ b/Source/Templates/arm/startup_stm32g070xx.s
@@ -238,5 +238,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g071xx.s b/Source/Templates/arm/startup_stm32g071xx.s
index c10f454..c1beb8a 100644
--- a/Source/Templates/arm/startup_stm32g071xx.s
+++ b/Source/Templates/arm/startup_stm32g071xx.s
@@ -247,5 +247,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g081xx.s b/Source/Templates/arm/startup_stm32g081xx.s
index 19744c5..fc54764 100644
--- a/Source/Templates/arm/startup_stm32g081xx.s
+++ b/Source/Templates/arm/startup_stm32g081xx.s
@@ -250,5 +250,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g0b0xx.s b/Source/Templates/arm/startup_stm32g0b0xx.s
index 2fae8c1..015f008 100644
--- a/Source/Templates/arm/startup_stm32g0b0xx.s
+++ b/Source/Templates/arm/startup_stm32g0b0xx.s
@@ -240,5 +240,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g0b1xx.s b/Source/Templates/arm/startup_stm32g0b1xx.s
index aa88485..677e103 100644
--- a/Source/Templates/arm/startup_stm32g0b1xx.s
+++ b/Source/Templates/arm/startup_stm32g0b1xx.s
@@ -247,5 +247,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g0c1xx.s b/Source/Templates/arm/startup_stm32g0c1xx.s
index f357825..086a44d 100644
--- a/Source/Templates/arm/startup_stm32g0c1xx.s
+++ b/Source/Templates/arm/startup_stm32g0c1xx.s
@@ -250,5 +250,3 @@
ENDIF
END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/gcc/startup_stm32g030xx.s b/Source/Templates/gcc/startup_stm32g030xx.s
index bb9c15d..fd82f10 100644
--- a/Source/Templates/gcc/startup_stm32g030xx.s
+++ b/Source/Templates/gcc/startup_stm32g030xx.s
@@ -268,6 +268,3 @@
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g031xx.s b/Source/Templates/gcc/startup_stm32g031xx.s
index 863c5da..51c922b 100644
--- a/Source/Templates/gcc/startup_stm32g031xx.s
+++ b/Source/Templates/gcc/startup_stm32g031xx.s
@@ -284,6 +284,3 @@
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g041xx.s b/Source/Templates/gcc/startup_stm32g041xx.s
index 8c48c16..af33433 100644
--- a/Source/Templates/gcc/startup_stm32g041xx.s
+++ b/Source/Templates/gcc/startup_stm32g041xx.s
@@ -288,6 +288,3 @@
.weak AES_RNG_IRQHandler
.thumb_set AES_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g050xx.s b/Source/Templates/gcc/startup_stm32g050xx.s
index 72fdd62..b117023 100644
--- a/Source/Templates/gcc/startup_stm32g050xx.s
+++ b/Source/Templates/gcc/startup_stm32g050xx.s
@@ -276,6 +276,3 @@
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g051xx.s b/Source/Templates/gcc/startup_stm32g051xx.s
index 7a1ef49..0247c61 100644
--- a/Source/Templates/gcc/startup_stm32g051xx.s
+++ b/Source/Templates/gcc/startup_stm32g051xx.s
@@ -286,6 +286,3 @@
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g061xx.s b/Source/Templates/gcc/startup_stm32g061xx.s
index b52b406..42f896b 100644
--- a/Source/Templates/gcc/startup_stm32g061xx.s
+++ b/Source/Templates/gcc/startup_stm32g061xx.s
@@ -291,6 +291,3 @@
.weak AES_RNG_IRQHandler
.thumb_set AES_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g070xx.s b/Source/Templates/gcc/startup_stm32g070xx.s
index ee179a4..7dfdd84 100644
--- a/Source/Templates/gcc/startup_stm32g070xx.s
+++ b/Source/Templates/gcc/startup_stm32g070xx.s
@@ -280,6 +280,3 @@
.weak USART3_4_IRQHandler
.thumb_set USART3_4_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g071xx.s b/Source/Templates/gcc/startup_stm32g071xx.s
index 8e2bbfa..5b4d4d8 100644
--- a/Source/Templates/gcc/startup_stm32g071xx.s
+++ b/Source/Templates/gcc/startup_stm32g071xx.s
@@ -293,6 +293,3 @@
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g081xx.s b/Source/Templates/gcc/startup_stm32g081xx.s
index 100a769..e4ee41b 100644
--- a/Source/Templates/gcc/startup_stm32g081xx.s
+++ b/Source/Templates/gcc/startup_stm32g081xx.s
@@ -297,6 +297,3 @@
.weak AES_RNG_IRQHandler
.thumb_set AES_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g0b0xx.s b/Source/Templates/gcc/startup_stm32g0b0xx.s
index 25ed54f..a32177c 100644
--- a/Source/Templates/gcc/startup_stm32g0b0xx.s
+++ b/Source/Templates/gcc/startup_stm32g0b0xx.s
@@ -283,6 +283,3 @@
.weak USART3_4_5_6_IRQHandler
.thumb_set USART3_4_5_6_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g0b1xx.s b/Source/Templates/gcc/startup_stm32g0b1xx.s
index ac06034..7bf683a 100644
--- a/Source/Templates/gcc/startup_stm32g0b1xx.s
+++ b/Source/Templates/gcc/startup_stm32g0b1xx.s
@@ -293,6 +293,3 @@
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/gcc/startup_stm32g0c1xx.s b/Source/Templates/gcc/startup_stm32g0c1xx.s
index 29458c8..0fd5896 100644
--- a/Source/Templates/gcc/startup_stm32g0c1xx.s
+++ b/Source/Templates/gcc/startup_stm32g0c1xx.s
@@ -297,6 +297,3 @@
.weak AES_RNG_IRQHandler
.thumb_set AES_RNG_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Source/Templates/iar/startup_stm32g030xx.s b/Source/Templates/iar/startup_stm32g030xx.s
index 0d88c7e..cfd22fe 100644
--- a/Source/Templates/iar/startup_stm32g030xx.s
+++ b/Source/Templates/iar/startup_stm32g030xx.s
@@ -257,4 +257,3 @@
B USART2_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g031xx.s b/Source/Templates/iar/startup_stm32g031xx.s
index 7c375cb..2b1fdfe 100644
--- a/Source/Templates/iar/startup_stm32g031xx.s
+++ b/Source/Templates/iar/startup_stm32g031xx.s
@@ -282,4 +282,3 @@
B LPUART1_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g041xx.s b/Source/Templates/iar/startup_stm32g041xx.s
index a4f9416..0383a12 100644
--- a/Source/Templates/iar/startup_stm32g041xx.s
+++ b/Source/Templates/iar/startup_stm32g041xx.s
@@ -287,4 +287,3 @@
B AES_RNG_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g050xx.s b/Source/Templates/iar/startup_stm32g050xx.s
index bf82a70..7870b3c 100644
--- a/Source/Templates/iar/startup_stm32g050xx.s
+++ b/Source/Templates/iar/startup_stm32g050xx.s
@@ -272,4 +272,3 @@
B USART2_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g051xx.s b/Source/Templates/iar/startup_stm32g051xx.s
index 95e67c3..8ade8fc 100644
--- a/Source/Templates/iar/startup_stm32g051xx.s
+++ b/Source/Templates/iar/startup_stm32g051xx.s
@@ -287,4 +287,3 @@
B LPUART1_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g061xx.s b/Source/Templates/iar/startup_stm32g061xx.s
index 4f3d98e..f391cae 100644
--- a/Source/Templates/iar/startup_stm32g061xx.s
+++ b/Source/Templates/iar/startup_stm32g061xx.s
@@ -292,4 +292,3 @@
B AES_RNG_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g070xx.s b/Source/Templates/iar/startup_stm32g070xx.s
index 80f7184..92c3121 100644
--- a/Source/Templates/iar/startup_stm32g070xx.s
+++ b/Source/Templates/iar/startup_stm32g070xx.s
@@ -275,4 +275,3 @@
B USART3_4_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g071xx.s b/Source/Templates/iar/startup_stm32g071xx.s
index c139ef6..4e6993a 100644
--- a/Source/Templates/iar/startup_stm32g071xx.s
+++ b/Source/Templates/iar/startup_stm32g071xx.s
@@ -296,4 +296,3 @@
B CEC_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g081xx.s b/Source/Templates/iar/startup_stm32g081xx.s
index 099f08b..47aa87e 100644
--- a/Source/Templates/iar/startup_stm32g081xx.s
+++ b/Source/Templates/iar/startup_stm32g081xx.s
@@ -302,4 +302,3 @@
B AES_RNG_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g0b0xx.s b/Source/Templates/iar/startup_stm32g0b0xx.s
index 1cb3bdf..1398738 100644
--- a/Source/Templates/iar/startup_stm32g0b0xx.s
+++ b/Source/Templates/iar/startup_stm32g0b0xx.s
@@ -280,4 +280,3 @@
B USART3_4_5_6_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g0b1xx.s b/Source/Templates/iar/startup_stm32g0b1xx.s
index 56abb5a..853fec0 100644
--- a/Source/Templates/iar/startup_stm32g0b1xx.s
+++ b/Source/Templates/iar/startup_stm32g0b1xx.s
@@ -296,4 +296,3 @@
B CEC_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/iar/startup_stm32g0c1xx.s b/Source/Templates/iar/startup_stm32g0c1xx.s
index b9e6d3d..c3adbbe 100644
--- a/Source/Templates/iar/startup_stm32g0c1xx.s
+++ b/Source/Templates/iar/startup_stm32g0c1xx.s
@@ -302,4 +302,3 @@
B AES_RNG_IRQHandler
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/system_stm32g0xx.c b/Source/Templates/system_stm32g0xx.c
index 368439a..d4ca437 100644
--- a/Source/Templates/system_stm32g0xx.c
+++ b/Source/Templates/system_stm32g0xx.c
@@ -300,5 +300,3 @@
/**
* @}
*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st.css
index 71fbc14..eb41d56 100644
--- a/_htmresc/mini-st.css
+++ b/_htmresc/mini-st.css
@@ -1463,7 +1463,7 @@
/*
Definitions for progress elements and spinners.
*/
-/* Progess module CSS variable definitions */
+/* Progress module CSS variable definitions */
:root {
--progress-back-color: #ddd;
--progress-fore-color: #555; }
