Release v1.2.2
diff --git a/Include/stm32g431xx.h b/Include/stm32g431xx.h
index 100406b..7be3c23 100644
--- a/Include/stm32g431xx.h
+++ b/Include/stm32g431xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -912,6 +911,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1189,6 +1192,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -13125,4 +13137,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g441xx.h b/Include/stm32g441xx.h
index a1e3d44..5bc32fa 100644
--- a/Include/stm32g441xx.h
+++ b/Include/stm32g441xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -944,6 +943,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1223,6 +1226,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -13357,4 +13369,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g471xx.h b/Include/stm32g471xx.h
index 9a3fe22..a9f3457 100644
--- a/Include/stm32g471xx.h
+++ b/Include/stm32g471xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -125,7 +124,6 @@
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
@@ -141,6 +139,10 @@
COMP4_IRQn = 65, /*!< COMP4 */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
+ TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
+ TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
+ TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
+ TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */
@@ -967,6 +969,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1002,7 +1008,6 @@
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
@@ -1052,6 +1057,7 @@
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
+#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
@@ -1144,7 +1150,6 @@
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
@@ -1192,6 +1197,7 @@
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
+#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
@@ -1277,6 +1283,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -2928,9 +2943,6 @@
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
-#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
-#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
@@ -2980,6 +2992,9 @@
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
+#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
+#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
+#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
/******************************************************************************/
/* */
@@ -8101,9 +8116,6 @@
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
-#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
-#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
-#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
@@ -8192,6 +8204,9 @@
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_TIM20RST_Pos (20U)
+#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
+#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
@@ -8272,9 +8287,6 @@
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
-#define RCC_APB1ENR1_TIM5EN_Pos (3U)
-#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
-#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
@@ -8369,6 +8381,9 @@
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_TIM20EN_Pos (20U)
+#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
+#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
@@ -8458,9 +8473,6 @@
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
-#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
-#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
-#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
@@ -8555,6 +8567,9 @@
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
+#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
+#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
+#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
@@ -13396,122 +13411,127 @@
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM5))
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15))
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
@@ -13541,12 +13561,6 @@
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
- (((INSTANCE) == TIM5) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
@@ -13563,7 +13577,15 @@
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
- (((CHANNEL) == TIM_CHANNEL_1))))
+ (((CHANNEL) == TIM_CHANNEL_1))) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4) || \
+ ((CHANNEL) == TIM_CHANNEL_5) || \
+ ((CHANNEL) == TIM_CHANNEL_6))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
@@ -13586,135 +13608,143 @@
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
- ((CHANNEL) == TIM_CHANNEL_1)))
+ ((CHANNEL) == TIM_CHANNEL_1)) \
+ || \
+ (((INSTANCE) == TIM20) && \
+ (((CHANNEL) == TIM_CHANNEL_1) || \
+ ((CHANNEL) == TIM_CHANNEL_2) || \
+ ((CHANNEL) == TIM_CHANNEL_3) || \
+ ((CHANNEL) == TIM_CHANNEL_4))))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15))
+ ((INSTANCE) == TIM15)|| \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15))
+ ((INSTANCE) == TIM15)|| \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15))
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15))
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15))
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
@@ -13723,51 +13753,54 @@
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM8))
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
- ((INSTANCE) == TIM15))
+ ((INSTANCE) == TIM15) || \
+ ((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
- ((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
- ((INSTANCE) == TIM17))
+ ((INSTANCE) == TIM17) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM8))
-
+ ((INSTANCE) == TIM8) || \
+ ((INSTANCE) == TIM20))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
@@ -13907,4 +13940,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g473xx.h b/Include/stm32g473xx.h
index 3d33331..0b53c56 100644
--- a/Include/stm32g473xx.h
+++ b/Include/stm32g473xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1009,6 +1008,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1358,6 +1361,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -14535,4 +14547,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g474xx.h b/Include/stm32g474xx.h
index 4656379..e32fb9e 100644
--- a/Include/stm32g474xx.h
+++ b/Include/stm32g474xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1492,6 +1491,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -8047,6 +8055,8 @@
#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
+
+/* Slave Timer A reset enable bits upon other slave timers events */
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
@@ -8056,6 +8066,7 @@
#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
@@ -8065,6 +8076,7 @@
#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
@@ -8074,6 +8086,7 @@
#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
#define HRTIM_RSTR_TIMECMP1_Pos (28U)
#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
@@ -8083,10 +8096,236 @@
#define HRTIM_RSTR_TIMECMP4_Pos (30U)
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
#define HRTIM_RSTR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
+#define HRTIM_RSTBR_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTBR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTBR_TIMFCMP2 HRTIM_RSTBR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
+#define HRTIM_RSTCR_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTCR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTCR_TIMFCMP2 HRTIM_RSTCR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
+#define HRTIM_RSTDR_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTDR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTDR_TIMFCMP2 HRTIM_RSTDR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTER_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTER_TIMFCMP2_Msk (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTER_TIMFCMP2 HRTIM_RSTER_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer F reset enable bits upon other slave timers events */
+#define HRTIM_RSTFR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTFR_TIMACMP1_Msk (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTFR_TIMACMP1 HRTIM_RSTFR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTFR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTFR_TIMACMP2_Msk (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTFR_TIMACMP2 HRTIM_RSTFR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTFR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTFR_TIMACMP4_Msk (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTFR_TIMACMP4 HRTIM_RSTFR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTFR_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTFR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTFR_TIMBCMP1 HRTIM_RSTFR_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTFR_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTFR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTFR_TIMBCMP2 HRTIM_RSTFR_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTFR_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTFR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTFR_TIMBCMP4 HRTIM_RSTFR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTFR_TIMCCMP1_Pos (25U)
+#define HRTIM_RSTFR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTFR_TIMCCMP1 HRTIM_RSTFR_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTFR_TIMCCMP2_Pos (26U)
+#define HRTIM_RSTFR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTFR_TIMCCMP2 HRTIM_RSTFR_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTFR_TIMCCMP4_Pos (27U)
+#define HRTIM_RSTFR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTFR_TIMCCMP4 HRTIM_RSTFR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTFR_TIMDCMP1_Pos (28U)
+#define HRTIM_RSTFR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTFR_TIMDCMP1 HRTIM_RSTFR_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTFR_TIMDCMP2_Pos (29U)
+#define HRTIM_RSTFR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTFR_TIMDCMP2 HRTIM_RSTFR_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTFR_TIMDCMP4_Pos (30U)
+#define HRTIM_RSTFR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTFR_TIMDCMP4 HRTIM_RSTFR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTFR_TIMECMP2_Pos (31U)
+#define HRTIM_RSTFR_TIMECMP2_Msk (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTFR_TIMECMP2 HRTIM_RSTFR_TIMECMP2_Msk /*!< Timer E compare 2 */
+
/**** Bit definition for Slave Timer Chopper register *************************/
#define HRTIM_CHPR_CARFRQ_Pos (0U)
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
@@ -17889,4 +18128,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g483xx.h b/Include/stm32g483xx.h
index c1bf5ab..9300cf2 100644
--- a/Include/stm32g483xx.h
+++ b/Include/stm32g483xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1041,6 +1040,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1392,6 +1395,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -14767,4 +14779,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g484xx.h b/Include/stm32g484xx.h
index 402b8e3..9687b01 100644
--- a/Include/stm32g484xx.h
+++ b/Include/stm32g484xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1526,6 +1525,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -8268,6 +8276,8 @@
#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
+
+/* Slave Timer A reset enable bits upon other slave timers events */
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
@@ -8277,6 +8287,7 @@
#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
@@ -8286,6 +8297,7 @@
#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
@@ -8295,6 +8307,7 @@
#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
#define HRTIM_RSTR_TIMECMP1_Pos (28U)
#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
@@ -8304,10 +8317,236 @@
#define HRTIM_RSTR_TIMECMP4_Pos (30U)
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
#define HRTIM_RSTR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
+#define HRTIM_RSTBR_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTBR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTBR_TIMFCMP2 HRTIM_RSTBR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
+#define HRTIM_RSTCR_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTCR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTCR_TIMFCMP2 HRTIM_RSTCR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
+
+#define HRTIM_RSTDR_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTDR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTDR_TIMFCMP2 HRTIM_RSTDR_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTER_TIMFCMP2_Pos (31U)
+#define HRTIM_RSTER_TIMFCMP2_Msk (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTER_TIMFCMP2 HRTIM_RSTER_TIMFCMP2_Msk /*!< Timer F compare 2 */
+
+/* Slave Timer F reset enable bits upon other slave timers events */
+#define HRTIM_RSTFR_TIMACMP1_Pos (19U)
+#define HRTIM_RSTFR_TIMACMP1_Msk (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos) /*!< 0x00080000 */
+#define HRTIM_RSTFR_TIMACMP1 HRTIM_RSTFR_TIMACMP1_Msk /*!< Timer A compare 1 */
+#define HRTIM_RSTFR_TIMACMP2_Pos (20U)
+#define HRTIM_RSTFR_TIMACMP2_Msk (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos) /*!< 0x00100000 */
+#define HRTIM_RSTFR_TIMACMP2 HRTIM_RSTFR_TIMACMP2_Msk /*!< Timer A compare 2 */
+#define HRTIM_RSTFR_TIMACMP4_Pos (21U)
+#define HRTIM_RSTFR_TIMACMP4_Msk (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos) /*!< 0x00200000 */
+#define HRTIM_RSTFR_TIMACMP4 HRTIM_RSTFR_TIMACMP4_Msk /*!< Timer A compare 4 */
+
+#define HRTIM_RSTFR_TIMBCMP1_Pos (22U)
+#define HRTIM_RSTFR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos) /*!< 0x00400000 */
+#define HRTIM_RSTFR_TIMBCMP1 HRTIM_RSTFR_TIMBCMP1_Msk /*!< Timer B compare 1 */
+#define HRTIM_RSTFR_TIMBCMP2_Pos (23U)
+#define HRTIM_RSTFR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos) /*!< 0x00800000 */
+#define HRTIM_RSTFR_TIMBCMP2 HRTIM_RSTFR_TIMBCMP2_Msk /*!< Timer B compare 2 */
+#define HRTIM_RSTFR_TIMBCMP4_Pos (24U)
+#define HRTIM_RSTFR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos) /*!< 0x01000000 */
+#define HRTIM_RSTFR_TIMBCMP4 HRTIM_RSTFR_TIMBCMP4_Msk /*!< Timer B compare 4 */
+
+#define HRTIM_RSTFR_TIMCCMP1_Pos (25U)
+#define HRTIM_RSTFR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos) /*!< 0x02000000 */
+#define HRTIM_RSTFR_TIMCCMP1 HRTIM_RSTFR_TIMCCMP1_Msk /*!< Timer C compare 1 */
+#define HRTIM_RSTFR_TIMCCMP2_Pos (26U)
+#define HRTIM_RSTFR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos) /*!< 0x04000000 */
+#define HRTIM_RSTFR_TIMCCMP2 HRTIM_RSTFR_TIMCCMP2_Msk /*!< Timer C compare 2 */
+#define HRTIM_RSTFR_TIMCCMP4_Pos (27U)
+#define HRTIM_RSTFR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos) /*!< 0x08000000 */
+#define HRTIM_RSTFR_TIMCCMP4 HRTIM_RSTFR_TIMCCMP4_Msk /*!< Timer C compare 4 */
+
+#define HRTIM_RSTFR_TIMDCMP1_Pos (28U)
+#define HRTIM_RSTFR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos) /*!< 0x10000000 */
+#define HRTIM_RSTFR_TIMDCMP1 HRTIM_RSTFR_TIMDCMP1_Msk /*!< Timer D compare 1 */
+#define HRTIM_RSTFR_TIMDCMP2_Pos (29U)
+#define HRTIM_RSTFR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos) /*!< 0x20000000 */
+#define HRTIM_RSTFR_TIMDCMP2 HRTIM_RSTFR_TIMDCMP2_Msk /*!< Timer D compare 2 */
+#define HRTIM_RSTFR_TIMDCMP4_Pos (30U)
+#define HRTIM_RSTFR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos) /*!< 0x40000000 */
+#define HRTIM_RSTFR_TIMDCMP4 HRTIM_RSTFR_TIMDCMP4_Msk /*!< Timer D compare 4 */
+
+#define HRTIM_RSTFR_TIMECMP2_Pos (31U)
+#define HRTIM_RSTFR_TIMECMP2_Msk (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos) /*!< 0x80000000 */
+#define HRTIM_RSTFR_TIMECMP2 HRTIM_RSTFR_TIMECMP2_Msk /*!< Timer E compare 2 */
+
/**** Bit definition for Slave Timer Chopper register *************************/
#define HRTIM_CHPR_CARFRQ_Pos (0U)
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
@@ -18121,4 +18360,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g491xx.h b/Include/stm32g491xx.h
index f5927aa..ca9874b 100644
--- a/Include/stm32g491xx.h
+++ b/Include/stm32g491xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -961,6 +960,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1269,6 +1272,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -13699,4 +13711,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g4a1xx.h b/Include/stm32g4a1xx.h
index feae9f2..2fb6e6f 100644
--- a/Include/stm32g4a1xx.h
+++ b/Include/stm32g4a1xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -993,6 +992,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1303,6 +1306,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -13931,4 +13943,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32g4xx.h b/Include/stm32g4xx.h
index 65d3559..144aa60 100644
--- a/Include/stm32g4xx.h
+++ b/Include/stm32g4xx.h
@@ -16,13 +16,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -85,11 +84,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.1
+ * @brief CMSIS Device version number V1.2.2
*/
#define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
-#define __STM32G4_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32G4_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\
|(__STM32G4_CMSIS_VERSION_SUB1 << 16)\
@@ -178,6 +177,61 @@
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
/**
* @}
@@ -203,4 +257,3 @@
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32gbk1cb.h b/Include/stm32gbk1cb.h
index 7678172..a9d8cf0 100644
--- a/Include/stm32gbk1cb.h
+++ b/Include/stm32gbk1cb.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -902,6 +901,10 @@
} UCPD_TypeDef;
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_memory_map
* @{
*/
@@ -1175,6 +1178,15 @@
* @{
*/
+ /** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+ /**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -13063,4 +13075,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/system_stm32g4xx.h b/Include/system_stm32g4xx.h
index b79a9b6..ed341a8 100644
--- a/Include/system_stm32g4xx.h
+++ b/Include/system_stm32g4xx.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -103,4 +102,3 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/License.md b/License.md
index e0d829b..48dcd96 100644
--- a/License.md
+++ b/License.md
@@ -68,7 +68,7 @@
APPENDIX:
- Copyright [2019] [STMicroelectronics]
+ Copyright 2019 STMicroelectronics
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/README.md b/README.md
index 23e465c..4816c86 100644
--- a/README.md
+++ b/README.md
@@ -2,18 +2,18 @@
## Overview
-**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost.
+**STM32Cube** is an STMicroelectronics original initiative to ease developers' life by reducing efforts, time and cost.
-**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series.
- * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product
- * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio
- * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series
- * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ...
- * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series
+**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
+ * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
+ * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
+ * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
+ * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
+ * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
-Two models of publication are proposed for the STM32Cube embedded software :
- * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series)
- * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions.
+Two models of publication are proposed for the STM32Cube embedded software:
+ * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series).
+ * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions.
## Description
@@ -34,10 +34,10 @@
Tag v1.1.1 | Tag v5.4.0_cm4 | Tag v1.2.0
Tag v1.2.0 | Tag v5.6.0_cm4 | Tag v1.3.0
Tag v1.2.1 | Tag v5.6.0_cm4 | Tag v1.4.0
+Tag v1.2.2 | Tag v5.6.0_cm4 | Tag v1.5.0
The full **STM32CubeG4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG4).
## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_g4/issues/new).
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
+Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
diff --git a/Release_Notes.html b/Release_Notes.html
index 10c8b81..7ce5d11 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -29,9 +29,6 @@
</center>
</div>
</div>
-<h1 id="license">License</h1>
-<p>This software component is licensed by ST under Apache 2.0 license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
-<p><a href="https://opensource.org/licenses/Apache-2.0">https://opensource.org/licenses/Apache-2.0</a></p>
<h1 id="purpose">Purpose</h1>
<p>This driver provides the CMSIS device for the stm32g4xx products. This covers following series :</p>
<ul>
@@ -51,12 +48,12 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true">V1.2.1 / 11-January-2021</label>
+<input type="checkbox" id="collapse-section1_2_2" checked aria-hidden="true"> <label for="collapse-section1_2_2" aria-hidden="true">V1.2.2 / 10-November-2021</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<ul>
-<li>General updates to fix known defects and enhancements implementation</li>
+<li>General updates to fix known defects and enhancements implementation.</li>
</ul>
<h2 id="contents">Contents</h2>
<table>
@@ -72,20 +69,81 @@
<td>- General updates to fix known defects and enhancements implementation.</td>
</tr>
<tr class="even">
+<td>- All source files: update disclaimer to add reference to the new license agreement.</td>
+</tr>
+<tr class="odd">
+<td>- Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</td>
+</tr>
+<tr class="even">
+<td>- Add reset enable bits definitions for slave timers other than timer A.</td>
+</tr>
+<tr class="odd">
+<td>- Fix Doxygen grouping issues.</td>
+</tr>
+<tr class="even">
+<td>- Add new atomic register access macros in stm32g4xx.h file.</td>
+</tr>
+<tr class="odd">
+<td>- Remove extra TIM5 references in the stm32g471xx.h CMSIS file and add support to the TIM20.</td>
+</tr>
+</tbody>
+</table>
+<p>: Fixed bugs list<br />
+</p>
+<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-Link</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-Link</li>
+<li>CubeIDE toolchain V1.6.0</li>
+</ul>
+<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<ul>
+<li>STM32G431xx, STM32G441xx devices</li>
+<li>STM32G471xx devices</li>
+<li>STM32G473xx, STM32G483xx devices</li>
+<li>STM32G474xx, STM32G484xx devices</li>
+<li>STM32G491xx, STM32G4A1xx devices</li>
+</ul>
+<p>Note: in the section above, main changes are highlighted in <strong>bold</strong> since previous release.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true">V1.2.1 / 11-January-2021</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-1">Maintenance release</h3>
+<ul>
+<li>General updates to fix known defects and enhancements implementation</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<table>
+<caption>Additional features<br />
+</caption>
+<thead>
+<tr class="header">
+<th>Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td>- General updates to fix known defects and enhancements implementation.</td>
+</tr>
+<tr class="even">
<td>- Protect Vector table modification following SRAM or FLASH preprocessor directive by a generic preprocessor directive: USER_VECT_TAB_ADDRESS.</td>
</tr>
</tbody>
</table>
<p>: Fixed bugs list<br />
</p>
-<h2 id="known-limitations">Known Limitations</h2>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.50.4</strong> + ST-Link</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.31</strong> + ST-Link</li>
<li>CubeIDE toolchain <strong>V1.6.0</strong></li>
</ul>
-<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
<ul>
<li>STM32G431xx, STM32G441xx devices</li>
<li>STM32G471xx devices</li>
@@ -99,13 +157,13 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true">V1.2.0 / 26-June-2020</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance release</h3>
+<h2 id="main-changes-2">Main Changes</h2>
+<h3 id="maintenance-release-2">Maintenance release</h3>
<ul>
<li>Add support for STM32G491xx and STM32G4A1 devices</li>
<li>General updates to fix known defects and enhancements implementation</li>
</ul>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<table>
<caption>Additional features<br />
</caption>
@@ -131,14 +189,14 @@
</table>
<p>: Fixed bugs list<br />
</p>
-<h2 id="known-limitations-1">Known Limitations</h2>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.40.1</strong></li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
<li>STM32CubeIDE toolchain V1.3.0</li>
</ul>
-<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
<ul>
<li>STM32G431xx, STM32G441xx devices</li>
<li>STM32G471xx devices</li>
@@ -152,10 +210,10 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_1" aria-hidden="true"> <label for="collapse-section1_1_1" aria-hidden="true">V1.1.1 / 14-February-2020</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance release</h3>
+<h2 id="main-changes-3">Main Changes</h2>
+<h3 id="maintenance-release-3">Maintenance release</h3>
<p>General updates to fix known defects and enhancements implementation</p>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<table>
<caption>Additional features<br />
</caption>
@@ -187,14 +245,14 @@
</tr>
</tbody>
</table>
-<h2 id="known-limitations-2">Known Limitations</h2>
-<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
<li>STM32CubeIDE toolchain V1.3.0</li>
</ul>
-<h2 id="supported-devices-and-boards-2">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
<ul>
<li>STM32G431xx, STM32G441xx devices</li>
<li>STM32G471xx devices</li>
@@ -207,10 +265,10 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true">V1.1.0 / 28-June-2019</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance release</h3>
+<h2 id="main-changes-4">Main Changes</h2>
+<h3 id="maintenance-release-4">Maintenance release</h3>
<p>Maintenance release of CMSIS Devices drivers supporting STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, <strong>STM32G483xx</strong>, STM32G474xx and STM32G484xx devices</p>
-<h2 id="contents-3">Contents</h2>
+<h2 id="contents-4">Contents</h2>
<table>
<caption>Additional features<br />
</caption>
@@ -251,14 +309,14 @@
</tr>
</tbody>
</table>
-<h2 id="known-limitations-3">Known Limitations</h2>
-<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards-3">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
<ul>
<li>STM32G431xx, STM32G441xx devices</li>
<li>STM32G471xx devices</li>
@@ -271,12 +329,12 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true">V1.0.0 / 12-April-2019</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release for STM32G4xx devices</p>
-<h2 id="contents-4">Contents</h2>
+<h2 id="contents-5">Contents</h2>
<p>CMSIS devices files for STM32G431xx, STM32G441xx, STM32G471xx, STM32G473xx, STM32G474xx and STM32G484xx.</p>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
<table>
<thead>
<tr class="header">
@@ -289,13 +347,13 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-and-boards-4">Supported Devices and boards</h2>
+<h2 id="supported-devices-and-boards-5">Supported Devices and boards</h2>
<ul>
<li>STM32G431xx, STM32G441xx devices</li>
<li>STM32G471xx devices</li>
diff --git a/Source/Templates/arm/startup_stm32g431xx.s b/Source/Templates/arm/startup_stm32g431xx.s
index 3d52d2c..3ac4f31 100644
--- a/Source/Templates/arm/startup_stm32g431xx.s
+++ b/Source/Templates/arm/startup_stm32g431xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -422,4 +421,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g441xx.s b/Source/Templates/arm/startup_stm32g441xx.s
index e0dcabd..9c2c58f 100644
--- a/Source/Templates/arm/startup_stm32g441xx.s
+++ b/Source/Templates/arm/startup_stm32g441xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -424,4 +423,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g471xx.s b/Source/Templates/arm/startup_stm32g471xx.s
index 99faf6c..5f6bddc 100644
--- a/Source/Templates/arm/startup_stm32g471xx.s
+++ b/Source/Templates/arm/startup_stm32g471xx.s
@@ -17,14 +17,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -441,4 +440,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g473xx.s b/Source/Templates/arm/startup_stm32g473xx.s
index 6ed919b..bb01241 100644
--- a/Source/Templates/arm/startup_stm32g473xx.s
+++ b/Source/Templates/arm/startup_stm32g473xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -468,4 +467,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g474xx.s b/Source/Templates/arm/startup_stm32g474xx.s
index 7671bc2..50a8035 100644
--- a/Source/Templates/arm/startup_stm32g474xx.s
+++ b/Source/Templates/arm/startup_stm32g474xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -484,4 +483,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g483xx.s b/Source/Templates/arm/startup_stm32g483xx.s
index 7a123c8..babab19 100644
--- a/Source/Templates/arm/startup_stm32g483xx.s
+++ b/Source/Templates/arm/startup_stm32g483xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -470,4 +469,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g484xx.s b/Source/Templates/arm/startup_stm32g484xx.s
index c27ec15..d20ec44 100644
--- a/Source/Templates/arm/startup_stm32g484xx.s
+++ b/Source/Templates/arm/startup_stm32g484xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -486,4 +485,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g491xx.s b/Source/Templates/arm/startup_stm32g491xx.s
index fdf6b63..7a27395 100644
--- a/Source/Templates/arm/startup_stm32g491xx.s
+++ b/Source/Templates/arm/startup_stm32g491xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -448,4 +447,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32g4a1xx.s b/Source/Templates/arm/startup_stm32g4a1xx.s
index 1df6603..f4e4783 100644
--- a/Source/Templates/arm/startup_stm32g4a1xx.s
+++ b/Source/Templates/arm/startup_stm32g4a1xx.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -450,4 +449,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/arm/startup_stm32gbk1cb.s b/Source/Templates/arm/startup_stm32gbk1cb.s
index 2f8733c..7c6e290 100644
--- a/Source/Templates/arm/startup_stm32gbk1cb.s
+++ b/Source/Templates/arm/startup_stm32gbk1cb.s
@@ -16,14 +16,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
;
@@ -420,4 +419,3 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/Source/Templates/gcc/startup_stm32g431xx.s b/Source/Templates/gcc/startup_stm32g431xx.s
index be5cc3f..3397428 100644
--- a/Source/Templates/gcc/startup_stm32g431xx.s
+++ b/Source/Templates/gcc/startup_stm32g431xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -496,4 +495,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g441xx.s b/Source/Templates/gcc/startup_stm32g441xx.s
index dc621f9..11c3af1 100644
--- a/Source/Templates/gcc/startup_stm32g441xx.s
+++ b/Source/Templates/gcc/startup_stm32g441xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -499,4 +498,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g471xx.s b/Source/Templates/gcc/startup_stm32g471xx.s
index 918ebee..b9aa6de 100644
--- a/Source/Templates/gcc/startup_stm32g471xx.s
+++ b/Source/Templates/gcc/startup_stm32g471xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -523,4 +522,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g473xx.s b/Source/Templates/gcc/startup_stm32g473xx.s
index f59f3fc..3d7d8d6 100644
--- a/Source/Templates/gcc/startup_stm32g473xx.s
+++ b/Source/Templates/gcc/startup_stm32g473xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -565,4 +564,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g474xx.s b/Source/Templates/gcc/startup_stm32g474xx.s
index 2b39625..a6add31 100644
--- a/Source/Templates/gcc/startup_stm32g474xx.s
+++ b/Source/Templates/gcc/startup_stm32g474xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -589,4 +588,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g483xx.s b/Source/Templates/gcc/startup_stm32g483xx.s
index 797f3c8..8690d34 100644
--- a/Source/Templates/gcc/startup_stm32g483xx.s
+++ b/Source/Templates/gcc/startup_stm32g483xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -568,4 +567,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g484xx.s b/Source/Templates/gcc/startup_stm32g484xx.s
index be06404..9ec0f3c 100644
--- a/Source/Templates/gcc/startup_stm32g484xx.s
+++ b/Source/Templates/gcc/startup_stm32g484xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -591,4 +590,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g491xx.s b/Source/Templates/gcc/startup_stm32g491xx.s
index 9aff46c..9e3bf02 100644
--- a/Source/Templates/gcc/startup_stm32g491xx.s
+++ b/Source/Templates/gcc/startup_stm32g491xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -535,4 +534,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32g4a1xx.s b/Source/Templates/gcc/startup_stm32g4a1xx.s
index aa41389..163bf0b 100644
--- a/Source/Templates/gcc/startup_stm32g4a1xx.s
+++ b/Source/Templates/gcc/startup_stm32g4a1xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -538,4 +537,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/gcc/startup_stm32gbk1cb.s b/Source/Templates/gcc/startup_stm32gbk1cb.s
index f302f42..778cb46 100644
--- a/Source/Templates/gcc/startup_stm32gbk1cb.s
+++ b/Source/Templates/gcc/startup_stm32gbk1cb.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -489,4 +488,3 @@
.weak FMAC_IRQHandler
.thumb_set FMAC_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g431xx.s b/Source/Templates/iar/startup_stm32g431xx.s
index 4ff33e1..b8d1f30 100644
--- a/Source/Templates/iar/startup_stm32g431xx.s
+++ b/Source/Templates/iar/startup_stm32g431xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
; The modules in this file are included in the libraries, and may be replaced
@@ -584,4 +583,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g441xx.s b/Source/Templates/iar/startup_stm32g441xx.s
index 3ab795c..007371c 100644
--- a/Source/Templates/iar/startup_stm32g441xx.s
+++ b/Source/Templates/iar/startup_stm32g441xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -590,4 +589,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g471xx.s b/Source/Templates/iar/startup_stm32g471xx.s
index 8382f87..02958f5 100644
--- a/Source/Templates/iar/startup_stm32g471xx.s
+++ b/Source/Templates/iar/startup_stm32g471xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -630,4 +629,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g473xx.s b/Source/Templates/iar/startup_stm32g473xx.s
index 7340942..a140098 100644
--- a/Source/Templates/iar/startup_stm32g473xx.s
+++ b/Source/Templates/iar/startup_stm32g473xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -700,4 +699,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g474xx.s b/Source/Templates/iar/startup_stm32g474xx.s
index 3ad0882..bc4171d 100644
--- a/Source/Templates/iar/startup_stm32g474xx.s
+++ b/Source/Templates/iar/startup_stm32g474xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -740,4 +739,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g483xx.s b/Source/Templates/iar/startup_stm32g483xx.s
index 05b1e5b..b47c141 100644
--- a/Source/Templates/iar/startup_stm32g483xx.s
+++ b/Source/Templates/iar/startup_stm32g483xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -705,4 +704,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g484xx.s b/Source/Templates/iar/startup_stm32g484xx.s
index 5fc380b..04fe493 100644
--- a/Source/Templates/iar/startup_stm32g484xx.s
+++ b/Source/Templates/iar/startup_stm32g484xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -745,4 +744,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g491xx.s b/Source/Templates/iar/startup_stm32g491xx.s
index eebb100..a5c7904 100644
--- a/Source/Templates/iar/startup_stm32g491xx.s
+++ b/Source/Templates/iar/startup_stm32g491xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -650,4 +649,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32g4a1xx.s b/Source/Templates/iar/startup_stm32g4a1xx.s
index 47d7f0c..909d9ec 100644
--- a/Source/Templates/iar/startup_stm32g4a1xx.s
+++ b/Source/Templates/iar/startup_stm32g4a1xx.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -655,4 +654,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/iar/startup_stm32gbk1cb.s b/Source/Templates/iar/startup_stm32gbk1cb.s
index 6712b27..f27961e 100644
--- a/Source/Templates/iar/startup_stm32gbk1cb.s
+++ b/Source/Templates/iar/startup_stm32gbk1cb.s
@@ -15,14 +15,13 @@
;********************************************************************************
;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under BSD 3-Clause license,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/BSD-3-Clause
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
; The modules in this file are included in the libraries, and may be replaced
@@ -579,4 +578,3 @@
B FMAC_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Source/Templates/system_stm32g4xx.c b/Source/Templates/system_stm32g4xx.c
index 92fc662..922e57a 100644
--- a/Source/Templates/system_stm32g4xx.c
+++ b/Source/Templates/system_stm32g4xx.c
@@ -53,13 +53,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -283,5 +282,4 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/md2html.sh b/md2html.sh
deleted file mode 100644
index b996e7a..0000000
--- a/md2html.sh
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/bash
-
-# How to use Pandoc
-# To convert your existing HTML release notes into Markdown (useful to build your history), type the following command in your bash window:
- # pandoc --from html --to markdown Release_Notes.html > Release_Notes.md
-# To convert a .md file into an HTML one, type the following command in your bash window:
- # pandoc -s -r markdown -t html5 -c "_htmresc/mini-st.css" Release_Notes.md > Release_Notes.html
-
-pandoc -s -r markdown -t html5 -c "_htmresc/mini-st.css" Release_Notes.md > Release_Notes.html
-
-read -n1 -r -p "Press any key to continue..." key
