Release v1.10.3
diff --git a/Include/stm32h723xx.h b/Include/stm32h723xx.h index 65529a4..dfe7f0f 100644 --- a/Include/stm32h723xx.h +++ b/Include/stm32h723xx.h
@@ -4131,7 +4131,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6149,10 +6149,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6907,7 +6907,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6926,14 +6926,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7044,7 +7044,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7080,21 +7080,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7113,7 +7113,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7138,7 +7138,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7194,7 +7194,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7230,7 +7230,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7263,7 +7263,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7465,7 +7465,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7489,7 +7489,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7646,7 +7646,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7801,12 +7801,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8304,14 +8304,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8346,10 +8346,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8396,10 +8396,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8422,7 +8422,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8435,7 +8435,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8467,14 +8467,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8514,7 +8514,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8536,7 +8536,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8560,11 +8560,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8573,12 +8573,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8596,12 +8596,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -14593,7 +14593,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -14627,7 +14627,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -14649,7 +14649,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -14684,7 +14684,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -14706,7 +14706,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -14729,7 +14729,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -14749,7 +14749,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18136,10 +18136,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -18636,57 +18636,57 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -18704,56 +18704,56 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -18772,58 +18772,58 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -18841,55 +18841,55 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21464,7 +21464,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h725xx.h b/Include/stm32h725xx.h index 3fbdf5f..2a22964 100644 --- a/Include/stm32h725xx.h +++ b/Include/stm32h725xx.h
@@ -4132,7 +4132,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6150,10 +6150,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6908,7 +6908,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6927,14 +6927,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7045,7 +7045,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7081,21 +7081,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7114,7 +7114,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7139,7 +7139,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7195,7 +7195,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7231,7 +7231,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7264,7 +7264,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7466,7 +7466,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7490,7 +7490,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7647,7 +7647,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7802,12 +7802,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8305,14 +8305,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8347,10 +8347,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8397,10 +8397,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8423,7 +8423,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8436,7 +8436,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8468,14 +8468,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8515,7 +8515,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8537,7 +8537,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8561,11 +8561,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8574,12 +8574,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8597,12 +8597,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -14605,7 +14605,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -14639,7 +14639,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -14661,7 +14661,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -14696,7 +14696,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -14718,7 +14718,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -14741,7 +14741,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -14761,7 +14761,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18148,10 +18148,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -18648,57 +18648,57 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -18716,56 +18716,56 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -18784,58 +18784,58 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -18853,55 +18853,55 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21476,7 +21476,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h730xx.h b/Include/stm32h730xx.h index 1fd058d..ede15c5 100644 --- a/Include/stm32h730xx.h +++ b/Include/stm32h730xx.h
@@ -4266,7 +4266,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6044,7 +6044,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -6095,7 +6095,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6403,10 +6403,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -7161,7 +7161,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -7180,14 +7180,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7298,7 +7298,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7334,21 +7334,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7367,7 +7367,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7392,7 +7392,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7448,7 +7448,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7484,7 +7484,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7517,7 +7517,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7719,7 +7719,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7743,7 +7743,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7900,7 +7900,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -8055,12 +8055,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8558,14 +8558,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8600,10 +8600,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8650,10 +8650,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8676,7 +8676,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8689,7 +8689,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8721,14 +8721,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8768,7 +8768,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8790,7 +8790,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8814,11 +8814,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8827,12 +8827,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8850,12 +8850,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -15044,7 +15044,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -15078,7 +15078,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -15100,7 +15100,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -15135,7 +15135,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -15157,7 +15157,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -15180,7 +15180,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -15200,7 +15200,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18623,10 +18623,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -19123,57 +19123,57 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19191,56 +19191,56 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19259,58 +19259,58 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19328,55 +19328,55 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21951,7 +21951,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h730xxq.h b/Include/stm32h730xxq.h index 222189a..5ff323e 100644 --- a/Include/stm32h730xxq.h +++ b/Include/stm32h730xxq.h
@@ -4267,7 +4267,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6045,7 +6045,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -6096,7 +6096,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6404,10 +6404,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -7162,7 +7162,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -7181,14 +7181,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7299,7 +7299,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7335,21 +7335,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7368,7 +7368,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7393,7 +7393,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7449,7 +7449,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7485,7 +7485,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7518,7 +7518,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7720,7 +7720,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7744,7 +7744,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7901,7 +7901,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -8056,12 +8056,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8559,14 +8559,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8601,10 +8601,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8651,10 +8651,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8677,7 +8677,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8690,7 +8690,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8722,14 +8722,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8769,7 +8769,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8791,7 +8791,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8815,11 +8815,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8828,12 +8828,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8851,12 +8851,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -15056,7 +15056,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -15090,7 +15090,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -15112,7 +15112,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -15147,7 +15147,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -15169,7 +15169,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -15192,7 +15192,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -15212,7 +15212,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18635,10 +18635,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -19135,57 +19135,57 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19203,56 +19203,56 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19271,58 +19271,58 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19340,55 +19340,55 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21963,7 +21963,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h733xx.h b/Include/stm32h733xx.h index 0fc6704..ebc647f 100644 --- a/Include/stm32h733xx.h +++ b/Include/stm32h733xx.h
@@ -4266,7 +4266,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6044,7 +6044,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -6095,7 +6095,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6403,10 +6403,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -7161,7 +7161,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -7180,14 +7180,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7298,7 +7298,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7334,21 +7334,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7367,7 +7367,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7392,7 +7392,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7448,7 +7448,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7484,7 +7484,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7517,7 +7517,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7719,7 +7719,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7743,7 +7743,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7900,7 +7900,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -8055,12 +8055,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8558,14 +8558,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8600,10 +8600,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8650,10 +8650,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8676,7 +8676,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8689,7 +8689,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8721,14 +8721,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8768,7 +8768,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8790,7 +8790,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8814,11 +8814,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8827,12 +8827,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8850,12 +8850,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -15044,7 +15044,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -15078,7 +15078,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -15100,7 +15100,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -15135,7 +15135,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -15157,7 +15157,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -15180,7 +15180,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -15200,7 +15200,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18623,10 +18623,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -19123,57 +19123,57 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19191,56 +19191,56 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19259,58 +19259,58 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19328,55 +19328,55 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21951,7 +21951,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h735xx.h b/Include/stm32h735xx.h index d6db2f3..9e9515c 100644 --- a/Include/stm32h735xx.h +++ b/Include/stm32h735xx.h
@@ -4267,7 +4267,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6045,7 +6045,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -6096,7 +6096,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6404,10 +6404,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -7162,7 +7162,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -7181,14 +7181,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7299,7 +7299,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7335,21 +7335,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7368,7 +7368,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7393,7 +7393,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7449,7 +7449,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7485,7 +7485,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7518,7 +7518,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7720,7 +7720,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7744,7 +7744,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7901,7 +7901,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -8056,12 +8056,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8559,14 +8559,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8601,10 +8601,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8651,10 +8651,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8677,7 +8677,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8690,7 +8690,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8722,14 +8722,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8769,7 +8769,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8791,7 +8791,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8815,11 +8815,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8828,12 +8828,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8851,12 +8851,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -15056,7 +15056,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -15090,7 +15090,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -15112,7 +15112,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -15147,7 +15147,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -15169,7 +15169,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -15192,7 +15192,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -15212,7 +15212,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18635,10 +18635,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -19135,57 +19135,57 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19203,56 +19203,56 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19271,58 +19271,58 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19340,55 +19340,55 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21963,7 +21963,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h742xx.h b/Include/stm32h742xx.h index ae61fe5..38d5905 100644 --- a/Include/stm32h742xx.h +++ b/Include/stm32h742xx.h
@@ -3928,7 +3928,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5885,10 +5885,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6643,7 +6643,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6662,14 +6662,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -6780,7 +6780,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -6816,21 +6816,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -6849,7 +6849,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -6874,7 +6874,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -6930,7 +6930,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -6966,7 +6966,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -6999,7 +6999,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7201,7 +7201,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7225,7 +7225,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7382,7 +7382,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7537,12 +7537,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8040,14 +8040,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8082,10 +8082,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8132,10 +8132,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8158,7 +8158,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8171,7 +8171,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8203,14 +8203,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8250,7 +8250,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8272,7 +8272,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8296,11 +8296,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8309,12 +8309,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8332,12 +8332,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -13939,7 +13939,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -13973,7 +13973,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -13995,7 +13995,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -14030,7 +14030,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -14052,7 +14052,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -14075,7 +14075,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -14095,7 +14095,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -17426,10 +17426,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -17875,12 +17875,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -18155,61 +18156,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -18227,60 +18228,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -18299,62 +18300,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -18372,59 +18373,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -20392,7 +20393,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h743xx.h b/Include/stm32h743xx.h index cf2c2d3..3802024 100644 --- a/Include/stm32h743xx.h +++ b/Include/stm32h743xx.h
@@ -4023,7 +4023,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5980,10 +5980,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6738,7 +6738,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6757,14 +6757,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -6875,7 +6875,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -6911,21 +6911,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -6944,7 +6944,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -6969,7 +6969,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7025,7 +7025,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7061,7 +7061,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7094,7 +7094,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7296,7 +7296,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7320,7 +7320,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7477,7 +7477,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7632,12 +7632,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8135,14 +8135,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8177,10 +8177,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8227,10 +8227,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8253,7 +8253,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8266,7 +8266,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8298,14 +8298,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8345,7 +8345,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8367,7 +8367,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8391,11 +8391,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8404,12 +8404,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8427,12 +8427,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -14569,7 +14569,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -14603,7 +14603,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -14625,7 +14625,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -14660,7 +14660,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -14682,7 +14682,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -14705,7 +14705,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -14725,7 +14725,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18074,10 +18074,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -18523,12 +18523,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -18803,61 +18804,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -18875,60 +18876,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -18947,62 +18948,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19020,59 +19021,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21040,7 +21041,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h745xg.h b/Include/stm32h745xg.h index 654c8a7..d0d63dd 100644 --- a/Include/stm32h745xg.h +++ b/Include/stm32h745xg.h
@@ -4130,7 +4130,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6087,10 +6087,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6845,7 +6845,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6864,14 +6864,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -6982,7 +6982,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7018,21 +7018,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7051,7 +7051,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7076,7 +7076,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7132,7 +7132,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7168,7 +7168,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7201,7 +7201,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7403,7 +7403,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7427,7 +7427,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7584,7 +7584,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7739,12 +7739,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8242,14 +8242,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8284,10 +8284,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8334,10 +8334,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8360,7 +8360,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8373,7 +8373,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8405,14 +8405,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8452,7 +8452,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8474,7 +8474,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8498,11 +8498,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8511,12 +8511,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8534,12 +8534,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -15145,7 +15145,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -15179,7 +15179,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -15201,7 +15201,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -15236,7 +15236,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -15258,7 +15258,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -15281,7 +15281,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -15301,7 +15301,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18709,10 +18709,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -19158,12 +19158,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -19438,61 +19439,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19510,60 +19511,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19582,62 +19583,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19655,59 +19656,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_CM4L_Pos (0U) @@ -21702,7 +21703,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h745xx.h b/Include/stm32h745xx.h index daa5331..08a6183 100644 --- a/Include/stm32h745xx.h +++ b/Include/stm32h745xx.h
@@ -4130,7 +4130,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6087,10 +6087,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6845,7 +6845,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6864,14 +6864,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -6982,7 +6982,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7018,21 +7018,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7051,7 +7051,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7076,7 +7076,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7132,7 +7132,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7168,7 +7168,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7201,7 +7201,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7403,7 +7403,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7427,7 +7427,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7584,7 +7584,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7739,12 +7739,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8242,14 +8242,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8284,10 +8284,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8334,10 +8334,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8360,7 +8360,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8373,7 +8373,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8405,14 +8405,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8452,7 +8452,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8474,7 +8474,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8498,11 +8498,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8511,12 +8511,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8534,12 +8534,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -15145,7 +15145,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -15179,7 +15179,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -15201,7 +15201,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -15236,7 +15236,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -15258,7 +15258,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -15281,7 +15281,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -15301,7 +15301,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18709,10 +18709,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -19158,12 +19158,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -19438,61 +19439,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19510,60 +19511,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19582,62 +19583,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19655,59 +19656,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_CM4L_Pos (0U) @@ -21702,7 +21703,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h747xg.h b/Include/stm32h747xg.h index 2e86b2e..ba1e025 100644 --- a/Include/stm32h747xg.h +++ b/Include/stm32h747xg.h
@@ -4213,7 +4213,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6170,10 +6170,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6928,7 +6928,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6947,14 +6947,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7065,7 +7065,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7101,21 +7101,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7134,7 +7134,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7159,7 +7159,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7215,7 +7215,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7251,7 +7251,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7284,7 +7284,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7486,7 +7486,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7510,7 +7510,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7667,7 +7667,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7822,12 +7822,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8325,14 +8325,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8367,10 +8367,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8417,10 +8417,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8443,7 +8443,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8456,7 +8456,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8488,14 +8488,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8535,7 +8535,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8557,7 +8557,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8581,11 +8581,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8594,12 +8594,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8617,12 +8617,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -11024,13 +11024,13 @@ #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk /******************* Bit definition for DSI_TDCR register ***************/ -#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */ -#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U) -#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U) +#define DSI_TDCR_3DM (0x00000003U) /*!< 3D Mode */ +#define DSI_TDCR_3DM0 (0x00000001U) +#define DSI_TDCR_3DM1 (0x00000002U) -#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */ -#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U) -#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U) +#define DSI_TDCR_3DF (0x0000000CU) /*!< 3D Format */ +#define DSI_TDCR_3DF0 (0x00000004U) +#define DSI_TDCR_3DF1 (0x00000008U) #define DSI_TDCR_SVS_Pos (4U) #define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */ @@ -12200,13 +12200,13 @@ #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk /******************* Bit definition for DSI_TDCCR register **************/ -#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */ -#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U) -#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U) +#define DSI_TDCCR_3DM (0x00000003U) /*!< 3D Mode */ +#define DSI_TDCCR_3DM0 (0x00000001U) +#define DSI_TDCCR_3DM1 (0x00000002U) -#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */ -#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U) -#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U) +#define DSI_TDCCR_3DF (0x0000000CU) /*!< 3D Format */ +#define DSI_TDCCR_3DF0 (0x00000004U) +#define DSI_TDCCR_3DF1 (0x00000008U) #define DSI_TDCCR_SVS_Pos (4U) #define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */ @@ -18302,7 +18302,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -18336,7 +18336,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -18358,7 +18358,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -18393,7 +18393,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -18415,7 +18415,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -18438,7 +18438,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -18458,7 +18458,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -21882,10 +21882,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -22331,12 +22331,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -22611,61 +22612,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -22683,60 +22684,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -22755,62 +22756,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -22828,59 +22829,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_CM4L_Pos (0U) @@ -24875,7 +24876,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h747xx.h b/Include/stm32h747xx.h index 248396a..dd052c6 100644 --- a/Include/stm32h747xx.h +++ b/Include/stm32h747xx.h
@@ -4213,7 +4213,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6170,10 +6170,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6928,7 +6928,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6947,14 +6947,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7065,7 +7065,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7101,21 +7101,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7134,7 +7134,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7159,7 +7159,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7215,7 +7215,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7251,7 +7251,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7284,7 +7284,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7486,7 +7486,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7510,7 +7510,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7667,7 +7667,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7822,12 +7822,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8325,14 +8325,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8367,10 +8367,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8417,10 +8417,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8443,7 +8443,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8456,7 +8456,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8488,14 +8488,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8535,7 +8535,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8557,7 +8557,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8581,11 +8581,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8594,12 +8594,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8617,12 +8617,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -11024,13 +11024,13 @@ #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk /******************* Bit definition for DSI_TDCR register ***************/ -#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */ -#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U) -#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U) +#define DSI_TDCR_3DM (0x00000003U) /*!< 3D Mode */ +#define DSI_TDCR_3DM0 (0x00000001U) +#define DSI_TDCR_3DM1 (0x00000002U) -#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */ -#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U) -#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U) +#define DSI_TDCR_3DF (0x0000000CU) /*!< 3D Format */ +#define DSI_TDCR_3DF0 (0x00000004U) +#define DSI_TDCR_3DF1 (0x00000008U) #define DSI_TDCR_SVS_Pos (4U) #define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */ @@ -12200,13 +12200,13 @@ #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk /******************* Bit definition for DSI_TDCCR register **************/ -#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */ -#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U) -#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U) +#define DSI_TDCCR_3DM (0x00000003U) /*!< 3D Mode */ +#define DSI_TDCCR_3DM0 (0x00000001U) +#define DSI_TDCCR_3DM1 (0x00000002U) -#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */ -#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U) -#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U) +#define DSI_TDCCR_3DF (0x0000000CU) /*!< 3D Format */ +#define DSI_TDCCR_3DF0 (0x00000004U) +#define DSI_TDCCR_3DF1 (0x00000008U) #define DSI_TDCCR_SVS_Pos (4U) #define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */ @@ -18302,7 +18302,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -18336,7 +18336,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -18358,7 +18358,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -18393,7 +18393,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -18415,7 +18415,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -18438,7 +18438,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -18458,7 +18458,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -21882,10 +21882,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -22331,12 +22331,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -22611,61 +22612,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -22683,60 +22684,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -22755,62 +22756,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -22828,59 +22829,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_CM4L_Pos (0U) @@ -24875,7 +24876,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h750xx.h b/Include/stm32h750xx.h index f7d5a6a..b117c13 100644 --- a/Include/stm32h750xx.h +++ b/Include/stm32h750xx.h
@@ -4099,7 +4099,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5814,7 +5814,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -5865,7 +5865,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6173,10 +6173,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6931,7 +6931,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6950,14 +6950,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7068,7 +7068,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7104,21 +7104,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7137,7 +7137,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7162,7 +7162,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7218,7 +7218,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7254,7 +7254,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7287,7 +7287,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7489,7 +7489,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7513,7 +7513,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7670,7 +7670,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7825,12 +7825,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8328,14 +8328,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8370,10 +8370,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8420,10 +8420,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8446,7 +8446,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8459,7 +8459,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8491,14 +8491,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8538,7 +8538,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8560,7 +8560,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8584,11 +8584,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8597,12 +8597,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8620,12 +8620,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -14832,7 +14832,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -14866,7 +14866,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -14888,7 +14888,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -14923,7 +14923,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -14945,7 +14945,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -14968,7 +14968,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -14988,7 +14988,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18355,10 +18355,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -18804,12 +18804,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -19084,61 +19085,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19156,60 +19157,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19228,62 +19229,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19301,59 +19302,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21321,7 +21322,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h753xx.h b/Include/stm32h753xx.h index ffd9385..1bb6955 100644 --- a/Include/stm32h753xx.h +++ b/Include/stm32h753xx.h
@@ -4099,7 +4099,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5814,7 +5814,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -5865,7 +5865,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6173,10 +6173,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -6931,7 +6931,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -6950,14 +6950,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7068,7 +7068,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7104,21 +7104,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7137,7 +7137,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7162,7 +7162,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7218,7 +7218,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7254,7 +7254,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7287,7 +7287,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7489,7 +7489,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7513,7 +7513,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7670,7 +7670,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7825,12 +7825,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8328,14 +8328,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8370,10 +8370,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8420,10 +8420,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8446,7 +8446,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8459,7 +8459,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8491,14 +8491,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8538,7 +8538,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8560,7 +8560,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8584,11 +8584,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8597,12 +8597,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8620,12 +8620,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -14838,7 +14838,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -14872,7 +14872,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -14894,7 +14894,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -14929,7 +14929,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -14951,7 +14951,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -14974,7 +14974,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -14994,7 +14994,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18361,10 +18361,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -18810,12 +18810,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -19090,61 +19091,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19162,60 +19163,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19234,62 +19235,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19307,59 +19308,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -21327,7 +21328,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h755xx.h b/Include/stm32h755xx.h index a771cce..ffe28c5 100644 --- a/Include/stm32h755xx.h +++ b/Include/stm32h755xx.h
@@ -4206,7 +4206,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5921,7 +5921,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -5972,7 +5972,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6280,10 +6280,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -7038,7 +7038,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -7057,14 +7057,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7175,7 +7175,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7211,21 +7211,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7244,7 +7244,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7269,7 +7269,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7325,7 +7325,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7361,7 +7361,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7394,7 +7394,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7596,7 +7596,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7620,7 +7620,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7777,7 +7777,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -7932,12 +7932,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8435,14 +8435,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8477,10 +8477,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8527,10 +8527,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8553,7 +8553,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8566,7 +8566,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8598,14 +8598,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8645,7 +8645,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8667,7 +8667,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8691,11 +8691,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8704,12 +8704,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8727,12 +8727,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -15414,7 +15414,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -15448,7 +15448,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -15470,7 +15470,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -15505,7 +15505,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -15527,7 +15527,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -15550,7 +15550,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -15570,7 +15570,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -18996,10 +18996,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -19445,12 +19445,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -19725,61 +19726,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -19797,60 +19798,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -19869,62 +19870,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -19942,59 +19943,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_CM4L_Pos (0U) @@ -21989,7 +21990,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h757xx.h b/Include/stm32h757xx.h index 2003107..7cf9487 100644 --- a/Include/stm32h757xx.h +++ b/Include/stm32h757xx.h
@@ -4289,7 +4289,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -6004,7 +6004,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -6055,7 +6055,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6363,10 +6363,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -7121,7 +7121,7 @@ #define ETH_MACCR_SARC_Pos (28U) #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */ #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */ -#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ +#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */ #define ETH_MACCR_SARC_INSADDR0_Pos (29U) #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */ #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */ @@ -7140,14 +7140,14 @@ #define ETH_MACCR_IPG_Pos (24U) #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */ #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */ -#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */ -#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */ -#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */ -#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */ -#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */ -#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */ -#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */ -#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */ +#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */ +#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */ +#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */ +#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */ +#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */ +#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */ +#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */ +#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */ #define ETH_MACCR_GPSLCE_Pos (23U) #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */ #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */ @@ -7258,7 +7258,7 @@ #define ETH_MACPFR_PCF_Pos (6U) #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */ -#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */ +#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U) #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */ #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */ @@ -7294,21 +7294,21 @@ #define ETH_MACWTR_WTO_Pos (0U) #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */ #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */ -#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/ -#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */ -#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */ -#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */ -#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */ -#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */ -#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */ -#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */ -#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */ -#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */ -#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */ -#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */ -#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */ -#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */ -#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */ +#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/ +#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */ +#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */ +#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */ +#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */ +#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */ +#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */ +#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */ +#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */ +#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */ +#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */ +#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */ +#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */ +#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */ +#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) @@ -7327,7 +7327,7 @@ #define ETH_MACVTR_EIVLS_Pos (28U) #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */ #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U) #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */ #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7352,7 +7352,7 @@ #define ETH_MACVTR_EVLS_Pos (21U) #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */ #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */ -#define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */ +#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */ #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U) #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */ #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */ @@ -7408,7 +7408,7 @@ #define ETH_MACVIR_VLC_Pos (16U) #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7444,7 +7444,7 @@ #define ETH_MACIVIR_VLC_Pos (16U) #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */ #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */ -#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */ +#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */ #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U) #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */ #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */ @@ -7477,7 +7477,7 @@ #define ETH_MACTFCR_PLT_Pos (4U) #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */ #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */ -#define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */ #define ETH_MACTFCR_PLT_MINUS28_Pos (4U) #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */ #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */ @@ -7679,7 +7679,7 @@ #define ETH_MACDR_TFCSTS_Pos (17U) #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */ #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */ -#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */ #define ETH_MACDR_TFCSTS_WAIT_Pos (17U) #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */ #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */ @@ -7703,7 +7703,7 @@ #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U) #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */ #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */ -#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */ +#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */ #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U) #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */ #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */ @@ -7860,7 +7860,7 @@ #define ETH_MACMDIOAR_CR_Pos (8U) #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */ #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */ -#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ +#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ #define ETH_MACMDIOAR_CR_DIV62_Pos (8U) #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */ #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */ @@ -8015,12 +8015,12 @@ #define ETH_MACAHR_MBC_Pos (24U) #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ -#define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ -#define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ -#define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ -#define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ -#define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ -#define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACAHR_MACAH_Pos (0U) #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */ #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */ @@ -8518,14 +8518,14 @@ #define ETH_MTLTQOMR_TTC_Pos (4U) #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */ #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */ -#define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */ -#define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */ -#define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */ -#define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */ -#define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */ -#define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */ -#define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */ -#define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */ +#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */ +#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */ +#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */ +#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */ +#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */ +#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */ +#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */ +#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */ #define ETH_MTLTQOMR_TSF_Pos (1U) #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */ #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */ @@ -8560,10 +8560,10 @@ #define ETH_MTLTQDR_TRCSTS_Pos (1U) #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */ -#define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ -#define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */ -#define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */ -#define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ +#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */ +#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */ +#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */ +#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */ #define ETH_MTLTQDR_TXQPAUSED_Pos (0U) #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */ #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */ @@ -8610,10 +8610,10 @@ #define ETH_MTLRQOMR_RTC_Pos (0U) #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */ #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */ -#define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */ -#define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */ -#define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */ -#define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */ +#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */ +#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */ +#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */ +#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */ /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */ #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U) @@ -8636,7 +8636,7 @@ #define ETH_MTLRQDR_RXQSTS_Pos (4U) #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */ #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */ -#define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */ +#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U) #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */ #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */ @@ -8649,7 +8649,7 @@ #define ETH_MTLRQDR_RRCSTS_Pos (1U) #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */ #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */ -#define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */ +#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */ #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U) #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */ #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */ @@ -8681,14 +8681,14 @@ #define ETH_DMAMR_PR_Pos (12U) #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */ #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */ -#define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */ -#define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */ -#define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */ -#define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */ -#define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */ -#define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */ -#define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */ -#define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */ +#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */ +#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */ +#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */ +#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */ +#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */ +#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */ +#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */ +#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */ #define ETH_DMAMR_TXPR_Pos (11U) #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */ #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */ @@ -8728,7 +8728,7 @@ #define ETH_DMADSR_TPS_Pos (12U) #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */ #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */ -#define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */ +#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */ #define ETH_DMADSR_TPS_FETCHING_Pos (12U) #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */ @@ -8750,7 +8750,7 @@ #define ETH_DMADSR_RPS_Pos (8U) #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */ #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */ -#define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */ +#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */ #define ETH_DMADSR_RPS_FETCHING_Pos (12U) #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */ #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */ @@ -8774,11 +8774,11 @@ #define ETH_DMACCR_DSL_Pos (18U) #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */ #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */ -#define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000) -#define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000) -#define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000) -#define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000) -#define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */ +#define ETH_DMACCR_DSL_0BIT (0U) +#define ETH_DMACCR_DSL_32BIT (0x00040000U) +#define ETH_DMACCR_DSL_64BIT (0x00080000U) +#define ETH_DMACCR_DSL_128BIT (0x00100000U) +#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */ #define ETH_DMACCR_MSS_Pos (0U) #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */ #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */ @@ -8787,12 +8787,12 @@ #define ETH_DMACTCR_TPBL_Pos (16U) #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */ -#define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */ -#define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */ -#define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */ -#define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */ -#define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */ -#define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */ +#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */ +#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */ +#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */ +#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */ +#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */ +#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */ #define ETH_DMACTCR_TSE_Pos (12U) #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */ #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */ @@ -8810,12 +8810,12 @@ #define ETH_DMACRCR_RPBL_Pos (16U) #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */ #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */ -#define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */ -#define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */ -#define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */ -#define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */ -#define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */ -#define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */ +#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */ +#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */ +#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */ +#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */ +#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */ +#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */ #define ETH_DMACRCR_RBSZ_Pos (1U) #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */ #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */ @@ -11217,13 +11217,13 @@ #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk /******************* Bit definition for DSI_TDCR register ***************/ -#define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */ -#define DSI_TDCR_3DM0 ((uint32_t)0x00000001U) -#define DSI_TDCR_3DM1 ((uint32_t)0x00000002U) +#define DSI_TDCR_3DM (0x00000003U) /*!< 3D Mode */ +#define DSI_TDCR_3DM0 (0x00000001U) +#define DSI_TDCR_3DM1 (0x00000002U) -#define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */ -#define DSI_TDCR_3DF0 ((uint32_t)0x00000004U) -#define DSI_TDCR_3DF1 ((uint32_t)0x00000008U) +#define DSI_TDCR_3DF (0x0000000CU) /*!< 3D Format */ +#define DSI_TDCR_3DF0 (0x00000004U) +#define DSI_TDCR_3DF1 (0x00000008U) #define DSI_TDCR_SVS_Pos (4U) #define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */ @@ -12393,13 +12393,13 @@ #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk /******************* Bit definition for DSI_TDCCR register **************/ -#define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */ -#define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U) -#define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U) +#define DSI_TDCCR_3DM (0x00000003U) /*!< 3D Mode */ +#define DSI_TDCCR_3DM0 (0x00000001U) +#define DSI_TDCCR_3DM1 (0x00000002U) -#define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */ -#define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U) -#define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U) +#define DSI_TDCCR_3DF (0x0000000CU) /*!< 3D Format */ +#define DSI_TDCCR_3DF0 (0x00000004U) +#define DSI_TDCCR_3DF1 (0x00000008U) #define DSI_TDCCR_SVS_Pos (4U) #define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */ @@ -18571,7 +18571,7 @@ #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_D1CFGR_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_D1CFGR_HPRE_DIV2_Pos (3U) #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -18605,7 +18605,7 @@ #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */ #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_D1CFGR_D1PPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U) #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -18627,7 +18627,7 @@ #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */ #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */ -#define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_D1CFGR_D1CPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U) #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -18662,7 +18662,7 @@ #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */ #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */ -#define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_D2CFGR_D2PPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U) #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -18684,7 +18684,7 @@ #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */ #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */ -#define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_D2CFGR_D2PPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U) #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -18707,7 +18707,7 @@ #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */ #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */ -#define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_D3CFGR_D3PPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U) #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -18727,7 +18727,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -22169,10 +22169,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -22618,12 +22618,13 @@ #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) -#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ -#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ +#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ @@ -22898,61 +22899,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -22970,60 +22971,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -23042,62 +23043,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -23115,59 +23116,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_CM4L_Pos (0U) @@ -25162,7 +25163,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h7a3xx.h b/Include/stm32h7a3xx.h index 63c4fd3..5491297 100644 --- a/Include/stm32h7a3xx.h +++ b/Include/stm32h7a3xx.h
@@ -3906,7 +3906,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5863,10 +5863,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -12753,7 +12753,7 @@ #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */ #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U) #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -12787,7 +12787,7 @@ #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U) #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -12809,7 +12809,7 @@ #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */ -#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U) #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -12844,7 +12844,7 @@ #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U) #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -12866,7 +12866,7 @@ #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */ #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */ -#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U) #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -12889,7 +12889,7 @@ #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */ #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U) #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -12909,7 +12909,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -16578,10 +16578,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -17061,61 +17061,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -17133,60 +17133,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -17205,62 +17205,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -17278,59 +17278,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -19797,7 +19797,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h7a3xxq.h b/Include/stm32h7a3xxq.h index a54a5b0..46da5de 100644 --- a/Include/stm32h7a3xxq.h +++ b/Include/stm32h7a3xxq.h
@@ -3907,7 +3907,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5864,10 +5864,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -12765,7 +12765,7 @@ #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */ #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U) #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -12799,7 +12799,7 @@ #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U) #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -12821,7 +12821,7 @@ #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */ -#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U) #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -12856,7 +12856,7 @@ #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U) #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -12878,7 +12878,7 @@ #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */ #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */ -#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U) #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -12901,7 +12901,7 @@ #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */ #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U) #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -12921,7 +12921,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -16590,10 +16590,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -17073,61 +17073,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -17145,60 +17145,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -17217,62 +17217,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -17290,59 +17290,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -19809,7 +19809,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h7b0xx.h b/Include/stm32h7b0xx.h index 2085bf3..d23db59 100644 --- a/Include/stm32h7b0xx.h +++ b/Include/stm32h7b0xx.h
@@ -4041,7 +4041,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5758,7 +5758,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -5809,7 +5809,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6117,10 +6117,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -13197,7 +13197,7 @@ #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */ #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U) #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -13231,7 +13231,7 @@ #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U) #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -13253,7 +13253,7 @@ #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */ -#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U) #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -13288,7 +13288,7 @@ #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U) #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -13310,7 +13310,7 @@ #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */ #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */ -#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U) #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -13333,7 +13333,7 @@ #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */ #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U) #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -13353,7 +13353,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -17058,10 +17058,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -17541,61 +17541,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -17613,60 +17613,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -17685,62 +17685,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -17758,59 +17758,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -20277,7 +20277,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h7b0xxq.h b/Include/stm32h7b0xxq.h index a020cbe..1b59940 100644 --- a/Include/stm32h7b0xxq.h +++ b/Include/stm32h7b0xxq.h
@@ -4042,7 +4042,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5759,7 +5759,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -5810,7 +5810,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6118,10 +6118,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -13209,7 +13209,7 @@ #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */ #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U) #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -13243,7 +13243,7 @@ #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U) #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -13265,7 +13265,7 @@ #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */ -#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U) #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -13300,7 +13300,7 @@ #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U) #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -13322,7 +13322,7 @@ #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */ #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */ -#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U) #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -13345,7 +13345,7 @@ #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */ #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U) #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -13365,7 +13365,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -17070,10 +17070,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -17553,61 +17553,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -17625,60 +17625,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -17697,62 +17697,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -17770,59 +17770,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -20289,7 +20289,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h7b3xx.h b/Include/stm32h7b3xx.h index c99101f..fcfdac6 100644 --- a/Include/stm32h7b3xx.h +++ b/Include/stm32h7b3xx.h
@@ -4041,7 +4041,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5758,7 +5758,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -5809,7 +5809,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6117,10 +6117,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -13204,7 +13204,7 @@ #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */ #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U) #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -13238,7 +13238,7 @@ #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U) #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -13260,7 +13260,7 @@ #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */ -#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U) #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -13295,7 +13295,7 @@ #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U) #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -13317,7 +13317,7 @@ #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */ #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */ -#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U) #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -13340,7 +13340,7 @@ #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */ #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U) #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -13360,7 +13360,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -17065,10 +17065,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -17548,61 +17548,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -17620,60 +17620,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -17692,62 +17692,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -17765,59 +17765,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -20284,7 +20284,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h7b3xxq.h b/Include/stm32h7b3xxq.h index e0be69c..f0d1405 100644 --- a/Include/stm32h7b3xxq.h +++ b/Include/stm32h7b3xxq.h
@@ -4042,7 +4042,7 @@ #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ -#define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */ +#define VREFBUF_CSR_VRS_OUT1 (0U) /*!<Voltage reference VREF_OUT1 */ #define VREFBUF_CSR_VRS_OUT2_Pos (4U) #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */ #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */ @@ -5759,7 +5759,7 @@ #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */ #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */ -#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) +#define CRYP_CR_ALGOMODE_TDES_ECB (0U) #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U) #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */ #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk @@ -5810,7 +5810,7 @@ #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */ #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */ -#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) +#define CRYP_CR_ALGOMODE_3 (0x00080000U) #define CRYP_CR_NPBLB_Pos (20U) #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */ #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk @@ -6118,10 +6118,10 @@ #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk -#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U) -#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U) -#define DCMI_CR_EDM_0 ((uint32_t)0x00000400U) -#define DCMI_CR_EDM_1 ((uint32_t)0x00000800U) +#define DCMI_CR_FCRC_0 (0x00000100U) +#define DCMI_CR_FCRC_1 (0x00000200U) +#define DCMI_CR_EDM_0 (0x00000400U) +#define DCMI_CR_EDM_1 (0x00000800U) #define DCMI_CR_CRE_Pos (12U) #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */ #define DCMI_CR_CRE DCMI_CR_CRE_Msk @@ -13216,7 +13216,7 @@ #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */ #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */ -#define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */ +#define RCC_CDCFGR1_HPRE_DIV1 (0U) /*!< AHB3 Clock not divided */ #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U) #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */ #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */ @@ -13250,7 +13250,7 @@ #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */ +#define RCC_CDCFGR1_CDPPRE_DIV1 (0U) /*!< APB3 clock not divided */ #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U) #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */ @@ -13272,7 +13272,7 @@ #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */ -#define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */ +#define RCC_CDCFGR1_CDCPRE_DIV1 (0U) /*!< Domain 1 Core clock not divided */ #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U) #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */ #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */ @@ -13307,7 +13307,7 @@ #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */ #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */ -#define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */ +#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U) /*!< APB1 clock not divided */ #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U) #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */ #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */ @@ -13329,7 +13329,7 @@ #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */ #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */ -#define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */ +#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U) /*!< APB2 clock not divided */ #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U) #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */ #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */ @@ -13352,7 +13352,7 @@ #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */ #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */ -#define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */ +#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U) /*!< APB4 clock not divided */ #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U) #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */ #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */ @@ -13372,7 +13372,7 @@ #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */ #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk -#define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */ +#define RCC_PLLCKSELR_PLLSRC_HSI (0U) /*!< HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U) #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */ #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */ @@ -17077,10 +17077,10 @@ #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */ /***************** Bit definition for SDMMC_IDMABASE0 register ***************/ -#define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */ +#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU) /*!< Buffer 0 memory base address */ /***************** Bit definition for SDMMC_IDMABASE1 register ***************/ -#define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */ +#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU) /*!< Buffer 1 memory base address */ /******************************************************************************/ /* */ @@ -17560,61 +17560,61 @@ /** * @brief EXTI0 configuration */ -#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */ -#define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PA (0U) /*!<PA[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U) /*!<PJ[0] pin */ +#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU) /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ -#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */ -#define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PA (0U) /*!<PA[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U) /*!<PJ[1] pin */ +#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U) /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ -#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */ -#define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PA (0U) /*!<PA[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U) /*!<PJ[2] pin */ +#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U) /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ -#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */ -#define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PA (0U) /*!<PA[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U) /*!<PJ[3] pin */ +#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U) /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) @@ -17632,60 +17632,60 @@ /** * @brief EXTI4 configuration */ -#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */ -#define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PA (0U) /*!<PA[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U) /*!<PJ[4] pin */ +#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU) /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ -#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */ -#define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PA (0U) /*!<PA[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U) /*!<PJ[5] pin */ +#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U) /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ -#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */ -#define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PA (0U) /*!<PA[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U) /*!<PJ[6] pin */ +#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U) /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ -#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */ -#define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PA (0U) /*!<PA[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U) /*!<PJ[7] pin */ +#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U) /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) @@ -17704,62 +17704,62 @@ /** * @brief EXTI8 configuration */ -#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */ -#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PA (0U) /*!<PA[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U) /*!<PJ[8] pin */ +#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU) /*!<PK[8] pin */ /** * @brief EXTI9 configuration */ -#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */ -#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PA (0U) /*!<PA[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U) /*!<PJ[9] pin */ +#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U) /*!<PK[9] pin */ /** * @brief EXTI10 configuration */ -#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */ -#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PA (0U) /*!<PA[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U) /*!<PJ[10] pin */ +#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U) /*!<PK[10] pin */ /** * @brief EXTI11 configuration */ -#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */ -#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PA (0U) /*!<PA[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U) /*!<PJ[11] pin */ +#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U) /*!<PK[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) @@ -17777,59 +17777,59 @@ /** * @brief EXTI12 configuration */ -#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */ -#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PA (0U) /*!<PA[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U) /*!<PI[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U) /*!<PJ[12] pin */ +#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU) /*!<PK[12] pin */ /** * @brief EXTI13 configuration */ -#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */ -#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PA (0U) /*!<PA[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U) /*!<PI[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U) /*!<PJ[13] pin */ +#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U) /*!<PK[13] pin */ /** * @brief EXTI14 configuration */ -#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */ -#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PA (0U) /*!<PA[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U) /*!<PI[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U) /*!<PJ[14] pin */ +#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U) /*!<PK[14] pin */ /** * @brief EXTI15 configuration */ -#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */ -#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PA (0U) /*!<PA[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U) /*!<PI[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U) /*!<PJ[15] pin */ +#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U) /*!<PK[15] pin */ /****************** Bit definition for SYSCFG_CFGR register ******************/ #define SYSCFG_CFGR_PVDL_Pos (2U) @@ -20296,7 +20296,7 @@ #define SWPMI_RFL_RFL_Pos (0U) #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */ #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */ -#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ +#define SWPMI_RFL_RFL_0_1 (0x00000003U) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ /******************* Bit definition for SWPMI_TDR register ********************/ #define SWPMI_TDR_TD_Pos (0U)
diff --git a/Include/stm32h7xx.h b/Include/stm32h7xx.h index c3774c6..c1fcad2 100644 --- a/Include/stm32h7xx.h +++ b/Include/stm32h7xx.h
@@ -102,11 +102,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.10.2 + * @brief CMSIS Device version number V1.10.3 */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */ -#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
diff --git a/README.md b/README.md index aeffdb6..25e4668 100644 --- a/README.md +++ b/README.md
@@ -27,20 +27,10 @@ ## Compatibility information -In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package: - -CMSIS Device H7 | CMSIS Core | Was delivered in the full MCU package ---------------- | ---------- | ------------------------------------- -Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 -Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 -Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 -Tag v1.9.0 | Tag v5.4.0 | Tag v1.8.0 -Tag v1.10.0 | Tag v5.6.0 | Tag v1.9.0 -Tag v1.10.1 | Tag v5.6.0 | Tag v1.9.1 -Tag v1.10.2 | Tag v5.6.0 | Tag v1.10.0 (and following, if any, till next CMSIS tag) +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeH7/blob/master/Release_Notes.html) release note. The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7). ## Troubleshooting -Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file
diff --git a/Release_Notes.html b/Release_Notes.html index 91fad24..ad4b20b 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -11,7 +11,7 @@ span.underline{text-decoration: underline;} div.column{display: inline-block; vertical-align: top; width: 50%;} </style> - <link rel="stylesheet" href="_htmresc/mini-st_2020.css" /> + <link rel="stylesheet" href="_htmresc/mini-st.css" /> <!--[if lt IE 9]> <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script> <![endif]--> @@ -30,11 +30,22 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history"><strong>Update History</strong></h1> <div class="collapse"> -<input type="checkbox" id="collapse-section14" checked aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.2 / 12-February-2022</strong></label> +<input type="checkbox" id="collapse-section15" checked aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.10.3 / 04-November-2022</strong></label> <div> <h2 id="main-changes">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> +<li>Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.</li> +<li>Adjust QUADSPI FIFO level threshold bits mask definition on 5 bits instead of 4bits.</li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.2 / 12-February-2022</strong></label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<ul> +<li>General updates to fix known defects and implementation enhancements</li> <li>Add support for ADC LDO output voltage ready bit.</li> <li>Remove useless OCTOSPI_DCR1_CKCSHT definition: alignment with the reference manual</li> <li>All system_stm32h7xx.c template files @@ -47,7 +58,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>All source files: update disclaimer to add reference to the new license agreement.</li> @@ -73,7 +84,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label> <div> -<h2 id="main-changes-2">Main Changes</h2> +<h2 id="main-changes-3">Main Changes</h2> <ul> <li>Fix minor issues related to English typo in comments of registers and fields description</li> <li>Update STM32H7 devices header files to add GPV registers definition, base address and instance</li> @@ -91,7 +102,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label> <div> -<h2 id="main-changes-3">Main Changes</h2> +<h2 id="main-changes-4">Main Changes</h2> <ul> <li>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices: <ul> @@ -149,7 +160,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <ul> <li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li> <li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li> @@ -170,7 +181,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <ul> <li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li> <li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: @@ -200,7 +211,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <ul> <li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li> <li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li> @@ -215,7 +226,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <ul> <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li> <li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li> @@ -279,7 +290,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label> <div> -<h2 id="main-changes-8">Main Changes</h2> +<h2 id="main-changes-9">Main Changes</h2> <ul> <li><strong>Patch Release on top of V1.3.0</strong></li> <li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -292,7 +303,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label> <div> -<h2 id="main-changes-9">Main Changes</h2> +<h2 id="main-changes-10">Main Changes</h2> <ul> <li>STM32H7xx include files: <ul> @@ -337,7 +348,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label> <div> -<h2 id="main-changes-10">Main Changes</h2> +<h2 id="main-changes-11">Main Changes</h2> <ul> <li>Add support for stm32h750xx value line devices: <ul> @@ -350,7 +361,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label> <div> -<h2 id="main-changes-11">Main Changes</h2> +<h2 id="main-changes-12">Main Changes</h2> <ul> <li>Update FDCAN bit definition</li> <li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li> @@ -360,7 +371,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label> <div> -<h2 id="main-changes-12">Main Changes</h2> +<h2 id="main-changes-13">Main Changes</h2> <ul> <li>Update USB OTG bit definition</li> <li>Adjust PLL fractional computation</li> @@ -370,7 +381,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label> <div> -<h2 id="main-changes-13">Main Changes</h2> +<h2 id="main-changes-14">Main Changes</h2> <ul> <li>First official release for <strong>STM32H743xx/753xx</strong> devices</li> </ul>
diff --git a/Source/Templates/arm/startup_stm32h723xx.s b/Source/Templates/arm/startup_stm32h723xx.s index b575ee1..a66af50 100644 --- a/Source/Templates/arm/startup_stm32h723xx.s +++ b/Source/Templates/arm/startup_stm32h723xx.s
@@ -236,8 +236,8 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt __Vectors_End
diff --git a/Source/Templates/arm/startup_stm32h725xx.s b/Source/Templates/arm/startup_stm32h725xx.s index aea3955..0c84601 100644 --- a/Source/Templates/arm/startup_stm32h725xx.s +++ b/Source/Templates/arm/startup_stm32h725xx.s
@@ -236,8 +236,8 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt __Vectors_End
diff --git a/Source/Templates/arm/startup_stm32h730xx.s b/Source/Templates/arm/startup_stm32h730xx.s index ee025bd..1604fa4 100644 --- a/Source/Templates/arm/startup_stm32h730xx.s +++ b/Source/Templates/arm/startup_stm32h730xx.s
@@ -236,8 +236,8 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt __Vectors_End
diff --git a/Source/Templates/arm/startup_stm32h730xxq.s b/Source/Templates/arm/startup_stm32h730xxq.s index c8e48ab..d2f1097 100644 --- a/Source/Templates/arm/startup_stm32h730xxq.s +++ b/Source/Templates/arm/startup_stm32h730xxq.s
@@ -236,8 +236,8 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt __Vectors_End
diff --git a/Source/Templates/arm/startup_stm32h733xx.s b/Source/Templates/arm/startup_stm32h733xx.s index 1085925..651613f 100644 --- a/Source/Templates/arm/startup_stm32h733xx.s +++ b/Source/Templates/arm/startup_stm32h733xx.s
@@ -236,8 +236,8 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt __Vectors_End
diff --git a/Source/Templates/arm/startup_stm32h735xx.s b/Source/Templates/arm/startup_stm32h735xx.s index 562fef4..219ee5f 100644 --- a/Source/Templates/arm/startup_stm32h735xx.s +++ b/Source/Templates/arm/startup_stm32h735xx.s
@@ -236,8 +236,8 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt __Vectors_End
diff --git a/Source/Templates/iar/startup_stm32h723xx.s b/Source/Templates/iar/startup_stm32h723xx.s index 69827bd..85b1adf 100644 --- a/Source/Templates/iar/startup_stm32h723xx.s +++ b/Source/Templates/iar/startup_stm32h723xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h723xx.s ;* Author : MCD Application Team ;* Description : STM32H723xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI - DCD 0 ; Reserved + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,14 +166,14 @@ DCD OCTOSPI1_IRQHandler ; OCTOSPI1 DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -181,45 +181,45 @@ DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD 0 ; Reserved - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD DTS_IRQHandler ; Digital Temperature Sensor - DCD 0 ; Reserved + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt DCD 0 ; Reserved @@ -232,9 +232,9 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup - + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -296,47 +296,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -345,319 +345,319 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_PSSI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -665,318 +665,318 @@ B DCMI_PSSI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK OCTOSPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI1_IRQHandler - B OCTOSPI1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler B DMAMUX1_OVR_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler B DFSDM1_FLT3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK DTS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler B DTS_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler B WAKEUP_PIN_IRQHandler PUBWEAK OCTOSPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler B OCTOSPI2_IRQHandler PUBWEAK FMAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler B FMAC_IRQHandler PUBWEAK CORDIC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler B CORDIC_IRQHandler PUBWEAK UART9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler B UART9_IRQHandler PUBWEAK USART10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler B USART10_IRQHandler PUBWEAK I2C5_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler B I2C5_EV_IRQHandler PUBWEAK I2C5_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler B I2C5_ER_IRQHandler PUBWEAK FDCAN3_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler B FDCAN3_IT0_IRQHandler PUBWEAK FDCAN3_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler B FDCAN3_IT1_IRQHandler PUBWEAK TIM23_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler B TIM23_IRQHandler PUBWEAK TIM24_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM24_IRQHandler - B TIM24_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + END
diff --git a/Source/Templates/iar/startup_stm32h725xx.s b/Source/Templates/iar/startup_stm32h725xx.s index 345fad4..1f05b10 100644 --- a/Source/Templates/iar/startup_stm32h725xx.s +++ b/Source/Templates/iar/startup_stm32h725xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h725xx.s ;* Author : MCD Application Team ;* Description : STM32H725xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI - DCD 0 ; Reserved + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,14 +166,14 @@ DCD OCTOSPI1_IRQHandler ; OCTOSPI1 DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -181,45 +181,45 @@ DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD 0 ; Reserved - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD DTS_IRQHandler ; Digital Temperature Sensor - DCD 0 ; Reserved + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt DCD 0 ; Reserved @@ -232,9 +232,9 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup - + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -296,47 +296,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -345,319 +345,319 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_PSSI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -665,318 +665,318 @@ B DCMI_PSSI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK OCTOSPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI1_IRQHandler - B OCTOSPI1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler B DMAMUX1_OVR_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler B DFSDM1_FLT3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK DTS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler B DTS_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler B WAKEUP_PIN_IRQHandler PUBWEAK OCTOSPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler B OCTOSPI2_IRQHandler PUBWEAK FMAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler B FMAC_IRQHandler PUBWEAK CORDIC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler B CORDIC_IRQHandler PUBWEAK UART9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler B UART9_IRQHandler PUBWEAK USART10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler B USART10_IRQHandler PUBWEAK I2C5_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler B I2C5_EV_IRQHandler PUBWEAK I2C5_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler B I2C5_ER_IRQHandler PUBWEAK FDCAN3_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler B FDCAN3_IT0_IRQHandler PUBWEAK FDCAN3_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler B FDCAN3_IT1_IRQHandler PUBWEAK TIM23_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler B TIM23_IRQHandler PUBWEAK TIM24_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM24_IRQHandler - B TIM24_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + END
diff --git a/Source/Templates/iar/startup_stm32h730xx.s b/Source/Templates/iar/startup_stm32h730xx.s index 0a141c6..13139d0 100644 --- a/Source/Templates/iar/startup_stm32h730xx.s +++ b/Source/Templates/iar/startup_stm32h730xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h730xx.s ;* Author : MCD Application Team ;* Description : STM32H730xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI - DCD CRYP_IRQHandler ; CRYP crypto + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,14 +166,14 @@ DCD OCTOSPI1_IRQHandler ; OCTOSPI1 DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -181,45 +181,45 @@ DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD 0 ; Reserved - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD DTS_IRQHandler ; Digital Temperature Sensor - DCD 0 ; Reserved + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt @@ -232,9 +232,9 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup - + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -296,47 +296,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -345,319 +345,319 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_PSSI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -665,333 +665,333 @@ B DCMI_PSSI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK OCTOSPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI1_IRQHandler - B OCTOSPI1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler B DMAMUX1_OVR_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler B DFSDM1_FLT3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK DTS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler B DTS_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler B WAKEUP_PIN_IRQHandler PUBWEAK OCTOSPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler B OCTOSPI2_IRQHandler PUBWEAK OTFDEC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC1_IRQHandler B OTFDEC1_IRQHandler PUBWEAK OTFDEC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC2_IRQHandler B OTFDEC2_IRQHandler PUBWEAK FMAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler B FMAC_IRQHandler PUBWEAK CORDIC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler B CORDIC_IRQHandler PUBWEAK UART9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler B UART9_IRQHandler PUBWEAK USART10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler B USART10_IRQHandler PUBWEAK I2C5_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler B I2C5_EV_IRQHandler PUBWEAK I2C5_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler B I2C5_ER_IRQHandler PUBWEAK FDCAN3_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler B FDCAN3_IT0_IRQHandler PUBWEAK FDCAN3_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler B FDCAN3_IT1_IRQHandler PUBWEAK TIM23_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler B TIM23_IRQHandler PUBWEAK TIM24_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM24_IRQHandler - B TIM24_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + END
diff --git a/Source/Templates/iar/startup_stm32h730xxq.s b/Source/Templates/iar/startup_stm32h730xxq.s index 1447d66..b5e33b2 100644 --- a/Source/Templates/iar/startup_stm32h730xxq.s +++ b/Source/Templates/iar/startup_stm32h730xxq.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h730xxq.s ;* Author : MCD Application Team ;* Description : STM32H730xxQ devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI - DCD CRYP_IRQHandler ; CRYP crypto + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,14 +166,14 @@ DCD OCTOSPI1_IRQHandler ; OCTOSPI1 DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -181,45 +181,45 @@ DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD 0 ; Reserved - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD DTS_IRQHandler ; Digital Temperature Sensor - DCD 0 ; Reserved + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt @@ -232,9 +232,9 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup - + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -296,47 +296,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -345,319 +345,319 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_PSSI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -665,333 +665,333 @@ B DCMI_PSSI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK OCTOSPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI1_IRQHandler - B OCTOSPI1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler B DMAMUX1_OVR_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler B DFSDM1_FLT3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK DTS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler B DTS_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler B WAKEUP_PIN_IRQHandler PUBWEAK OCTOSPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler B OCTOSPI2_IRQHandler PUBWEAK OTFDEC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC1_IRQHandler B OTFDEC1_IRQHandler PUBWEAK OTFDEC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC2_IRQHandler B OTFDEC2_IRQHandler PUBWEAK FMAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler B FMAC_IRQHandler PUBWEAK CORDIC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler B CORDIC_IRQHandler PUBWEAK UART9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler B UART9_IRQHandler PUBWEAK USART10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler B USART10_IRQHandler PUBWEAK I2C5_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler B I2C5_EV_IRQHandler PUBWEAK I2C5_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler B I2C5_ER_IRQHandler PUBWEAK FDCAN3_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler B FDCAN3_IT0_IRQHandler PUBWEAK FDCAN3_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler B FDCAN3_IT1_IRQHandler PUBWEAK TIM23_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler B TIM23_IRQHandler PUBWEAK TIM24_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM24_IRQHandler - B TIM24_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + END
diff --git a/Source/Templates/iar/startup_stm32h733xx.s b/Source/Templates/iar/startup_stm32h733xx.s index 96ce335..3f7a8fa 100644 --- a/Source/Templates/iar/startup_stm32h733xx.s +++ b/Source/Templates/iar/startup_stm32h733xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h733xx.s ;* Author : MCD Application Team ;* Description : STM32H733xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI - DCD CRYP_IRQHandler ; CRYP crypto + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,14 +166,14 @@ DCD OCTOSPI1_IRQHandler ; OCTOSPI1 DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -181,45 +181,45 @@ DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD 0 ; Reserved - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD DTS_IRQHandler ; Digital Temperature Sensor - DCD 0 ; Reserved + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt @@ -232,9 +232,9 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup - + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -296,47 +296,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -345,319 +345,319 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_PSSI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -665,333 +665,333 @@ B DCMI_PSSI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK OCTOSPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI1_IRQHandler - B OCTOSPI1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler B DMAMUX1_OVR_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler B DFSDM1_FLT3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK DTS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler B DTS_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler B WAKEUP_PIN_IRQHandler PUBWEAK OCTOSPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler B OCTOSPI2_IRQHandler PUBWEAK OTFDEC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC1_IRQHandler B OTFDEC1_IRQHandler PUBWEAK OTFDEC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC2_IRQHandler B OTFDEC2_IRQHandler PUBWEAK FMAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler B FMAC_IRQHandler PUBWEAK CORDIC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler B CORDIC_IRQHandler PUBWEAK UART9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler B UART9_IRQHandler PUBWEAK USART10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler B USART10_IRQHandler PUBWEAK I2C5_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler B I2C5_EV_IRQHandler PUBWEAK I2C5_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler B I2C5_ER_IRQHandler PUBWEAK FDCAN3_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler B FDCAN3_IT0_IRQHandler PUBWEAK FDCAN3_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler B FDCAN3_IT1_IRQHandler PUBWEAK TIM23_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler B TIM23_IRQHandler PUBWEAK TIM24_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM24_IRQHandler - B TIM24_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + END
diff --git a/Source/Templates/iar/startup_stm32h735xx.s b/Source/Templates/iar/startup_stm32h735xx.s index f71f70e..fa3454c 100644 --- a/Source/Templates/iar/startup_stm32h735xx.s +++ b/Source/Templates/iar/startup_stm32h735xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h735xx.s ;* Author : MCD Application Team ;* Description : STM32H735xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI - DCD CRYP_IRQHandler ; CRYP crypto + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,14 +166,14 @@ DCD OCTOSPI1_IRQHandler ; OCTOSPI1 DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD 0 ; Reserved + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved @@ -181,45 +181,45 @@ DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD 0 ; Reserved - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD 0 ; Reserved - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD DTS_IRQHandler ; Digital Temperature Sensor - DCD 0 ; Reserved + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD DTS_IRQHandler ; Digital Temperature Sensor + DCD 0 ; Reserved DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins DCD OCTOSPI2_IRQHandler ; OCTOSPI2 Interrupt DCD OTFDEC1_IRQHandler ; OTFDEC1 Interrupt @@ -232,9 +232,9 @@ DCD I2C5_ER_IRQHandler ; I2C5 Error Interrupt DCD FDCAN3_IT0_IRQHandler ; FDCAN3 interrupt line 0 DCD FDCAN3_IT1_IRQHandler ; FDCAN3 interrupt line 1 - DCD TIM23_IRQHandler ; TIM23 global interrup - DCD TIM24_IRQHandler ; TIM24 global interrup - + DCD TIM23_IRQHandler ; TIM23 global interrupt + DCD TIM24_IRQHandler ; TIM24 global interrupt + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -296,47 +296,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -345,319 +345,319 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_PSSI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) @@ -665,333 +665,333 @@ B DCMI_PSSI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK OCTOSPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI1_IRQHandler - B OCTOSPI1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI1_IRQHandler + B OCTOSPI1_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler B DMAMUX1_OVR_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler B DFSDM1_FLT3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK DTS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DTS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DTS_IRQHandler B DTS_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler B WAKEUP_PIN_IRQHandler PUBWEAK OCTOSPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OCTOSPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OCTOSPI2_IRQHandler B OCTOSPI2_IRQHandler PUBWEAK OTFDEC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC1_IRQHandler B OTFDEC1_IRQHandler PUBWEAK OTFDEC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTFDEC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTFDEC2_IRQHandler B OTFDEC2_IRQHandler PUBWEAK FMAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMAC_IRQHandler B FMAC_IRQHandler PUBWEAK CORDIC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CORDIC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CORDIC_IRQHandler B CORDIC_IRQHandler PUBWEAK UART9_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART9_IRQHandler B UART9_IRQHandler PUBWEAK USART10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART10_IRQHandler B USART10_IRQHandler PUBWEAK I2C5_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_EV_IRQHandler B I2C5_EV_IRQHandler PUBWEAK I2C5_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C5_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C5_ER_IRQHandler B I2C5_ER_IRQHandler PUBWEAK FDCAN3_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT0_IRQHandler B FDCAN3_IT0_IRQHandler PUBWEAK FDCAN3_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN3_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN3_IT1_IRQHandler B FDCAN3_IT1_IRQHandler PUBWEAK TIM23_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM23_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM23_IRQHandler B TIM23_IRQHandler PUBWEAK TIM24_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM24_IRQHandler - B TIM24_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +TIM24_IRQHandler + B TIM24_IRQHandler + END
diff --git a/Source/Templates/iar/startup_stm32h742xx.s b/Source/Templates/iar/startup_stm32h742xx.s index cca740d..690d544 100644 --- a/Source/Templates/iar/startup_stm32h742xx.s +++ b/Source/Templates/iar/startup_stm32h742xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h742xx.s ;* Author : MCD Application Team ;* Description : STM32H742xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD 0 ; Reserved - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD 0 ; Reserved + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,632 +331,632 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h743xx.s b/Source/Templates/iar/startup_stm32h743xx.s index 97cbd57..e7f79f6 100644 --- a/Source/Templates/iar/startup_stm32h743xx.s +++ b/Source/Templates/iar/startup_stm32h743xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h743xx.s ;* Author : MCD Application Team ;* Description : STM32H743xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,647 +331,647 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h745xg.s b/Source/Templates/iar/startup_stm32h745xg.s index c1cf4db..aa44a12 100644 --- a/Source/Templates/iar/startup_stm32h745xg.s +++ b/Source/Templates/iar/startup_stm32h745xg.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h745xg.s ;* Author : MCD Application Team ;* Description : STM32H745xg devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 - DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD HSEM2_IRQHandler ; HSEM2 global Interrupt - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD HOLD_CORE_IRQHandler ; Hold core interrupt - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,672 +331,672 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK CM7_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler B CM7_SEV_IRQHandler PUBWEAK CM4_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler B CM4_SEV_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK HSEM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler B HSEM2_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK WWDG_RST_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler B WWDG_RST_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler - B ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK HOLD_CORE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler B HOLD_CORE_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h745xx.s b/Source/Templates/iar/startup_stm32h745xx.s index 1b32162..0d9e086 100644 --- a/Source/Templates/iar/startup_stm32h745xx.s +++ b/Source/Templates/iar/startup_stm32h745xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h745xx.s ;* Author : MCD Application Team ;* Description : STM32H745xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 - DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD HSEM2_IRQHandler ; HSEM2 global Interrupt - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD HOLD_CORE_IRQHandler ; Hold core interrupt - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,672 +331,672 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK CM7_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler B CM7_SEV_IRQHandler PUBWEAK CM4_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler B CM4_SEV_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK HSEM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler B HSEM2_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK WWDG_RST_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler B WWDG_RST_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler - B ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK HOLD_CORE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler B HOLD_CORE_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h747xg.s b/Source/Templates/iar/startup_stm32h747xg.s index b5765d2..6e46798 100644 --- a/Source/Templates/iar/startup_stm32h747xg.s +++ b/Source/Templates/iar/startup_stm32h747xg.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h747xg.s ;* Author : MCD Application Team ;* Description : STM32H747xG devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 - DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD DSI_IRQHandler ; DSI global Interrupt - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD HSEM2_IRQHandler ; HSEM2 global Interrupt - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD DSI_IRQHandler ; DSI global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD HOLD_CORE_IRQHandler ; Hold core interrupt - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,677 +331,677 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK CM7_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler B CM7_SEV_IRQHandler PUBWEAK CM4_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler B CM4_SEV_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK DSI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DSI_IRQHandler B DSI_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK HSEM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler B HSEM2_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK WWDG_RST_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler B WWDG_RST_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK HOLD_CORE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler B HOLD_CORE_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h747xx.s b/Source/Templates/iar/startup_stm32h747xx.s index 2ed6e93..f4d4ed2 100644 --- a/Source/Templates/iar/startup_stm32h747xx.s +++ b/Source/Templates/iar/startup_stm32h747xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h747xx.s ;* Author : MCD Application Team ;* Description : STM32H747xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 - DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD RNG_IRQHandler ; Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD DSI_IRQHandler ; DSI global Interrupt - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD HSEM2_IRQHandler ; HSEM2 global Interrupt - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD DSI_IRQHandler ; DSI global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD HOLD_CORE_IRQHandler ; Hold core interrupt - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,677 +331,677 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK CM7_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler B CM7_SEV_IRQHandler PUBWEAK CM4_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler B CM4_SEV_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler B RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK DSI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DSI_IRQHandler B DSI_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK HSEM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler B HSEM2_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK WWDG_RST_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler B WWDG_RST_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK HOLD_CORE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler B HOLD_CORE_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h750xx.s b/Source/Templates/iar/startup_stm32h750xx.s index 4b6b0fa..a083ee6 100644 --- a/Source/Templates/iar/startup_stm32h750xx.s +++ b/Source/Templates/iar/startup_stm32h750xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h750xx.s ;* Author : MCD Application Team ;* Description : STM32H750xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,652 +331,652 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler - + PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h753xx.s b/Source/Templates/iar/startup_stm32h753xx.s index cf1a6f1..6aa4583 100644 --- a/Source/Templates/iar/startup_stm32h753xx.s +++ b/Source/Templates/iar/startup_stm32h753xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h753xx.s ;* Author : MCD Application Team ;* Description : STM32H753xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD 0 ; Reserved - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD 0 ; Reserved - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD 0 ; Reserved + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD 0 ; Reserved + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,652 +331,652 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler - + PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h755xx.s b/Source/Templates/iar/startup_stm32h755xx.s index e8220f0..070aa63 100644 --- a/Source/Templates/iar/startup_stm32h755xx.s +++ b/Source/Templates/iar/startup_stm32h755xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h755xx.s ;* Author : MCD Application Team ;* Description : STM32H755xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 - DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD 0 ; Reserved - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD HSEM2_IRQHandler ; HSEM2 global Interrupt - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD 0 ; Reserved + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD HOLD_CORE_IRQHandler ; Hold core interrupt - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,677 +331,677 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK CM7_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler B CM7_SEV_IRQHandler PUBWEAK CM4_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler B CM4_SEV_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK HSEM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler B HSEM2_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK WWDG_RST_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler B WWDG_RST_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK HOLD_CORE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler B HOLD_CORE_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h757xx.s b/Source/Templates/iar/startup_stm32h757xx.s index 40e8a54..3de3463 100644 --- a/Source/Templates/iar/startup_stm32h757xx.s +++ b/Source/Templates/iar/startup_stm32h757xx.s
@@ -1,11 +1,11 @@ -;******************************************************************************** +;/******************************************************************************** ;* File Name : startup_stm32h757xx.s ;* Author : MCD Application Team ;* Description : STM32H757xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR +;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Branches to main in the C library (which eventually ;* calls main()). @@ -54,7 +54,7 @@ __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler - + DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler @@ -71,86 +71,86 @@ DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) - DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 - DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 - DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10] - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 - DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 @@ -166,61 +166,61 @@ DCD QUADSPI_IRQHandler ; QUADSPI DCD LPTIM1_IRQHandler ; LPTIM1 DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out - DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt - DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts - DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt - DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt - DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt - DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt - DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt - DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt - DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt - DCD SAI3_IRQHandler ; SAI3 global Interrupt - DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt - DCD TIM15_IRQHandler ; TIM15 global Interrupt - DCD TIM16_IRQHandler ; TIM16 global Interrupt - DCD TIM17_IRQHandler ; TIM17 global Interrupt - DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt - DCD MDIOS_IRQHandler ; MDIOS global Interrupt - DCD JPEG_IRQHandler ; JPEG global Interrupt - DCD MDMA_IRQHandler ; MDMA global Interrupt - DCD DSI_IRQHandler ; DSI global Interrupt - DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt - DCD HSEM1_IRQHandler ; HSEM1 global Interrupt - DCD HSEM2_IRQHandler ; HSEM2 global Interrupt - DCD ADC3_IRQHandler ; ADC3 global Interrupt - DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt - DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt - DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt - DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt - DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt - DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt - DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt - DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt - DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt - DCD COMP1_IRQHandler ; COMP1 global Interrupt - DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt - DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt - DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt - DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt - DCD LPUART1_IRQHandler ; LP UART1 interrupt - DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) - DCD CRS_IRQHandler ; Clock Recovery Global Interrupt - DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt - DCD SAI4_IRQHandler ; SAI4 global interrupt - DCD 0 ; Reserved - DCD HOLD_CORE_IRQHandler ; Hold core interrupt - DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD DSI_IRQHandler ; DSI global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. @@ -282,47 +282,47 @@ PUBWEAK WWDG_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler +WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_AVD_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -PVD_AVD_IRQHandler +PVD_AVD_IRQHandler B PVD_AVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler +FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler +RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler +EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler +EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler +EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler @@ -331,682 +331,682 @@ B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ADC_IRQHandler +ADC_IRQHandler B ADC_IRQHandler PUBWEAK FDCAN1_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler B FDCAN1_IT0_IRQHandler PUBWEAK FDCAN2_IT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler B FDCAN2_IT0_IRQHandler PUBWEAK FDCAN1_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler B FDCAN1_IT1_IRQHandler PUBWEAK FDCAN2_IT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler B FDCAN2_IT1_IRQHandler PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler B TIM1_BRK_IRQHandler PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler B TIM1_UP_IRQHandler PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler B TIM1_TRG_COM_IRQHandler - + PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler +TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler +TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM4_IRQHandler +TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler +SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler +SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler +USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler +USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART3_IRQHandler +USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler - + PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler +FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDMMC1_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC1_IRQHandler +SDMMC1_IRQHandler B SDMMC1_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -TIM5_IRQHandler +TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -SPI3_IRQHandler +SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART4_IRQHandler +UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -UART5_IRQHandler +UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -ETH_IRQHandler +ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK FDCAN_CAL_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler B FDCAN_CAL_IRQHandler PUBWEAK CM7_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler B CM7_SEV_IRQHandler PUBWEAK CM4_SEV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler B CM4_SEV_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -USART6_IRQHandler +USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_WKUP_IRQHandler +OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler - PUBWEAK OTG_HS_IRQHandler + PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler +OTG_HS_IRQHandler + B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:NOROOT:REORDER(1) -DCMI_IRQHandler +DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRYP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART7_IRQHandler - B UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler PUBWEAK UART8_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler B UART8_IRQHandler - + PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) + SECTION .text:CODE:NOROOT:REORDER(1) SPI4_IRQHandler - B SPI4_IRQHandler + B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI5_IRQHandler - B SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI6_IRQHandler - B SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI1_IRQHandler - B SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_IRQHandler - B LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI2_IRQHandler - B SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + PUBWEAK CEC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_IRQHandler - B CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler PUBWEAK I2C4_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_EV_IRQHandler - B I2C4_EV_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + PUBWEAK I2C4_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C4_ER_IRQHandler - B I2C4_ER_IRQHandler - + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler PUBWEAK OTG_FS_EP1_OUT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_OUT_IRQHandler - B OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler PUBWEAK OTG_FS_EP1_IN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler B OTG_FS_EP1_IN_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler PUBWEAK HRTIM1_Master_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_Master_IRQHandler - B HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler PUBWEAK HRTIM1_TIMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMA_IRQHandler - B HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler PUBWEAK HRTIM1_TIMB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMB_IRQHandler - B HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler PUBWEAK HRTIM1_TIMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMC_IRQHandler - B HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler PUBWEAK HRTIM1_TIMD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler B HRTIM1_TIMD_IRQHandler PUBWEAK HRTIM1_TIME_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler B HRTIM1_TIME_IRQHandler PUBWEAK HRTIM1_FLT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler B HRTIM1_FLT_IRQHandler PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler B DFSDM1_FLT1_IRQHandler PUBWEAK DFSDM1_FLT2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler B DFSDM1_FLT2_IRQHandler PUBWEAK DFSDM1_FLT3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DFSDM1_FLT3_IRQHandler - B DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler PUBWEAK SAI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler B SAI3_IRQHandler PUBWEAK SWPMI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler B SWPMI1_IRQHandler PUBWEAK TIM15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler B TIM15_IRQHandler PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler B TIM16_IRQHandler PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler B TIM17_IRQHandler PUBWEAK MDIOS_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler B MDIOS_WKUP_IRQHandler PUBWEAK MDIOS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler B MDIOS_IRQHandler PUBWEAK JPEG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler B JPEG_IRQHandler PUBWEAK MDMA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler B MDMA_IRQHandler PUBWEAK DSI_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DSI_IRQHandler B DSI_IRQHandler PUBWEAK SDMMC2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler B SDMMC2_IRQHandler PUBWEAK HSEM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler B HSEM1_IRQHandler PUBWEAK HSEM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler B HSEM2_IRQHandler PUBWEAK ADC3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler B ADC3_IRQHandler PUBWEAK DMAMUX2_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler B DMAMUX2_OVR_IRQHandler PUBWEAK BDMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler B BDMA_Channel0_IRQHandler PUBWEAK BDMA_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler B BDMA_Channel1_IRQHandler PUBWEAK BDMA_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler B BDMA_Channel2_IRQHandler PUBWEAK BDMA_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler B BDMA_Channel3_IRQHandler PUBWEAK BDMA_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler B BDMA_Channel4_IRQHandler PUBWEAK BDMA_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler B BDMA_Channel5_IRQHandler PUBWEAK BDMA_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler B BDMA_Channel6_IRQHandler PUBWEAK BDMA_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler B BDMA_Channel7_IRQHandler PUBWEAK COMP1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler B COMP1_IRQHandler PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler B LPTIM2_IRQHandler PUBWEAK LPTIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler B LPTIM3_IRQHandler PUBWEAK LPTIM4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler B LPTIM4_IRQHandler PUBWEAK LPTIM5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM5_IRQHandler - B LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler B LPUART1_IRQHandler PUBWEAK WWDG_RST_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler B WWDG_RST_IRQHandler PUBWEAK CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler B CRS_IRQHandler PUBWEAK ECC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler B ECC_IRQHandler PUBWEAK SAI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler B SAI4_IRQHandler PUBWEAK HOLD_CORE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler B HOLD_CORE_IRQHandler PUBWEAK WAKEUP_PIN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WAKEUP_PIN_IRQHandler - B WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler END
diff --git a/Source/Templates/iar/startup_stm32h7a3xx.s b/Source/Templates/iar/startup_stm32h7a3xx.s index 476873e..0d7b20d 100644 --- a/Source/Templates/iar/startup_stm32h7a3xx.s +++ b/Source/Templates/iar/startup_stm32h7a3xx.s
@@ -1,7 +1,7 @@ -;/****************************************************************************** -; * @file startup_stm32h7a3xx.s -; * @author MCD Application Team -; * @brief STM32H7B3xx devices vector table for EWARM toolchain. +;/****************************************************************************** +;* @file startup_stm32h7a3xx.s +;* @author MCD Application Team +;* @brief STM32H7B3xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start,
diff --git a/Source/Templates/iar/startup_stm32h7a3xxq.s b/Source/Templates/iar/startup_stm32h7a3xxq.s index 584c473..1c5c2d3 100644 --- a/Source/Templates/iar/startup_stm32h7a3xxq.s +++ b/Source/Templates/iar/startup_stm32h7a3xxq.s
@@ -1,7 +1,7 @@ -;/****************************************************************************** -; * @file startup_stm32h7a3xxq.s -; * @author MCD Application Team -; * @brief STM32H7B3xx devices vector table for EWARM toolchain. +;/****************************************************************************** +;* @file startup_stm32h7a3xxq.s +;* @author MCD Application Team +;* @brief STM32H7B3xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start,
diff --git a/Source/Templates/iar/startup_stm32h7b0xx.s b/Source/Templates/iar/startup_stm32h7b0xx.s index f0edc99..a7ab39e 100644 --- a/Source/Templates/iar/startup_stm32h7b0xx.s +++ b/Source/Templates/iar/startup_stm32h7b0xx.s
@@ -1,7 +1,7 @@ -;/****************************************************************************** -; * @file startup_stm32h7b0xx.s -; * @author MCD Application Team -; * @brief STM32H7B0xx devices vector table for EWARM toolchain. +;/****************************************************************************** +;* @file startup_stm32h7b0xx.s +;* @author MCD Application Team +;* @brief STM32H7B0xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start,
diff --git a/Source/Templates/iar/startup_stm32h7b0xxq.s b/Source/Templates/iar/startup_stm32h7b0xxq.s index 072ecc9..707b21b 100644 --- a/Source/Templates/iar/startup_stm32h7b0xxq.s +++ b/Source/Templates/iar/startup_stm32h7b0xxq.s
@@ -1,7 +1,7 @@ -;/****************************************************************************** -; * @file startup_stm32h7b0xxq.s -; * @author MCD Application Team -; * @brief STM32H7B0xx devices vector table for EWARM toolchain. +;/****************************************************************************** +;* @file startup_stm32h7b0xxq.s +;* @author MCD Application Team +;* @brief STM32H7B0xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start,
diff --git a/Source/Templates/iar/startup_stm32h7b3xx.s b/Source/Templates/iar/startup_stm32h7b3xx.s index 5f7fb7f..9c7b7ac 100644 --- a/Source/Templates/iar/startup_stm32h7b3xx.s +++ b/Source/Templates/iar/startup_stm32h7b3xx.s
@@ -1,7 +1,7 @@ -;/****************************************************************************** -; * @file startup_stm32h7b3xx.s -; * @author MCD Application Team -; * @brief STM32H7B3xx devices vector table for EWARM toolchain. +;/****************************************************************************** +;* @file startup_stm32h7b3xx.s +;* @author MCD Application Team +;* @brief STM32H7B3xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start,
diff --git a/Source/Templates/iar/startup_stm32h7b3xxq.s b/Source/Templates/iar/startup_stm32h7b3xxq.s index 3040caa..dbe140b 100644 --- a/Source/Templates/iar/startup_stm32h7b3xxq.s +++ b/Source/Templates/iar/startup_stm32h7b3xxq.s
@@ -1,7 +1,7 @@ -;/****************************************************************************** -; * @file startup_stm32h7b3xxq.s -; * @author MCD Application Team -; * @brief STM32H7B3xx devices vector table for EWARM toolchain. +;/****************************************************************************** +;* @file startup_stm32h7b3xxq.s +;* @author MCD Application Team +;* @brief STM32H7B3xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start,
diff --git a/Source/Templates/system_stm32h7xx.c b/Source/Templates/system_stm32h7xx.c index c99a7b1..86e6784 100644 --- a/Source/Templates/system_stm32h7xx.c +++ b/Source/Templates/system_stm32h7xx.c
@@ -94,14 +94,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else /*!< Uncomment the following line if you need to relocate your vector Table @@ -109,14 +109,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #endif /* DUAL_CORE && CORE_CM4 */ #endif /* USER_VECT_TAB_ADDRESS */
diff --git a/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 4af82c9..2d0b59e 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c
@@ -94,14 +94,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #elif defined(CORE_CM7) /*!< Uncomment the following line if you need to relocate your vector Table @@ -109,14 +109,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else #error Please #define CORE_CM4 or CORE_CM7
diff --git a/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c index bf6bfcd..dc86d25 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c +++ b/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c
@@ -97,14 +97,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #elif defined(CORE_CM7) /*!< Uncomment the following line if you need to relocate your vector Table @@ -112,14 +112,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else #error Please #define CORE_CM4 or CORE_CM7
diff --git a/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c index c6c1c8e..f3f3406 100644 --- a/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c +++ b/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c
@@ -97,14 +97,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #elif defined(CORE_CM7) /*!< Uncomment the following line if you need to relocate your vector Table @@ -112,14 +112,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else #error Please #define CORE_CM4 or CORE_CM7
diff --git a/Source/Templates/system_stm32h7xx_singlecore.c b/Source/Templates/system_stm32h7xx_singlecore.c index de86fc3..6ab8cc2 100644 --- a/Source/Templates/system_stm32h7xx_singlecore.c +++ b/Source/Templates/system_stm32h7xx_singlecore.c
@@ -95,14 +95,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st.css index 71fbc14..eb41d56 100644 --- a/_htmresc/mini-st.css +++ b/_htmresc/mini-st.css
@@ -1463,7 +1463,7 @@ /* Definitions for progress elements and spinners. */ -/* Progess module CSS variable definitions */ +/* Progress module CSS variable definitions */ :root { --progress-back-color: #ddd; --progress-fore-color: #555; }