Fix bit definition for APB1HFZ1 and FMC_SDCMR register
Change-Id: I52f1f0f93845a3ef88a0a979d646aeb0fe6dd99c
diff --git a/Include/stm32h723xx.h b/Include/stm32h723xx.h
index 4c8a9d0..170fa48 100644
--- a/Include/stm32h723xx.h
+++ b/Include/stm32h723xx.h
@@ -21641,7 +21641,7 @@
#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U)
#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
/******************** Bit definition for APB2FZ1 register ************/
diff --git a/Include/stm32h725xx.h b/Include/stm32h725xx.h
index 56eb393..24aeb69 100644
--- a/Include/stm32h725xx.h
+++ b/Include/stm32h725xx.h
@@ -21653,7 +21653,7 @@
#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U)
#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
/******************** Bit definition for APB2FZ1 register ************/
diff --git a/Include/stm32h730xx.h b/Include/stm32h730xx.h
index 2b2cea2..3785a4c 100644
--- a/Include/stm32h730xx.h
+++ b/Include/stm32h730xx.h
@@ -22128,7 +22128,7 @@
#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U)
#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
/******************** Bit definition for APB2FZ1 register ************/
diff --git a/Include/stm32h730xxq.h b/Include/stm32h730xxq.h
index 01c6a27..ce80012 100644
--- a/Include/stm32h730xxq.h
+++ b/Include/stm32h730xxq.h
@@ -22140,7 +22140,7 @@
#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U)
#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
/******************** Bit definition for APB2FZ1 register ************/
diff --git a/Include/stm32h733xx.h b/Include/stm32h733xx.h
index 2182327..be28e7f 100644
--- a/Include/stm32h733xx.h
+++ b/Include/stm32h733xx.h
@@ -11981,7 +11981,7 @@
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
#define FMC_SDCMR_CTB2_Pos (3U)
#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
@@ -22128,7 +22128,7 @@
#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U)
#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
/******************** Bit definition for APB2FZ1 register ************/
diff --git a/Include/stm32h735xx.h b/Include/stm32h735xx.h
index bc5cd0d..5bab7a1 100644
--- a/Include/stm32h735xx.h
+++ b/Include/stm32h735xx.h
@@ -22140,7 +22140,7 @@
#define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U)
#define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U)
#define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
#define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk
/******************** Bit definition for APB2FZ1 register ************/
