Release v1.10.7
diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md deleted file mode 100644 index 7de3bed..0000000 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ /dev/null
@@ -1,35 +0,0 @@ ---- -name: Bug report -about: Create a report to help us improve -title: '' -labels: '' -assignees: '' - ---- - -**Caution** -The Issues are strictly limited for the reporting of problem encountered with the software provided in this project. -For any other problem related to the STM32 product, the performance, the hardware characteristics and boards, the tools the environment in general, please post a topic in the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). - -**Describe the set-up** - * The board (either ST RPN reference or your custom board) - * IDE or at least the compiler and its version - -**Describe the bug** -A clear and concise description of what the bug is. - -**How To Reproduce** -1. Indicate the global behavior of your application project - -2. The modules that you suspect to be the cause of the problem (Driver, BSP, MW ...) - -3. The use case that generates the problem - -4. How we can reproduce the problem - - -**Additional context** -If you have a first analysis or patch correction, thank you to share your proposal. - -**Screenshots** -If applicable, add screenshots to help explain your problem.
diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml new file mode 100644 index 0000000..7960c73 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -0,0 +1,51 @@ +name: "\U0001F41B Bug Report" +description: Report a bug in the project +title: "[Bug]: " +labels: [bug] +body: + - type: markdown + attributes: + value: | + Thanks for helping us improve the quality of our software! Please provide as much detail as possible. + - type: input + id: bug_summary + attributes: + label: Bug Summary + description: Briefly describe the bug. + placeholder: "The application crashes when..." + validations: + required: true + - type: textarea + id: bug_details + attributes: + label: Detailed Description + description: Provide a detailed description of the bug, including steps to reproduce it. + validations: + required: true + - type: input + id: expected-behavior + attributes: + label: Expected Behavior + description: A clear and concise description of what you expected to happen. + placeholder: Describe the expected behavior + - type: input + id: actual-behavior + attributes: + label: Actual Behavior + description: A clear and concise description of what actually happens. + placeholder: Describe what actually happened + - type: input + id: environment + attributes: + label: Environment + description: Describe the environment in which the bug occurs (e.g., board, compiler, IDE, version). + - type: dropdown + id: severity + attributes: + label: Severity + description: How severe is the bug? + options: + - Critical + - Major + - Normal + - Minor \ No newline at end of file
diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 0000000..bdb8119 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml
@@ -0,0 +1,8 @@ +blank_issues_enabled: false +contact_links: + - name: "\U0001F6E1 Report a security vulnerability" + about: Please refer to the SECURITY.md file for instructions. + url: ./../../SECURITY.md + - name: "\U0001F6F1 Request support" + about: You can reach out to the ST Community. + url: https://community.st.com/s/topiccatalog \ No newline at end of file
diff --git a/.github/ISSUE_TEMPLATE/feature_request.yml b/.github/ISSUE_TEMPLATE/feature_request.yml new file mode 100644 index 0000000..fa02ce5 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/feature_request.yml
@@ -0,0 +1,29 @@ +name: "\U0001F4A1 Feature Request" +description: Suggest a new feature or enhancement +title: "[Feature]: " +labels: [enhancement] +body: + - type: markdown + attributes: + value: | + We appreciate your interest in improving the quality of our software! Please provide details about the feature. + - type: input + id: feature_summary + attributes: + label: Feature Summary + description: Briefly describe the feature or enhancement. + placeholder: "Add support for..." + validations: + required: true + - type: textarea + id: feature_details + attributes: + label: Detailed Description + description: Provide a detailed description of the feature, including potential benefits. + validations: + required: true + - type: input + id: use_case + attributes: + label: Use Case + description: Describe how this feature will be used and who will benefit from it. \ No newline at end of file
diff --git a/.github/ISSUE_TEMPLATE/other-issue.md b/.github/ISSUE_TEMPLATE/other-issue.md deleted file mode 100644 index a424001..0000000 --- a/.github/ISSUE_TEMPLATE/other-issue.md +++ /dev/null
@@ -1,22 +0,0 @@ ---- -name: 'Other Issue ' -about: Generic issue description -title: '' -labels: '' -assignees: '' - ---- - -**Caution** -The Issues are strictly limited for the reporting of problem encountered with the software provided in this project. -For any other problem related to the STM32 product, the performance, the hardware characteristics and boards, the tools the environment in general, please post a topic in the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). - -**Describe the set-up** - * The board (either ST RPN reference or your custom board) - * IDE or at least the compiler and its version - -**Additional context** -If you have a first analysis or a patch proposal, thank you to share your proposal. - -**Screenshots** -If applicable, add screenshots to help explain your problem.
diff --git a/.github/ISSUE_TEMPLATE/question.yml b/.github/ISSUE_TEMPLATE/question.yml new file mode 100644 index 0000000..09f8e02 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/question.yml
@@ -0,0 +1,24 @@ +name: "\U0001F4AC Question" +description: Ask a question about the project +title: "[Question]: " +labels: [question] +body: + - type: markdown + attributes: + value: | + Have a question? We're here to help! Please provide details about your inquiry. + - type: input + id: question_summary + attributes: + label: Question Summary + description: Briefly describe your question. + placeholder: "How do I..." + validations: + required: true + - type: textarea + id: question_details + attributes: + label: Detailed Description + description: Provide a detailed description of your question, including any relevant context. + validations: + required: true \ No newline at end of file
diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md deleted file mode 100644 index 18d5a4f..0000000 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ /dev/null
@@ -1,8 +0,0 @@ -## IMPORTANT INFORMATION - -### Contributor License Agreement (CLA) -* The Pull Request feature will be considered by STMicroelectronics after the signature of a **Contributor License Agreement (CLA)** by the submiter. -* If you have not signed such agreement, please follow the rules mentioned in the [CONTRIBUTING.md](https://github.com/STMicroelectronics/cmsis_device_h7/blob/master/CONTRIBUTING.md) file. - - -
diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md index 0952b04..bf0ca35 100644 --- a/CODE_OF_CONDUCT.md +++ b/CODE_OF_CONDUCT.md
@@ -55,8 +55,8 @@ ## Enforcement Instances of abusive, harassing, or otherwise unacceptable behavior may be -reported by contacting the project team at https://www.st.com/content/st_com/en/contact-us.html. All -complaints will be reviewed and investigated and will result in a response that +reported by contacting the project team via this [link](https://www.st.com/content/st_com/en/contact-us.html). +All complaints will be reviewed and investigated and will result in a response that is deemed necessary and appropriate to the circumstances. The project team is obligated to maintain confidentiality with regard to the reporter of an incident. Further details of specific enforcement policies may be posted separately. @@ -67,10 +67,7 @@ ## Attribution -This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, -available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html +This Code of Conduct is adapted from the [Contributor Covenant](https://www.contributor-covenant.org), version 1.4, +available [here](https://www.contributor-covenant.org/version/1/4/code-of-conduct.html). -[homepage]: https://www.contributor-covenant.org - -For answers to common questions about this code of conduct, see -https://www.contributor-covenant.org/faq +For answers to common questions about this code of conduct, refer to the FAQ section [here](https://www.contributor-covenant.org/faq).
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 8668d97..f0d0cbb 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md
@@ -1,40 +1,46 @@ # Contributing guide -This guide serves as a checklist before contributing to this repository. It mainly focuses on the steps to follow to submit an issue or a pull-request. +This guide mainly focuses on the steps to follow to submit an issue or a pull request. ## 1. Issues ### 1.1 Before opening an issue -Please check the following points before posting an issue: -* Make sure you are using the latest commit (major releases are tagged, but corrections are available as new commits). -* Make sure your issue is a question/feedback/suggestions **related to** the software provided in this repository. Otherwise, please refer to section [3](CONTRIBUTING.md#3-support-requests-and-questions) below. -* Make sure your issue is not already reported/fixed on GitHub or discussed on a previous issue. Do not forget to browse into the **closed** issues. +Before posting an issue, please ensure: +* You are using the latest commit. +* Your issue is **not** a vulnerability. Otherwise, please refer to section [3](CONTRIBUTING.md#3-vulnerabilities) below. +* Your issue is **related to** the software provided in this repository. Otherwise, please refer to section [4](CONTRIBUTING.md#4-support-requests-and-miscellaneous) below. +* Your issue is not already reported, fixed or discussed in a previous one. Remember to browse the **closed** issues. ### 1.2 Posting the issue -When you have checked the previous points, create a new report from the **Issues** tab of this repository. A template is available [here](../../issues/new/choose) to help you report the issue you are facing or the enhancement you would like to propose. +When you have checked the previous points, create a new report from the **Issues** tab of this repository. A couple of templates are available [here](../../issues/new/choose). ## 2. Pull Requests -### 2.1 Before opening a pull-request +### 2.1 Before opening a pull request STMicrolectronics is happy to receive contributions from the community, based on an initial Contributor License Agreement (CLA) procedure. -* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an Individual [CLA](https://cla.st.com). -* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a Corporate [CLA](https://cla.st.com) mentioning your GitHub account name. +* If you are an individual writing original source code and you are sure **you own the intellectual property**, then you need to sign an **Individual** [CLA](https://cla.st.com). +* If you work for a company that wants also to allow you to contribute with your work, your company needs to provide a **Corporate** [CLA](https://cla.st.com) mentioning your GitHub account name. * If you are not sure that a CLA (Individual or Corporate) has been signed for your GitHub account you can check the [CLA](https://cla.st.com) dedicated page. -Please note that: -* The Corporate CLA will always take precedence over the Individual CLA. -* One CLA submission is sufficient, for any project proposed by STMicroelectronics. +> [!IMPORTANT] +> Please note that: +> * The Corporate CLA will always take precedence over the Individual CLA. +> * One CLA submission is sufficient, for any project proposed by STMicroelectronics. ### 2.2 How to proceed * We recommend to engage first a communication thru an issue, in order to present your proposal, just to confirm that it corresponds to STMicroelectronics' domain or scope. * Then fork the project to your GitHub account to further develop your contribution. Please use the latest commit version. -* Please, submit one pull-request per new feature or proposal. This will ease the analysis and the final merge if accepted. +* Please, submit one pull request per new feature or proposal. This will ease the analysis and the final merge if accepted. -## 3. Support requests and questions +## 3. Vulnerabilities -For support requests or any other question related to the product, the tools, the environment, you can submit a post to the **ST Community** on the appropriate topic [page](https://community.st.com/s/topiccatalog). +To report a **vulnerability**, please refer to the [SECURITY.md](./SECURITY.md) file for instructions. + +## 4. Support requests and miscellaneous + +For support requests or any other topics not related to the content of this repository, you can submit a post to the **ST Community** on the appropriate topic [page](https://community.st.com/s/topiccatalog).
diff --git a/Include/stm32h723xx.h b/Include/stm32h723xx.h index 102e476..0507a00 100644 --- a/Include/stm32h723xx.h +++ b/Include/stm32h723xx.h
@@ -16452,10 +16452,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -19893,7 +19893,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -23694,7 +23694,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h725xx.h b/Include/stm32h725xx.h index 64d4ab6..b918b4b 100644 --- a/Include/stm32h725xx.h +++ b/Include/stm32h725xx.h
@@ -16464,10 +16464,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -19905,7 +19905,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -23706,7 +23706,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h730xx.h b/Include/stm32h730xx.h index 8197cd2..fda3af8 100644 --- a/Include/stm32h730xx.h +++ b/Include/stm32h730xx.h
@@ -16939,10 +16939,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -20380,7 +20380,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -24185,7 +24185,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h730xxq.h b/Include/stm32h730xxq.h index 8036b39..b113db7 100644 --- a/Include/stm32h730xxq.h +++ b/Include/stm32h730xxq.h
@@ -16951,10 +16951,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -20392,7 +20392,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -24197,7 +24197,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h733xx.h b/Include/stm32h733xx.h index a681f1b..c2ef946 100644 --- a/Include/stm32h733xx.h +++ b/Include/stm32h733xx.h
@@ -16939,10 +16939,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -20380,7 +20380,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -24185,7 +24185,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h735xx.h b/Include/stm32h735xx.h index a7b5b0d..3b121e6 100644 --- a/Include/stm32h735xx.h +++ b/Include/stm32h735xx.h
@@ -16951,10 +16951,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -20392,7 +20392,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -24197,7 +24197,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h742xx.h b/Include/stm32h742xx.h index c99ca34..713a5e6 100644 --- a/Include/stm32h742xx.h +++ b/Include/stm32h742xx.h
@@ -19262,7 +19262,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -25361,7 +25361,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h743xx.h b/Include/stm32h743xx.h index d636fbc..7d57432 100644 --- a/Include/stm32h743xx.h +++ b/Include/stm32h743xx.h
@@ -19910,7 +19910,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -26009,7 +26009,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h745xg.h b/Include/stm32h745xg.h index 66b80c9..aff3917 100644 --- a/Include/stm32h745xg.h +++ b/Include/stm32h745xg.h
@@ -20572,7 +20572,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -26783,8 +26783,8 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) /******************** Bit definition for HSEM_CR register *****************/ -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ -#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ +#define HSEM_CPU2_COREID (0x00000001UL) /* Semaphore Core CM4 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) #if defined(CORE_CM4)
diff --git a/Include/stm32h745xx.h b/Include/stm32h745xx.h index f29b4db..196b46d 100644 --- a/Include/stm32h745xx.h +++ b/Include/stm32h745xx.h
@@ -20572,7 +20572,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -26783,8 +26783,8 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) /******************** Bit definition for HSEM_CR register *****************/ -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ -#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ +#define HSEM_CPU2_COREID (0x00000001UL) /* Semaphore Core CM4 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) #if defined(CORE_CM4)
diff --git a/Include/stm32h747xg.h b/Include/stm32h747xg.h index 2192c58..2a59490 100644 --- a/Include/stm32h747xg.h +++ b/Include/stm32h747xg.h
@@ -23745,7 +23745,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -29956,8 +29956,8 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) /******************** Bit definition for HSEM_CR register *****************/ -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ -#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ +#define HSEM_CPU2_COREID (0x00000001UL) /* Semaphore Core CM4 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) #if defined(CORE_CM4)
diff --git a/Include/stm32h747xx.h b/Include/stm32h747xx.h index 10f9bb1..9f43fa8 100644 --- a/Include/stm32h747xx.h +++ b/Include/stm32h747xx.h
@@ -23745,7 +23745,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -29956,8 +29956,8 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) /******************** Bit definition for HSEM_CR register *****************/ -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ -#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ +#define HSEM_CPU2_COREID (0x00000001UL) /* Semaphore Core CM4 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) #if defined(CORE_CM4)
diff --git a/Include/stm32h750xx.h b/Include/stm32h750xx.h index 1e3119f..fe0f458 100644 --- a/Include/stm32h750xx.h +++ b/Include/stm32h750xx.h
@@ -20191,7 +20191,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -26290,7 +26290,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h753xx.h b/Include/stm32h753xx.h index 3fc2624..96591fa 100644 --- a/Include/stm32h753xx.h +++ b/Include/stm32h753xx.h
@@ -20197,7 +20197,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -26296,7 +26296,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h755xx.h b/Include/stm32h755xx.h index edd31b1..a596819 100644 --- a/Include/stm32h755xx.h +++ b/Include/stm32h755xx.h
@@ -20859,7 +20859,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -27070,8 +27070,8 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) /******************** Bit definition for HSEM_CR register *****************/ -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ -#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ +#define HSEM_CPU2_COREID (0x00000001UL) /* Semaphore Core CM4 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) #if defined(CORE_CM4)
diff --git a/Include/stm32h757xx.h b/Include/stm32h757xx.h index 5e639ad..1e5df1f 100644 --- a/Include/stm32h757xx.h +++ b/Include/stm32h757xx.h
@@ -24032,7 +24032,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -30243,8 +30243,8 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) /******************** Bit definition for HSEM_CR register *****************/ -#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ -#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ +#define HSEM_CPU1_COREID (0x00000003UL) /* Semaphore Core CM7 ID */ +#define HSEM_CPU2_COREID (0x00000001UL) /* Semaphore Core CM4 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) #if defined(CORE_CM4)
diff --git a/Include/stm32h7a3xx.h b/Include/stm32h7a3xx.h index 7abcda7..4540f03 100644 --- a/Include/stm32h7a3xx.h +++ b/Include/stm32h7a3xx.h
@@ -14628,10 +14628,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -18157,7 +18157,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -21931,7 +21931,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000001UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h7a3xxq.h b/Include/stm32h7a3xxq.h index 63ebfdd..c8c1a9a 100644 --- a/Include/stm32h7a3xxq.h +++ b/Include/stm32h7a3xxq.h
@@ -14640,10 +14640,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -18169,7 +18169,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -21943,7 +21943,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000001UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h7b0xx.h b/Include/stm32h7b0xx.h index ead4b0b..fdd395e 100644 --- a/Include/stm32h7b0xx.h +++ b/Include/stm32h7b0xx.h
@@ -15108,10 +15108,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -18637,7 +18637,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -22415,7 +22415,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000001UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h7b0xxq.h b/Include/stm32h7b0xxq.h index e5e1f5d..9b9d739 100644 --- a/Include/stm32h7b0xxq.h +++ b/Include/stm32h7b0xxq.h
@@ -15120,10 +15120,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -18649,7 +18649,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -22427,7 +22427,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000001UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h7b3xx.h b/Include/stm32h7b3xx.h index 4732348..95d40ba 100644 --- a/Include/stm32h7b3xx.h +++ b/Include/stm32h7b3xx.h
@@ -15115,10 +15115,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -18644,7 +18644,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -22422,7 +22422,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000001UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h7b3xxq.h b/Include/stm32h7b3xxq.h index afa83e9..fe8acc9 100644 --- a/Include/stm32h7b3xxq.h +++ b/Include/stm32h7b3xxq.h
@@ -15127,10 +15127,10 @@ #define RNG_CR_CLKDIV_Pos (16U) #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */ #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ #define RNG_CR_RNG_CONFIG1_Pos (20U) #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */ #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk @@ -18656,7 +18656,7 @@ /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ #define TIM_CCR5_GC5C1_Pos (29U) #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ @@ -22434,7 +22434,7 @@ /******************************** HSEM Instances *******************************/ #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) -#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ +#define HSEM_CPU1_COREID (0x00000001UL) /* Semaphore Core CM7 ID */ #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
diff --git a/Include/stm32h7xx.h b/Include/stm32h7xx.h index 283ab60..f8751d0 100644 --- a/Include/stm32h7xx.h +++ b/Include/stm32h7xx.h
@@ -99,11 +99,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.10.6 + * @brief CMSIS Device version number V1.10.7 */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */ -#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ +#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
diff --git a/Include/system_stm32h7xx.h b/Include/system_stm32h7xx.h index 2610741..cfb383d 100644 --- a/Include/system_stm32h7xx.h +++ b/Include/system_stm32h7xx.h
@@ -84,7 +84,11 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); -extern void ExitRun0Mode(void); +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + extern void ExitRun0Mode(void) __attribute__((optimize("Os"))); +#else + extern void ExitRun0Mode(void); +#endif /* __GNUC__ */ /** * @} */
diff --git a/README.md b/README.md index 25e4668..7d29260 100644 --- a/README.md +++ b/README.md
@@ -1,6 +1,6 @@ # STM32CubeH7 CMSIS Device MCU Component - + ## Overview
diff --git a/Release_Notes.html b/Release_Notes.html index 2d5aaa3..6b76f91 100644 --- a/Release_Notes.html +++ b/Release_Notes.html
@@ -30,10 +30,23 @@ <div class="col-sm-12 col-lg-8"> <h1 id="update-history"><strong>Update History</strong></h1> <div class="collapse"> -<input type="checkbox" id="collapse-section18" checked aria-hidden="true"> <label for="collapse-section18" aria-hidden="true"><strong>V1.10.6 / 06-December-2024</strong></label> +<input type="checkbox" id="collapse-section19" checked aria-hidden="true"> <label for="collapse-section19" aria-hidden="true"><strong>V1.10.7 / 04-February-2026</strong></label> <div> <h2 id="main-changes">Main Changes</h2> <ul> +<li>Fix typos in GPIO MODER bit naming definitions (no need to add legacy defines).</li> +<li>Add QUADSPI_CCR_FRCM bit definitions.</li> +<li>Move the check for the ‘DUAL_CORE’ symbol after including the header file where it is defined.</li> +<li>Allow external redefinition of the macro ‘VECT_TAB_OFFSET’ via IDE, makefile, or command line.</li> +<li>Fix the Capture Compare register TIMx_CCR5 definition.</li> +</ul> +</div> +</div> +<div class="collapse"> +<input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true"><strong>V1.10.6 / 06-December-2024</strong></label> +<div> +<h2 id="main-changes-1">Main Changes</h2> +<ul> <li><strong>system_stm32h7xx.c template files</strong> <ul> <li>Fix computed frequencies returned by the HAL_RCC_GetHCLKFreq(), HAL_RCC_GetPCLK1Freq(), and HAL_RCC_GetPCLK2Freq() APIs.</li> @@ -59,7 +72,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true"><strong>V1.10.5 / 30-October-2024</strong></label> <div> -<h2 id="main-changes-1">Main Changes</h2> +<h2 id="main-changes-2">Main Changes</h2> <ul> <li>Update startup files to safely exit from Run* mode. <ul> @@ -77,7 +90,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true"><strong>V1.10.4 / 15-March-2024</strong></label> <div> -<h2 id="main-changes-2">Main Changes</h2> +<h2 id="main-changes-3">Main Changes</h2> <ul> <li>Update the values of the sensor calibration temperatures for H742, H743, and H753 part numbers.</li> <li>Remove the unsupported MDMA BASE channel.</li> @@ -92,7 +105,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.10.3 / 23-September-2022</strong></label> <div> -<h2 id="main-changes-3">Main Changes</h2> +<h2 id="main-changes-4">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.</li> @@ -103,7 +116,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.2 / 12-February-2022</strong></label> <div> -<h2 id="main-changes-4">Main Changes</h2> +<h2 id="main-changes-5">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>Add support for ADC LDO output voltage ready bit.</li> @@ -118,7 +131,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label> <div> -<h2 id="main-changes-5">Main Changes</h2> +<h2 id="main-changes-6">Main Changes</h2> <ul> <li>General updates to fix known defects and implementation enhancements</li> <li>All source files: update disclaimer to add reference to the new license agreement.</li> @@ -144,7 +157,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label> <div> -<h2 id="main-changes-6">Main Changes</h2> +<h2 id="main-changes-7">Main Changes</h2> <ul> <li>Fix minor issues related to English typo in comments of registers and fields description</li> <li>Update STM32H7 devices header files to add GPV registers definition, base address and instance</li> @@ -162,7 +175,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label> <div> -<h2 id="main-changes-7">Main Changes</h2> +<h2 id="main-changes-8">Main Changes</h2> <ul> <li>Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices: <ul> @@ -220,7 +233,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label> <div> -<h2 id="main-changes-8">Main Changes</h2> +<h2 id="main-changes-9">Main Changes</h2> <ul> <li>General updates to align Bits and registers definitions with the STM32H7 reference manual</li> <li>Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero</li> @@ -241,7 +254,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label> <div> -<h2 id="main-changes-9">Main Changes</h2> +<h2 id="main-changes-10">Main Changes</h2> <ul> <li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li> <li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: @@ -271,7 +284,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label> <div> -<h2 id="main-changes-10">Main Changes</h2> +<h2 id="main-changes-11">Main Changes</h2> <ul> <li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li> <li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li> @@ -286,7 +299,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label> <div> -<h2 id="main-changes-11">Main Changes</h2> +<h2 id="main-changes-12">Main Changes</h2> <ul> <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li> <li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li> @@ -350,7 +363,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label> <div> -<h2 id="main-changes-12">Main Changes</h2> +<h2 id="main-changes-13">Main Changes</h2> <ul> <li><strong>Patch Release on top of V1.3.0</strong></li> <li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -363,7 +376,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label> <div> -<h2 id="main-changes-13">Main Changes</h2> +<h2 id="main-changes-14">Main Changes</h2> <ul> <li>STM32H7xx include files: <ul> @@ -408,7 +421,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label> <div> -<h2 id="main-changes-14">Main Changes</h2> +<h2 id="main-changes-15">Main Changes</h2> <ul> <li>Add support for stm32h750xx value line devices: <ul> @@ -421,7 +434,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label> <div> -<h2 id="main-changes-15">Main Changes</h2> +<h2 id="main-changes-16">Main Changes</h2> <ul> <li>Update FDCAN bit definition</li> <li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li> @@ -431,7 +444,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label> <div> -<h2 id="main-changes-16">Main Changes</h2> +<h2 id="main-changes-17">Main Changes</h2> <ul> <li>Update USB OTG bit definition</li> <li>Adjust PLL fractional computation</li> @@ -441,7 +454,7 @@ <div class="collapse"> <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label> <div> -<h2 id="main-changes-17">Main Changes</h2> +<h2 id="main-changes-18">Main Changes</h2> <ul> <li>First official release for <strong>STM32H743xx/753xx</strong> devices</li> </ul>
diff --git a/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld index cb4f989..1d52187 100644 --- a/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h745xg_flash_CM4.ld
@@ -136,7 +136,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld index 4723385..5294029 100644 --- a/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h745xg_flash_CM7.ld
@@ -147,7 +147,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld index e6811bf..d93fbd2 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_flash_CM4.ld
@@ -136,7 +136,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld index a95eed3..2df6ff2 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld
@@ -147,7 +147,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld index 0cc9ff3..567f33b 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_sram1_CM7.ld
@@ -136,7 +136,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld index db7719a..08c89f6 100644 --- a/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h745xx_sram2_CM4.ld
@@ -136,7 +136,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld index cb4f989..1d52187 100644 --- a/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h747xg_flash_CM4.ld
@@ -136,7 +136,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld index 4723385..5294029 100644 --- a/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h747xg_flash_CM7.ld
@@ -147,7 +147,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld index e6811bf..d93fbd2 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_flash_CM4.ld
@@ -136,7 +136,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld index a95eed3..2df6ff2 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_flash_CM7.ld
@@ -147,7 +147,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld index 1abac8c..4f3c6a4 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_sram1_CM7.ld
@@ -135,7 +135,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld index db7719a..08c89f6 100644 --- a/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h747xx_sram2_CM4.ld
@@ -136,7 +136,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld index 4752465..23c4b07 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_flash_CM4.ld
@@ -135,7 +135,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld index cec5128..dd122cc 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_flash_CM7.ld
@@ -146,7 +146,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld index 1abac8c..4f3c6a4 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_sram1_CM7.ld
@@ -135,7 +135,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld index 5c112dd..cc4a252 100644 --- a/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h755xx_sram2_CM4.ld
@@ -137,7 +137,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld b/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld index 4752465..23c4b07 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_flash_CM4.ld
@@ -135,7 +135,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld b/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld index cec5128..dd122cc 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_flash_CM7.ld
@@ -146,7 +146,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld b/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld index 1abac8c..4f3c6a4 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_sram1_CM7.ld
@@ -135,7 +135,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld b/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld index aa29003..44e6a51 100644 --- a/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld +++ b/Source/Templates/gcc/linker/stm32h757xx_sram2_CM4.ld
@@ -135,7 +135,7 @@ . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss)
diff --git a/Source/Templates/gcc/startup_stm32h723xx.s b/Source/Templates/gcc/startup_stm32h723xx.s index 631bcc1..d61e404 100644 --- a/Source/Templates/gcc/startup_stm32h723xx.s +++ b/Source/Templates/gcc/startup_stm32h723xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h725xx.s b/Source/Templates/gcc/startup_stm32h725xx.s index 0ed928e..94982ec 100644 --- a/Source/Templates/gcc/startup_stm32h725xx.s +++ b/Source/Templates/gcc/startup_stm32h725xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h730xx.s b/Source/Templates/gcc/startup_stm32h730xx.s index c1b539f..94739d9 100644 --- a/Source/Templates/gcc/startup_stm32h730xx.s +++ b/Source/Templates/gcc/startup_stm32h730xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h730xxq.s b/Source/Templates/gcc/startup_stm32h730xxq.s index 3869e39..e153ff3 100644 --- a/Source/Templates/gcc/startup_stm32h730xxq.s +++ b/Source/Templates/gcc/startup_stm32h730xxq.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h733xx.s b/Source/Templates/gcc/startup_stm32h733xx.s index d6db131..d41a693 100644 --- a/Source/Templates/gcc/startup_stm32h733xx.s +++ b/Source/Templates/gcc/startup_stm32h733xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h735xx.s b/Source/Templates/gcc/startup_stm32h735xx.s index 7273c14..9f89524 100644 --- a/Source/Templates/gcc/startup_stm32h735xx.s +++ b/Source/Templates/gcc/startup_stm32h735xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h742xx.s b/Source/Templates/gcc/startup_stm32h742xx.s index e25ddd4..6f471df 100644 --- a/Source/Templates/gcc/startup_stm32h742xx.s +++ b/Source/Templates/gcc/startup_stm32h742xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h743xx.s b/Source/Templates/gcc/startup_stm32h743xx.s index 2663d53..1456354 100644 --- a/Source/Templates/gcc/startup_stm32h743xx.s +++ b/Source/Templates/gcc/startup_stm32h743xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h745xg.s b/Source/Templates/gcc/startup_stm32h745xg.s index c04b81c..50aab38 100644 --- a/Source/Templates/gcc/startup_stm32h745xg.s +++ b/Source/Templates/gcc/startup_stm32h745xg.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h745xx.s b/Source/Templates/gcc/startup_stm32h745xx.s index c04b81c..50aab38 100644 --- a/Source/Templates/gcc/startup_stm32h745xx.s +++ b/Source/Templates/gcc/startup_stm32h745xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h747xg.s b/Source/Templates/gcc/startup_stm32h747xg.s index 11fedce..47c158d 100644 --- a/Source/Templates/gcc/startup_stm32h747xg.s +++ b/Source/Templates/gcc/startup_stm32h747xg.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h747xx.s b/Source/Templates/gcc/startup_stm32h747xx.s index 9374976..e3c11b9 100644 --- a/Source/Templates/gcc/startup_stm32h747xx.s +++ b/Source/Templates/gcc/startup_stm32h747xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h750xx.s b/Source/Templates/gcc/startup_stm32h750xx.s index 0290118..2983fd5 100644 --- a/Source/Templates/gcc/startup_stm32h750xx.s +++ b/Source/Templates/gcc/startup_stm32h750xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h753xx.s b/Source/Templates/gcc/startup_stm32h753xx.s index 1c9d691..033bc78 100644 --- a/Source/Templates/gcc/startup_stm32h753xx.s +++ b/Source/Templates/gcc/startup_stm32h753xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h755xx.s b/Source/Templates/gcc/startup_stm32h755xx.s index 5fce528..94ad9f3 100644 --- a/Source/Templates/gcc/startup_stm32h755xx.s +++ b/Source/Templates/gcc/startup_stm32h755xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h757xx.s b/Source/Templates/gcc/startup_stm32h757xx.s index 81f80f0..4ee45c8 100644 --- a/Source/Templates/gcc/startup_stm32h757xx.s +++ b/Source/Templates/gcc/startup_stm32h757xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h7a3xx.s b/Source/Templates/gcc/startup_stm32h7a3xx.s index 26c26a2..6c2e38c 100644 --- a/Source/Templates/gcc/startup_stm32h7a3xx.s +++ b/Source/Templates/gcc/startup_stm32h7a3xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h7a3xxq.s b/Source/Templates/gcc/startup_stm32h7a3xxq.s index c81981d..f3b7963 100644 --- a/Source/Templates/gcc/startup_stm32h7a3xxq.s +++ b/Source/Templates/gcc/startup_stm32h7a3xxq.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h7b0xx.s b/Source/Templates/gcc/startup_stm32h7b0xx.s index 264550c..8e9cc68 100644 --- a/Source/Templates/gcc/startup_stm32h7b0xx.s +++ b/Source/Templates/gcc/startup_stm32h7b0xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h7b0xxq.s b/Source/Templates/gcc/startup_stm32h7b0xxq.s index b01f33d..768ff01 100644 --- a/Source/Templates/gcc/startup_stm32h7b0xxq.s +++ b/Source/Templates/gcc/startup_stm32h7b0xxq.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h7b3xx.s b/Source/Templates/gcc/startup_stm32h7b3xx.s index bc79176..a05a0c7 100644 --- a/Source/Templates/gcc/startup_stm32h7b3xx.s +++ b/Source/Templates/gcc/startup_stm32h7b3xx.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**
diff --git a/Source/Templates/gcc/startup_stm32h7b3xxq.s b/Source/Templates/gcc/startup_stm32h7b3xxq.s index 232092f..d8b1574 100644 --- a/Source/Templates/gcc/startup_stm32h7b3xxq.s +++ b/Source/Templates/gcc/startup_stm32h7b3xxq.s
@@ -98,8 +98,10 @@ /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ - bl main - bx lr + bl main +LoopForever: + b LoopForever + .size Reset_Handler, .-Reset_Handler /**