Release v1.7.2
diff --git a/Include/stm32l412xx.h b/Include/stm32l412xx.h
index d38b033..ce0ecc6 100644
--- a/Include/stm32l412xx.h
+++ b/Include/stm32l412xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1011,6 +1010,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1161,7 +1169,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -10910,4 +10918,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l422xx.h b/Include/stm32l422xx.h
index e1bc0e6..42a94bd 100644
--- a/Include/stm32l422xx.h
+++ b/Include/stm32l422xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1046,6 +1045,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1196,7 +1204,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -11138,4 +11146,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l431xx.h b/Include/stm32l431xx.h
index 7bf6011..a0dc414 100644
--- a/Include/stm32l431xx.h
+++ b/Include/stm32l431xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1145,6 +1144,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1295,7 +1303,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -15065,4 +15073,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l432xx.h b/Include/stm32l432xx.h
index 227313b..29525a9 100644
--- a/Include/stm32l432xx.h
+++ b/Include/stm32l432xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1130,6 +1129,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1280,7 +1288,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -14859,4 +14867,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l433xx.h b/Include/stm32l433xx.h
index 661009f..cade0c2 100644
--- a/Include/stm32l433xx.h
+++ b/Include/stm32l433xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1204,6 +1203,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1354,7 +1362,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -15963,4 +15971,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l442xx.h b/Include/stm32l442xx.h
index 889d442..586891c 100644
--- a/Include/stm32l442xx.h
+++ b/Include/stm32l442xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1165,6 +1164,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1315,7 +1323,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -15087,4 +15095,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l443xx.h b/Include/stm32l443xx.h
index d42b8a9..0b4c473 100644
--- a/Include/stm32l443xx.h
+++ b/Include/stm32l443xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1239,6 +1238,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1389,7 +1397,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -16191,4 +16199,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l451xx.h b/Include/stm32l451xx.h
index 571a32e..af43134 100644
--- a/Include/stm32l451xx.h
+++ b/Include/stm32l451xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1187,6 +1186,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1341,7 +1349,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -15326,4 +15334,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l452xx.h b/Include/stm32l452xx.h
index 096762f..aa46feb 100644
--- a/Include/stm32l452xx.h
+++ b/Include/stm32l452xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1229,6 +1228,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1383,7 +1391,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -16070,4 +16078,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l462xx.h b/Include/stm32l462xx.h
index 2bb58c7..7a47c23 100644
--- a/Include/stm32l462xx.h
+++ b/Include/stm32l462xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1264,6 +1263,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1418,7 +1426,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -16298,4 +16306,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l471xx.h b/Include/stm32l471xx.h
index 8347a8e..20bbdb6 100644
--- a/Include/stm32l471xx.h
+++ b/Include/stm32l471xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1301,6 +1300,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1451,7 +1459,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -7603,7 +7611,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
@@ -16842,4 +16850,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l475xx.h b/Include/stm32l475xx.h
index 09a3ca2..bb1ed05 100644
--- a/Include/stm32l475xx.h
+++ b/Include/stm32l475xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1438,6 +1437,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1588,7 +1596,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -7758,7 +7766,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
@@ -18330,4 +18338,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l476xx.h b/Include/stm32l476xx.h
index 61341a7..3971ae9 100644
--- a/Include/stm32l476xx.h
+++ b/Include/stm32l476xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1455,6 +1454,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1605,7 +1613,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -7781,7 +7789,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
@@ -9692,6 +9700,9 @@
/******************** Bit definition for PWR_CR4 register ********************/
+#define PWR_CR4_EXT_SMPS_ON_Pos (13U)
+#define PWR_CR4_EXT_SMPS_ON_Msk (0x1UL << PWR_CR4_EXT_SMPS_ON_Pos) /*!< 0x00002000 */
+#define PWR_CR4_EXT_SMPS_ON PWR_CR4_EXT_SMPS_ON_Msk /*!< Inform the internal regulator on external SMPS switch status */
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
@@ -9718,6 +9729,9 @@
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
+#define PWR_SR1_EXT_SMPS_RDY_Pos (13U)
+#define PWR_SR1_EXT_SMPS_RDY_Msk (0x1UL << PWR_SR1_EXT_SMPS_RDY_Pos) /*!< 0x00002000 */
+#define PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY_Msk /*!< Switching to external SMPS Ready Flag */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
@@ -18484,4 +18498,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l485xx.h b/Include/stm32l485xx.h
index 1bc37e5..45d2643 100644
--- a/Include/stm32l485xx.h
+++ b/Include/stm32l485xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1473,6 +1472,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1623,7 +1631,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -7974,7 +7982,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
@@ -18558,4 +18566,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l486xx.h b/Include/stm32l486xx.h
index 172b260..da9e344 100644
--- a/Include/stm32l486xx.h
+++ b/Include/stm32l486xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1490,6 +1489,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1640,7 +1648,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -7997,7 +8005,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
@@ -18712,4 +18720,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l496xx.h b/Include/stm32l496xx.h
index 5c1cc03..27a9921 100644
--- a/Include/stm32l496xx.h
+++ b/Include/stm32l496xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1540,6 +1539,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1694,7 +1702,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -8633,7 +8641,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -19736,4 +19744,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4a6xx.h b/Include/stm32l4a6xx.h
index c06aecd..a537256 100644
--- a/Include/stm32l4a6xx.h
+++ b/Include/stm32l4a6xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1604,6 +1603,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1758,7 +1766,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -8878,7 +8886,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -20079,4 +20087,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4p5xx.h b/Include/stm32l4p5xx.h
index 8398e57..6cb7c2d 100644
--- a/Include/stm32l4p5xx.h
+++ b/Include/stm32l4p5xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1751,6 +1750,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1905,7 +1913,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -9066,7 +9074,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -10931,7 +10939,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active Height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -10940,7 +10948,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -13831,6 +13839,9 @@
/* */
/******************************************************************************/
#define RNG_VER_3_2
+#define RNG_CR_CONFIG_VAL 0x00F00D00U /*!< Default CONFIG 1,2,3 in CR register */
+#define RNG_HTCFG 0x0000AA74U /*!< HTCR recommended value for best latency and NIST compliance */
+#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
@@ -21149,4 +21160,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4q5xx.h b/Include/stm32l4q5xx.h
index 58ad12a..cf0dd5c 100644
--- a/Include/stm32l4q5xx.h
+++ b/Include/stm32l4q5xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1803,6 +1802,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1957,7 +1965,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -9306,7 +9314,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11171,7 +11179,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active Height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11180,7 +11188,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -11722,12 +11730,12 @@
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
@@ -11763,13 +11771,13 @@
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
-/* Modular substraction input data */
+/* Modular subtraction input data */
#define PKA_MODULAR_SUB_NB_BITS ((0x0404UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x08B4UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0x0A44UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x0D5CUL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
-/* Modular substraction output data */
+/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0x0BD0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
@@ -14342,6 +14350,9 @@
/* */
/******************************************************************************/
#define RNG_VER_3_2
+#define RNG_CR_CONFIG_VAL 0x00F00D00U /*!< Default CONFIG 1,2,3 in CR register */
+#define RNG_HTCFG 0x0000AA74U /*!< HTCR recommended value for best latency and NIST compliance */
+#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
@@ -21666,4 +21677,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4r5xx.h b/Include/stm32l4r5xx.h
index 04d6d1d..ea347b1 100644
--- a/Include/stm32l4r5xx.h
+++ b/Include/stm32l4r5xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1607,6 +1606,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1760,7 +1768,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -8784,7 +8792,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -20112,4 +20120,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4r7xx.h b/Include/stm32l4r7xx.h
index b990073..0fa05e8 100644
--- a/Include/stm32l4r7xx.h
+++ b/Include/stm32l4r7xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1693,6 +1692,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1846,7 +1854,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -8870,7 +8878,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -10749,7 +10757,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active Height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -10758,7 +10766,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -20617,4 +20625,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4r9xx.h b/Include/stm32l4r9xx.h
index 47af355..e197298 100644
--- a/Include/stm32l4r9xx.h
+++ b/Include/stm32l4r9xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -568,7 +567,7 @@
uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
- __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
@@ -1775,6 +1774,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1928,7 +1936,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -8181,7 +8189,7 @@
#define DSI_LCOLCR_LPE_Pos (8U)
#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
-#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
+#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */
/******************* Bit definition for DSI_LPCR register ***************/
#define DSI_LPCR_DEP_Pos (0U)
@@ -11989,7 +11997,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -13868,7 +13876,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active Height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -13877,7 +13885,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -23749,4 +23757,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4s5xx.h b/Include/stm32l4s5xx.h
index f4d974d..c730d6f 100644
--- a/Include/stm32l4s5xx.h
+++ b/Include/stm32l4s5xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1671,6 +1670,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1824,7 +1832,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -9036,7 +9044,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -20462,4 +20470,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4s7xx.h b/Include/stm32l4s7xx.h
index 37b848e..2bce416 100644
--- a/Include/stm32l4s7xx.h
+++ b/Include/stm32l4s7xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -1757,6 +1756,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1910,7 +1918,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -9122,7 +9130,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -11078,7 +11086,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active Height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -11087,7 +11095,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -20967,4 +20975,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4s9xx.h b/Include/stm32l4s9xx.h
index 3e59484..673a682 100644
--- a/Include/stm32l4s9xx.h
+++ b/Include/stm32l4s9xx.h
@@ -7,18 +7,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
+ * - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -45,11 +44,11 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
-#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
-#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
-#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __FPU_PRESENT 1 /*!< FPU present */
+#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1U /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
@@ -569,7 +568,7 @@
uint32_t RESERVED7[7]; /*!< Reserved, 0x11C - 0x137 */
__IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
__IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
- __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */
__IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
__IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
__IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
@@ -1839,6 +1838,15 @@
* @{
*/
+/** @addtogroup Hardware_Constant_Definition
+ * @{
+ */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+/**
+ * @}
+ */
+
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
@@ -1992,7 +2000,7 @@
#define ADC_CFGR_ALIGN_Pos (5U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */
#define ADC_CFGR_EXTSEL_Pos (6U)
#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
@@ -8433,7 +8441,7 @@
#define DSI_LCOLCR_LPE_Pos (8U)
#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
-#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
+#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */
/******************* Bit definition for DSI_LPCR register ***************/
#define DSI_LPCR_DEP_Pos (0U)
@@ -12241,7 +12249,7 @@
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
@@ -14197,7 +14205,7 @@
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
-#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
+#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active Height */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
@@ -14206,7 +14214,7 @@
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
-#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
+#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Height */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
@@ -24099,4 +24107,3 @@
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/stm32l4xx.h b/Include/stm32l4xx.h
index f4ae4f7..d1e63c2 100644
--- a/Include/stm32l4xx.h
+++ b/Include/stm32l4xx.h
@@ -8,21 +8,20 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32L4xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -107,7 +106,7 @@
*/
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
-#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
+#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
@@ -224,8 +223,62 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint32_t val; \
+ do { \
+ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
+ do { \
+ uint16_t val; \
+ do { \
+ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+ } while(0)
+
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
@@ -248,7 +301,3 @@
* @}
*/
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Include/system_stm32l4xx.h b/Include/system_stm32l4xx.h
index 00166a5..957a364 100644
--- a/Include/system_stm32l4xx.h
+++ b/Include/system_stm32l4xx.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -104,4 +103,4 @@
/**
* @}
*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/License.md b/License.md
index e0d829b..479c4f6 100644
--- a/License.md
+++ b/License.md
@@ -1,83 +1,27 @@
-Apache License
- Version 2.0, January 2004
- http://www.apache.org/licenses/
+Copyright 2017 STMicroelectronics.
+All rights reserved.
-TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
-1. Definitions.
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
-"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document.
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
-"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License.
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
-"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. For the purposes of this definition, "control" means (i) the power, direct or indirect, to cause the direction or management of such entity, whether by contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the outstanding shares, or (iii) beneficial ownership of such entity.
-
-"You" (or "Your") shall mean an individual or Legal Entity exercising permissions granted by this License.
-
-"Source" form shall mean the preferred form for making modifications, including but not limited to software source code, documentation source, and configuration files.
-
-"Object" form shall mean any form resulting from mechanical transformation or translation of a Source form, including but not limited to compiled object code, generated documentation, and conversions to other media types.
-
-"Work" shall mean the work of authorship, whether in Source or Object form, made available under the License, as indicated by a copyright notice that is included in or attached to the work (an example is provided in the Appendix below).
-
-"Derivative Works" shall mean any work, whether in Source or Object form, that is based on (or derived from) the Work and for which the editorial revisions, annotations, elaborations, or other modifications represent, as a whole, an original work of authorship. For the purposes of this License, Derivative Works shall not include works that remain separable from, or merely link (or bind by name) to the interfaces of, the Work and Derivative Works thereof.
-
-"Contribution" shall mean any work of authorship, including the original version of the Work and any modifications or additions to that Work or Derivative Works thereof, that is intentionally submitted to Licensor for inclusion in the Work by the copyright owner or by an individual or Legal Entity authorized to submit on behalf of the copyright owner. For the purposes of this definition, "submitted" means any form of electronic, verbal, or written communication sent to the Licensor or its representatives, including but not limited to communication on electronic mailing lists, source code control systems, and issue tracking systems that are managed by, or on behalf of, the Licensor for the purpose of discussing and improving the Work, but excluding communication that is conspicuously marked or otherwise designated in writing by the copyright owner as "Not a Contribution."
-
-"Contributor" shall mean Licensor and any individual or Legal Entity on behalf of whom a Contribution has been received by Licensor and subsequently incorporated within the Work.
-
-2. Grant of Copyright License.
-
-Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare Derivative Works of, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form.
-
-3. Grant of Patent License.
-
-Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this section) patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the Work, where such license applies only to those patent claims licensable by such Contributor that are necessarily infringed by their Contribution(s) alone or by combination of their Contribution(s) with the Work to which such Contribution(s) was submitted. If You institute patent litigation against any entity (including a cross-claim or counterclaim in a lawsuit) alleging that the Work or a Contribution incorporated within the Work constitutes direct or contributory patent infringement, then any patent licenses granted to You under this License for that Work shall terminate as of the date such litigation is filed.
-
-4. Redistribution.
-
-You may reproduce and distribute copies of the Work or Derivative Works thereof in any medium, with or without modifications, and in Source or Object form, provided that You meet the following conditions:
-1.You must give any other recipients of the Work or Derivative Works a copy of this License; and
-2.You must cause any modified files to carry prominent notices stating that You changed the files; and
-3.You must retain, in the Source form of any Derivative Works that You distribute, all copyright, patent, trademark, and attribution notices from the Source form of the Work, excluding those notices that do not pertain to any part of the Derivative Works; and
-4.If the Work includes a "NOTICE" text file as part of its distribution, then any Derivative Works that You distribute must include a readable copy of the attribution notices contained within such NOTICE file, excluding those notices that do not pertain to any part of the Derivative Works, in at least one of the following places: within a NOTICE text file distributed as part of the Derivative Works; within the Source form or documentation, if provided along with the Derivative Works; or, within a display generated by the Derivative Works, if and wherever such third-party notices normally appear. The contents of the NOTICE file are for informational purposes only and do not modify the License. You may add Your own attribution notices within Derivative Works that You distribute, alongside or as an addendum to the NOTICE text from the Work, provided that such additional attribution notices cannot be construed as modifying the License.
-
-You may add Your own copyright statement to Your modifications and may provide additional or different license terms and conditions for use, reproduction, or distribution of Your modifications, or for any such Derivative Works as a whole, provided Your use, reproduction, and distribution of the Work otherwise complies with the conditions stated in this License.
-
-5. Submission of Contributions.
-
-Unless You explicitly state otherwise, any Contribution intentionally submitted for inclusion in the Work by You to the Licensor shall be under the terms and conditions of this License, without any additional terms or conditions. Notwithstanding the above, nothing herein shall supersede or modify the terms of any separate license agreement you may have executed with Licensor regarding such Contributions.
-
-6. Trademarks.
-
-This License does not grant permission to use the trade names, trademarks, service marks, or product names of the Licensor, except as required for reasonable and customary use in describing the origin of the Work and reproducing the content of the NOTICE file.
-
-7. Disclaimer of Warranty.
-
-Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.
-
-8. Limitation of Liability.
-
-In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.
-
-9. Accepting Warranty or Additional Liability.
-
-While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
-
-END OF TERMS AND CONDITIONS
-
-APPENDIX:
-
- Copyright [2019] [STMicroelectronics]
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/README.md b/README.md
index cadf6b8..c583dc5 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,16 @@
# STM32CubeL4 CMSIS Device MCU Component
+
+
## Overview
-**STM32Cube** is an STMicroelectronics original initiative to ease the developers' life by reducing efforts, time and cost.
+**STM32Cube** is an STMicroelectronics original initiative to ease developers' life by reducing efforts, time and cost.
**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series.
* The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product.
* The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio.
* The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series.
- * A consistent set of middleware components such as RTOS, USB, FatFS, graphics, touch sensing library...
+ * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library...
* A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series.
Two models of publication are proposed for the STM32Cube embedded software:
@@ -34,10 +36,12 @@
Tag v1.6.1 | Tag v5.4.0_cm4 | Tag v1.15.1 (and following, if any, till next CMSIS tag)
Tag v1.7.0 | Tag v5.6.0_cm4 | Tag v1.16.0 (and following, if any, till next CMSIS tag)
Tag v1.7.1 | Tag v5.6.0_cm4 | Tag v1.17.0 (and following, if any, till next CMSIS tag)
+Tag v1.7.2 | Tag v5.6.0_cm4 | Tag v1.17.1 (and following, if any, till next CMSIS tag)
The full **STM32CubeL4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL4).
## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l4/issues/new).
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
+If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/cmsis_device_l4/issues/new/choose).
+
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index d27bef4..9452c23 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -25,11 +25,8 @@
<h1 id="stm32l4xx-cmsis"><mark>STM32L4xx CMSIS</mark></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
-<a href="https://www.st.com" class="logo"><img src="./_htmresc/st_logo_2020.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
-<h1 id="license">License</h1>
-<p>This software component is licensed by ST under Apache-2.0 license, the "License"; You may not use this component except in compliance with the License. You may obtain a copy of the License at:</p>
-<p><a href="https://opensource.org/licenses/Apache-2.0">Apache License v2.0</a></p>
<h1 id="purpose">Purpose</h1>
<p>This driver provides the CMSIS device for the stm32l4xx products. This covers</p>
<ul>
@@ -52,10 +49,35 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section24" checked aria-hidden="true"> <label for="collapse-section24" aria-hidden="true">V1.7.1 / 11-February-2021</label>
+<input type="checkbox" id="collapse-section25" checked aria-hidden="true"> <label for="collapse-section25" aria-hidden="true">V1.7.2 / 26-November-2021</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>General updates to fix known defects and enhancements implementation.</li>
+<li><p>All source files: update disclaimer to add reference to the new license agreement.</p></li>
+<li><strong>Headline</strong>
+<ul>
+<li>Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.</li>
+<li>__FPU_PRESENT defined with 1U instead of 1 to avoid compilation warning</li>
+<li>Improve GCC startup files robustness.</li>
+<li><strong>STM32L476xx.h</strong> header file: Add PWR SR1 EXT_SMPS_RDY bit definition for WLCSP82 package with Ext SMPS</li>
+</ul></li>
+<li>stm32l4xx.h
+<ul>
+<li>Add new atomic register access macros.</li>
+</ul></li>
+<li>system_stm32l4xx.c
+<ul>
+<li>Update SystemInit() API to don’t reset RCC registers to its reset values</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section24" aria-hidden="true"> <label for="collapse-section24" aria-hidden="true">V1.7.1 / 11-February-2021</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
<li>stm32l431xx.h, stm32l432xx.h, stm32l433xx.h, stm32l442xx.h, stm32l443xx.h and stm32l4xxxxx.h
<ul>
<li>Revert correction done on HSITRIM field for STM32L43x/STM32L44x devices after update of reference manual</li>
@@ -79,7 +101,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section23" aria-hidden="true"> <label for="collapse-section23" aria-hidden="true">V1.7.0 / 26-June-2020</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>stm32l4p5xx.h, stm32l4q5xx.h, stm32l4r5xx.h, stm32l4r7xx.h, stm32l4r9xx.h, stm32l4s5xx.h, stm32l4s7xx.h, stm32l4s9xx.h and stm32l4xxxxx.h
<ul>
@@ -107,7 +129,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section22" aria-hidden="true"> <label for="collapse-section22" aria-hidden="true">V1.6.1 / 07-February-2020</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Add bit definitions in OCTOSPI registers
<ul>
@@ -126,7 +148,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section21" aria-hidden="true"> <label for="collapse-section21" aria-hidden="true">V1.6.0 / 22-November-2019</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>Add the support of <strong>STM32L4P5xx/STM32L4Q5xx</strong> devices
<ul>
@@ -180,7 +202,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section20" aria-hidden="true"> <label for="collapse-section20" aria-hidden="true">V1.5.1 / 03-April-2019</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>stm32l412xx.h, stm32l422xx.h, stm32l431xx.h, stm32l432xx.h, stm32l433xx.h, stm32l442xx.h, stm32l443xx.h, stm32l451xx.h, stm32l452xx.h, stm32l462xx.h and stm32l471xx.h
<ul>
@@ -221,7 +243,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section19" aria-hidden="true"> <label for="collapse-section19" aria-hidden="true">V1.5.0 / 27-July-2018</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li><span style="font-size: 10pt; font-family: Verdana;">Add </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">stm32l412xx.h and <span class="Apple-converted-space"></span></span><span style="font-size: 10pt; font-family: Verdana;">stm32l422xx.h</span><span style="font-size: 10pt; font-family: Verdana;">device description files</span></li>
<li><span style="font-size: 10pt; font-family: Verdana;">Add startup files</span><span style="font-size: 10pt; font-family: Verdana;">startup_</span><span style="font-size: 10pt; font-family: Verdana;">stm32l412xx.s</span><span style="font-size: 10pt; font-family: Verdana;"><span class="Apple-converted-space"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">and<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana;">startup_</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">stm32l422xx.s</span><span style="font-size: 10pt; font-family: Verdana;">for EWARM, MDK-ARM and SW4STM32 toolchains</span></li>
@@ -254,7 +276,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.4.3 / 30-April-2018</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">All </span><span style="font-size: 10pt; font-family: Verdana;">stm32l4XXxx.h device description files</span></p>
<ul>
@@ -277,7 +299,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.4.2 / 22-December-2017</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">SPI_TypeDef cleanup of Reserved fields.</span></li>
</ul>
@@ -286,7 +308,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.4.1 / 6-October-2017</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<p><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">stm32l4r5xx.h and stm32l4s5xx.h description files</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p>
<ul>
<li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Remove LTDC peripheral definitions as LTDC not available on STM32L4R5xx/STM32L4S5xx devices</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li>
@@ -296,7 +318,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.4.0 / 25-August-2017</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">Add the support of </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32L4R5xx/</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32L4R7xx/</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32L4R9xx/</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32L4S5xx/</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32L4S7xx/STM32L4S9xx</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> devices</span></p>
<ul>
@@ -333,7 +355,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.3.2 / 16-June-2017</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">stm32l451xx.h, stm32l452xx.h, stm32l462xx.h description files</span></p>
<ul>
@@ -360,7 +382,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">V1.3.1 / 21-April-2017</label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">stm32l496xx.h and stm32l4a6xx.h device description files</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p>
<ul>
@@ -379,7 +401,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.3.0 / 17-February-2017</label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">Add the support of <span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32L496xx/STM32L4A6xx</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span> devices</span></p>
<ul>
@@ -406,7 +428,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.2.0 / 28-October-2016</label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">Add the support of <span style="font-weight: bold;">STM32L451xx/STM32L452xx/STM32L462xx</span> devices</span></p>
<ul>
@@ -440,7 +462,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.1.2 / 12-September-2016</label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Fix DAC_SR_BWST1 bit definition</span></p></li>
<li><p><span style="font-size: 10pt; font-family: Verdana;">Fix SDMMC_DCTRL_DBLOCKSIZE_2 and SDMMC_DCTRL_DBLOCKSIZE_3 bits definition</span></p></li>
@@ -456,7 +478,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.1.1 / 29-April-2016</label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">All device register description files enriched with _Pos and _Msk defines to be used with _VAL2FLD(field, value) and _FLD2VAL(field, value) from CMSIS Core (previous defines are kept for compatibility)</span></p></li>
<li><p><span style="font-size: 10pt; font-family: Verdana;">stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p>
@@ -512,7 +534,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.1.0 / 26-February-2016</label>
<div>
-<h2 id="main-changes-16">Main Changes</h2>
+<h2 id="main-changes-17">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">Add the support of <span style="font-weight: bold;">STM32L431xx/STM32L432xx/STM32L433xx/STM32L442xx/STM32L443xx</span> devices</span></p>
<ul>
@@ -546,7 +568,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.0.3 / 29-January-2016</label>
<div>
-<h2 id="main-changes-17">Main Changes</h2>
+<h2 id="main-changes-18">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p>
<ul>
@@ -570,7 +592,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.0.2 / 25-November-2015</label>
<div>
-<h2 id="main-changes-18">Main Changes</h2>
+<h2 id="main-changes-19">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device description files</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></p>
<ul>
@@ -607,7 +629,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V1.0.1 / 16-September-2015</label>
<div>
-<h2 id="main-changes-19">Main Changes</h2>
+<h2 id="main-changes-20">Main Changes</h2>
<ul>
<li><p><span style="font-size: 10pt; font-family: Verdana;">stm32l471xx.h, stm32l475xx.h, stm32l476xx.h, stm32l485xx.h and stm32l486xx.h device</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">description files</span></p>
<ul>
@@ -639,7 +661,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section18" aria-hidden="true"> <label for="collapse-section18" aria-hidden="true">V1.0.0 / 26-June-2015</label>
<div>
-<h2 id="main-changes-20">Main Changes</h2>
+<h2 id="main-changes-21">Main Changes</h2>
<ul>
<li><span style="font-size: 10pt; font-family: Verdana;">First official release for </span><span style="font-size: 10pt; font-family: Verdana; font-style: italic; font-weight: bold;">STM32L471xx, STM32L475xx, STM32L476xx, STM32L485xx and STM32L486xx devices</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic; font-weight: bold;"><br />
</span></span></li>
diff --git a/Source/Templates/arm/startup_stm32l412xx.s b/Source/Templates/arm/startup_stm32l412xx.s
index 657f6bd..8fceb01 100644
--- a/Source/Templates/arm/startup_stm32l412xx.s
+++ b/Source/Templates/arm/startup_stm32l412xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -370,4 +370,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l422xx.s b/Source/Templates/arm/startup_stm32l422xx.s
index c3c52c6..b59dd26 100644
--- a/Source/Templates/arm/startup_stm32l422xx.s
+++ b/Source/Templates/arm/startup_stm32l422xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -372,4 +372,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l431xx.s b/Source/Templates/arm/startup_stm32l431xx.s
index aaa71c8..a6a7178 100644
--- a/Source/Templates/arm/startup_stm32l431xx.s
+++ b/Source/Templates/arm/startup_stm32l431xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -386,4 +386,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l432xx.s b/Source/Templates/arm/startup_stm32l432xx.s
index a945f50..9a1dc2e 100644
--- a/Source/Templates/arm/startup_stm32l432xx.s
+++ b/Source/Templates/arm/startup_stm32l432xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -378,4 +378,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l433xx.s b/Source/Templates/arm/startup_stm32l433xx.s
index 272f8df..89944e2 100644
--- a/Source/Templates/arm/startup_stm32l433xx.s
+++ b/Source/Templates/arm/startup_stm32l433xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -390,4 +390,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l442xx.s b/Source/Templates/arm/startup_stm32l442xx.s
index 61d30f5..99d62c6 100644
--- a/Source/Templates/arm/startup_stm32l442xx.s
+++ b/Source/Templates/arm/startup_stm32l442xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -380,4 +380,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l443xx.s b/Source/Templates/arm/startup_stm32l443xx.s
index 159a2e5..1cdc890 100644
--- a/Source/Templates/arm/startup_stm32l443xx.s
+++ b/Source/Templates/arm/startup_stm32l443xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -392,4 +392,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l451xx.s b/Source/Templates/arm/startup_stm32l451xx.s
index e0ba29c..2f94150 100644
--- a/Source/Templates/arm/startup_stm32l451xx.s
+++ b/Source/Templates/arm/startup_stm32l451xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -396,4 +396,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l452xx.s b/Source/Templates/arm/startup_stm32l452xx.s
index 9738a4d..731dab0 100644
--- a/Source/Templates/arm/startup_stm32l452xx.s
+++ b/Source/Templates/arm/startup_stm32l452xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -398,4 +398,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l462xx.s b/Source/Templates/arm/startup_stm32l462xx.s
index 18248e1..4397f6f 100644
--- a/Source/Templates/arm/startup_stm32l462xx.s
+++ b/Source/Templates/arm/startup_stm32l462xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -400,4 +400,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l471xx.s b/Source/Templates/arm/startup_stm32l471xx.s
index 22b2011..bcfe145 100644
--- a/Source/Templates/arm/startup_stm32l471xx.s
+++ b/Source/Templates/arm/startup_stm32l471xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -415,4 +415,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l475xx.s b/Source/Templates/arm/startup_stm32l475xx.s
index 6fe7904..2c165f3 100644
--- a/Source/Templates/arm/startup_stm32l475xx.s
+++ b/Source/Templates/arm/startup_stm32l475xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -417,4 +417,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l476xx.s b/Source/Templates/arm/startup_stm32l476xx.s
index 9f596f8..de601be 100644
--- a/Source/Templates/arm/startup_stm32l476xx.s
+++ b/Source/Templates/arm/startup_stm32l476xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -419,4 +419,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l485xx.s b/Source/Templates/arm/startup_stm32l485xx.s
index ac6a693..bcb68cc 100644
--- a/Source/Templates/arm/startup_stm32l485xx.s
+++ b/Source/Templates/arm/startup_stm32l485xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -419,4 +419,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l486xx.s b/Source/Templates/arm/startup_stm32l486xx.s
index 879332f..6409583 100644
--- a/Source/Templates/arm/startup_stm32l486xx.s
+++ b/Source/Templates/arm/startup_stm32l486xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -421,4 +421,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l496xx.s b/Source/Templates/arm/startup_stm32l496xx.s
index c75789a..850d200 100644
--- a/Source/Templates/arm/startup_stm32l496xx.s
+++ b/Source/Templates/arm/startup_stm32l496xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -446,4 +446,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4a6xx.s b/Source/Templates/arm/startup_stm32l4a6xx.s
index 15a39c0..39faa89 100644
--- a/Source/Templates/arm/startup_stm32l4a6xx.s
+++ b/Source/Templates/arm/startup_stm32l4a6xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -448,4 +448,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4p5xx.s b/Source/Templates/arm/startup_stm32l4p5xx.s
index 79668ad..6e61f36 100644
--- a/Source/Templates/arm/startup_stm32l4p5xx.s
+++ b/Source/Templates/arm/startup_stm32l4p5xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -444,4 +444,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4q5xx.s b/Source/Templates/arm/startup_stm32l4q5xx.s
index 658a8f5..6732235 100644
--- a/Source/Templates/arm/startup_stm32l4q5xx.s
+++ b/Source/Templates/arm/startup_stm32l4q5xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -448,4 +448,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4r5xx.s b/Source/Templates/arm/startup_stm32l4r5xx.s
index 2d1d3df..5de687b 100644
--- a/Source/Templates/arm/startup_stm32l4r5xx.s
+++ b/Source/Templates/arm/startup_stm32l4r5xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -446,4 +446,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4r7xx.s b/Source/Templates/arm/startup_stm32l4r7xx.s
index 41bc70a..bf180d0 100644
--- a/Source/Templates/arm/startup_stm32l4r7xx.s
+++ b/Source/Templates/arm/startup_stm32l4r7xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -446,4 +446,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4r9xx.s b/Source/Templates/arm/startup_stm32l4r9xx.s
index 62241c2..c266abd 100644
--- a/Source/Templates/arm/startup_stm32l4r9xx.s
+++ b/Source/Templates/arm/startup_stm32l4r9xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -448,4 +448,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4s5xx.s b/Source/Templates/arm/startup_stm32l4s5xx.s
index 1529d25..151073e 100644
--- a/Source/Templates/arm/startup_stm32l4s5xx.s
+++ b/Source/Templates/arm/startup_stm32l4s5xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -448,4 +448,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4s7xx.s b/Source/Templates/arm/startup_stm32l4s7xx.s
index 80d7c9f..caeaa21 100644
--- a/Source/Templates/arm/startup_stm32l4s7xx.s
+++ b/Source/Templates/arm/startup_stm32l4s7xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -448,4 +448,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/arm/startup_stm32l4s9xx.s b/Source/Templates/arm/startup_stm32l4s9xx.s
index c11d579..5d3cbe7 100644
--- a/Source/Templates/arm/startup_stm32l4s9xx.s
+++ b/Source/Templates/arm/startup_stm32l4s9xx.s
@@ -10,16 +10,16 @@
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
+;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
@@ -450,4 +450,4 @@
END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
+
diff --git a/Source/Templates/gcc/startup_stm32l412xx.s b/Source/Templates/gcc/startup_stm32l412xx.s
index 9bc7278..7b73b9f 100644
--- a/Source/Templates/gcc/startup_stm32l412xx.s
+++ b/Source/Templates/gcc/startup_stm32l412xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -432,4 +434,4 @@
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l422xx.s b/Source/Templates/gcc/startup_stm32l422xx.s
index faab576..acde813 100644
--- a/Source/Templates/gcc/startup_stm32l422xx.s
+++ b/Source/Templates/gcc/startup_stm32l422xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -435,4 +437,4 @@
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l431xx.s b/Source/Templates/gcc/startup_stm32l431xx.s
index 7e5fba4..f652136 100644
--- a/Source/Templates/gcc/startup_stm32l431xx.s
+++ b/Source/Templates/gcc/startup_stm32l431xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -456,4 +458,4 @@
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l432xx.s b/Source/Templates/gcc/startup_stm32l432xx.s
index 3f5fad1..27b2be0 100644
--- a/Source/Templates/gcc/startup_stm32l432xx.s
+++ b/Source/Templates/gcc/startup_stm32l432xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -444,4 +446,4 @@
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l433xx.s b/Source/Templates/gcc/startup_stm32l433xx.s
index ee6dde0..3f4b1a2 100644
--- a/Source/Templates/gcc/startup_stm32l433xx.s
+++ b/Source/Templates/gcc/startup_stm32l433xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -462,4 +464,4 @@
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l442xx.s b/Source/Templates/gcc/startup_stm32l442xx.s
index 1150540..06a0908 100644
--- a/Source/Templates/gcc/startup_stm32l442xx.s
+++ b/Source/Templates/gcc/startup_stm32l442xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -447,4 +449,4 @@
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l443xx.s b/Source/Templates/gcc/startup_stm32l443xx.s
index 8437e0b..256a86e 100644
--- a/Source/Templates/gcc/startup_stm32l443xx.s
+++ b/Source/Templates/gcc/startup_stm32l443xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -465,4 +467,4 @@
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l451xx.s b/Source/Templates/gcc/startup_stm32l451xx.s
index 441537e..c5ca6c3 100644
--- a/Source/Templates/gcc/startup_stm32l451xx.s
+++ b/Source/Templates/gcc/startup_stm32l451xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -470,4 +472,4 @@
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l452xx.s b/Source/Templates/gcc/startup_stm32l452xx.s
index 1ce9d78..6447a0d 100644
--- a/Source/Templates/gcc/startup_stm32l452xx.s
+++ b/Source/Templates/gcc/startup_stm32l452xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -473,4 +475,4 @@
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l462xx.s b/Source/Templates/gcc/startup_stm32l462xx.s
index 2ff8593..4f39f26 100644
--- a/Source/Templates/gcc/startup_stm32l462xx.s
+++ b/Source/Templates/gcc/startup_stm32l462xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -476,4 +478,4 @@
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l471xx.s b/Source/Templates/gcc/startup_stm32l471xx.s
index c9c68c3..6ad002f 100644
--- a/Source/Templates/gcc/startup_stm32l471xx.s
+++ b/Source/Templates/gcc/startup_stm32l471xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -500,4 +502,4 @@
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l475xx.s b/Source/Templates/gcc/startup_stm32l475xx.s
index 5e40b9c..f00efcf 100644
--- a/Source/Templates/gcc/startup_stm32l475xx.s
+++ b/Source/Templates/gcc/startup_stm32l475xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -503,4 +505,4 @@
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l476xx.s b/Source/Templates/gcc/startup_stm32l476xx.s
index f076fac..45b6e06 100644
--- a/Source/Templates/gcc/startup_stm32l476xx.s
+++ b/Source/Templates/gcc/startup_stm32l476xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -506,4 +508,4 @@
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l485xx.s b/Source/Templates/gcc/startup_stm32l485xx.s
index c944d7c..3acbfe6 100644
--- a/Source/Templates/gcc/startup_stm32l485xx.s
+++ b/Source/Templates/gcc/startup_stm32l485xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -506,4 +508,4 @@
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l486xx.s b/Source/Templates/gcc/startup_stm32l486xx.s
index 0e7f9b6..549c4ce 100644
--- a/Source/Templates/gcc/startup_stm32l486xx.s
+++ b/Source/Templates/gcc/startup_stm32l486xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -509,4 +511,4 @@
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l496xx.s b/Source/Templates/gcc/startup_stm32l496xx.s
index 35bd0fb..4cbd07c 100644
--- a/Source/Templates/gcc/startup_stm32l496xx.s
+++ b/Source/Templates/gcc/startup_stm32l496xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -542,4 +544,4 @@
.weak DMA2D_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4a6xx.s b/Source/Templates/gcc/startup_stm32l4a6xx.s
index 7beb858..b5af0ce 100644
--- a/Source/Templates/gcc/startup_stm32l4a6xx.s
+++ b/Source/Templates/gcc/startup_stm32l4a6xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -545,4 +547,4 @@
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4p5xx.s b/Source/Templates/gcc/startup_stm32l4p5xx.s
index 40f99ac..a81e7cf 100644
--- a/Source/Templates/gcc/startup_stm32l4p5xx.s
+++ b/Source/Templates/gcc/startup_stm32l4p5xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -534,4 +536,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4q5xx.s b/Source/Templates/gcc/startup_stm32l4q5xx.s
index 9c12dbe..53e85c7 100644
--- a/Source/Templates/gcc/startup_stm32l4q5xx.s
+++ b/Source/Templates/gcc/startup_stm32l4q5xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -540,4 +542,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4r5xx.s b/Source/Templates/gcc/startup_stm32l4r5xx.s
index e0ad423..01114ae 100644
--- a/Source/Templates/gcc/startup_stm32l4r5xx.s
+++ b/Source/Templates/gcc/startup_stm32l4r5xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -540,4 +542,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4r7xx.s b/Source/Templates/gcc/startup_stm32l4r7xx.s
index 4fe3c35..2d9dc65 100644
--- a/Source/Templates/gcc/startup_stm32l4r7xx.s
+++ b/Source/Templates/gcc/startup_stm32l4r7xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -540,4 +542,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4r9xx.s b/Source/Templates/gcc/startup_stm32l4r9xx.s
index 2057484..00d4845 100644
--- a/Source/Templates/gcc/startup_stm32l4r9xx.s
+++ b/Source/Templates/gcc/startup_stm32l4r9xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -543,4 +545,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4s5xx.s b/Source/Templates/gcc/startup_stm32l4s5xx.s
index 7f33197..80ddc93 100644
--- a/Source/Templates/gcc/startup_stm32l4s5xx.s
+++ b/Source/Templates/gcc/startup_stm32l4s5xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -543,4 +545,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4s7xx.s b/Source/Templates/gcc/startup_stm32l4s7xx.s
index c46f131..f6d8e04 100644
--- a/Source/Templates/gcc/startup_stm32l4s7xx.s
+++ b/Source/Templates/gcc/startup_stm32l4s7xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -543,4 +545,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/gcc/startup_stm32l4s9xx.s b/Source/Templates/gcc/startup_stm32l4s9xx.s
index e463089..d5b7c20 100644
--- a/Source/Templates/gcc/startup_stm32l4s9xx.s
+++ b/Source/Templates/gcc/startup_stm32l4s9xx.s
@@ -15,13 +15,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -66,32 +65,35 @@
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
FillZerobss:
- movs r3, #0
- str r3, [r2], #4
+ str r3, [r2]
+ adds r2, r2, #4
LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
+ cmp r2, r4
+ bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
@@ -546,4 +548,4 @@
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l412xx.s b/Source/Templates/iar/startup_stm32l412xx.s
index b7ecf24..4eeeff9 100644
--- a/Source/Templates/iar/startup_stm32l412xx.s
+++ b/Source/Templates/iar/startup_stm32l412xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -494,4 +494,4 @@
B CRS_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l422xx.s b/Source/Templates/iar/startup_stm32l422xx.s
index d49346a..f033952 100644
--- a/Source/Templates/iar/startup_stm32l422xx.s
+++ b/Source/Templates/iar/startup_stm32l422xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2018 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -499,4 +499,4 @@
B CRS_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l431xx.s b/Source/Templates/iar/startup_stm32l431xx.s
index 18917b0..2d753a2 100644
--- a/Source/Templates/iar/startup_stm32l431xx.s
+++ b/Source/Templates/iar/startup_stm32l431xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -534,4 +534,4 @@
B CRS_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l432xx.s b/Source/Templates/iar/startup_stm32l432xx.s
index 7382c3e..3ccae00 100644
--- a/Source/Templates/iar/startup_stm32l432xx.s
+++ b/Source/Templates/iar/startup_stm32l432xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -514,4 +514,4 @@
B CRS_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l433xx.s b/Source/Templates/iar/startup_stm32l433xx.s
index 1751b0a..dbe82e8 100644
--- a/Source/Templates/iar/startup_stm32l433xx.s
+++ b/Source/Templates/iar/startup_stm32l433xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -544,4 +544,4 @@
B CRS_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l442xx.s b/Source/Templates/iar/startup_stm32l442xx.s
index ae6935b..e1f7d0e 100644
--- a/Source/Templates/iar/startup_stm32l442xx.s
+++ b/Source/Templates/iar/startup_stm32l442xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -519,4 +519,4 @@
B CRS_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l443xx.s b/Source/Templates/iar/startup_stm32l443xx.s
index 45e5f85..bcc2ae7 100644
--- a/Source/Templates/iar/startup_stm32l443xx.s
+++ b/Source/Templates/iar/startup_stm32l443xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -549,4 +549,4 @@
B CRS_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l451xx.s b/Source/Templates/iar/startup_stm32l451xx.s
index 7bfc5e2..b1c9fd9 100644
--- a/Source/Templates/iar/startup_stm32l451xx.s
+++ b/Source/Templates/iar/startup_stm32l451xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -556,4 +556,4 @@
B I2C4_ER_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l452xx.s b/Source/Templates/iar/startup_stm32l452xx.s
index 54bc778..f623d89 100644
--- a/Source/Templates/iar/startup_stm32l452xx.s
+++ b/Source/Templates/iar/startup_stm32l452xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -561,4 +561,4 @@
B I2C4_ER_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l462xx.s b/Source/Templates/iar/startup_stm32l462xx.s
index 0b08635..426de15 100644
--- a/Source/Templates/iar/startup_stm32l462xx.s
+++ b/Source/Templates/iar/startup_stm32l462xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -566,4 +566,4 @@
B I2C4_ER_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l471xx.s b/Source/Templates/iar/startup_stm32l471xx.s
index 7b88f12..8529452 100644
--- a/Source/Templates/iar/startup_stm32l471xx.s
+++ b/Source/Templates/iar/startup_stm32l471xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -608,4 +608,4 @@
B FPU_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l475xx.s b/Source/Templates/iar/startup_stm32l475xx.s
index a6b9d45..573db05 100644
--- a/Source/Templates/iar/startup_stm32l475xx.s
+++ b/Source/Templates/iar/startup_stm32l475xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -613,4 +613,4 @@
B FPU_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l476xx.s b/Source/Templates/iar/startup_stm32l476xx.s
index aeed9c4..3136239 100644
--- a/Source/Templates/iar/startup_stm32l476xx.s
+++ b/Source/Templates/iar/startup_stm32l476xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -618,4 +618,4 @@
B FPU_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l485xx.s b/Source/Templates/iar/startup_stm32l485xx.s
index 90c8331..648195d 100644
--- a/Source/Templates/iar/startup_stm32l485xx.s
+++ b/Source/Templates/iar/startup_stm32l485xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -618,4 +618,4 @@
B FPU_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l486xx.s b/Source/Templates/iar/startup_stm32l486xx.s
index 61d4373..5d3c03f 100644
--- a/Source/Templates/iar/startup_stm32l486xx.s
+++ b/Source/Templates/iar/startup_stm32l486xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -623,4 +623,4 @@
B FPU_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l496xx.s b/Source/Templates/iar/startup_stm32l496xx.s
index 149cecc..9ba3391 100644
--- a/Source/Templates/iar/startup_stm32l496xx.s
+++ b/Source/Templates/iar/startup_stm32l496xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -672,4 +672,4 @@
B DMA2D_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4a6xx.s b/Source/Templates/iar/startup_stm32l4a6xx.s
index b1ff414..e3b48e8 100644
--- a/Source/Templates/iar/startup_stm32l4a6xx.s
+++ b/Source/Templates/iar/startup_stm32l4a6xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -677,4 +677,4 @@
B DMA2D_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4p5xx.s b/Source/Templates/iar/startup_stm32l4p5xx.s
index 40ce86d..993e79d 100644
--- a/Source/Templates/iar/startup_stm32l4p5xx.s
+++ b/Source/Templates/iar/startup_stm32l4p5xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -656,4 +656,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4q5xx.s b/Source/Templates/iar/startup_stm32l4q5xx.s
index de9156f..ab0d695 100644
--- a/Source/Templates/iar/startup_stm32l4q5xx.s
+++ b/Source/Templates/iar/startup_stm32l4q5xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2019 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -666,4 +666,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4r5xx.s b/Source/Templates/iar/startup_stm32l4r5xx.s
index 57ee3c2..1025ffd 100644
--- a/Source/Templates/iar/startup_stm32l4r5xx.s
+++ b/Source/Templates/iar/startup_stm32l4r5xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -666,4 +666,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4r7xx.s b/Source/Templates/iar/startup_stm32l4r7xx.s
index cd9fcde..279d2ff 100644
--- a/Source/Templates/iar/startup_stm32l4r7xx.s
+++ b/Source/Templates/iar/startup_stm32l4r7xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -666,4 +666,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4r9xx.s b/Source/Templates/iar/startup_stm32l4r9xx.s
index ff39ab2..751b769 100644
--- a/Source/Templates/iar/startup_stm32l4r9xx.s
+++ b/Source/Templates/iar/startup_stm32l4r9xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -671,4 +671,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4s5xx.s b/Source/Templates/iar/startup_stm32l4s5xx.s
index 00d0967..3ff4ddc 100644
--- a/Source/Templates/iar/startup_stm32l4s5xx.s
+++ b/Source/Templates/iar/startup_stm32l4s5xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -671,4 +671,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4s7xx.s b/Source/Templates/iar/startup_stm32l4s7xx.s
index c8b05db..ddc0141 100644
--- a/Source/Templates/iar/startup_stm32l4s7xx.s
+++ b/Source/Templates/iar/startup_stm32l4s7xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -671,4 +671,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/iar/startup_stm32l4s9xx.s b/Source/Templates/iar/startup_stm32l4s9xx.s
index b9b05c1..6dce863 100644
--- a/Source/Templates/iar/startup_stm32l4s9xx.s
+++ b/Source/Templates/iar/startup_stm32l4s9xx.s
@@ -12,15 +12,15 @@
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
+;* @attention
;*
-;* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-;* All rights reserved.</center></h2>
+;* Copyright (c) 2017 STMicroelectronics.
+;* All rights reserved.
;*
-;* This software component is licensed by ST under Apache License, Version 2.0,
-;* the "License"; You may not use this file except in compliance with the
-;* License. You may obtain a copy of the License at:
-;* opensource.org/licenses/Apache-2.0
-;*
+;* This software is licensed under terms that can be found in the LICENSE file
+;* in the root directory of this software component.
+;* If no LICENSE file comes with this software, it is provided AS-IS.
+;
;*******************************************************************************
;
;
@@ -676,4 +676,4 @@
B DMAMUX1_OVR_IRQHandler
END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Source/Templates/system_stm32l4xx.c b/Source/Templates/system_stm32l4xx.c
index f15fe57..be9cfee 100644
--- a/Source/Templates/system_stm32l4xx.c
+++ b/Source/Templates/system_stm32l4xx.c
@@ -66,13 +66,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under Apache License, Version 2.0,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/Apache-2.0
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -206,25 +205,6 @@
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
#endif
-
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set MSION bit */
- RCC->CR |= RCC_CR_MSION;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000U;
-
- /* Reset HSEON, CSSON , HSION, and PLLON bits */
- RCC->CR &= 0xEAF6FFFFU;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x00001000U;
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
-
- /* Disable all interrupts */
- RCC->CIER = 0x00000000U;
}
/**
