diff --git a/Include/partition_stm32l5xx.h b/Include/partition_stm32l5xx.h
index 05201cd..a3de66a 100644
--- a/Include/partition_stm32l5xx.h
+++ b/Include/partition_stm32l5xx.h
@@ -16,10 +16,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
diff --git a/Include/stm32l552xx.h b/Include/stm32l552xx.h
index 79da587..527d555 100644
--- a/Include/stm32l552xx.h
+++ b/Include/stm32l552xx.h
@@ -15,10 +15,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -1290,7 +1290,7 @@
 } WWDG_TypeDef;
 
 
-/*@}*/ /* end of group STM32L562xx_Peripherals */
+/*@}*/ /* end of group STM32L5xx_peripherals */
 
 
 /* --------  End of section using anonymous unions and disabling warnings  -------- */
@@ -3093,7 +3093,7 @@
 
 #define ADC_CFGR_ALIGN_Pos             (5U)
 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
 
 #define ADC_CFGR_EXTSEL_Pos            (6U)
 #define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x000003C0 */
@@ -4501,18 +4501,18 @@
 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
-#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
-#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN_Pos               (4U)
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000010 */
 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
+#define DBGMCU_CR_TRACE_EN_Pos                 (5U)
+#define DBGMCU_CR_TRACE_EN_Msk                 (0x1UL << DBGMCU_CR_TRACE_EN_Pos)/*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_EN                     DBGMCU_CR_TRACE_EN_Msk
 
 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
@@ -6689,7 +6689,7 @@
 /*****************  Bit definition for FDCAN_ENDN register  *******************/
 #define FDCAN_ENDN_ETV_Pos        (0U)
 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */
 
 /*****************  Bit definition for FDCAN_DBTP register  *******************/
 #define FDCAN_DBTP_DSJW_Pos       (0U)
@@ -7601,7 +7601,7 @@
 /******************  Bit definition for FMC_BCR1 register  *******************/
 #define FMC_BCR1_CCLKEN_Pos        (20U)
 #define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable    */
 #define FMC_BCR1_WFDIS_Pos         (21U)
 #define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
 #define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
@@ -9153,7 +9153,7 @@
 #define ICACHE_FCR_CBSYENDF            ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
 #define ICACHE_FCR_CERRF_Pos           (2U)
 #define ICACHE_FCR_CERRF_Msk           (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
-#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF                        /*!< Cache error flag clear */
+#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
 
 /******************  Bit definition for ICACHE_HMONR register  ****************/
 #define ICACHE_HMONR_HITMON_Pos         (0U)
@@ -9364,7 +9364,7 @@
 
 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timeout enable */
 #define LPTIM_CFGR_WAVE_Pos         (20U)
 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
@@ -11040,18 +11040,10 @@
 #define RCC_CR_MSIRANGE_Pos                  (4U)
 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
-#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
-#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
-#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
-#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
-#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
-#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
-#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
-#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
-#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
-#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
-#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
-#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
+#define RCC_CR_MSIRANGE_0                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_1                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_2                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_3                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
 
 #define RCC_CR_HSION_Pos                     (8U)
 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
@@ -11161,11 +11153,6 @@
 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
 
-#define RCC_CFGR_SW_MSI                      (0x00000000UL)                    /*!< MSI oscillator selection as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001UL)                    /*!< HSI16 oscillator selection as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002UL)                    /*!< HSE oscillator selection as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003UL)                    /*!< PLL selection as system clock */
-
 /*!< SWS configuration */
 #define RCC_CFGR_SWS_Pos                     (2U)
 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
@@ -11173,11 +11160,6 @@
 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
 
-#define RCC_CFGR_SWS_MSI                     (0x00000000UL)                    /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004UL)                    /*!< HSI16 oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008UL)                    /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CUL)                    /*!< PLL used as system clock */
-
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos                    (4U)
 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
@@ -11187,16 +11169,6 @@
 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
 
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000UL)                    /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080UL)                    /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090UL)                    /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0UL)                    /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0UL)                    /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0UL)                    /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0UL)                    /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0UL)                    /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0UL)                    /*!< SYSCLK divided by 512 */
-
 /*!< PPRE1 configuration */
 #define RCC_CFGR_PPRE1_Pos                   (8U)
 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
@@ -11205,12 +11177,6 @@
 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
 
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400UL)                    /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500UL)                    /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600UL)                    /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700UL)                    /*!< HCLK divided by 16 */
-
 /*!< PPRE2 configuration */
 #define RCC_CFGR_PPRE2_Pos                   (11U)
 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
@@ -11219,12 +11185,6 @@
 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
 
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000UL)                    /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800UL)                    /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000UL)                    /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800UL)                    /*!< HCLK divided by 16 */
-
 #define RCC_CFGR_STOPWUCK_Pos                (15U)
 #define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
@@ -11245,12 +11205,6 @@
 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
 
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000UL)                    /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000UL)                    /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000UL)                    /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000UL)                    /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000UL)                    /*!< MCO is divided by 16 */
-
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
@@ -11258,16 +11212,6 @@
 #define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
 #define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
 
-#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)
-#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos)/*!< 0x00000001 */
-#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
-#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
-#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
-#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
-#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
-#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
-#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
-
 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
 #define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
@@ -11328,16 +11272,6 @@
 #define RCC_PLLSAI1CFGR_PLLSAI1SRC_0         (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos)/*!< 0x00000001 */
 #define RCC_PLLSAI1CFGR_PLLSAI1SRC_1         (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos)/*!< 0x00000002 */
 
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Pos   (0U)
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Msk   (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Pos)/*!< 0x00000001 */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI       RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Msk           /*!< MSI oscillator source clock selected */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Pos   (1U)
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Msk   (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Pos)/*!< 0x00000002 */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI       RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Msk           /*!< HSI16 oscillator source clock selected */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Pos   (0U)
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Msk   (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Pos)/*!< 0x00000003 */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE       RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Msk           /*!< HSE oscillator source clock selected */
-
 #define RCC_PLLSAI1CFGR_PLLSAI1M_Pos         (4U)
 #define RCC_PLLSAI1CFGR_PLLSAI1M_Msk         (0xFUL << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)/*!< 0x000000F0 */
 #define RCC_PLLSAI1CFGR_PLLSAI1M             RCC_PLLSAI1CFGR_PLLSAI1M_Msk
@@ -11398,16 +11332,6 @@
 #define RCC_PLLSAI2CFGR_PLLSAI2SRC_0         (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos)/*!< 0x00000001 */
 #define RCC_PLLSAI2CFGR_PLLSAI2SRC_1         (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos)/*!< 0x00000002 */
 
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Pos   (0U)
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Msk   (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Pos)/*!< 0x00000001 */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI       RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Msk           /*!< MSI oscillator source clock selected */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Pos   (1U)
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Msk   (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Pos)/*!< 0x00000002 */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI       RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Msk           /*!< HSI16 oscillator source clock selected */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Pos   (0U)
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Msk   (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Pos)/*!< 0x00000003 */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE       RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Msk           /*!< HSE oscillator source clock selected */
-
 #define RCC_PLLSAI2CFGR_PLLSAI2M_Pos         (4U)
 #define RCC_PLLSAI2CFGR_PLLSAI2M_Msk         (0xFUL << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)/*!< 0x000000F0 */
 #define RCC_PLLSAI2CFGR_PLLSAI2M             RCC_PLLSAI2CFGR_PLLSAI2M_Msk
@@ -12275,10 +12199,10 @@
 #define RCC_CSR_MSISRANGE_Pos                (8U)
 #define RCC_CSR_MSISRANGE_Msk                (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
 #define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk
-#define RCC_CSR_MSISRANGE_1                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
-#define RCC_CSR_MSISRANGE_2                  (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
-#define RCC_CSR_MSISRANGE_4                  (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
-#define RCC_CSR_MSISRANGE_8                  (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
+#define RCC_CSR_MSISRANGE_0                  (0x1UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000100 */
+#define RCC_CSR_MSISRANGE_1                  (0x2UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000200 */
+#define RCC_CSR_MSISRANGE_2                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_3                  (0x8UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000800 */
 
 #define RCC_CSR_RMVF_Pos                     (23U)
 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
diff --git a/Include/stm32l562xx.h b/Include/stm32l562xx.h
index 0e730d6..0de40f1 100644
--- a/Include/stm32l562xx.h
+++ b/Include/stm32l562xx.h
@@ -15,10 +15,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -1364,7 +1364,7 @@
 } WWDG_TypeDef;
 
 
-/*@}*/ /* end of group STM32L562xx_Peripherals */
+/*@}*/ /* end of group STM32L5xx_peripherals */
 
 
 /* --------  End of section using anonymous unions and disabling warnings  -------- */
@@ -3237,7 +3237,7 @@
 
 #define ADC_CFGR_ALIGN_Pos             (5U)
 #define ADC_CFGR_ALIGN_Msk             (0x1UL << ADC_CFGR_ALIGN_Pos)           /*!< 0x00000020 */
-#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
+#define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignment */
 
 #define ADC_CFGR_EXTSEL_Pos            (6U)
 #define ADC_CFGR_EXTSEL_Msk            (0xFUL << ADC_CFGR_EXTSEL_Pos)          /*!< 0x000003C0 */
@@ -4833,18 +4833,18 @@
 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
 
 /********************  Bit definition for DBGMCU_CR register  *****************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk                (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
-#define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
-#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN_Pos               (4U)
+#define DBGMCU_CR_TRACE_IOEN_Msk               (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000010 */
 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
+#define DBGMCU_CR_TRACE_EN_Pos                 (5U)
+#define DBGMCU_CR_TRACE_EN_Msk                 (0x1UL << DBGMCU_CR_TRACE_EN_Pos)/*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_EN                     DBGMCU_CR_TRACE_EN_Msk
 
 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
@@ -7021,7 +7021,7 @@
 /*****************  Bit definition for FDCAN_ENDN register  *******************/
 #define FDCAN_ENDN_ETV_Pos        (0U)
 #define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
-#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */
 
 /*****************  Bit definition for FDCAN_DBTP register  *******************/
 #define FDCAN_DBTP_DSJW_Pos       (0U)
@@ -7933,7 +7933,7 @@
 /******************  Bit definition for FMC_BCR1 register  *******************/
 #define FMC_BCR1_CCLKEN_Pos        (20U)
 #define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
-#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable    */
 #define FMC_BCR1_WFDIS_Pos         (21U)
 #define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
 #define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
@@ -9485,7 +9485,7 @@
 #define ICACHE_FCR_CBSYENDF            ICACHE_FCR_CBSYENDF_Msk                 /*!< Busy end flag clear */
 #define ICACHE_FCR_CERRF_Pos           (2U)
 #define ICACHE_FCR_CERRF_Msk           (0x1UL << ICACHE_FCR_CERRF_Pos)         /*!< 0x00000004 */
-#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF                        /*!< Cache error flag clear */
+#define ICACHE_FCR_CERRF               ICACHE_FCR_CERRF_Msk                    /*!< Cache error flag clear */
 
 /******************  Bit definition for ICACHE_HMONR register  ****************/
 #define ICACHE_HMONR_HITMON_Pos         (0U)
@@ -9696,7 +9696,7 @@
 
 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timeout enable */
 #define LPTIM_CFGR_WAVE_Pos         (20U)
 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
@@ -10655,12 +10655,12 @@
 /* Arithmetic addition output data */
 #define PKA_ARITHMETIC_ADD_OUT_RESULT             ((0x0BD0UL - PKA_RAM_OFFSET)>>2)   /*!< Output result */
 
-/* Arithmetic substraction input data */
+/* Arithmetic subtraction input data */
 #define PKA_ARITHMETIC_SUB_NB_BITS                ((0x0404UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
 #define PKA_ARITHMETIC_SUB_IN_OP1                 ((0x08B4UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
 #define PKA_ARITHMETIC_SUB_IN_OP2                 ((0x0A44UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
 
-/* Arithmetic substraction output data */
+/* Arithmetic subtraction output data */
 #define PKA_ARITHMETIC_SUB_OUT_RESULT             ((0x0BD0UL - PKA_RAM_OFFSET)>>2)   /*!< Output result */
 
 /* Arithmetic multiplication input data */
@@ -10696,13 +10696,13 @@
 /* Modular inversion output data */
 #define PKA_MODULAR_INV_OUT_RESULT                ((0x0BD0UL - PKA_RAM_OFFSET)>>2)   /*!< Output result */
 
-/* Modular substraction input data */
+/* Modular subtraction input data */
 #define PKA_MODULAR_SUB_NB_BITS                   ((0x0404UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
 #define PKA_MODULAR_SUB_IN_OP1                    ((0x08B4UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
 #define PKA_MODULAR_SUB_IN_OP2                    ((0x0A44UL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
 #define PKA_MODULAR_SUB_IN_OP3_MOD                ((0x0D5CUL - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
 
-/* Modular substraction output data */
+/* Modular subtraction output data */
 #define PKA_MODULAR_SUB_OUT_RESULT                ((0x0BD0UL - PKA_RAM_OFFSET)>>2)   /*!< Output result */
 
 /* Montgomery multiplication input data */
@@ -11743,18 +11743,10 @@
 #define RCC_CR_MSIRANGE_Pos                  (4U)
 #define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
-#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
-#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
-#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
-#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
-#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
-#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
-#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
-#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
-#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
-#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
-#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
-#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
+#define RCC_CR_MSIRANGE_0                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
+#define RCC_CR_MSIRANGE_1                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
+#define RCC_CR_MSIRANGE_2                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
+#define RCC_CR_MSIRANGE_3                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
 
 #define RCC_CR_HSION_Pos                     (8U)
 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
@@ -11864,11 +11856,6 @@
 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
 
-#define RCC_CFGR_SW_MSI                      (0x00000000UL)                    /*!< MSI oscillator selection as system clock */
-#define RCC_CFGR_SW_HSI                      (0x00000001UL)                    /*!< HSI16 oscillator selection as system clock */
-#define RCC_CFGR_SW_HSE                      (0x00000002UL)                    /*!< HSE oscillator selection as system clock */
-#define RCC_CFGR_SW_PLL                      (0x00000003UL)                    /*!< PLL selection as system clock */
-
 /*!< SWS configuration */
 #define RCC_CFGR_SWS_Pos                     (2U)
 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
@@ -11876,11 +11863,6 @@
 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
 
-#define RCC_CFGR_SWS_MSI                     (0x00000000UL)                    /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                     (0x00000004UL)                    /*!< HSI16 oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                     (0x00000008UL)                    /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                     (0x0000000CUL)                    /*!< PLL used as system clock */
-
 /*!< HPRE configuration */
 #define RCC_CFGR_HPRE_Pos                    (4U)
 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
@@ -11890,16 +11872,6 @@
 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
 
-#define RCC_CFGR_HPRE_DIV1                   (0x00000000UL)                    /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                   (0x00000080UL)                    /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                   (0x00000090UL)                    /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                   (0x000000A0UL)                    /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                  (0x000000B0UL)                    /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                  (0x000000C0UL)                    /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                 (0x000000D0UL)                    /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                 (0x000000E0UL)                    /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                 (0x000000F0UL)                    /*!< SYSCLK divided by 512 */
-
 /*!< PPRE1 configuration */
 #define RCC_CFGR_PPRE1_Pos                   (8U)
 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
@@ -11908,12 +11880,6 @@
 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
 
-#define RCC_CFGR_PPRE1_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                  (0x00000400UL)                    /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                  (0x00000500UL)                    /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                  (0x00000600UL)                    /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                 (0x00000700UL)                    /*!< HCLK divided by 16 */
-
 /*!< PPRE2 configuration */
 #define RCC_CFGR_PPRE2_Pos                   (11U)
 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
@@ -11922,12 +11888,6 @@
 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
 
-#define RCC_CFGR_PPRE2_DIV1                  (0x00000000UL)                    /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                  (0x00002000UL)                    /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                  (0x00002800UL)                    /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                  (0x00003000UL)                    /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                 (0x00003800UL)                    /*!< HCLK divided by 16 */
-
 #define RCC_CFGR_STOPWUCK_Pos                (15U)
 #define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
@@ -11948,12 +11908,6 @@
 #define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
 #define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
 
-#define RCC_CFGR_MCOPRE_DIV1                 (0x00000000UL)                    /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCOPRE_DIV2                 (0x10000000UL)                    /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCOPRE_DIV4                 (0x20000000UL)                    /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCOPRE_DIV8                 (0x30000000UL)                    /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCOPRE_DIV16                (0x40000000UL)                    /*!< MCO is divided by 16 */
-
 /********************  Bit definition for RCC_PLLCFGR register  ***************/
 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
@@ -11961,16 +11915,6 @@
 #define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
 #define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
 
-#define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)
-#define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos)/*!< 0x00000001 */
-#define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
-#define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
-#define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
-#define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
-#define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
-#define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
-#define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
-
 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
 #define RCC_PLLCFGR_PLLM_Msk                 (0xFUL << RCC_PLLCFGR_PLLM_Pos)   /*!< 0x000000F0 */
 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
@@ -12031,16 +11975,6 @@
 #define RCC_PLLSAI1CFGR_PLLSAI1SRC_0         (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos)/*!< 0x00000001 */
 #define RCC_PLLSAI1CFGR_PLLSAI1SRC_1         (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_Pos)/*!< 0x00000002 */
 
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Pos   (0U)
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Msk   (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Pos)/*!< 0x00000001 */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI       RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI_Msk           /*!< MSI oscillator source clock selected */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Pos   (1U)
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Msk   (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Pos)/*!< 0x00000002 */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI       RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI_Msk           /*!< HSI16 oscillator source clock selected */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Pos   (0U)
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Msk   (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Pos)/*!< 0x00000003 */
-#define RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE       RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE_Msk           /*!< HSE oscillator source clock selected */
-
 #define RCC_PLLSAI1CFGR_PLLSAI1M_Pos         (4U)
 #define RCC_PLLSAI1CFGR_PLLSAI1M_Msk         (0xFUL << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)/*!< 0x000000F0 */
 #define RCC_PLLSAI1CFGR_PLLSAI1M             RCC_PLLSAI1CFGR_PLLSAI1M_Msk
@@ -12101,16 +12035,6 @@
 #define RCC_PLLSAI2CFGR_PLLSAI2SRC_0         (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos)/*!< 0x00000001 */
 #define RCC_PLLSAI2CFGR_PLLSAI2SRC_1         (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_Pos)/*!< 0x00000002 */
 
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Pos   (0U)
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Msk   (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Pos)/*!< 0x00000001 */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI       RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI_Msk           /*!< MSI oscillator source clock selected */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Pos   (1U)
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Msk   (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Pos)/*!< 0x00000002 */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI       RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI_Msk           /*!< HSI16 oscillator source clock selected */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Pos   (0U)
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Msk   (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Pos)/*!< 0x00000003 */
-#define RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE       RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE_Msk           /*!< HSE oscillator source clock selected */
-
 #define RCC_PLLSAI2CFGR_PLLSAI2M_Pos         (4U)
 #define RCC_PLLSAI2CFGR_PLLSAI2M_Msk         (0xFUL << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)/*!< 0x000000F0 */
 #define RCC_PLLSAI2CFGR_PLLSAI2M             RCC_PLLSAI2CFGR_PLLSAI2M_Msk
@@ -13005,10 +12929,10 @@
 #define RCC_CSR_MSISRANGE_Pos                (8U)
 #define RCC_CSR_MSISRANGE_Msk                (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
 #define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk
-#define RCC_CSR_MSISRANGE_1                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
-#define RCC_CSR_MSISRANGE_2                  (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
-#define RCC_CSR_MSISRANGE_4                  (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
-#define RCC_CSR_MSISRANGE_8                  (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
+#define RCC_CSR_MSISRANGE_0                  (0x1UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000100 */
+#define RCC_CSR_MSISRANGE_1                  (0x2UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000200 */
+#define RCC_CSR_MSISRANGE_2                  (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
+#define RCC_CSR_MSISRANGE_3                  (0x8UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000800 */
 
 #define RCC_CSR_RMVF_Pos                     (23U)
 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)       /*!< 0x00800000 */
diff --git a/Include/stm32l5xx.h b/Include/stm32l5xx.h
index 7eab4c7..6a1f21b 100644
--- a/Include/stm32l5xx.h
+++ b/Include/stm32l5xx.h
@@ -19,10 +19,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -79,7 +79,7 @@
   */
 #define __STM32L5_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
 #define __STM32L5_CMSIS_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
-#define __STM32L5_CMSIS_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */
+#define __STM32L5_CMSIS_VERSION_SUB2   (0x03U) /*!< [15:8]  sub2 version */
 #define __STM32L5_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32L5_CMSIS_VERSION        ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\
                                        |(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\
diff --git a/Include/system_stm32l5xx.h b/Include/system_stm32l5xx.h
index 5169371..f62aa18 100644
--- a/Include/system_stm32l5xx.h
+++ b/Include/system_stm32l5xx.h
@@ -9,10 +9,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
diff --git a/License.md b/License.md
index 64783f9..e0d829b 100644
--- a/License.md
+++ b/License.md
@@ -81,4 +81,3 @@
    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    See the License for the specific language governing permissions and
    limitations under the License.
-
diff --git a/README.md b/README.md
index 9c1244a..db280ae 100644
--- a/README.md
+++ b/README.md
@@ -19,18 +19,24 @@
 
 This **cmsis_device_l5** MCU component repo is one element of the STM32CubeL5 MCU embedded software package, providing the **cmsis device** part.
 
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_l5/blob/master/Release_Notes.html).
+
 ## Compatibility information
 
 In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package:
 
 CMSIS Device L5 | CMSIS Core | Was delivered in the full MCU package
 --------------- | ---------- | -------------------------------------
-Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0
-Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0
+Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0 (and following, if any, till next tag)
+Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0 (and following, if any, till next tag)
+Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0 (and following, if any, till next tag)
 
 The full **STM32CubeL5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL5).
 
 ## Troubleshooting
-If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l5/issues/new/choose).
 
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
+If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l5/issues/new).
+
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
diff --git a/Release_Notes.html b/Release_Notes.html
index b64cc4b..c7d2840 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -48,19 +48,25 @@
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history">Update History</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label>
+<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
-<p><strong>Third release</strong></p>
+<p><strong>Fourth release</strong></p>
 <h2 id="contents">Contents</h2>
-<p>Third official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
+<p>Fourth release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
 <ul>
 <li>stm32l552xx.h and stm32l562xx.h updates
 <ul>
-<li>Add root secure services library (RSSLIB) definitions</li>
-<li>Add bootloader id address</li>
-<li>Align DBGMCU_APB2FZR register and bits definitions with RM0438</li>
+<li>Fix ICACHE_FCR_CERRF bit definition</li>
+<li>Align DBGMCU_CR register and bits definitions with RM0438 revision 5</li>
+<li>Cleanup RCC_CFGR_* definitions to keep only bits definitions</li>
 </ul></li>
+<li>Templates\gcc\startup_stm32l552xx.s and startup_stm32l562xx.s
+<ul>
+<li>Call SystemInit() before RAM initialization in startup/Reset_Handler</li>
+</ul></li>
+<li>Add README.md and License.md files for GitHub publication</li>
+<li>Misspelled words corrections in driver descriptions</li>
 </ul>
 <h2 id="notes">Notes</h2>
 <p>Reminder:</p>
@@ -82,16 +88,18 @@
 </div>
 </div>
 <div class="collapse">
-<input type="checkbox" id="collapse-section2" unchecked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label>
+<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label>
 <div>
 <h2 id="main-changes-1">Main Changes</h2>
-<p><strong>Second release</strong></p>
+<p><strong>Third release</strong></p>
 <h2 id="contents-1">Contents</h2>
-<p>Second official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
+<p>Third official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
 <ul>
-<li>Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c
+<li>stm32l552xx.h and stm32l562xx.h updates
 <ul>
-<li>Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS</li>
+<li>Add root secure services library (RSSLIB) definitions</li>
+<li>Add bootloader id address</li>
+<li>Align DBGMCU_APB2FZR register and bits definitions with RM0438</li>
 </ul></li>
 </ul>
 <h2 id="notes-1">Notes</h2>
@@ -114,11 +122,43 @@
 </div>
 </div>
 <div class="collapse">
-<input type="checkbox" id="collapse-section1" unchecked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label>
+<input type="checkbox" id="collapse-section2" unchecked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label>
 <div>
 <h2 id="main-changes-2">Main Changes</h2>
-<p><strong>First release</strong></p>
+<p><strong>Second release</strong></p>
 <h2 id="contents-2">Contents</h2>
+<p>Second official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
+<ul>
+<li>Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c
+<ul>
+<li>Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS</li>
+</ul></li>
+</ul>
+<h2 id="notes-2">Notes</h2>
+<p>Reminder:</p>
+<ul>
+<li>When TrustZone is enabled in the system (Flash option bit TZEN=1)
+<ul>
+<li>template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).</li>
+<li>default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h:
+<ul>
+<li>SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)</li>
+<li>SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))</li>
+<li>SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))</li>
+<li>SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)</li>
+<li>SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)</li>
+<li>SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)</li>
+</ul></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" unchecked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label>
+<div>
+<h2 id="main-changes-3">Main Changes</h2>
+<p><strong>First release</strong></p>
+<h2 id="contents-3">Contents</h2>
 <p>First official release of STM32L5xx CMSIS Device drivers to support <strong>STM32L552xx and STM32L562xx</strong> devices</p>
 <ul>
 <li>Templates
@@ -136,7 +176,7 @@
 <li>Linker files for 256 and 512 Kbytes Flash device configurations</li>
 </ul></li>
 </ul>
-<h2 id="notes-2">Notes</h2>
+<h2 id="notes-3">Notes</h2>
 <p>When TrustZone is enabled in the system (Flash option bit TZEN=1), template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core)</p>
 </div>
 </div>
diff --git a/Source/Templates/arm/startup_stm32l552xx.s b/Source/Templates/arm/startup_stm32l552xx.s
index 90682f1..03e2c68 100644
--- a/Source/Templates/arm/startup_stm32l552xx.s
+++ b/Source/Templates/arm/startup_stm32l552xx.s
@@ -15,10 +15,10 @@
 ;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
 ;* All rights reserved.</center></h2>
 ;*
-;* This software component is licensed by ST under BSD 3-Clause license,
+;* This software component is licensed by ST under Apache License, Version 2.0,
 ;* the "License"; You may not use this file except in compliance with the
 ;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
diff --git a/Source/Templates/arm/startup_stm32l562xx.s b/Source/Templates/arm/startup_stm32l562xx.s
index 19744ff..eb8ac94 100644
--- a/Source/Templates/arm/startup_stm32l562xx.s
+++ b/Source/Templates/arm/startup_stm32l562xx.s
@@ -15,10 +15,10 @@
 ;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
 ;* All rights reserved.</center></h2>
 ;*
-;* This software component is licensed by ST under BSD 3-Clause license,
+;* This software component is licensed by ST under Apache License, Version 2.0,
 ;* the "License"; You may not use this file except in compliance with the
 ;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;* <<< Use Configuration Wizard in Context Menu >>>
diff --git a/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld b/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld
index da05ac2..e90ee13 100644
--- a/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld
+++ b/Source/Templates/gcc/linker/STM32L552xC_FLASH.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld b/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld
index 5cc5c38..69d6e74 100644
--- a/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld
+++ b/Source/Templates/gcc/linker/STM32L552xC_FLASH_ns.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld b/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld
index d356cd2..e1080c9 100644
--- a/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld
+++ b/Source/Templates/gcc/linker/STM32L552xC_FLASH_s.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld b/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld
index b259536..63c3239 100644
--- a/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld
+++ b/Source/Templates/gcc/linker/STM32L552xE_FLASH.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld b/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld
index 209654e..5bfcd70 100644
--- a/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld
+++ b/Source/Templates/gcc/linker/STM32L552xE_FLASH_ns.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld b/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld
index 2daac42..ad81b3f 100644
--- a/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld
+++ b/Source/Templates/gcc/linker/STM32L552xE_FLASH_s.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xx_RAM.ld b/Source/Templates/gcc/linker/STM32L552xx_RAM.ld
index 1bc6e9a..b3f68b6 100644
--- a/Source/Templates/gcc/linker/STM32L552xx_RAM.ld
+++ b/Source/Templates/gcc/linker/STM32L552xx_RAM.ld
@@ -21,29 +21,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld b/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld
index ab9b9fb..d4468e7 100644
--- a/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld
+++ b/Source/Templates/gcc/linker/STM32L552xx_RAM_ns.ld
@@ -21,29 +21,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld b/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld
index 642b616..ca1f90a 100644
--- a/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld
+++ b/Source/Templates/gcc/linker/STM32L552xx_RAM_s.ld
@@ -21,29 +21,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld b/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld
index b259536..63c3239 100644
--- a/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld
+++ b/Source/Templates/gcc/linker/STM32L562xE_FLASH.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld b/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld
index 209654e..5bfcd70 100644
--- a/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld
+++ b/Source/Templates/gcc/linker/STM32L562xE_FLASH_ns.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld b/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld
index 2daac42..ad81b3f 100644
--- a/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld
+++ b/Source/Templates/gcc/linker/STM32L562xE_FLASH_s.ld
@@ -22,29 +22,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L562xx_RAM.ld b/Source/Templates/gcc/linker/STM32L562xx_RAM.ld
index 1bc6e9a..b3f68b6 100644
--- a/Source/Templates/gcc/linker/STM32L562xx_RAM.ld
+++ b/Source/Templates/gcc/linker/STM32L562xx_RAM.ld
@@ -21,29 +21,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld b/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld
index ab9b9fb..d4468e7 100644
--- a/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld
+++ b/Source/Templates/gcc/linker/STM32L562xx_RAM_ns.ld
@@ -21,29 +21,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld b/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld
index 642b616..ca1f90a 100644
--- a/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld
+++ b/Source/Templates/gcc/linker/STM32L562xx_RAM_s.ld
@@ -21,29 +21,13 @@
 *****************************************************************************
 ** @attention
 **
-** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+** <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+** All rights reserved.</center></h2>
 **
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**   1. Redistributions of source code must retain the above copyright notice,
-**      this list of conditions and the following disclaimer.
-**   2. Redistributions in binary form must reproduce the above copyright notice,
-**      this list of conditions and the following disclaimer in the documentation
-**      and/or other materials provided with the distribution.
-**   3. Neither the name of STMicroelectronics nor the names of its contributors
-**      may be used to endorse or promote products derived from this software
-**      without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+** This software component is licensed by ST under Apache License, Version 2.0,
+** the "License"; You may not use this file except in compliance with the
+** License. You may obtain a copy of the License at:
+**                        opensource.org/licenses/Apache-2.0
 **
 *****************************************************************************
 */
diff --git a/Source/Templates/gcc/startup_stm32l552xx.s b/Source/Templates/gcc/startup_stm32l552xx.s
index d060895..2bcb8d2 100644
--- a/Source/Templates/gcc/startup_stm32l552xx.s
+++ b/Source/Templates/gcc/startup_stm32l552xx.s
@@ -18,10 +18,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -62,6 +62,9 @@
 Reset_Handler:
   ldr   sp, =_estack    /* set stack pointer */
 
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
 /* Copy the data segment initializers from flash to SRAM */
   movs	r1, #0
   b	LoopCopyDataInit
@@ -90,10 +93,8 @@
 	cmp	r2, r3
 	bcc	FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
-    bl __libc_init_array
+  bl __libc_init_array
 /* Call the application's entry point.*/
 	bl	main
 
diff --git a/Source/Templates/gcc/startup_stm32l562xx.s b/Source/Templates/gcc/startup_stm32l562xx.s
index ffc08eb..4f68e99 100644
--- a/Source/Templates/gcc/startup_stm32l562xx.s
+++ b/Source/Templates/gcc/startup_stm32l562xx.s
@@ -18,10 +18,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
@@ -62,6 +62,9 @@
 Reset_Handler:
   ldr   sp, =_estack    /* set stack pointer */
 
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
 /* Copy the data segment initializers from flash to SRAM */
   movs	r1, #0
   b	LoopCopyDataInit
@@ -90,10 +93,8 @@
 	cmp	r2, r3
 	bcc	FillZerobss
 
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
 /* Call static constructors */
-    bl __libc_init_array
+  bl __libc_init_array
 /* Call the application's entry point.*/
 	bl	main
 
diff --git a/Source/Templates/iar/startup_stm32l552xx.s b/Source/Templates/iar/startup_stm32l552xx.s
index 543e417..84b0d87 100644
--- a/Source/Templates/iar/startup_stm32l552xx.s
+++ b/Source/Templates/iar/startup_stm32l552xx.s
@@ -16,10 +16,10 @@
 ;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
 ;* All rights reserved.</center></h2>
 ;*
-;* This software component is licensed by ST under BSD 3-Clause license,
+;* This software component is licensed by ST under Apache License, Version 2.0,
 ;* the "License"; You may not use this file except in compliance with the
 ;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;
diff --git a/Source/Templates/iar/startup_stm32l562xx.s b/Source/Templates/iar/startup_stm32l562xx.s
index f46a164..e7725ae 100644
--- a/Source/Templates/iar/startup_stm32l562xx.s
+++ b/Source/Templates/iar/startup_stm32l562xx.s
@@ -16,10 +16,10 @@
 ;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
 ;* All rights reserved.</center></h2>
 ;*
-;* This software component is licensed by ST under BSD 3-Clause license,
+;* This software component is licensed by ST under Apache License, Version 2.0,
 ;* the "License"; You may not use this file except in compliance with the
 ;* License. You may obtain a copy of the License at:
-;*                        opensource.org/licenses/BSD-3-Clause
+;*                        opensource.org/licenses/Apache-2.0
 ;*
 ;*******************************************************************************
 ;
diff --git a/Source/Templates/system_stm32l5xx.c b/Source/Templates/system_stm32l5xx.c
index c311a3b..bc273ed 100644
--- a/Source/Templates/system_stm32l5xx.c
+++ b/Source/Templates/system_stm32l5xx.c
@@ -79,10 +79,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
diff --git a/Source/Templates/system_stm32l5xx_ns.c b/Source/Templates/system_stm32l5xx_ns.c
index 4129c41..79a960a 100644
--- a/Source/Templates/system_stm32l5xx_ns.c
+++ b/Source/Templates/system_stm32l5xx_ns.c
@@ -33,10 +33,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */
diff --git a/Source/Templates/system_stm32l5xx_s.c b/Source/Templates/system_stm32l5xx_s.c
index 96d2c41..f740942 100644
--- a/Source/Templates/system_stm32l5xx_s.c
+++ b/Source/Templates/system_stm32l5xx_s.c
@@ -88,10 +88,10 @@
   * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
+  * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                        opensource.org/licenses/Apache-2.0
   *
   ******************************************************************************
   */