Release v1.7.3
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index f605e57..cc41dfd 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -460,7 +460,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
/**
* @}
@@ -623,6 +625,118 @@
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
/**
* @}
*/
@@ -1297,7 +1411,7 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
@@ -3246,7 +3360,7 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index d71e0c3..fb61382 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -8,29 +8,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -56,9 +40,9 @@
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(char* file, uint32_t line);
+ void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
diff --git a/Inc/stm32f0xx_hal.h b/Inc/stm32f0xx_hal.h
index e9747ee..6fe6c64 100644
--- a/Inc/stm32f0xx_hal.h
+++ b/Inc/stm32f0xx_hal.h
@@ -7,32 +7,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_H
@@ -89,7 +73,22 @@
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
-
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+
+/**
+ * @}
+ */
+
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
/** @defgroup HAL_Pin_remapping HAL Pin remapping
* @{
@@ -496,8 +495,18 @@
/**
* @}
- */
-
+ */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
@@ -515,28 +524,42 @@
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/**
* @}
- */
+ */
+
+/* Exported variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Variables
+ * @{
+ */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+ * @}
+ */
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
-uint32_t HAL_GetTick(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
diff --git a/Inc/stm32f0xx_hal_adc.h b/Inc/stm32f0xx_hal_adc.h
index 9addcb7..7897f58 100644
--- a/Inc/stm32f0xx_hal_adc.h
+++ b/Inc/stm32f0xx_hal_adc.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_ADC_H
-#define __STM32F0xx_HAL_ADC_H
+#ifndef STM32F0xx_HAL_ADC_H
+#define STM32F0xx_HAL_ADC_H
#ifdef __cplusplus
extern "C" {
@@ -85,21 +69,21 @@
This parameter can be a value of @ref ADC_Scan_mode */
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
This parameter can be a value of @ref ADC_EOCSelection. */
- uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
+ FunctionalState LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue().
This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */
- uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
+ FunctionalState LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
This parameter can be set to ENABLE or DISABLE.
Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
- uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
+ FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
after the selected trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
- uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
+ FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE
@@ -110,7 +94,7 @@
uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
- uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
+ FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
This parameter can be set to ENABLE or DISABLE. */
@@ -168,7 +152,7 @@
uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
This parameter can be a value of @ref ADC_channels. */
- uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
+ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
@@ -220,7 +204,7 @@
/**
* @brief ADC handle Structure definition
*/
-typedef struct
+typedef struct __ADC_HandleTypeDef
{
ADC_TypeDef *Instance; /*!< Register base address */
@@ -233,7 +217,40 @@
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
+
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
+ void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
+ void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
+ void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
+ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
+ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ADC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
+ HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
+ HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
+ HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
+ HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
+ HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
+ HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ADC Callback pointer definition
+ */
+typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -251,10 +268,14 @@
*/
#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
- enable/disable, erroneous state */
+ enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -561,8 +582,17 @@
* @param __HANDLE__ ADC handle
* @retval None
*/
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
+ do{ \
+ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif
/**
* @}
@@ -897,6 +927,13 @@
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -976,7 +1013,7 @@
#endif
-#endif /* __STM32F0xx_HAL_ADC_H */
+#endif /* STM32F0xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_adc_ex.h b/Inc/stm32f0xx_hal_adc_ex.h
index 04d2438..eb72ab7 100644
--- a/Inc/stm32f0xx_hal_adc_ex.h
+++ b/Inc/stm32f0xx_hal_adc_ex.h
@@ -6,32 +6,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_ADC_EX_H
diff --git a/Inc/stm32f0xx_hal_can.h b/Inc/stm32f0xx_hal_can.h
index def0952..8b40c45 100644
--- a/Inc/stm32f0xx_hal_can.h
+++ b/Inc/stm32f0xx_hal_can.h
@@ -212,8 +212,58 @@
__IO uint32_t ErrorCode; /*!< CAN Error code.
This parameter can be a value of @ref CAN_Error_Code */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
+ void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
+ void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
+ void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
+ void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
+ void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
+ void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
+ void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
+ void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
+ void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
+ void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
+ void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
+ void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
+
+ void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
+ void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
} CAN_HandleTypeDef;
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief HAL CAN common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
+ HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
+ HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
+ HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
+ HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
+ HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
+ HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
+ HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
+ HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
+ HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
+ HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
+ HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */
+ HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
+
+ HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
+ HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
+
+} HAL_CAN_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CAN Callback pointer definition
+ */
+typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
+
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -251,6 +301,9 @@
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
/**
@@ -486,7 +539,15 @@
* @param __HANDLE__ CAN handle.
* @retval None
*/
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_CAN_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @brief Enable the specified CAN interrupts.
@@ -577,6 +638,12 @@
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/**
* @}
*/
diff --git a/Inc/stm32f0xx_hal_cec.h b/Inc/stm32f0xx_hal_cec.h
index d3b001e..545e3d8 100644
--- a/Inc/stm32f0xx_hal_cec.h
+++ b/Inc/stm32f0xx_hal_cec.h
@@ -6,48 +6,30 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_CEC_H
-#define __STM32F0xx_HAL_CEC_H
+#ifndef STM32F0xx_HAL_CEC_H
+#define STM32F0xx_HAL_CEC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F042x6) || defined(STM32F048xx) ||\
- defined(STM32F051x8) || defined(STM32F058xx) ||\
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
- defined(STM32F091xC) || defined(STM32F098xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
+#if defined (CEC)
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -56,87 +38,87 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
*/
-
-/**
- * @brief CEC Init Structure definition
- */
+
+/**
+ * @brief CEC Init Structure definition
+ */
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
- It can be one of @ref CEC_Signal_Free_Time
- and belongs to the set {0,...,7} where
- 0x0 is the default configuration
+ It can be one of @ref CEC_Signal_Free_Time
+ and belongs to the set {0,...,7} where
+ 0x0 is the default configuration
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
- it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
+ it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
or CEC_EXTENDED_TOLERANCE */
- uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
- CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
+ uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
CEC_RX_STOP_ON_BRE: reception is stopped. */
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
-
+
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
- CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
- CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
-
+ CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
+ CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
+
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
- upon an error detected on a broadcast message.
-
+ upon an error detected on a broadcast message.
+
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
-
+
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
- a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
+ a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
- b) LBPE detection: error-bit generation on the CEC line
+ b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
-
+
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
- there is no error-bit generation in case of Short Bit Period Error detection in
+ there is no error-bit generation in case of Short Bit Period Error detection in
a broadcast message while LSTN bit is set. */
-
+
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
-
+
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
-
- CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
- own address (OAR). Messages addressed to different destination are ignored.
+
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
+ own address (OAR). Messages addressed to different destination are ignored.
Broadcast messages are always received.
-
- CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
- address (OAR) with positive acknowledge. Messages addressed to different destination
+
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
+ address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
-
+
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
-
-}CEC_InitTypeDef;
-/**
- * @brief HAL CEC State structures definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
- * - gState contains CEC state information related to global Handle management
+} CEC_InitTypeDef;
+
+/**
+ * @brief HAL CEC State definition
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
+ * - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
- * b6 Error information
+ * b6 Error information
* 0 : No Error
* 1 : Error
* b5 IP initilisation status
@@ -165,52 +147,74 @@
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
-}HAL_CEC_StateTypeDef;
+ * x : Should be set to 0.
+ */
+typedef uint32_t HAL_CEC_StateTypeDef;
-/**
- * @brief CEC handle Structure definition
- */
+/**
+ * @brief CEC handle Structure definition
+ */
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+typedef struct __CEC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
-
+
CEC_InitTypeDef Init; /*!< CEC communication parameters */
-
+
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
-
+
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
-
+
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
-
+
HAL_LockTypeDef Lock; /*!< Locking object */
- HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
+ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
+
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
- uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
- in case error is reported */
-}CEC_HandleTypeDef;
+
+ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
+ in case error is reported */
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __CEC_HandleTypeDef
+ *hcec); /*!< CEC Tx Transfer completed callback */
+ void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
+ uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
+
+ void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
+ void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
+
+#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
+} CEC_HandleTypeDef;
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL CEC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
+ HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
+ HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
+ HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
+ HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
+} HAL_CEC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL CEC Callback pointer definition
+ */
+typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
+typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
+ uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -219,11 +223,29 @@
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
-
+/** @defgroup CEC_State_Definition CEC State Code Definition
+ * @{
+ */
+#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
+/**
+ * @}
+ */
/** @defgroup CEC_Error_Code CEC Error Code
* @{
- */
-#define HAL_CEC_ERROR_NONE (0x00000000U) /*!< no error */
+ */
+#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
@@ -233,21 +255,24 @@
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
-
+
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
-#define CEC_DEFAULT_SFT (0x00000000U)
-#define CEC_0_5_BITPERIOD_SFT (0x00000001U)
-#define CEC_1_5_BITPERIOD_SFT (0x00000002U)
-#define CEC_2_5_BITPERIOD_SFT (0x00000003U)
-#define CEC_3_5_BITPERIOD_SFT (0x00000004U)
-#define CEC_4_5_BITPERIOD_SFT (0x00000005U)
-#define CEC_5_5_BITPERIOD_SFT (0x00000006U)
-#define CEC_6_5_BITPERIOD_SFT (0x00000007U)
+#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
+#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
+#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
+#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
+#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
+#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
+#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
+#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
/**
* @}
*/
@@ -255,83 +280,83 @@
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
-#define CEC_STANDARD_TOLERANCE (0x00000000U)
+#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
- */
+ */
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
-#define CEC_NO_RX_STOP_ON_BRE (0x00000000U)
+#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
- */
-
+ */
+
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
- */
-#define CEC_BRE_ERRORBIT_NO_GENERATION (0x00000000U)
+ */
+#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
- */
-
+ */
+
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
- */
-#define CEC_LBPE_ERRORBIT_NO_GENERATION (0x00000000U)
+ */
+#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
- */
+ */
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
- */
-#define CEC_BROADCASTERROR_ERRORBIT_GENERATION (0x00000000U)
+ */
+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
*/
-
+
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
- */
-#define CEC_SFT_START_ON_TXSOM (0x00000000U)
+ */
+#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
*/
-
+
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
- */
-#define CEC_REDUCED_LISTENING_MODE (0x00000000U)
+ */
+#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
*/
-
-/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
+
+/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
-#define CEC_CFGR_OAR_LSB_POS (16U)
-/**
- * @}
- */
-
-/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
- * @{
- */
-#define CEC_INITIATOR_LSB_POS (4U)
+#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
/**
* @}
*/
-/** @defgroup CEC_OWN_ADDRESS CEC Own Address
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
+ * @{
+ */
+#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
+/**
+ * @}
+ */
+
+/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
@@ -353,7 +378,7 @@
/**
* @}
*/
-
+
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
* @{
*/
@@ -393,36 +418,36 @@
/**
* @}
*/
-
-/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
+
+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
-/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
-
-/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
+
+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
-
+
/**
* @}
- */
-
+ */
+
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CEC_Exported_Macros CEC Exported Macros
* @{
@@ -432,11 +457,19 @@
* @param __HANDLE__ CEC handle.
* @retval None
*/
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
} while(0)
-
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to check.
@@ -446,16 +479,16 @@
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval ITStatus
*/
-#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1)
* @param __HANDLE__ specifies the CEC Handle.
@@ -467,134 +500,134 @@
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
+ * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval none
+ * @arg CEC_FLAG_RXBR: Rx-Byte Received.
+ * @retval none
*/
-#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
-#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
- */
-#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
+ */
+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
- * @arg CEC_IT_TXERR: Tx Error IT Enable
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
- * @arg CEC_IT_TXEND: End of transmission IT Enable
- * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
- * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
- * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
- * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
- * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
- * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
- * @arg CEC_IT_RXEND: End Of Reception IT Enable
- * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
- * @retval FlagStatus
+ * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
+ * @arg CEC_IT_TXERR: Tx Error IT Enable
+ * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
+ * @arg CEC_IT_TXEND: End of transmission IT Enable
+ * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
+ * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
+ * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
+ * @arg CEC_IT_LBPE: Rx Long period Error IT Enable
+ * @arg CEC_IT_SBPE: Rx Short period Error IT Enable
+ * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
+ * @arg CEC_IT_RXOVR: Rx Overrun IT Enable
+ * @arg CEC_IT_RXEND: End Of Reception IT Enable
+ * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
+ * @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
- * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
+ * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval FlagStatus
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval FlagStatus
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval FlagStatus
*/
-#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register
- * @param __HANDLE__ specifies the CEC Handle.
- * @retval none
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
- * @param __HANDLE__ specifies the CEC Handle.
- * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
- * @retval none
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
+ * @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CEC_Exported_Functions
@@ -610,6 +643,15 @@
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
+ pCEC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -618,9 +660,10 @@
* @{
*/
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
+ uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
@@ -642,7 +685,7 @@
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/** @defgroup CEC_Private_Types CEC Private Types
* @{
@@ -650,16 +693,16 @@
/**
* @}
- */
+ */
/* Private variables ---------------------------------------------------------*/
/** @defgroup CEC_Private_Variables CEC Private Variables
* @{
*/
-
+
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
@@ -668,14 +711,14 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup CEC_Private_Macros CEC Private Macros
* @{
*/
-
-#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
+
+#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
@@ -699,27 +742,27 @@
((__MODE__) == CEC_FULL_LISTENING_MODE))
/** @brief Check CEC message size.
- * The message size is the payload size: without counting the header,
- * it varies from 0 byte (ping operation, one header only, no payload) to
- * 15 bytes (1 opcode and up to 14 operands following the header).
- * @param __SIZE__ CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
-
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
+
/** @brief Check CEC device Own Address Register (OAR) setting.
- * OAR address is written in a 15-bit field within CEC_CFGR register.
- * @param __ADDRESS__ CEC own address.
+ * OAR address is written in a 15-bit field within CEC_CFGR register.
+ * @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
/** @brief Check CEC initiator or destination logical address setting.
- * Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__ CEC initiator or logical address.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
/**
* @}
*/
@@ -727,27 +770,25 @@
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
/**
* @}
- */
-
-#endif /* defined(STM32F042x6) || defined(STM32F048xx) || */
- /* defined(STM32F051x8) || defined(STM32F058xx) || */
- /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
- /* defined(STM32F091xC) || defined(STM32F098xx) */
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* CEC */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_CEC_H */
+#endif /* STM32F0xxHAL_CEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_comp.h b/Inc/stm32f0xx_hal_comp.h
index ae0df50..e6c8a39 100644
--- a/Inc/stm32f0xx_hal_comp.h
+++ b/Inc/stm32f0xx_hal_comp.h
@@ -6,44 +6,26 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_COMP_H
-#define __STM32F0xx_HAL_COMP_H
+#ifndef STM32F0xx_HAL_COMP_H
+#define STM32F0xx_HAL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined (COMP1) || defined (COMP2)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -97,15 +79,39 @@
/**
* @brief COMP Handle Structure definition
*/
-typedef struct
+typedef struct __COMP_HandleTypeDef
{
- COMP_TypeDef *Instance; /*!< Register base address */
- COMP_InitTypeDef Init; /*!< COMP required parameters */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO uint32_t State; /*!< COMP communication state
- This parameter can be a value of @ref COMP_State */
+ COMP_TypeDef *Instance; /*!< Register base address */
+ COMP_InitTypeDef Init; /*!< COMP required parameters */
+ HAL_LockTypeDef Lock; /*!< Locking object */
+ __IO uint32_t State; /*!< COMP communication state
+ This parameter can be a value of @ref COMP_State */
+ __IO uint32_t ErrorCode; /*!< COMP Error code */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
+ void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
+ void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}COMP_HandleTypeDef;
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL COMP Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
+ HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
+ HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
+} HAL_COMP_CallbackIDTypeDef;
+
+/**
+ * @brief HAL COMP Callback pointer definition
+ */
+typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
+
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -115,6 +121,17 @@
* @{
*/
+/** @defgroup COMP_Error_Code COMP Error Code
+ * @{
+ */
+#define HAL_COMP_ERROR_NONE (0x00U) /*!< No error */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U) /*!< Invalid Callback error */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
/** @defgroup COMP_State COMP State
* @{
*/
@@ -263,7 +280,22 @@
* @param __HANDLE__ COMP handle.
* @retval None
*/
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_COMP_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+#endif
+
+/**
+ * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
+ * @param __HANDLE__ COMP handle
+ * @retval None
+ */
+#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/**
* @brief Enable the specified comparator.
@@ -486,6 +518,13 @@
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -523,7 +562,8 @@
* @{
*/
/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
@@ -648,15 +688,13 @@
* @}
*/
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* COMP1 || COMP2 */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_COMP_H */
+#endif /* STM32F0xx_HAL_COMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_conf_template.h b/Inc/stm32f0xx_hal_conf_template.h
index 3c2ff74..0e9a50e 100644
--- a/Inc/stm32f0xx_hal_conf_template.h
+++ b/Inc/stm32f0xx_hal_conf_template.h
@@ -6,32 +6,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CONF_H
@@ -59,6 +43,7 @@
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
@@ -133,7 +118,7 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
- #define LSI_VALUE 40000U
+ #define LSI_VALUE 32000U
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -169,6 +154,25 @@
#define DATA_CACHE_ENABLE 0U
#define USE_SPI_CRC 1U
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
@@ -189,6 +193,10 @@
#include "stm32f0xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f0xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
@@ -295,9 +303,9 @@
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(char* file, uint32_t line);
+ void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
diff --git a/Inc/stm32f0xx_hal_cortex.h b/Inc/stm32f0xx_hal_cortex.h
index ebea4ea..d8a4251 100644
--- a/Inc/stm32f0xx_hal_cortex.h
+++ b/Inc/stm32f0xx_hal_cortex.h
@@ -6,32 +6,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CORTEX_H
diff --git a/Inc/stm32f0xx_hal_crc.h b/Inc/stm32f0xx_hal_crc.h
index 620ba76..e3aaa83 100644
--- a/Inc/stm32f0xx_hal_crc.h
+++ b/Inc/stm32f0xx_hal_crc.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_CRC_H
-#define __STM32F0xx_HAL_CRC_H
+#ifndef STM32F0xx_HAL_CRC_H
+#define STM32F0xx_HAL_CRC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -48,180 +32,202 @@
* @{
*/
-/** @addtogroup CRC CRC
+/** @addtogroup CRC
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
-/**
- * @brief CRC HAL State Structure definition
- */
+
+/**
+ * @brief CRC HAL State Structure definition
+ */
typedef enum
-{
+{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
-}HAL_CRC_StateTypeDef;
+} HAL_CRC_StateTypeDef;
-
-/**
- * @brief CRC Init Structure definition
- */
+/**
+ * @brief CRC Init Structure definition
+ */
typedef struct
{
- uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
- If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
- X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+#if defined(CRC_POL_POL)
+ uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
+ If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
+ X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
- If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
+ If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+#endif /* CRC_POL_POL */
- uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
+ uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
- 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
- If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
+ 0xFFFFFFFF value. In that case, there is no need to set InitValue field.
+ If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
- uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
- respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
+#if defined(CRC_POL_POL)
+ uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
+ respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
- No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
+ No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
- uint32_t CRCLength; /*!< This parameter is a value of @ref CRCEx_Polynomial_Sizes and indicates CRC length.
+ uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
- CRC_POLYLENGTH_32B (32-bit CRC)
- CRC_POLYLENGTH_16B (16-bit CRC)
- CRC_POLYLENGTH_8B (8-bit CRC)
- CRC_POLYLENGTH_7B (7-bit CRC) */
-
- uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
- is set to DEFAULT_INIT_VALUE_ENABLE */
-
- uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
- Can be either one of the following values
- CRC_INPUTDATA_INVERSION_NONE no input data inversion
- CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
- CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
- CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
-
+ @arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
+ @arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
+ @arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
+ @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
+#endif /* CRC_POL_POL */
+
+ uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
+ is set to DEFAULT_INIT_VALUE_ENABLE. */
+
+ uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
+ Can be either one of the following values
+ @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
+ @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
+ @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
+ @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
- Can be either
- CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or
- CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
-}CRC_InitTypeDef;
+ Can be either
+ @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
+ @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
+} CRC_InitTypeDef;
-
-/**
- * @brief CRC Handle Structure definition
- */
+/**
+ * @brief CRC Handle Structure definition
+ */
typedef struct
{
- CRC_TypeDef *Instance; /*!< Register base address */
-
+ CRC_TypeDef *Instance; /*!< Register base address */
+
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
-
+
HAL_LockTypeDef Lock; /*!< CRC Locking object */
-
+
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
-
- uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
- Can be either
- CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
- CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
- CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
+
+ uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
+ Can be either
+ @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
+ @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
+
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
- must occur if InputBufferFormat is not one of the three values listed above */
-}CRC_HandleTypeDef;
+ must occur if InputBufferFormat is not one of the three values listed above */
+} CRC_HandleTypeDef;
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
-/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
+
+#if defined(CRC_POL_POL)
+/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
-#define DEFAULT_CRC32_POLY 0x04C11DB7
+#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
+/**
+ * @}
+ */
+#endif /* CRC_POL_POL */
+/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+ * @{
+ */
+#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
-/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
+#if defined(CRC_POL_POL)
+/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
-#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
-
+#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
+#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
/**
* @}
*/
+#endif /* CRC_POL_POL */
-/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
- * @{
- */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
-#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
-
-#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
- ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-#else
-#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
-
-#define IS_DEFAULT_POLYNOMIAL(DEFAULT) ((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE)
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
-
-/**
- * @}
- */
-
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
- */
-#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
-#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
-
-#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
- ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+ */
+#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
+#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
+#if defined(CRC_POL_POL)
+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
+ * @{
+ */
+#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
+#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
+#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
+#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
+/**
+ * @}
+ */
+
+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
+ * @{
+ */
+#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
+#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
+#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
+#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
+/**
+ * @}
+ */
+#endif /* CRC_POL_POL */
+
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
- * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
- * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
- * the CRC APIs to provide a correct result */
-#define CRC_INPUTDATA_FORMAT_UNDEFINED (0x00000000U)
-#define CRC_INPUTDATA_FORMAT_BYTES (0x00000001U)
-#define CRC_INPUTDATA_FORMAT_HALFWORDS (0x00000002U)
-#define CRC_INPUTDATA_FORMAT_WORDS (0x00000003U)
-
-#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
- ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
- ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
-/**
+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
+ * the CRC APIs to provide a correct result */
+#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
+#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
+#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
+#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
+/**
* @}
- */
+ */
+
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+/**
+ * @}
+ */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
-
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
-/** @brief Reset CRC handle state
+/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
@@ -230,30 +236,32 @@
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
- * @retval None.
+ * @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ CRC handle
- * @param __INIT__ 32-bit initial value
- * @retval None.
+ * @param __INIT__ 32-bit initial value
+ * @retval None
*/
-#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
+ * @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
- * @param __VALUE__ 8-bit value to be stored in the ID register
+ * @param __VALUE__ Value to be stored in the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
+ * @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
- * @retval 8-bit value of the ID register
+ * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
+ * @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
@@ -261,64 +269,69 @@
*/
-/* Include CRC HAL Extension module */
-#include "stm32f0xx_hal_crc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CRC_Exported_Functions CRC Exported Functions
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
-/** @addtogroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
+#if defined(CRC_POL_POL)
+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
+ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
+#endif /* CRC_POL_POL */
+
+#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
+ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
+
+#if defined(CRC_POL_POL)
+#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
+ ((LENGTH) == CRC_POLYLENGTH_16B) || \
+ ((LENGTH) == CRC_POLYLENGTH_8B) || \
+ ((LENGTH) == CRC_POLYLENGTH_7B))
+#endif /* CRC_POL_POL */
+
+#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
+ ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
+
+/**
+ * @}
+ */
+
+/* Include CRC HAL Extended module */
+#include "stm32f0xx_hal_crc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
-
-/** @addtogroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions.
- * @{
- */
-
+
/* Peripheral Control functions ***********************************************/
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @{
+ */
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
-
-/** @addtogroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/** @addtogroup CRC_Exported_Constants CRC Exported Constants
- * @brief aliases for inter STM32 series compatibility
- * @{
- */
-/** @defgroup CRC_Aliases Aliases for inter STM32 series compatibility
+/* Peripheral State and Error functions ***************************************/
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
- */
-/* Aliases for inter STM32 series compatibility */
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
+ */
+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
@@ -339,7 +352,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_CRC_H */
+#endif /* STM32F0xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_crc_ex.h b/Inc/stm32f0xx_hal_crc_ex.h
index 06a5187..6678dc9 100644
--- a/Inc/stm32f0xx_hal_crc_ex.h
+++ b/Inc/stm32f0xx_hal_crc_ex.h
@@ -2,43 +2,27 @@
******************************************************************************
* @file stm32f0xx_hal_crc_ex.h
* @author MCD Application Team
- * @brief Header file of CRC HAL extension module.
+ * @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_CRC_EX_H
-#define __STM32F0xx_HAL_CRC_EX_H
+#ifndef STM32F0xx_HAL_CRC_EX_H
+#define STM32F0xx_HAL_CRC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -48,27 +32,23 @@
* @{
*/
-/** @addtogroup CRCEx CRCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Constants CRCEx Exported Constants
+/** @addtogroup CRCEx
* @{
*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
+ * @{
+ */
+
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
* @{
*/
-#define CRC_INPUTDATA_INVERSION_NONE (0x00000000U)
-#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
-#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
-#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
-
-#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
- ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
- ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
- ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
+#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
+#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/**
* @}
*/
@@ -76,125 +56,98 @@
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
-#define CRC_OUTPUTDATA_INVERSION_DISABLE (0x00000000U)
-#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
-
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
- ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup CRCEx_Polynomial_Sizes Polynomial sizes to configure the IP
- * @{
- */
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-#define CRC_POLYLENGTH_32B (0x00000000U)
-#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
-#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
-#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
-#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
- ((LENGTH) == CRC_POLYLENGTH_16B) || \
- ((LENGTH) == CRC_POLYLENGTH_8B) || \
- ((LENGTH) == CRC_POLYLENGTH_7B))
-#else
-#define CRC_POLYLENGTH_32B (0x00000000U)
-#define IS_CRC_POL_LENGTH(LENGTH) ((LENGTH) == CRC_POLYLENGTH_32B)
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
+#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/**
* @}
*/
-/** @defgroup CRCEx_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
- * @{
+/**
+ * @}
*/
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-#define HAL_CRC_LENGTH_32B 32U
-#define HAL_CRC_LENGTH_16B 16U
-#define HAL_CRC_LENGTH_8B 8U
-#define HAL_CRC_LENGTH_7B 7U
-#else
-#define HAL_CRC_LENGTH_32B 32U
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
-/**
- * @}
- */
-/**
- * @}
- */
/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRCEx_Exported_Macros CRCEx Exported Macros
+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
-
+
/**
* @brief Set CRC output reversal
* @param __HANDLE__ CRC handle
- * @retval None.
+ * @retval None
*/
-#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
+#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ CRC handle
- * @retval None.
+ * @retval None
*/
-#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ CRC handle
- * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
- * @retval None.
+ * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
+ * @retval None
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
+
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
+ * @{
+ */
+
+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
+ ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
+
+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
+ ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
+
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+
/** @addtogroup CRCEx_Exported_Functions
* @{
*/
-
-/** @addtogroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
- * @brief Extended Initialization and Configuration functions.
+
+/** @addtogroup CRCEx_Exported_Functions_Group1
* @{
*/
-
/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc);
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) */
/**
* @}
*/
-/* Peripheral Control functions ***********************************************/
-/* Peripheral State and Error functions ***************************************/
-/**
- * @}
- */
-
-/**
- * @}
- */
/**
* @}
*/
-
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_CRC_EX_H */
+#endif /* STM32F0xx_HAL_CRC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_dac.h b/Inc/stm32f0xx_hal_dac.h
index 3d3263c..05a86a0 100644
--- a/Inc/stm32f0xx_hal_dac.h
+++ b/Inc/stm32f0xx_hal_dac.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_DAC_H
-#define __STM32F0xx_HAL_DAC_H
+#ifndef STM32F0xx_HAL_DAC_H
+#define STM32F0xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
@@ -45,9 +29,7 @@
* @{
*/
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined (DAC1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -78,7 +60,7 @@
/**
* @brief DAC handle Structure definition
*/
-typedef struct
+typedef struct __DAC_HandleTypeDef
{
DAC_TypeDef *Instance; /*!< Register base address */
@@ -92,6 +74,20 @@
__IO uint32_t ErrorCode; /*!< DAC Error code */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+ void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
+
+ void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
}DAC_HandleTypeDef;
/**
@@ -107,6 +103,31 @@
}DAC_ChannelConfTypeDef;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL DAC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
+ HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
+ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
+ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
+ HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
+ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
+ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
+ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
+ HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
+ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
+ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
+} HAL_DAC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL DAC Callback pointer definition
+ */
+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -124,6 +145,10 @@
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
+#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -181,7 +206,15 @@
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_DAC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel
* @param __HANDLE__ specifies the DAC handle.
@@ -259,20 +292,16 @@
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(DAC_CHANNEL2_SUPPORT)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-
-#if defined(STM32F051x8) || defined(STM32F058xx)
+#else
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1))
-#endif /* STM32F051x8 || STM32F058xx */
+#endif /* DAC_CHANNEL2_SUPPORT */
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
@@ -342,6 +371,13 @@
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/* DAC callback registering/unregistering */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId, pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -376,9 +412,7 @@
* @}
*/
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* DAC1 */
/**
* @}
@@ -389,7 +423,7 @@
#endif
-#endif /*__STM32F0xx_HAL_DAC_H */
+#endif /* STM32F0xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_dac_ex.h b/Inc/stm32f0xx_hal_dac_ex.h
index 57240ee..b69b42c 100644
--- a/Inc/stm32f0xx_hal_dac_ex.h
+++ b/Inc/stm32f0xx_hal_dac_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_hal_def.h b/Inc/stm32f0xx_hal_def.h
index a65b44e..43ca3ee 100644
--- a/Inc/stm32f0xx_hal_def.h
+++ b/Inc/stm32f0xx_hal_def.h
@@ -7,29 +7,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -47,7 +31,7 @@
#if defined(USE_HAL_LEGACY)
#include "Legacy/stm32_hal_legacy.h"
#endif
-#include <stdio.h>
+#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
@@ -75,8 +59,8 @@
#define HAL_MAX_DELAY 0xFFFFFFFFU
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
+#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
do{ \
@@ -84,8 +68,8 @@
(__DMA_HANDLE_).Parent = (__HANDLE__); \
} while(0)
-#define UNUSED(x) ((void)(x))
-
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
diff --git a/Inc/stm32f0xx_hal_dma.h b/Inc/stm32f0xx_hal_dma.h
index 6a9fb70..1304d1d 100644
--- a/Inc/stm32f0xx_hal_dma.h
+++ b/Inc/stm32f0xx_hal_dma.h
@@ -6,32 +6,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_DMA_H
diff --git a/Inc/stm32f0xx_hal_dma_ex.h b/Inc/stm32f0xx_hal_dma_ex.h
index 03217b1..1eaf396 100644
--- a/Inc/stm32f0xx_hal_dma_ex.h
+++ b/Inc/stm32f0xx_hal_dma_ex.h
@@ -6,32 +6,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_DMA_EX_H
diff --git a/Inc/stm32f0xx_hal_exti.h b/Inc/stm32f0xx_hal_exti.h
new file mode 100644
index 0000000..d835a4f
--- /dev/null
+++ b/Inc/stm32f0xx_hal_exti.h
@@ -0,0 +1,375 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_exti.h
+ * @author MCD Application Team
+ * @brief Header file of EXTI HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F0xx_HAL_EXTI_H
+#define STM32F0xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup EXTI EXTI
+ * @brief EXTI HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL EXTI common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_EXTI_COMMON_CB_ID = 0x00U
+} EXTI_CallbackIDTypeDef;
+
+/**
+ * @brief EXTI Handle structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< Exti line number */
+ void (* PendingCallback)(void); /*!< Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+ * @brief EXTI Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Line; /*!< The Exti line to be configured. This parameter
+ can be a value of @ref EXTI_Line */
+ uint32_t Mode; /*!< The Exit Mode to be configured for a core.
+ This parameter can be a combination of @ref EXTI_Mode */
+ uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
+ can be a value of @ref EXTI_Trigger */
+ uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
+ This parameter is only possible for line 0 to 15. It
+ can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_Line EXTI Line
+ * @{
+ */
+#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
+#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
+#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
+#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
+#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
+#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
+#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
+#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
+#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
+#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
+#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
+#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
+#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
+#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
+#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
+#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
+
+#if defined (EXTI_IMR_MR16)
+#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
+#else
+#define EXTI_LINE_16 (EXTI_RESERVED | 0x10u)
+#endif /* EXTI_IMR_MR16 */
+
+#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+
+#if defined (EXTI_IMR_MR18)
+#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#else
+#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u)
+#endif /* EXTI_IMR_MR18 */
+
+#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+
+#if defined (EXTI_IMR_MR20)
+#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
+#else
+#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u)
+#endif /* EXTI_IMR_MR20 */
+
+#if defined (EXTI_IMR_MR21)
+#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */
+#else
+#define EXTI_LINE_21 (EXTI_RESERVED | 0x15u)
+#endif /* EXTI_IMR_MR21 */
+
+#if defined (EXTI_IMR_MR22)
+#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */
+#else
+#define EXTI_LINE_22 (EXTI_RESERVED | 0x16u)
+#endif /* EXTI_IMR_MR22 */
+
+#if defined (EXTI_IMR_MR23)
+#define EXTI_LINE_23 (EXTI_DIRECT | 0x17u) /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */
+#else
+#define EXTI_LINE_23 (EXTI_RESERVED | 0x17u)
+#endif /* EXTI_IMR_MR23 */
+
+#define EXTI_LINE_24 (EXTI_RESERVED | 0x18u)
+
+#if defined (EXTI_IMR_MR25)
+#define EXTI_LINE_25 (EXTI_CONFIG | 0x19u) /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */
+#else
+#define EXTI_LINE_25 (EXTI_RESERVED | 0x19u)
+#endif /* EXTI_IMR_MR25 */
+
+#if defined (EXTI_IMR_MR26)
+#define EXTI_LINE_26 (EXTI_CONFIG | 0x1Au) /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */
+#else
+#define EXTI_LINE_26 (EXTI_RESERVED | 0x1Au)
+#endif /* EXTI_IMR_MR26 */
+
+#if defined (EXTI_IMR_MR27)
+#define EXTI_LINE_27 (EXTI_CONFIG | 0x1Bu) /*!< External interrupt line 27 Connected to the internal CEC wakeup event */
+#else
+#define EXTI_LINE_27 (EXTI_RESERVED | 0x1Bu)
+#endif /* EXTI_IMR_MR27 */
+
+#if defined (EXTI_IMR_MR28)
+#define EXTI_LINE_28 (EXTI_CONFIG | 0x1Cu) /*!< External interrupt line 28 Connected to the internal USART3 wakeup event */
+#else
+#define EXTI_LINE_28 (EXTI_RESERVED | 0x1Cu)
+#endif /* EXTI_IMR_MR28 */
+
+#define EXTI_LINE_29 (EXTI_RESERVED | 0x1Du)
+#define EXTI_LINE_30 (EXTI_RESERVED | 0x1Eu)
+
+#if defined (EXTI_IMR_MR31)
+#define EXTI_LINE_31 (EXTI_CONFIG | 0x1Fu) /*!< External interrupt line 31 Connected to the VDDIO2 supply comparator output */
+#else
+#define EXTI_LINE_31 (EXTI_RESERVED | 0x1Fu)
+#endif /* EXTI_IMR_MR31 */
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Mode EXTI Mode
+ * @{
+ */
+#define EXTI_MODE_NONE 0x00000000u
+#define EXTI_MODE_INTERRUPT 0x00000001u
+#define EXTI_MODE_EVENT 0x00000002u
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Trigger EXTI Trigger
+ * @{
+ */
+#define EXTI_TRIGGER_NONE 0x00000000u
+#define EXTI_TRIGGER_RISING 0x00000001u
+#define EXTI_TRIGGER_FALLING 0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_GPIOSel EXTI GPIOSel
+ * @brief
+ * @{
+ */
+#define EXTI_GPIOA 0x00000000u
+#define EXTI_GPIOB 0x00000001u
+#define EXTI_GPIOC 0x00000002u
+#if defined (GPIOD)
+#define EXTI_GPIOD 0x00000003u
+#endif /* GPIOD */
+#if defined (GPIOE)
+#define EXTI_GPIOE 0x00000004u
+#endif /* GPIOE */
+#define EXTI_GPIOF 0x00000005u
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+/**
+ * @brief EXTI Line property definition
+ */
+#define EXTI_PROPERTY_SHIFT 24u
+#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
+
+/**
+ * @brief EXTI bit usage
+ */
+#define EXTI_PIN_MASK 0x0000001Fu
+
+/**
+ * @brief EXTI Mask for interrupt & event mode
+ */
+#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+ * @brief EXTI Mask for trigger possibilities
+ */
+#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+ * @brief EXTI Line number
+ */
+#define EXTI_LINE_NB 32uL
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+ ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
+
+#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+ (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
+
+#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if defined (GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOE) || \
+ ((__PORT__) == EXTI_GPIOF))
+#elif defined (GPIOD)
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOD) || \
+ ((__PORT__) == EXTI_GPIOF))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
+ ((__PORT__) == EXTI_GPIOB) || \
+ ((__PORT__) == EXTI_GPIOC) || \
+ ((__PORT__) == EXTI_GPIOF))
+#endif /* GPIOE */
+
+#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+ * @brief EXTI Exported Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F0xx_HAL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_flash.h b/Inc/stm32f0xx_hal_flash.h
index f2ee248..0302037 100644
--- a/Inc/stm32f0xx_hal_flash.h
+++ b/Inc/stm32f0xx_hal_flash.h
@@ -6,31 +6,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
diff --git a/Inc/stm32f0xx_hal_flash_ex.h b/Inc/stm32f0xx_hal_flash_ex.h
index 0d127e3..ddd5ea3 100644
--- a/Inc/stm32f0xx_hal_flash_ex.h
+++ b/Inc/stm32f0xx_hal_flash_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_hal_gpio.h b/Inc/stm32f0xx_hal_gpio.h
index 21157f8..ca18f53 100644
--- a/Inc/stm32f0xx_hal_gpio.h
+++ b/Inc/stm32f0xx_hal_gpio.h
@@ -6,31 +6,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -227,8 +211,8 @@
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
- (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+ ((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
diff --git a/Inc/stm32f0xx_hal_gpio_ex.h b/Inc/stm32f0xx_hal_gpio_ex.h
index 82169b4..3a6d604 100644
--- a/Inc/stm32f0xx_hal_gpio_ex.h
+++ b/Inc/stm32f0xx_hal_gpio_ex.h
@@ -6,32 +6,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_GPIO_EX_H
diff --git a/Inc/stm32f0xx_hal_i2c.h b/Inc/stm32f0xx_hal_i2c.h
index dfdbdec..d879d16 100644
--- a/Inc/stm32f0xx_hal_i2c.h
+++ b/Inc/stm32f0xx_hal_i2c.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_I2C_H
-#define __STM32F0xx_HAL_I2C_H
+#ifndef STM32F0xx_HAL_I2C_H
+#define STM32F0xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
@@ -102,17 +86,17 @@
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
- * b5 IP initilisation status\n
- * 0 : Reset (IP not initialized)\n
- * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
+ * b5 Peripheral initialization status\n
+ * 0 : Reset (peripheral not initialized)\n
+ * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
- * 1 : Listen (IP in Address Listen Mode)\n
+ * 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
- * 1 : Busy (IP busy with some configuration or internal operations)\n
+ * 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
@@ -186,6 +170,11 @@
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
@@ -226,7 +215,54 @@
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
+ void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
+ void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
+ void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
+
+ void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
+
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL I2C Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
+ HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
+ HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
+ HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
+ HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
+ HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
+ HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
+ HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
+ HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
+
+ HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
+ HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
+
+} HAL_I2C_CallbackIDTypeDef;
+
+/**
+ * @brief HAL I2C Callback pointer definition
+ */
+typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
+typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -248,6 +284,13 @@
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
+
+/* List of XferOptions in usage of :
+ * 1- Restart condition in all use cases (direction change or not)
+ */
+#define I2C_OTHER_FRAME (0x000000AAU)
+#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
@@ -335,9 +378,9 @@
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
-#define I2C_GENERATE_STOP I2C_CR2_STOP
-#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_GENERATE_START_WRITE I2C_CR2_START
+#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
@@ -396,7 +439,15 @@
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2C_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+#endif
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
@@ -469,6 +520,7 @@
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
+#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
@@ -528,6 +580,15 @@
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -553,10 +614,10 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
@@ -568,6 +629,11 @@
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
/**
* @}
*/
@@ -659,15 +725,20 @@
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME))
+ ((REQUEST) == I2C_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
+ IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+
+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
+ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
-#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
-#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
+#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
+#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
@@ -677,6 +748,9 @@
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
@@ -703,6 +777,6 @@
#endif
-#endif /* __STM32F0xx_HAL_I2C_H */
+#endif /* STM32F0xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_i2c_ex.h b/Inc/stm32f0xx_hal_i2c_ex.h
index 69bc8fb..0c57988 100644
--- a/Inc/stm32f0xx_hal_i2c_ex.h
+++ b/Inc/stm32f0xx_hal_i2c_ex.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_I2C_EX_H
-#define __STM32F0xx_HAL_I2C_EX_H
+#ifndef STM32F0xx_HAL_I2C_EX_H
+#define STM32F0xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
@@ -183,6 +167,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_I2C_EX_H */
+#endif /* STM32F0xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_i2s.h b/Inc/stm32f0xx_hal_i2s.h
index 1cf51f2..d2f96c4 100644
--- a/Inc/stm32f0xx_hal_i2s.h
+++ b/Inc/stm32f0xx_hal_i2s.h
@@ -6,65 +6,44 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_I2S_H
-#define __STM32F0xx_HAL_I2S_H
+#ifndef STM32F0xx_HAL_I2S_H
+#define STM32F0xx_HAL_I2S_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
+#if defined(SPI_I2S_SUPPORT)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @addtogroup I2S
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
-/**
- * @brief I2S Init structure definition
+/**
+ * @brief I2S Init structure definition
*/
typedef struct
{
@@ -85,60 +64,96 @@
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
+} I2S_InitTypeDef;
-/**
- * @brief HAL State structures definition
- */
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_PAUSE = 0x06U, /*!< I2S pause state: used in case of DMA */
- HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
-}HAL_I2S_StateTypeDef;
+ HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
+} HAL_I2S_StateTypeDef;
-/**
- * @brief I2S handle Structure definition
+/**
+ * @brief I2S handle Structure definition
*/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
+typedef struct __I2S_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
-
- uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
-
- __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
-
- __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
-
- uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
-
- __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
-
- __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
- (This field is initialized at the
- same value as transfer size at the
- beginning of the transfer and
- decremented when a sample is received.
- NbSamplesReceived = RxBufferSize-RxBufferCount) */
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received
+ NbSamplesReceived = RxBufferSize-RxBufferCount) */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
-
+
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
-
+
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
- __IO uint32_t ErrorCode; /*!< I2S Error code
+ __IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
-}I2S_HandleTypeDef;
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
+ void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
+ void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
+ void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
+ void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
+ void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
+
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+} I2S_HandleTypeDef;
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL I2S Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
+ HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
+ HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
+ HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
+ HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
+ HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
+ HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
+
+} HAL_I2S_CallbackIDTypeDef;
+
+/**
+ * @brief HAL I2S Callback pointer definition
+ */
+typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
+
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -150,12 +165,15 @@
/** @defgroup I2S_Error I2S Error
* @{
*/
-#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
-#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
-#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
-#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
-#define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */
+#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
+#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
+#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
+#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -164,48 +182,32 @@
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
-#define I2S_MODE_SLAVE_RX (0x00000100U)
-#define I2S_MODE_MASTER_TX (0x00000200U)
-#define I2S_MODE_MASTER_RX (0x00000300U)
-
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX)|| \
- ((MODE) == I2S_MODE_MASTER_RX))
+#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
/**
* @}
*/
-
+
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
-#define I2S_STANDARD_MSB (0x00000010U)
-#define I2S_STANDARD_LSB (0x00000020U)
-#define I2S_STANDARD_PCM_SHORT (0x00000030U)
-#define I2S_STANDARD_PCM_LONG (0x000000B0U)
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
+#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
/**
* @}
*/
-
+
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
-#define I2S_DATAFORMAT_24B (0x00000003U)
-#define I2S_DATAFORMAT_32B (0x00000005U)
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
+#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
+#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
/**
* @}
*/
@@ -213,11 +215,8 @@
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
-#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
+#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
+#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
/**
* @}
*/
@@ -235,86 +234,105 @@
#define I2S_AUDIOFREQ_11K (11025U)
#define I2S_AUDIOFREQ_8K (8000U)
#define I2S_AUDIOFREQ_DEFAULT (2U)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
/**
* @}
*/
-
+
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
-#define I2S_CPOL_LOW (0x00000000U)
-#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
+#define I2S_CPOL_LOW (0x00000000U)
+#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
-/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
-#define I2S_IT_TXE SPI_CR2_TXEIE
-#define I2S_IT_RXNE SPI_CR2_RXNEIE
-#define I2S_IT_ERR SPI_CR2_ERRIE
+#define I2S_IT_TXE SPI_CR2_TXEIE
+#define I2S_IT_RXNE SPI_CR2_RXNEIE
+#define I2S_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
-/** @defgroup I2S_Flag_definition I2S Flag definition
+/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
- */
-#define I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_RXNE SPI_SR_RXNE
+ */
+#define I2S_FLAG_TXE SPI_SR_TXE
+#define I2S_FLAG_RXNE SPI_SR_RXNE
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define I2S_FLAG_OVR SPI_SR_OVR
-#define I2S_FLAG_FRE SPI_SR_FRE
+#define I2S_FLAG_UDR SPI_SR_UDR
+#define I2S_FLAG_OVR SPI_SR_OVR
+#define I2S_FLAG_FRE SPI_SR_FRE
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_BSY SPI_SR_BSY
+#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
+#define I2S_FLAG_BSY SPI_SR_BSY
+
+#define I2S_FLAG_MASK (SPI_SR_RXNE\
+ | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
/**
* @}
- */
-
+ */
+
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
- * @param __HANDLE__ I2S handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__ specifies the I2S Handle.
+/** @brief Enable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
+#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-/** @brief Enable or disable the specified I2S interrupts.
+/** @brief Disable the specified SPI peripheral (in I2S mode).
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @retval None
+ */
+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
- */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
-
+ */
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
+/** @brief Disable the specified I2S interrupts.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval None
+ */
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
+
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
@@ -325,12 +343,13 @@
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
@@ -345,39 +364,46 @@
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
- */
+ */
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- }while(0)
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ }while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
- */
+ */
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
- __IO uint32_t tmpreg;\
- tmpreg = ((__HANDLE__)->Instance->SR);\
- UNUSED(tmpreg); \
- }while(0)
+ __IO uint32_t tmpreg_udr = 0x00U;\
+ tmpreg_udr = ((__HANDLE__)->Instance->SR);\
+ UNUSED(tmpreg_udr); \
+ }while(0U)
/**
* @}
- */
-
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
*/
-
+
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
-/* Initialization/de-initialization functions **********************************/
+/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -386,11 +412,11 @@
* @{
*/
/* I/O operation functions ***************************************************/
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
@@ -425,8 +451,78 @@
/**
* @}
- */
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of I2S SR regsiter.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
+ * @arg I2S_FLAG_TXE: Transmit buffer empty flag
+ * @arg I2S_FLAG_UDR: Underrun error flag
+ * @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_CHSIDE: Channel side flag
+ * @arg I2S_FLAG_BSY: Busy flag
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
+ & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of I2S CR2 regsiter.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
+ * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg I2S_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Checks if I2S Mode parameter is in allowed range.
+ * @param __MODE__ specifies the I2S Mode.
+ * This parameter can be a value of @ref I2S_Mode
+ * @retval None
+ */
+#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
+ ((__MODE__) == I2S_MODE_SLAVE_RX) || \
+ ((__MODE__) == I2S_MODE_MASTER_TX) || \
+ ((__MODE__) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
+ ((__STANDARD__) == I2S_STANDARD_MSB) || \
+ ((__STANDARD__) == I2S_STANDARD_LSB) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
+ ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
+
+#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
+ ((__FORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
+ ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
+ ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
+ ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+
+/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__ specifies the I2S serial clock steady state.
+ * This parameter can be a value of @ref I2S_Clock_Polarity
+ * @retval None
+ */
+#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
+ ((__CPOL__) == I2S_CPOL_HIGH))
/**
* @}
@@ -435,17 +531,16 @@
/**
* @}
*/
-#endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
- /* defined(STM32F051x8) || defined(STM32F058xx) || */
- /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||*/
- /* defined(STM32F042x6) || defined(STM32F048xx) || */
- /* defined(STM32F091xC) || defined(STM32F098xx) */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
#ifdef __cplusplus
}
#endif
-
-#endif /* __STM32F0xx_HAL_I2S_H */
+#endif /* STM32F0xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_irda.h b/Inc/stm32f0xx_hal_irda.h
index 6df14dd..25cdd79 100644
--- a/Inc/stm32f0xx_hal_irda.h
+++ b/Inc/stm32f0xx_hal_irda.h
@@ -2,48 +2,30 @@
******************************************************************************
* @file stm32f0xx_hal_irda.h
* @author MCD Application Team
- * @brief This file contains all the functions prototypes for the IRDA
- * firmware library.
+ * @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_IRDA_H
-#define __STM32F0xx_HAL_IRDA_H
+#ifndef STM32F0xx_HAL_IRDA_H
+#define STM32F0xx_HAL_IRDA_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-
+#if defined(USART_IRDA_SUPPORT)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -67,7 +49,8 @@
{
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
+ Baud Rate Register = ((usart_ker_clk) / ((hirda->Init.BaudRate)))
+ where usart_ker_clk is the IRDA input clock */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDAEx_Word_Length */
@@ -88,27 +71,28 @@
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
+
+} IRDA_InitTypeDef;
/**
- * @brief HAL IRDA State structures definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
- * - gState contains IRDA state information related to global Handle management
+ * @brief HAL IRDA State definition
+ * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
+ * - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
- * b7-b6 Error information
+ * b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -118,9 +102,9 @@
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -129,45 +113,30 @@
* b0 (not used)
* x : Should be set to 0.
*/
-typedef enum
-{
- HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_IRDA_StateTypeDef;
+typedef uint32_t HAL_IRDA_StateTypeDef;
/**
* @brief IRDA clock sources definition
*/
typedef enum
{
- IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- IRDA_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- IRDA_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}IRDA_ClockSourceTypeDef;
+ IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
+ IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
+} IRDA_ClockSourceTypeDef;
/**
* @brief IRDA handle Structure definition
*/
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+typedef struct __IRDA_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
{
- USART_TypeDef *Instance; /*!< IRDA registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
@@ -183,7 +152,7 @@
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
- uint16_t Mask; /*!< IRDA RX RDR register mask */
+ uint16_t Mask; /*!< USART RX RDR register mask */
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
@@ -191,30 +160,66 @@
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
+ __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
- __IO uint32_t ErrorCode; /*!< IRDA Error code
- This parameter can be a value of @ref IRDA_Error */
+ __IO uint32_t ErrorCode; /*!< IRDA Error code */
-}IRDA_HandleTypeDef;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
+
+ void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
+
+ void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
+
+ void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
+
+
+ void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+} IRDA_HandleTypeDef;
+
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
- * @brief IRDA Configuration enumeration values definition
+ * @brief HAL IRDA Callback ID enumeration definition
*/
typedef enum
{
- IRDA_BAUDRATE = 0x00U, /*!< IRDA Baud rate */
- IRDA_PARITY = 0x01U, /*!< IRDA frame parity */
- IRDA_WORDLENGTH = 0x02U, /*!< IRDA frame length */
- IRDA_MODE = 0x03U, /*!< IRDA communication mode */
- IRDA_PRESCALER = 0x04U, /*!< IRDA prescaling */
- IRDA_POWERMODE = 0x05U /*!< IRDA power mode */
-}IRDA_ControlTypeDef;
+ HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
+ HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
+ HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
+ HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
+ HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
+ HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
+ HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
+ HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
+
+ HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
+ HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
+
+} HAL_IRDA_CallbackIDTypeDef;
+
+/**
+ * @brief HAL IRDA Callback pointer definition
+ */
+typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
+
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
@@ -225,16 +230,43 @@
* @{
*/
-/** @defgroup IRDA_Error IRDA Error
+/** @defgroup IRDA_State_Definition IRDA State Code Definition
* @{
*/
-#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
+#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
+ * @{
+ */
+#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
+#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -242,9 +274,9 @@
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
-#define IRDA_PARITY_NONE (0x00000000U) /*!< No parity */
-#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
+#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
@@ -252,9 +284,9 @@
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
* @{
*/
-#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
+#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
+#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
@@ -262,8 +294,8 @@
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
-#define IRDA_POWERMODE_NORMAL (0x00000000U) /*!< IRDA normal power mode */
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
+#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
+#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
/**
* @}
*/
@@ -271,26 +303,26 @@
/** @defgroup IRDA_State IRDA State
* @{
*/
-#define IRDA_STATE_DISABLE (0x00000000U) /*!< IRDA disabled */
-#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
+#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
+#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
/**
* @}
*/
-/** @defgroup IRDA_Mode IRDA Mode
+/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
-#define IRDA_MODE_DISABLE (0x00000000U) /*!< Associated UART disabled in IRDA mode */
-#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
+#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
+#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
/**
* @}
*/
-/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
* @{
*/
-#define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disabled */
-#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
+#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
+#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
/**
* @}
*/
@@ -298,17 +330,17 @@
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
-#define IRDA_DMA_TX_DISABLE (0x00000000U) /*!< IRDA DMA TX disabled */
-#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
+#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
+#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
/**
* @}
*/
-/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
-#define IRDA_DMA_RX_DISABLE (0x00000000U) /*!< IRDA DMA RX disabled */
-#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
+#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
+#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
/**
* @}
*/
@@ -316,9 +348,9 @@
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
* @{
*/
-#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
+#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
@@ -328,18 +360,18 @@
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
-#define IRDA_FLAG_REACK (0x00400000U) /*!< IRDA Receive enable acknowledge flag */
-#define IRDA_FLAG_TEACK (0x00200000U) /*!< IRDA Transmit enable acknowledge flag */
-#define IRDA_FLAG_BUSY (0x00010000U) /*!< IRDA Busy flag */
-#define IRDA_FLAG_ABRF (0x00008000U) /*!< IRDA Auto baud rate flag */
-#define IRDA_FLAG_ABRE (0x00004000U) /*!< IRDA Auto baud rate error */
-#define IRDA_FLAG_TXE (0x00000080U) /*!< IRDA Transmit data register empty */
-#define IRDA_FLAG_TC (0x00000040U) /*!< IRDA Transmission complete */
-#define IRDA_FLAG_RXNE (0x00000020U) /*!< IRDA Read data register not empty */
-#define IRDA_FLAG_ORE (0x00000008U) /*!< IRDA Overrun error */
-#define IRDA_FLAG_NE (0x00000004U) /*!< IRDA Noise error */
-#define IRDA_FLAG_FE (0x00000002U) /*!< IRDA Framing error */
-#define IRDA_FLAG_PE (0x00000001U) /*!< IRDA Parity error */
+#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
+#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
+#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
+#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
+#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
+#define IRDA_FLAG_TXE USART_ISR_TXE /*!< IRDA transmit data register empty */
+#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
+#define IRDA_FLAG_RXNE USART_ISR_RXNE /*!< IRDA read data register not empty */
+#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
+#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
+#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
+#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
/**
* @}
*/
@@ -354,25 +386,35 @@
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
-#define IRDA_IT_PE ((uint16_t)0x0028U) /*!< IRDA Parity error interruption */
-#define IRDA_IT_TXE ((uint16_t)0x0727U) /*!< IRDA Transmit data register empty interruption */
-#define IRDA_IT_TC ((uint16_t)0x0626U) /*!< IRDA Transmission complete interruption */
-#define IRDA_IT_RXNE ((uint16_t)0x0525U) /*!< IRDA Read data register not empty interruption */
-#define IRDA_IT_IDLE ((uint16_t)0x0424U) /*!< IRDA Idle interruption */
-#define IRDA_IT_ERR ((uint16_t)0x0060U) /*!< IRDA Error interruption */
-#define IRDA_IT_ORE ((uint16_t)0x0300U) /*!< IRDA Overrun error interruption */
-#define IRDA_IT_NE ((uint16_t)0x0200U) /*!< IRDA Noise error interruption */
-#define IRDA_IT_FE ((uint16_t)0x0100U) /*!< IRDA Frame error interruption */
+#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
+#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
+#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
+#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
+#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
+
+/* Elements values convention: 000000000XXYYYYYb
+ - YYYYY : Interrupt source position in the XX register (5bits)
+ - XX : Interrupt source register (2bits)
+ - 01: CR1 register
+ - 10: CR2 register
+ - 11: CR3 register */
+#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
+
+/* Elements values convention: 0000ZZZZ00000000b
+ - ZZZZ : Flag position in the ISR register(4bits) */
+#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
+#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
+#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
/**
* @}
*/
-/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
* @{
*/
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
+#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
@@ -380,18 +422,21 @@
* @}
*/
-/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
* @{
*/
-#define IRDA_IT_MASK ((uint16_t)0x001FU) /*!< IRDA Interruptions flags mask */
+#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
+#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
+#define IRDA_CR_POS 5U /*!< IRDA control register position */
+#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
+#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
/**
* @}
*/
/**
- * @}
- */
-
+ * @}
+ */
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
@@ -402,20 +447,29 @@
* @param __HANDLE__ IRDA handle.
* @retval None
*/
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
- } while(0)
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
/** @brief Flush the IRDA DR register.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
- } while(0)
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -495,9 +549,9 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -511,14 +565,14 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
- * @param __IT__ specifies the IRDA interrupt source to check.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
@@ -528,13 +582,14 @@
* @arg @ref IRDA_IT_NE Noise Error interrupt
* @arg @ref IRDA_IT_FE Framing Error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
- * @param __IT__ specifies the IRDA interrupt source to check.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
@@ -542,11 +597,11 @@
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
-
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -570,22 +625,22 @@
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
- *
* @retval None
*/
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the IRDA one bit sample method.
- * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the IRDA one bit sample method.
- * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+ &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -604,7 +659,7 @@
*/
/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
+/** @addtogroup IRDA_Private_Macros
* @{
*/
@@ -620,81 +675,73 @@
*/
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
-/**
- * @brief Ensure that IRDA frame parity is valid.
- * @param __PARITY__ IRDA frame parity.
+/** @brief Ensure that IRDA frame parity is valid.
+ * @param __PARITY__ IRDA frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
+ */
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
((__PARITY__) == IRDA_PARITY_EVEN) || \
((__PARITY__) == IRDA_PARITY_ODD))
-/**
- * @brief Ensure that IRDA communication mode is valid.
- * @param __MODE__ IRDA communication mode.
+/** @brief Ensure that IRDA communication mode is valid.
+ * @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+ */
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
+ & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
-/**
- * @brief Ensure that IRDA power mode is valid.
- * @param __MODE__ IRDA power mode.
+/** @brief Ensure that IRDA power mode is valid.
+ * @param __MODE__ IRDA power mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
+ */
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
((__MODE__) == IRDA_POWERMODE_NORMAL))
-/**
- * @brief Ensure that IRDA state is valid.
- * @param __STATE__ IRDA state mode.
+/** @brief Ensure that IRDA state is valid.
+ * @param __STATE__ IRDA state mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
+ */
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
((__STATE__) == IRDA_STATE_ENABLE))
-/**
- * @brief Ensure that IRDA associated UART/USART mode is valid.
- * @param __MODE__ IRDA associated UART/USART mode.
+/** @brief Ensure that IRDA associated UART/USART mode is valid.
+ * @param __MODE__ IRDA associated UART/USART mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
+ */
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
((__MODE__) == IRDA_MODE_ENABLE))
-/**
- * @brief Ensure that IRDA sampling rate is valid.
- * @param __ONEBIT__ IRDA sampling rate.
+/** @brief Ensure that IRDA sampling rate is valid.
+ * @param __ONEBIT__ IRDA sampling rate.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
- */
+ */
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
-/**
- * @brief Ensure that IRDA DMA TX mode is valid.
- * @param __DMATX__ IRDA DMA TX mode.
+/** @brief Ensure that IRDA DMA TX mode is valid.
+ * @param __DMATX__ IRDA DMA TX mode.
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
- */
+ */
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
((__DMATX__) == IRDA_DMA_TX_ENABLE))
-/**
- * @brief Ensure that IRDA DMA RX mode is valid.
- * @param __DMARX__ IRDA DMA RX mode.
+/** @brief Ensure that IRDA DMA RX mode is valid.
+ * @param __DMARX__ IRDA DMA RX mode.
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
- */
+ */
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
((__DMARX__) == IRDA_DMA_RX_ENABLE))
-/**
- * @brief Ensure that IRDA request is valid.
- * @param __PARAM__ IRDA request.
+/** @brief Ensure that IRDA request is valid.
+ * @param __PARAM__ IRDA request.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
+ */
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
- * @}
- */
+ * @}
+ */
/* Include IRDA HAL Extended module */
#include "stm32f0xx_hal_irda_ex.h"
@@ -714,6 +761,13 @@
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+ pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -746,9 +800,9 @@
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
/**
* @}
@@ -756,7 +810,7 @@
/* Peripheral Control functions ************************************************/
-/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
@@ -779,14 +833,12 @@
/**
* @}
*/
-
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* USART_IRDA_SUPPORT */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_IRDA_H */
+#endif /* STM32F0xx_HAL_IRDA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_irda_ex.h b/Inc/stm32f0xx_hal_irda_ex.h
index 52df110..09fd28b 100644
--- a/Inc/stm32f0xx_hal_irda_ex.h
+++ b/Inc/stm32f0xx_hal_irda_ex.h
@@ -6,43 +6,26 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_IRDA_EX_H
-#define __STM32F0xx_HAL_IRDA_EX_H
+#ifndef STM32F0xx_HAL_IRDA_EX_H
+#define STM32F0xx_HAL_IRDA_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-
+#if defined(USART_IRDA_SUPPORT)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -50,41 +33,37 @@
* @{
*/
-/** @addtogroup IRDAEx
+/** @defgroup IRDAEx IRDAEx
+ * @brief IRDA Extended HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDAEx_Exported_Constants IRDAEx Exported Constants
+/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
* @{
*/
-
-/** @defgroup IRDAEx_Word_Length IRDA Word Length
+
+/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
* @{
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
-#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
-#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
-#else
+#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
+#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
+#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
+#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
+#elif defined(USART_CR1_M)
#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long frame */
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)*/
+#endif
/**
* @}
*/
-
+
/**
* @}
- */
+ */
/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
@@ -120,8 +99,7 @@
break; \
} \
} while(0)
-#elif defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F051x8) || defined (STM32F058xx)
+#elif defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -316,46 +294,48 @@
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x003FU ; \
- } \
- } \
-} while(0)
-#else
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+#elif defined(USART_CR1_M)
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
@@ -380,29 +360,21 @@
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
-} while(0)
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined(STM32F098xx) */
+} while(0U)
+#endif
-/**
- * @brief Ensure that IRDA frame length is valid.
- * @param __LENGTH__ IRDA frame length.
+/** @brief Ensure that IRDA frame length is valid.
+ * @param __LENGTH__ IRDA frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#if defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+ */
+#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#else
+#elif defined(USART_CR1_M)
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)*/
-
+#endif
/**
* @}
*/
@@ -416,14 +388,12 @@
/**
* @}
*/
+#endif /* USART_IRDA_SUPPORT */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_IRDA_EX_H */
+#endif /* STM32F0xx_HAL_IRDA_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_iwdg.h b/Inc/stm32f0xx_hal_iwdg.h
index b3f3cd2..73bbb27 100644
--- a/Inc/stm32f0xx_hal_iwdg.h
+++ b/Inc/stm32f0xx_hal_iwdg.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_IWDG_H
-#define __STM32F0xx_HAL_IWDG_H
+#ifndef STM32F0xx_HAL_IWDG_H
+#define STM32F0xx_HAL_IWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -57,7 +41,7 @@
* @{
*/
-/**
+/**
* @brief IWDG Init structure definition
*/
typedef struct
@@ -73,16 +57,16 @@
} IWDG_InitTypeDef;
-/**
- * @brief IWDG Handle Structure definition
+/**
+ * @brief IWDG Handle Structure definition
*/
typedef struct
{
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
+} IWDG_HandleTypeDef;
-}IWDG_HandleTypeDef;
/**
* @}
@@ -96,13 +80,14 @@
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
-#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
+
/**
* @}
*/
@@ -115,6 +100,7 @@
* @}
*/
+
/**
* @}
*/
@@ -133,7 +119,7 @@
/**
* @brief Reload IWDG counter with value defined in the reload register
- * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
+ * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
@@ -178,10 +164,10 @@
/**
* @brief IWDG Key Register BitMask
*/
-#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
-#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
@@ -233,6 +219,7 @@
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
+
/**
* @}
*/
@@ -250,7 +237,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_IWDG_H */
+#endif /* STM32F0xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_pcd.h b/Inc/stm32f0xx_hal_pcd.h
index 9fd5094..36ed6a8 100644
--- a/Inc/stm32f0xx_hal_pcd.h
+++ b/Inc/stm32f0xx_hal_pcd.h
@@ -6,45 +6,29 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_PCD_H
-#define __STM32F0xx_HAL_PCD_H
+#ifndef STM32F0xx_HAL_PCD_H
+#define STM32F0xx_HAL_PCD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
-
/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_hal_def.h"
+#include "stm32f0xx_ll_usb.h"
+
+#if defined (USB)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
@@ -52,161 +36,152 @@
/** @addtogroup PCD
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup PCD_Exported_Types PCD Exported Types
* @{
*/
-/**
- * @brief PCD State structure definition
- */
-typedef enum
-{
- HAL_PCD_STATE_RESET = 0x00U,
- HAL_PCD_STATE_READY = 0x01U,
- HAL_PCD_STATE_ERROR = 0x02U,
- HAL_PCD_STATE_BUSY = 0x03U,
- HAL_PCD_STATE_TIMEOUT = 0x04U
-} PCD_StateTypeDef;
-
/**
- * @brief PCD double buffered endpoint direction
+ * @brief PCD State structure definition
*/
typedef enum
{
- PCD_EP_DBUF_OUT,
- PCD_EP_DBUF_IN,
- PCD_EP_DBUF_ERR,
-}PCD_EP_DBUF_DIR;
+ HAL_PCD_STATE_RESET = 0x00,
+ HAL_PCD_STATE_READY = 0x01,
+ HAL_PCD_STATE_ERROR = 0x02,
+ HAL_PCD_STATE_BUSY = 0x03,
+ HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum
+{
+ LPM_L0 = 0x00, /* on */
+ LPM_L1 = 0x01, /* LPM L1 sleep */
+ LPM_L2 = 0x02, /* suspend */
+ LPM_L3 = 0x03, /* off */
+} PCD_LPM_StateTypeDef;
+
+typedef enum
+{
+ PCD_LPM_L0_ACTIVE = 0x00, /* on */
+ PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+} PCD_LPM_MsgTypeDef;
+
+typedef enum
+{
+ PCD_BCD_ERROR = 0xFF,
+ PCD_BCD_CONTACT_DETECTION = 0xFE,
+ PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
+ PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
+ PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
+ PCD_BCD_DISCOVERY_COMPLETED = 0x00,
+
+} PCD_BCD_MsgTypeDef;
+
+
+
+
+
+typedef USB_TypeDef PCD_TypeDef;
+typedef USB_CfgTypeDef PCD_InitTypeDef;
+typedef USB_EPTypeDef PCD_EPTypeDef;
+
/**
- * @brief PCD endpoint buffer number
+ * @brief PCD Handle Structure definition
*/
-typedef enum
-{
- PCD_EP_NOBUF,
- PCD_EP_BUF0,
- PCD_EP_BUF1
-}PCD_EP_BUF_NUM;
-
-/**
- * @brief PCD Initialization Structure definition
- */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+typedef struct __PCD_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Core_Speed */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref PCD_EP0_MPS */
-
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_Core_PHY */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t lpm_enable; /*!< Enable or disable the Link Power Management .
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.
- This parameter can be set to ENABLE or DISABLE */
-
-}PCD_InitTypeDef;
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ uint32_t BESL;
-typedef struct
-{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref PCD_EP_Type */
-
- uint16_t pmaadress; /*!< PMA Address
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t pmaaddr0; /*!< PMA Address0
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
+ This parameter can be set to ENABLE or DISABLE */
- uint16_t pmaaddr1; /*!< PMA Address1
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
+ This parameter can be set to ENABLE or DISABLE */
+ void *pData; /*!< Pointer to upper stack Handler */
- uint8_t doublebuffer; /*!< Double buffer enable
- This parameter can be 0 or 1 */
-
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
+ void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
+ void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
+ void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
+ void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
+ void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
+ void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
- uint32_t xfer_len; /*!< Current transfer length */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+ void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
+ void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
+ void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
+ void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
+ void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
+ void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
-}PCD_EPTypeDef;
-
-typedef USB_TypeDef PCD_TypeDef;
-
-/**
- * @brief PCD Handle Structure definition
- */
-typedef struct
-{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- void *pData; /*!< Pointer to upper stack Handler */
-
+ void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
+ void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
} PCD_HandleTypeDef;
/**
* @}
- */
-
-/* Include PCD HAL Extension module */
+ */
+
+/* Include PCD HAL Extended module */
#include "stm32f0xx_hal_pcd_ex.h"
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-/** @defgroup PCD_Core_Speed PCD Core Speed
+/** @defgroup PCD_Speed PCD Speed
* @{
*/
-#define PCD_SPEED_HIGH 0 /* Not Supported */
-#define PCD_SPEED_FULL 2
+#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
-
- /** @defgroup PCD_Core_PHY PCD Core PHY
+
+/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
-#define PCD_PHY_EMBEDDED 2
+#define PCD_PHY_ULPI 1U
+#define PCD_PHY_EMBEDDED 2U
+#define PCD_PHY_UTMI 3U
/**
* @}
*/
+
+/** @defgroup PCD_Error_Code_definition PCD Error Code definition
+ * @brief PCD Error Code definition
+ * @{
+ */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -214,18 +189,22 @@
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__))))
+ * @{
+ */
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
-
+
+#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
+
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+
+
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
@@ -237,33 +216,96 @@
* @{
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
+ * @brief HAL USB OTG PCD Callback ID enumeration definition
+ * @{
+ */
+typedef enum
+{
+ HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
+ HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
+ HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
+ HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
+ HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
+ HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+
+ HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
+ HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
+
+} HAL_PCD_CallbackIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
+ * @brief HAL USB OTG PCD Callback pointer definition
+ * @{
+ */
+
+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
+
+/**
+ * @}
+ */
+
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
+
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
/**
* @}
*/
@@ -279,7 +321,7 @@
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
@@ -309,7 +351,11 @@
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
* @{
*/
-#define USB_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR_MR18) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+
+
+#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
+
+
/**
* @}
*/
@@ -317,41 +363,25 @@
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
-#define DEP0CTL_MPS_64 0
-#define DEP0CTL_MPS_32 1
-#define DEP0CTL_MPS_16 2
-#define DEP0CTL_MPS_8 3
-
-#define PCD_EP0MPS_64 DEP0CTL_MPS_64
-#define PCD_EP0MPS_32 DEP0CTL_MPS_32
-#define PCD_EP0MPS_16 DEP0CTL_MPS_16
-#define PCD_EP0MPS_08 DEP0CTL_MPS_8
+#define PCD_EP0MPS_64 DEP0CTL_MPS_64
+#define PCD_EP0MPS_32 DEP0CTL_MPS_32
+#define PCD_EP0MPS_16 DEP0CTL_MPS_16
+#define PCD_EP0MPS_08 DEP0CTL_MPS_8
/**
* @}
- */
-
-/** @defgroup PCD_EP_Type PCD EP Type
- * @{
*/
-#define PCD_EP_TYPE_CTRL 0
-#define PCD_EP_TYPE_ISOC 1
-#define PCD_EP_TYPE_BULK 2
-#define PCD_EP_TYPE_INTR 3
-/**
- * @}
- */
/** @defgroup PCD_ENDP PCD ENDP
* @{
*/
-#define PCD_ENDP0 ((uint8_t)0U)
-#define PCD_ENDP1 ((uint8_t)1U)
-#define PCD_ENDP2 ((uint8_t)2U)
-#define PCD_ENDP3 ((uint8_t)3U)
-#define PCD_ENDP4 ((uint8_t)4U)
-#define PCD_ENDP5 ((uint8_t)5U)
-#define PCD_ENDP6 ((uint8_t)6U)
-#define PCD_ENDP7 ((uint8_t)7U)
+#define PCD_ENDP0 0U
+#define PCD_ENDP1 1U
+#define PCD_ENDP2 2U
+#define PCD_ENDP3 3U
+#define PCD_ENDP4 4U
+#define PCD_ENDP5 5U
+#define PCD_ENDP6 6U
+#define PCD_ENDP7 7U
/**
* @}
*/
@@ -359,8 +389,8 @@
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
* @{
*/
-#define PCD_SNG_BUF 0
-#define PCD_DBL_BUF 1
+#define PCD_SNG_BUF 0U
+#define PCD_DBL_BUF 1U
/**
* @}
*/
@@ -370,17 +400,22 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @addtogroup PCD_Private_Macros PCD Private Macros
- * @{
- */
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/******************** Bit definition for USB_COUNTn_RX register *************/
+#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
+#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
-
+/* ENDPOINT transfer */
+#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -389,8 +424,8 @@
* @param wType Endpoint Type.
* @retval None
*/
-#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- (((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType))) | USB_EP_CTR_RX | USB_EP_CTR_TX)))
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -398,45 +433,27 @@
* @param bEpNum Endpoint Number.
* @retval Endpoint Type
*/
-#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
-
+#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
/**
* @brief free buffer used from the application realizing it to the line
- toggles bit SW_BUF in the double buffered endpoint register
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @param bDir Direction
+ * toggles bit SW_BUF in the double buffered endpoint register
+ * @param USBx USB device.
+ * @param bEpNum, bDir
* @retval None
*/
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
-{\
- if ((bDir) == PCD_EP_DBUF_OUT)\
- { /* OUT double buffered endpoint */\
- PCD_TX_DTOG((USBx), (bEpNum));\
- }\
- else if ((bDir) == PCD_EP_DBUF_IN)\
- { /* IN double buffered endpoint */\
- PCD_RX_DTOG((USBx), (bEpNum));\
- }\
-}
-
-/**
- * @brief gets direction of the double buffered endpoint
- * @param USBx USB peripheral instance register address.
- * @param bEpNum Endpoint Number.
- * @retval EP_DBUF_OUT, EP_DBUF_IN,
- * EP_DBUF_ERR if the endpoint counter not yet programmed.
- */
-#define PCD_GET_DB_DIR(USBx, bEpNum)\
-{\
- if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00U) != 0U)\
- return(PCD_EP_DBUF_OUT);\
- else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FFU) != 0U)\
- return(PCD_EP_DBUF_IN);\
- else\
- return(PCD_EP_DBUF_ERR);\
-}
+#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
+ if ((bDir) == 0U) \
+ { \
+ /* OUT double buffered endpoint */ \
+ PCD_TX_DTOG((USBx), (bEpNum)); \
+ } \
+ else if ((bDir) == 1U) \
+ { \
+ /* IN double buffered endpoint */ \
+ PCD_RX_DTOG((USBx), (bEpNum)); \
+ } \
+} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
@@ -445,21 +462,22 @@
* @param wState new state
* @retval None
*/
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
+#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
+ register uint16_t _wRegVal; \
\
- _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
- /* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wState))!= 0U)\
- { \
- _wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
- { \
- _wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
- } /* PCD_SET_EP_TX_STATUS */
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while(0) /* PCD_SET_EP_TX_STATUS */
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
@@ -468,22 +486,22 @@
* @param wState new state
* @retval None
*/
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
- register uint16_t _wRegVal; \
+#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
+ register uint16_t _wRegVal; \
\
- _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
- /* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & (wState))!= 0U) \
- { \
- _wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
- { \
- _wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
- } /* PCD_SET_EP_RX_STATUS */
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
+ /* toggle first bit ? */ \
+ if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ } \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while(0) /* PCD_SET_EP_RX_STATUS */
/**
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
@@ -493,32 +511,33 @@
* @param wStatetx new state.
* @retval None
*/
-#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
- register uint32_t _wRegVal; \
+#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
+ register uint16_t _wRegVal; \
\
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
- /* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG2; \
- } \
- /* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
- { \
- _wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
- { \
- _wRegVal ^= USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
- } /* PCD_SET_EP_TXRX_STATUS */
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
+ /* toggle first bit ? */ \
+ if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPRX_DTOG2; \
+ } \
+ /* toggle first bit ? */ \
+ if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG1; \
+ } \
+ /* toggle second bit ? */ \
+ if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
+ { \
+ _wRegVal ^= USB_EPTX_DTOG2; \
+ } \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while(0) /* PCD_SET_EP_TXRX_STATUS */
/**
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
@@ -527,8 +546,8 @@
* @param bEpNum Endpoint Number.
* @retval status
*/
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
/**
* @brief sets directly the VALID tx/rx-status into the endpoint register
@@ -536,8 +555,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
+#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
+#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
/**
* @brief checks stall condition in an endpoint.
@@ -556,10 +575,21 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
+#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
+ } while(0) /* PCD_SET_EP_KIND */
+
+#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while(0) /* PCD_CLEAR_EP_KIND */
/**
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
@@ -567,8 +597,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
@@ -576,8 +606,8 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
+#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
+#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
@@ -585,10 +615,21 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
+#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
+ } while(0) /* PCD_CLEAR_RX_EP_CTR */
+
+#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
+ } while(0) /* PCD_CLEAR_TX_EP_CTR */
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
@@ -596,26 +637,49 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
-#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
+#define PCD_RX_DTOG(USBx, bEpNum) do { \
+ register uint16_t _wEPVal; \
+ \
+ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
+ } while(0) /* PCD_RX_DTOG */
+#define PCD_TX_DTOG(USBx, bEpNum) do { \
+ register uint16_t _wEPVal; \
+ \
+ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
+ } while(0) /* PCD_TX_DTOG */
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
- { \
- PCD_RX_DTOG((USBx),(bEpNum));\
- }
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
- {\
- PCD_TX_DTOG((USBx),(bEpNum));\
- }
-
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
+ \
+ if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
+ { \
+ PCD_RX_DTOG((USBx), (bEpNum)); \
+ } \
+ } while(0) /* PCD_CLEAR_RX_DTOG */
+
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
+ \
+ if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
+ { \
+ PCD_TX_DTOG((USBx), (bEpNum)); \
+ } \
+ } while(0) /* PCD_CLEAR_TX_DTOG */
+
/**
* @brief Sets address in an endpoint register.
* @param USBx USB peripheral instance register address.
@@ -623,8 +687,13 @@
* @param bAddr Address.
* @retval None
*/
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
- USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
+#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
+ register uint16_t _wRegVal; \
+ \
+ _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
+ \
+ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
+ } while(0) /* PCD_SET_EP_ADDRESS */
/**
* @brief Gets address in an endpoint register.
@@ -634,11 +703,8 @@
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)+ ((uint32_t)(USBx) + 0x400U)))))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)+ ((uint32_t)(USBx) + 0x400U)))))
-
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/**
* @brief sets address of the tx/rx buffer.
@@ -647,8 +713,23 @@
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
+ register uint16_t *_wRegVal; \
+ register uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+} while(0) /* PCD_SET_EP_TX_ADDRESS */
+
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
+ register uint16_t *_wRegVal; \
+ register uint32_t _wRegBase = (uint32_t)USBx; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
+ *_wRegVal = ((wAddr) >> 1) << 1; \
+} while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
@@ -661,48 +742,54 @@
/**
* @brief Sets counter of rx buffer with no. of blocks.
- * @param dwReg Register
+ * @param pdwReg Register pointer
* @param wCount Counter.
* @param wNBlocks no. of Blocks.
* @retval None
*/
-#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 5U;\
- if(((wCount) & 0x1fU) == 0U)\
- { \
- (wNBlocks)--;\
- } \
- *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
- }/* PCD_CALC_BLK32 */
+#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
+ (wNBlocks) = (wCount) >> 5; \
+ if (((wCount) & 0x1fU) == 0U) \
+ { \
+ (wNBlocks)--; \
+ } \
+ *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
+ } while(0) /* PCD_CALC_BLK32 */
+#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
+ (wNBlocks) = (wCount) >> 1; \
+ if (((wCount) & 0x1U) != 0U) \
+ { \
+ (wNBlocks)++; \
+ } \
+ *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
+ } while(0) /* PCD_CALC_BLK2 */
-#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 1U;\
- if(((wCount) & 0x1U) != 0U)\
- { \
- (wNBlocks)++;\
- } \
- *pdwReg = (uint16_t)((wNBlocks) << 10U);\
- }/* PCD_CALC_BLK2 */
+#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
+ uint32_t wNBlocks; \
+ if ((wCount) == 0U) \
+ { \
+ *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } \
+ else if((wCount) <= 62U) \
+ { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ } \
+ else \
+ { \
+ PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \
+ } \
+ } while(0) /* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
- uint16_t wNBlocks;\
- if((wCount) > 62U) \
- { \
- PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
- } \
- else \
- { \
- PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
- } \
- }/* PCD_SET_EP_CNT_RX_REG */
-
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
- uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
- }
+#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
+ register uint32_t _wRegBase = (uint32_t)(USBx); \
+ uint16_t *pdwReg; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
+ } while(0)
/**
* @brief sets counter for the tx/rx buffer.
@@ -711,11 +798,23 @@
* @param wCount Counter value.
* @retval None
*/
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
- uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
- PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
- }
+#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
+ register uint32_t _wRegBase = (uint32_t)(USBx); \
+ uint16_t *_wRegVal; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+ *_wRegVal = (uint16_t)(wCount); \
+} while(0)
+
+#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
+ register uint32_t _wRegBase = (uint32_t)(USBx); \
+ uint16_t *_wRegVal; \
+ \
+ _wRegBase += (uint32_t)(USBx)->BTABLE; \
+ _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
+ PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
+} while(0)
/**
* @brief gets counter of the tx buffer.
@@ -723,8 +822,8 @@
* @param bEpNum Endpoint Number.
* @retval Counter value
*/
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.
@@ -733,21 +832,25 @@
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
+ PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
+ } while(0) /* PCD_SET_EP_DBUF0_ADDR */
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
+ PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
+ } while(0) /* PCD_SET_EP_DBUF1_ADDR */
/**
* @brief Sets addresses in a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
- * @param wBuf0Addr buffer 0 address.
- * @param wBuf1Addr buffer 1 address.
+ * @param wBuf0Addr: buffer 0 address.
+ * @param wBuf1Addr = buffer 1 address.
* @retval None
*/
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
- PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
- PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
- } /* PCD_SET_EP_DBUF_ADDR */
+#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
+ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
+ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
+ } while(0) /* PCD_SET_EP_DBUF_ADDR */
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
@@ -755,43 +858,59 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
- * @param bDir endpoint dir EP_DBUF_OUT = OUT
- * EP_DBUF_IN = IN
- * @param wCount Counter value
+ * @param bDir endpoint dir EP_DBUF_OUT = OUT
+ * EP_DBUF_IN = IN
+ * @param wCount: Counter value
* @retval None
*/
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
- if((bDir) == PCD_EP_DBUF_OUT)\
+#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
+ if ((bDir) == 0U) \
/* OUT endpoint */ \
- {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
- else if((bDir) == PCD_EP_DBUF_IN)\
- { \
- *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
- } \
- } /* SetEPDblBuf0Count*/
+ { \
+ PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
+ } \
+ else \
+ { \
+ if ((bDir) == 1U) \
+ { \
+ /* IN endpoint */ \
+ PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
+ } \
+ } \
+ } while(0) /* SetEPDblBuf0Count*/
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
- if((bDir) == PCD_EP_DBUF_OUT)\
- {/* OUT endpoint */ \
- PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \
- } \
- else if((bDir) == PCD_EP_DBUF_IN)\
- {/* IN endpoint */ \
- *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
- } \
- } /* SetEPDblBuf1Count */
+#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
+ register uint32_t _wBase = (uint32_t)(USBx); \
+ uint16_t *_wEPRegVal; \
+ \
+ if ((bDir) == 0U) \
+ { \
+ /* OUT endpoint */ \
+ PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
+ } \
+ else \
+ { \
+ if ((bDir) == 1U) \
+ { \
+ /* IN endpoint */ \
+ _wBase += (uint32_t)(USBx)->BTABLE; \
+ _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
+ *_wEPRegVal = (uint16_t)(wCount); \
+ } \
+ } \
+ } while(0) /* SetEPDblBuf1Count */
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
- PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
- PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
- } /* PCD_SET_EP_DBUF_CNT */
+#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
+ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+ } while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
@@ -799,16 +918,10 @@
* @param bEpNum Endpoint Number.
* @retval None
*/
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
+#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-/** @defgroup PCD_Instance_definition PCD Instance definition
- * @{
- */
-#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
-/**
- * @}
- */
+
/**
* @}
@@ -816,20 +929,17 @@
/**
* @}
- */
+ */
/**
* @}
- */
-
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
+ */
+#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif
-
-#endif /* __STM32F0xx_HAL_PCD_H */
+#endif /* STM32F0xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_pcd_ex.h b/Inc/stm32f0xx_hal_pcd_ex.h
index 35a70b6..93c3418 100644
--- a/Inc/stm32f0xx_hal_pcd_ex.h
+++ b/Inc/stm32f0xx_hal_pcd_ex.h
@@ -6,76 +6,65 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_PCD_EX_H
-#define __STM32F0xx_HAL_PCD_EX_H
+#ifndef STM32F0xx_HAL_PCD_EX_H
+#define STM32F0xx_HAL_PCD_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)|| defined(STM32F070xB)|| defined(STM32F070x6)
-
/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_hal_def.h"
-
+#include "stm32f0xx_hal_def.h"
+
+#if defined (USB)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @addtogroup PCDEx
* @{
- */
-
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
-/* Internal macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
- */
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress);
-/**
- * @}
- */
-
-/**
- * @}
- */
+ */
+
+
+
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress);
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+
+
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
@@ -83,16 +72,22 @@
/**
* @}
- */
+ */
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_PCD_EX_H */
+#endif /* STM32F0xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_pwr.h b/Inc/stm32f0xx_hal_pwr.h
index ce9b7dd..bab5997 100644
--- a/Inc/stm32f0xx_hal_pwr.h
+++ b/Inc/stm32f0xx_hal_pwr.h
@@ -6,31 +6,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
diff --git a/Inc/stm32f0xx_hal_pwr_ex.h b/Inc/stm32f0xx_hal_pwr_ex.h
index ef74a81..4fbac5c 100644
--- a/Inc/stm32f0xx_hal_pwr_ex.h
+++ b/Inc/stm32f0xx_hal_pwr_ex.h
@@ -6,31 +6,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
diff --git a/Inc/stm32f0xx_hal_rcc.h b/Inc/stm32f0xx_hal_rcc.h
index c9cf5a6..acd386c 100644
--- a/Inc/stm32f0xx_hal_rcc.h
+++ b/Inc/stm32f0xx_hal_rcc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -1303,7 +1287,7 @@
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
*/
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
/**
* @}
@@ -1650,7 +1634,7 @@
*/
/* Initialization and de-initialization functions ******************************/
-void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
diff --git a/Inc/stm32f0xx_hal_rcc_ex.h b/Inc/stm32f0xx_hal_rcc_ex.h
index e86d950..e1f7633 100644
--- a/Inc/stm32f0xx_hal_rcc_ex.h
+++ b/Inc/stm32f0xx_hal_rcc_ex.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_hal_rtc.h b/Inc/stm32f0xx_hal_rtc.h
index dd1c54f..bbc000e 100644
--- a/Inc/stm32f0xx_hal_rtc.h
+++ b/Inc/stm32f0xx_hal_rtc.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RTC_H
#define __STM32F0xx_HAL_RTC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -50,52 +34,52 @@
/** @defgroup RTC RTC
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
-
-/**
- * @brief HAL State structures definition
- */
+
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
- HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-
-}HAL_RTCStateTypeDef;
+ HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-/**
- * @brief RTC Configuration Structure definition
+} HAL_RTCStateTypeDef;
+
+/**
+ * @brief RTC Configuration Structure definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
+ This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
- uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
- uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
- This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
- uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
- This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-}RTC_InitTypeDef;
+ uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
+ This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-/**
- * @brief RTC Time structure definition
+ uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
+ This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+} RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
*/
typedef struct
{
@@ -105,7 +89,7 @@
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
+
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
@@ -115,79 +99,131 @@
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
-
+
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
-
+
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-
- uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
+
+ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
in CR register to store the operation.
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
+} RTC_TimeTypeDef;
+
+/**
+ * @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
+
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
+
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-}RTC_DateTypeDef;
-/**
- * @brief RTC Alarm structure definition
+} RTC_DateTypeDef;
+
+/**
+ * @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
-
+
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
+
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
- This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+ This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
+
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint32_t Alarm; /*!< Specifies the alarm .
- This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-/**
- * @brief RTC Handle Structure definition
- */
+ uint32_t Alarm; /*!< Specifies the alarm .
+ This parameter can be a value of @ref RTC_Alarms_Definitions */
+} RTC_AlarmTypeDef;
+
+/**
+ * @brief RTC Handle Structure definition
+ */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+typedef struct __RTC_HandleTypeDef
+#else
typedef struct
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
{
RTC_TypeDef *Instance; /*!< Register base address */
-
- RTC_InitTypeDef Init; /*!< RTC required parameters */
-
- HAL_LockTypeDef Lock; /*!< RTC locking object */
-
- __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
-
-}RTC_HandleTypeDef;
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
+
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
+
+ void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
+
+#if defined(RTC_WAKEUP_SUPPORT)
+ void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
+
+#endif /* RTC_WAKEUP_SUPPORT */
+ void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
+
+ void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
+
+#if defined(RTC_TAMPER3_SUPPORT)
+ void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
+
+#endif /* RTC_TAMPER3_SUPPORT */
+ void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
+
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+} RTC_HandleTypeDef;
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL RTC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
+ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
+#if defined(RTC_WAKEUP_SUPPORT)
+ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC WakeUp Timer Event Callback ID */
+#endif /* RTC_WAKEUP_SUPPORT */
+ HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
+ HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
+#if defined(RTC_TAMPER3_SUPPORT)
+ HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06u, /*!< RTC Tamper 3 Callback ID */
+#endif /* RTC_TAMPER3_SUPPORT */
+ HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
+ HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
+} HAL_RTC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL RTC Callback pointer definition
+ */
+typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -199,44 +235,44 @@
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
- */
+ */
#define RTC_HOURFORMAT_24 0x00000000U
#define RTC_HOURFORMAT_12 0x00000040U
/**
* @}
- */
+ */
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
- */
+ */
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
/**
* @}
- */
+ */
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
- */
+ */
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U
/**
* @}
- */
+ */
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
- */
+ */
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
/**
* @}
- */
+ */
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
- */
+ */
#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
@@ -246,7 +282,7 @@
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
- */
+ */
#define RTC_STOREOPERATION_RESET 0x00000000U
#define RTC_STOREOPERATION_SET 0x00040000U
/**
@@ -255,7 +291,7 @@
/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
* @{
- */
+ */
#define RTC_FORMAT_BIN 0x000000000U
#define RTC_FORMAT_BCD 0x000000001U
/**
@@ -264,7 +300,7 @@
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
- */
+ */
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
@@ -280,11 +316,11 @@
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
/**
* @}
- */
+ */
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
- */
+ */
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
@@ -294,20 +330,20 @@
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
/**
* @}
- */
+ */
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
- */
+ */
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
/**
* @}
- */
+ */
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
- */
+ */
#define RTC_ALARMMASK_NONE 0x00000000U
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
@@ -316,20 +352,20 @@
#define RTC_ALARMMASK_ALL 0x80808080U
/**
* @}
- */
+ */
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
- */
+ */
#define RTC_ALARM_A RTC_CR_ALRAE
/**
* @}
- */
+ */
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
- */
+ */
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
@@ -365,7 +401,7 @@
to activate alarm. */
/**
* @}
- */
+ */
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
@@ -404,8 +440,8 @@
/**
* @}
- */
-
+ */
+
/* Exported macros ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
@@ -415,7 +451,15 @@
* @param __HANDLE__ RTC handle.
* @retval None
*/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
+ (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
+ (__HANDLE__)->MspInitCallback = NULL;\
+ (__HANDLE__)->MspDeInitCallback = NULL;\
+ }while(0u)
+#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Disable the write protection for RTC registers.
@@ -436,8 +480,8 @@
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFFU; \
- } while(0)
-
+ } while(0)
+
/**
* @brief Enable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
@@ -538,37 +582,37 @@
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
- * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
- * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
- * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
/**
- * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
@@ -605,12 +649,18 @@
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-
+
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -618,7 +668,7 @@
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @{
*/
-
+
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
@@ -627,7 +677,7 @@
/**
* @}
*/
-
+
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @{
*/
@@ -645,16 +695,16 @@
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @{
- */
+ */
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @{
- */
+ */
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
/**
@@ -663,9 +713,9 @@
/**
* @}
- */
+ */
-/* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_Private_Constants RTC Private Constants
@@ -699,7 +749,7 @@
*/
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
-
+
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
@@ -772,7 +822,7 @@
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
@@ -781,12 +831,12 @@
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32f0xx_hal_rtc_ex.h b/Inc/stm32f0xx_hal_rtc_ex.h
index 999844d..fdbf930 100644
--- a/Inc/stm32f0xx_hal_rtc_ex.h
+++ b/Inc/stm32f0xx_hal_rtc_ex.h
@@ -6,31 +6,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -38,7 +22,7 @@
#define __STM32F0xx_HAL_RTC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -52,7 +36,7 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
* @{
@@ -83,7 +67,7 @@
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-}RTC_TamperTypeDef;
+} RTC_TamperTypeDef;
/**
* @}
*/
@@ -139,7 +123,7 @@
* @}
*/
-
+
/** @defgroup RTCEx_Tamper_Pins_Definitions RTCEx Tamper Pins Definition
* @{
*/
@@ -184,7 +168,7 @@
* @}
*/
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definition
* @{
*/
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
@@ -287,9 +271,9 @@
/**
* @}
*/
- /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
- * @{
- */
+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
+ * @{
+ */
#define RTC_CALIBOUTPUT_512HZ 0x00000000U
#define RTC_CALIBOUTPUT_1HZ 0x00080000U
@@ -306,7 +290,7 @@
/**
* @}
*/
-
+
/**
* @}
*/
@@ -394,7 +378,7 @@
* @arg RTC_FLAG_WUTF
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/* WAKE-UP TIMER EXTI */
/* ------------------ */
@@ -423,7 +407,7 @@
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
- * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
@@ -512,7 +496,7 @@
/**
* @brief Disable the RTC TimeStamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -544,8 +528,8 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
* This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
+ * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSOVF
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
@@ -555,7 +539,7 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_TSF
+ * @arg RTC_FLAG_TSF
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -620,13 +604,13 @@
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: Tamper interrupt
* @retval None
- */
+ */
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
/**
* @brief Disable the RTC Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: Tamper interrupt
* @retval None
@@ -676,7 +660,7 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP1F
* @arg RTC_FLAG_TAMP2F
* @arg RTC_FLAG_TAMP3F
* @retval None
@@ -691,7 +675,7 @@
* This parameter can be:
* @arg RTC_FLAG_TAMP1F
* @arg RTC_FLAG_TAMP2F
- * @arg RTC_FLAG_TAMP3F
+ * @arg RTC_FLAG_TAMP3F
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -703,8 +687,8 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP1F
+ * @arg RTC_FLAG_TAMP2F
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
@@ -716,7 +700,7 @@
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP2F
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -730,7 +714,7 @@
/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
* @{
*/
-
+
/* TAMPER TIMESTAMP EXTI */
/* --------------------- */
/**
@@ -758,7 +742,7 @@
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
/**
- * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
@@ -853,7 +837,7 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
* This parameter can be:
- * @arg RTC_FLAG_SHPF
+ * @arg RTC_FLAG_SHPF
* @retval None
*/
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
@@ -873,15 +857,15 @@
/* RTC TimeStamp and Tamper functions *****************************************/
/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
* @{
- */
+ */
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
@@ -900,13 +884,13 @@
/**
* @}
*/
-
+
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
/* RTC Wake-up functions ******************************************************/
/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
* @{
- */
-
+ */
+
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
@@ -922,7 +906,7 @@
/* Extended Control functions ************************************************/
/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @{
- */
+ */
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F030xC) && !defined(STM32F070x6) && !defined(STM32F070xB)
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
@@ -940,21 +924,21 @@
/**
* @}
*/
-
+
/* Extended RTC features functions *******************************************/
/**
* @}
*/
-/* Private types -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
/**
* @}
*/
@@ -966,7 +950,7 @@
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
* @{
- */
+ */
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F070xB) || defined(STM32F030xC)
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
@@ -974,9 +958,9 @@
#else
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
((OUTPUT) == RTC_OUTPUT_ALARMA))
-#endif
-
-#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+#endif
+
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
@@ -986,15 +970,15 @@
#else
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
-#endif
-
+#endif
+
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
@@ -1027,14 +1011,14 @@
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
- ((SEL) == RTC_SHIFTADD1S_SET))
+ ((SEL) == RTC_SHIFTADD1S_SET))
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
@@ -1048,12 +1032,12 @@
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32f0xx_hal_smartcard.h b/Inc/stm32f0xx_hal_smartcard.h
index f8c229c..2734fb3 100644
--- a/Inc/stm32f0xx_hal_smartcard.h
+++ b/Inc/stm32f0xx_hal_smartcard.h
@@ -6,43 +6,25 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_SMARTCARD_H
-#define __STM32F0xx_HAL_SMARTCARD_H
+#ifndef STM32F0xx_HAL_SMARTCARD_H
+#define STM32F0xx_HAL_SMARTCARD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -66,7 +48,8 @@
{
uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
The baud rate register is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+ Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
+ where usart_ker_ckpres is the USART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
@@ -97,7 +80,9 @@
Selecting the single sample method increases the receiver tolerance to clock
deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
- uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. */
+ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
+ This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
+ by 2 to give the division factor of the source clock frequency */
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
@@ -120,7 +105,7 @@
disabled. Otherwise, its maximum value is 7 (before signalling
an error) */
-}SMARTCARD_InitTypeDef;
+} SMARTCARD_InitTypeDef;
/**
* @brief SMARTCARD advanced features initalization structure definition
@@ -129,7 +114,7 @@
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
advanced features may be initialized at the same time. This parameter
- can be a value of @ref SMARTCARD_Advanced_Features_Initialization_Type */
+ can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref SMARTCARD_Tx_Inv */
@@ -152,27 +137,31 @@
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref SMARTCARD_MSB_First */
-}SMARTCARD_AdvFeatureInitTypeDef;
+
+ uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
+ relevant flag is available) or once guard time period has elapsed.
+ This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+} SMARTCARD_AdvFeatureInitTypeDef;
/**
- * @brief HAL SMARTCARD State structures definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
- * - gState contains SMARTCARD state information related to global Handle management
+ * @brief HAL SMARTCARD State definition
+ * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
+ * - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
- * b7-b6 Error information
+ * b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -182,9 +171,9 @@
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -193,79 +182,107 @@
* b0 (not used)
* x : Should be set to 0.
*/
+typedef uint32_t HAL_SMARTCARD_StateTypeDef;
+
+/**
+ * @brief SMARTCARD handle Structure definition
+ */
+typedef struct __SMARTCARD_HandleTypeDef
+{
+ USART_TypeDef *Instance; /*!< USART registers base address */
+
+ SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
+
+ SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+
+
+ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+ void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code */
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */
+
+ void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */
+
+ void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */
+
+ void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */
+
+ void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
+
+ void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */
+
+ void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */
+
+ void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+} SMARTCARD_HandleTypeDef;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMARTCARD Callback ID enumeration definition
+ */
typedef enum
{
- HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_SMARTCARD_StateTypeDef;
+ HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
+ HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
+ HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
+ HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
+ HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
+ HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
+
+ HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
+ HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
+
+} HAL_SMARTCARD_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMARTCARD Callback pointer definition
+ */
+typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */
+
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @brief SMARTCARD clock sources
*/
typedef enum
{
- SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
- SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
- SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
-}SMARTCARD_ClockSourceTypeDef;
-
-/**
- * @brief SMARTCARD handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
-
- SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< SmartCard Error code
- This parameter can be a value of @ref SMARTCARD_Error */
-
-}SMARTCARD_HandleTypeDef;
+ SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
+ SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
+} SMARTCARD_ClockSourceTypeDef;
/**
* @}
@@ -276,16 +293,43 @@
* @{
*/
-/** @defgroup SMARTCARD_Error SMARTCARD Error
+/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
* @{
*/
-#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
+#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
+ * @{
+ */
+#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
+#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -293,11 +337,11 @@
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
-#if defined (USART_CR1_M0)
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< SMARTCARD frame length */
+#if defined(USART_CR1_M0)
+#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */
#else
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< SMARTCARD frame length */
-#endif
+#define SMARTCARD_WORDLENGTH_9B USART_CR1_M /*!< SMARTCARD frame length */
+#endif /* USART_CR1_M0 */
/**
* @}
*/
@@ -305,8 +349,8 @@
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
-#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< SMARTCARD frame with 0.5 stop bit */
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
+#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */
+#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */
/**
* @}
*/
@@ -314,8 +358,8 @@
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< SMARTCARD frame even parity */
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity */
+#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */
/**
* @}
*/
@@ -323,9 +367,9 @@
/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
* @{
*/
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) /*!< SMARTCARD RX mode */
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE) /*!< SMARTCARD TX mode */
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< SMARTCARD RX and TX mode */
+#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */
+#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */
+#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */
/**
* @}
*/
@@ -333,8 +377,8 @@
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
-#define SMARTCARD_POLARITY_LOW (0x00000000U) /*!< SMARTCARD frame low polarity */
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< SMARTCARD frame high polarity */
+#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */
+#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */
/**
* @}
*/
@@ -342,8 +386,8 @@
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
-#define SMARTCARD_PHASE_1EDGE (0x00000000U) /*!< SMARTCARD frame phase on first clock transition */
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< SMARTCARD frame phase on second clock transition */
+#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */
+#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */
/**
* @}
*/
@@ -351,8 +395,8 @@
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
-#define SMARTCARD_LASTBIT_DISABLE (0x00000000U) /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
+#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
@@ -360,18 +404,17 @@
/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
* @{
*/
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< SMARTCARD frame one-bit sample disabled */
-#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< SMARTCARD frame one-bit sample enabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */
/**
* @}
*/
-
/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
* @{
*/
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) /*!< SMARTCARD NACK transmission disabled */
-#define SMARTCARD_NACK_DISABLE (0x00000000U) /*!< SMARTCARD NACK transmission enabled */
+#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */
/**
* @}
*/
@@ -379,23 +422,8 @@
/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
* @{
*/
-#define SMARTCARD_TIMEOUT_DISABLE (0x00000000U) /*!< SMARTCARD receiver timeout disabled */
-#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< SMARTCARD receiver timeout enabled */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
- * @{
- */
-#define SMARTCARD_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
-#define SMARTCARD_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
+#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */
/**
* @}
*/
@@ -403,8 +431,8 @@
/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
/**
* @}
*/
@@ -412,8 +440,8 @@
/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
/**
* @}
*/
@@ -421,8 +449,8 @@
/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
* @{
*/
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
/**
* @}
*/
@@ -430,8 +458,8 @@
/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
* @{
*/
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
/**
* @}
*/
@@ -439,8 +467,8 @@
/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
* @{
*/
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
/**
* @}
*/
@@ -448,8 +476,8 @@
/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
* @{
*/
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
/**
* @}
*/
@@ -457,105 +485,8 @@
/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
* @{
*/
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Flags SMARTCARD Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
-#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
-#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
-#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
-#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
-#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
-#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
-#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
-#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
-#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
-#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
-#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
-#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
- * @{
- */
-
-#define SMARTCARD_IT_PE ((uint16_t)0x0028U) /*!< SMARTCARD parity error interruption */
-#define SMARTCARD_IT_TXE ((uint16_t)0x0727U) /*!< SMARTCARD transmit data register empty interruption */
-#define SMARTCARD_IT_TC ((uint16_t)0x0626U) /*!< SMARTCARD transmission complete interruption */
-#define SMARTCARD_IT_RXNE ((uint16_t)0x0525U) /*!< SMARTCARD read data register not empty interruption */
-#define SMARTCARD_IT_IDLE ((uint16_t)0x0424U) /*!< SMARTCARD idle line detection interruption */
-
-#define SMARTCARD_IT_ERR ((uint16_t)0x0060U) /*!< SMARTCARD error interruption */
-#define SMARTCARD_IT_ORE ((uint16_t)0x0300U) /*!< SMARTCARD overrun error interruption */
-#define SMARTCARD_IT_NE ((uint16_t)0x0200U) /*!< SMARTCARD noise error interruption */
-#define SMARTCARD_IT_FE ((uint16_t)0x0100U) /*!< SMARTCARD frame error interruption */
-
-#define SMARTCARD_IT_EOB ((uint16_t)0x0C3BU) /*!< SMARTCARD end of block interruption */
-#define SMARTCARD_IT_RTO ((uint16_t)0x0B3AU) /*!< SMARTCARD receiver timeout interruption */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
- * @{
- */
-#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
-#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
-#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
-#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
-#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
-#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
-#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
-#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
- * @{
- */
-#define SMARTCARD_CR3_SCARCNT_LSB_POS ( 17U) /*!< SMARTCARD auto retry counter LSB position in CR3 register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
- * @{
- */
-#define SMARTCARD_GTPR_GT_LSB_POS ( 8U) /*!< SMARTCARD guard time value LSB position in GTPR register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
- * @{
- */
-#define SMARTCARD_RTOR_BLEN_LSB_POS ( 24U) /*!< SMARTCARD block length LSB position in RTOR register */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
- * @{
- */
-#define SMARTCARD_IT_MASK ((uint16_t)0x001FU) /*!< SMARTCARD interruptions flags mask */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
/**
* @}
*/
@@ -563,8 +494,20 @@
/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
* @{
*/
-#define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive data flush request */
-#define SMARTCARD_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush request */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+ * @{
+ */
+#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */
+#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */
+#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */
+#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */
+#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */
/**
* @}
*/
@@ -582,20 +525,29 @@
* @param __HANDLE__ SMARTCARD handle.
* @retval None
*/
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
+#else
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/** @brief Flush the Smartcard Data registers.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
- } while(0U)
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
/** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -607,6 +559,7 @@
* @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
* @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
* @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
* @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @retval None
@@ -619,7 +572,6 @@
*/
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
-
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
@@ -648,6 +600,7 @@
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
+ * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
* @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
* @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref SMARTCARD_FLAG_BUSY Busy flag
@@ -656,7 +609,7 @@
* @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
* @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
* @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
- * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
+ * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
* @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
* @arg @ref SMARTCARD_FLAG_NE Noise error flag
* @arg @ref SMARTCARD_FLAG_FE Framing error flag
@@ -665,80 +618,80 @@
*/
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
/** @brief Enable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
* This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __IT__ specifies the SMARTCARD interrupt to check.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check.
* This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_ORE Overrun error interrupt
- * @arg @ref SMARTCARD_IT_NE Noise error interrupt
- * @arg @ref SMARTCARD_IT_FE Framing error interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
- * @param __IT__ specifies the SMARTCARD interrupt source to check.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
- * @arg @ref SMARTCARD_IT_EOB End of block interrupt
- * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
- * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
- * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
- * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
- * @arg @ref SMARTCARD_IT_ERR Framing, overrun or noise error interrupt
- * @arg @ref SMARTCARD_IT_PE Parity error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @arg @ref SMARTCARD_IT_EOB End of block interrupt
+ * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
+ * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
+ * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
+ * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
+ * @arg @ref SMARTCARD_IT_PE Parity error interrupt
+ * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((__IT__) & 0xFFU) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1 : \
- (((((__IT__) & 0xFFU) >> 5U) == 2U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
-
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -749,13 +702,14 @@
* @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
* @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
* @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
- * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
+ * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
* @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
+ * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
* @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @retval None
*/
-#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific SMARTCARD request flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -763,22 +717,22 @@
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
* @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
- *
* @retval None
*/
#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the SMARTCARD one bit sample method.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
- */
+ */
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the SMARTCARD one bit sample method.
- * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
- */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+ */
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+ &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -801,13 +755,14 @@
* @{
*/
-/** @brief Check the Baud rate range.
+
+/** @brief Check the Baud rate range.
* @note The maximum Baud Rate is derived from the maximum clock on F0 (48 MHz)
* divided by the oversampling used on the SMARTCARD (i.e. 16).
* @param __BAUDRATE__ Baud rate set by the configuration function.
* @retval Test result (TRUE or FALSE)
*/
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 3000001U)
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000000U)
/** @brief Check the block length range.
* @note The maximum SMARTCARD block length is 0xFF.
@@ -816,99 +771,89 @@
*/
#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
-/** @brief Check the receiver timeout value.
+/** @brief Check the receiver timeout value.
* @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
* @param __TIMEOUTVALUE__ receiver timeout value.
* @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
-/** @brief Check the SMARTCARD autoretry counter value.
+/** @brief Check the SMARTCARD autoretry counter value.
* @note The maximum number of retransmissions is 0x7.
* @param __COUNT__ number of retransmissions.
* @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
-/**
- * @brief Ensure that SMARTCARD frame length is valid.
- * @param __LENGTH__ SMARTCARD frame length.
+/** @brief Ensure that SMARTCARD frame length is valid.
+ * @param __LENGTH__ SMARTCARD frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
+ */
#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
-/**
- * @brief Ensure that SMARTCARD frame number of stop bits is valid.
- * @param __STOPBITS__ SMARTCARD frame number of stop bits.
+/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
+ * @param __STOPBITS__ SMARTCARD frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
- */
+ */
#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
-/**
- * @brief Ensure that SMARTCARD frame parity is valid.
- * @param __PARITY__ SMARTCARD frame parity.
+/** @brief Ensure that SMARTCARD frame parity is valid.
+ * @param __PARITY__ SMARTCARD frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
+ */
#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
((__PARITY__) == SMARTCARD_PARITY_ODD))
-/**
- * @brief Ensure that SMARTCARD communication mode is valid.
- * @param __MODE__ SMARTCARD communication mode.
+/** @brief Ensure that SMARTCARD communication mode is valid.
+ * @param __MODE__ SMARTCARD communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
-#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3U) == 0x00U) && ((__MODE__) != (uint16_t)0x00U))
+ */
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
-/**
- * @brief Ensure that SMARTCARD frame polarity is valid.
- * @param __CPOL__ SMARTCARD frame polarity.
+/** @brief Ensure that SMARTCARD frame polarity is valid.
+ * @param __CPOL__ SMARTCARD frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
- */
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+ */
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
+ || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
-/**
- * @brief Ensure that SMARTCARD frame phase is valid.
- * @param __CPHA__ SMARTCARD frame phase.
+/** @brief Ensure that SMARTCARD frame phase is valid.
+ * @param __CPHA__ SMARTCARD frame phase.
* @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
*/
#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
-/**
- * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
- * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
+/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+ * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
* @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
*/
#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
-/**
- * @brief Ensure that SMARTCARD frame sampling is valid.
- * @param __ONEBIT__ SMARTCARD frame sampling.
+/** @brief Ensure that SMARTCARD frame sampling is valid.
+ * @param __ONEBIT__ SMARTCARD frame sampling.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
*/
#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
-/**
- * @brief Ensure that SMARTCARD NACK transmission setting is valid.
- * @param __NACK__ SMARTCARD NACK transmission setting.
+/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
+ * @param __NACK__ SMARTCARD NACK transmission setting.
* @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
*/
#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
((__NACK__) == SMARTCARD_NACK_DISABLE))
-/**
- * @brief Ensure that SMARTCARD receiver timeout setting is valid.
- * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
+/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
+ * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
*/
#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
-/**
- * @brief Ensure that SMARTCARD advanced features initialization is valid.
- * @param __INIT__ SMARTCARD advanced features initialization.
+/** @brief Ensure that SMARTCARD advanced features initialization is valid.
+ * @param __INIT__ SMARTCARD advanced features initialization.
* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
@@ -920,65 +865,57 @@
SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
-/**
- * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
- * @param __TXINV__ SMARTCARD frame TX inversion setting.
+/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+ * @param __TXINV__ SMARTCARD frame TX inversion setting.
* @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
-/**
- * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
- * @param __RXINV__ SMARTCARD frame RX inversion setting.
+/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+ * @param __RXINV__ SMARTCARD frame RX inversion setting.
* @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
-/**
- * @brief Ensure that SMARTCARD frame data inversion setting is valid.
- * @param __DATAINV__ SMARTCARD frame data inversion setting.
+/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
+ * @param __DATAINV__ SMARTCARD frame data inversion setting.
* @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
-/**
- * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
- * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
+/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+ * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
* @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
-/**
- * @brief Ensure that SMARTCARD frame overrun setting is valid.
- * @param __OVERRUN__ SMARTCARD frame overrun setting.
+/** @brief Ensure that SMARTCARD frame overrun setting is valid.
+ * @param __OVERRUN__ SMARTCARD frame overrun setting.
* @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
*/
#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
-/**
- * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
- * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
+/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+ * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
* @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
-/**
- * @brief Ensure that SMARTCARD frame MSB first setting is valid.
- * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
+/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
+ * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
* @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
-/**
- * @brief Ensure that SMARTCARD request parameter is valid.
- * @param __PARAM__ SMARTCARD request parameter.
+/** @brief Ensure that SMARTCARD request parameter is valid.
+ * @param __PARAM__ SMARTCARD request parameter.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
@@ -997,7 +934,6 @@
*/
/* Initialization and de-initialization functions ****************************/
-
/** @addtogroup SMARTCARD_Exported_Functions_Group1
* @{
*/
@@ -1007,6 +943,14 @@
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions ***********************************/
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1016,8 +960,10 @@
* @{
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
@@ -1034,16 +980,16 @@
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group3
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
* @{
*/
@@ -1065,14 +1011,11 @@
/**
* @}
*/
-
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_SMARTCARD_H */
+#endif /* STM32F0xx_HAL_SMARTCARD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_smartcard_ex.h b/Inc/stm32f0xx_hal_smartcard_ex.h
index ce806d4..9879965 100644
--- a/Inc/stm32f0xx_hal_smartcard_ex.h
+++ b/Inc/stm32f0xx_hal_smartcard_ex.h
@@ -6,43 +6,25 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_SMARTCARD_EX_H
-#define __STM32F0xx_HAL_SMARTCARD_EX_H
+#ifndef STM32F0xx_HAL_SMARTCARD_EX_H
+#define STM32F0xx_HAL_SMARTCARD_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
@@ -54,227 +36,477 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
+ * @{
+ */
+
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+ * @{
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+ * @{
+ */
+#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */
+#endif /* USART_TCBGT_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
+#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
+#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
+#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
+#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
+#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
+#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
+#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
+#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
+#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
+#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
+#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5 bits)
+ * - XX : Interrupt source register (2 bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5 bits)
+ * @{
+ */
+#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
+#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
+#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
+
+#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
+#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
+#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
+
+#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
+#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
+#endif /* USART_TCBGT_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+ * @{
+ */
+#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
+#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
+#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise error detected clear flag */
+#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
+#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
+#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#endif /* USART_TCBGT_SUPPORT */
+#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
+#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
* @{
*/
-
+
/** @brief Report the SMARTCARD clock source.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(STM32F031x6) || defined(STM32F038xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } while(0)
-#elif defined (STM32F030x8) || \
- defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F051x8) || defined (STM32F058xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0)
-#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
+ do { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } while(0)
+#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
+ break; \
+ default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART4) \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0)
-#elif defined(STM32F091xC) || defined(STM32F098xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
- do { \
- if((__HANDLE__)->Instance == USART1) \
- { \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
- case RCC_USART1CLKSOURCE_PCLK1: \
+ } \
+ } while(0)
+#elif defined (STM32F070xB)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART1CLKSOURCE_HSI: \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART1CLKSOURCE_SYSCLK: \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART1CLKSOURCE_LSE: \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
+ break; \
+ default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART2) \
- { \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
- case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART3) \
- { \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
- case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- break; \
- case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
- break; \
- case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
- break; \
- case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
- break; \
- default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- break; \
- } \
- } \
- else if((__HANDLE__)->Instance == USART4) \
- { \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART5) \
- { \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART6) \
- { \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART7) \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else if((__HANDLE__)->Instance == USART8) \
- { \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
- } \
- } while(0)
-#endif /* defined(STM32F031x6) || defined(STM32F038xx) */
-
+ } \
+ } while(0)
+#elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F091xC) || defined (STM32F098xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
+ case RCC_USART3CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART3CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART3CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART3CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART7) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART8) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#elif defined(STM32F030xC)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART3) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART4) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART5) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else if((__HANDLE__)->Instance == USART6) \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
+/** @brief Set the Transmission Completion flag
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
+ * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
+ * to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
+ * @retval None
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
+ do { \
+ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
+ { \
+ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+ } \
+ else \
+ { \
+ assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+ } \
+ } while(0U)
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
+ do { \
+ (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
+ } while(0U)
+#endif /* USART_TCBGT_SUPPORT */
+
+/** @brief Return the transmission completion flag.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+ * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
+ * reported.
+ * @retval Transmission completion flag
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+ (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
+#else
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
+#endif /* USART_TCBGT_SUPPORT */
+
+
+/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+ * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
+ * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+ */
+#if defined(USART_TCBGT_SUPPORT)
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
+ ((__TXCOMPLETE__) == SMARTCARD_TC))
+#else
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
+#endif /* USART_TCBGT_SUPPORT */
+
/**
* @}
*/
@@ -301,10 +533,24 @@
* @}
*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+
/**
* @}
*/
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+
/**
* @}
*/
@@ -312,14 +558,11 @@
/**
* @}
*/
-
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F0xx_HAL_SMARTCARD_EX_H */
+#endif /* STM32F0xx_HAL_SMARTCARD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_smbus.h b/Inc/stm32f0xx_hal_smbus.h
index 4a499bc..22a9077 100644
--- a/Inc/stm32f0xx_hal_smbus.h
+++ b/Inc/stm32f0xx_hal_smbus.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_SMBUS_H
-#define __STM32F0xx_HAL_SMBUS_H
+#ifndef STM32F0xx_HAL_SMBUS_H
+#define STM32F0xx_HAL_SMBUS_H
#ifdef __cplusplus
extern "C" {
@@ -136,6 +120,10 @@
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
@@ -144,7 +132,7 @@
* @brief SMBUS handle Structure definition
* @{
*/
-typedef struct
+typedef struct __SMBUS_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
@@ -166,7 +154,47 @@
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */
+ void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */
+ void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */
+ void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */
+ void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */
+ void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */
+
+ void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */
+
+ void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */
+ void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef;
+
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL SMBUS Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
+ HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
+ HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
+ HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
+ HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
+
+ HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
+ HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
+
+} HAL_SMBUS_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SMBUS Callback pointer definition
+ */
+typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
+typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -234,7 +262,7 @@
* @}
*/
-/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
@@ -279,9 +307,9 @@
*/
#define SMBUS_NO_STARTSTOP (0x00000000U)
-#define SMBUS_GENERATE_STOP I2C_CR2_STOP
-#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
+#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
@@ -373,7 +401,15 @@
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
+#endif
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -419,7 +455,7 @@
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
@@ -444,10 +480,10 @@
* @arg @ref SMBUS_FLAG_BUSY Bus busy
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
*
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @retval The new state of __FLAG__ (SET or RESET).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -546,13 +582,13 @@
((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
- IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
@@ -571,8 +607,8 @@
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
@@ -590,7 +626,7 @@
* @{
*/
-/* Initialization and de-initialization functions **********************************/
+/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
@@ -598,6 +634,14 @@
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -694,6 +738,6 @@
#endif
-#endif /* __STM32F0xx_HAL_SMBUS_H */
+#endif /* STM32F0xx_HAL_SMBUS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_spi.h b/Inc/stm32f0xx_hal_spi.h
index 4c62440..e11dd8a 100644
--- a/Inc/stm32f0xx_hal_spi.h
+++ b/Inc/stm32f0xx_hal_spi.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_SPI_H
-#define __STM32F0xx_HAL_SPI_H
+#ifndef STM32F0xx_HAL_SPI_H
+#define STM32F0xx_HAL_SPI_H
#ifdef __cplusplus
extern "C" {
@@ -163,8 +147,46 @@
__IO uint32_t ErrorCode; /*!< SPI Error code */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
+ void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
+ void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
+ void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
+ void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
+ void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
+ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
+ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
+ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
+ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
} SPI_HandleTypeDef;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief HAL SPI Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
+ HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
+ HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
+ HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
+ HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
+ HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
+ HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
+ HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
+ HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
+ HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
+
+} HAL_SPI_CallbackIDTypeDef;
+
+/**
+ * @brief HAL SPI Callback pointer definition
+ */
+typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
+
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -185,6 +207,9 @@
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -326,13 +351,12 @@
* This parameter can be one of the following values:
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
* RXNE event is generated if the FIFO
- * level is greater or equal to 1/2(16-bits).
+ * level is greater or equal to 1/4(8-bits).
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/4(8 bits). */
+ * level is greater or equal to 1/2(16 bits). */
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
-
/**
* @}
*/
@@ -359,6 +383,8 @@
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
+#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
+ | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
/**
* @}
*/
@@ -400,7 +426,15 @@
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
@@ -436,7 +470,8 @@
* @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
+ & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__ specifies the SPI Handle.
@@ -496,9 +531,9 @@
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
- __IO uint32_t tmpreg_fre = 0x00U; \
- tmpreg_fre = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_fre); \
+ __IO uint32_t tmpreg_fre = 0x00U; \
+ tmpreg_fre = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_fre); \
}while(0U)
/** @brief Enable the SPI peripheral.
@@ -546,72 +581,181 @@
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
+/** @brief Check whether the specified SPI flag is set or not.
+ * @param __SR__ copy of SPI SR regsiter.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+ * @arg SPI_FLAG_TXE: Transmit buffer empty flag
+ * @arg SPI_FLAG_CRCERR: CRC error flag
+ * @arg SPI_FLAG_MODF: Mode fault flag
+ * @arg SPI_FLAG_OVR: Overrun flag
+ * @arg SPI_FLAG_BSY: Busy flag
+ * @arg SPI_FLAG_FRE: Frame format error flag
+ * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+ * @arg SPI_FLAG_FRLVL: SPI fifo reception level
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE))
+/** @brief Check whether the specified SPI Interrupt is set or not.
+ * @param __CR2__ copy of SPI CR2 regsiter.
+ * @param __INTERRUPT__ specifies the SPI interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+ * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+ * @arg SPI_IT_ERR: Error interrupt enable
+ * @retval SET or RESET.
+ */
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+/** @brief Checks if SPI Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Mode.
+ * This parameter can be a value of @ref SPI_Mode
+ * @retval None
+ */
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
+ ((__MODE__) == SPI_MODE_MASTER))
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_1LINE))
+/** @brief Checks if SPI Direction Mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * This parameter can be a value of @ref SPI_Direction
+ * @retval None
+ */
+#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_15BIT) || \
- ((DATASIZE) == SPI_DATASIZE_14BIT) || \
- ((DATASIZE) == SPI_DATASIZE_13BIT) || \
- ((DATASIZE) == SPI_DATASIZE_12BIT) || \
- ((DATASIZE) == SPI_DATASIZE_11BIT) || \
- ((DATASIZE) == SPI_DATASIZE_10BIT) || \
- ((DATASIZE) == SPI_DATASIZE_9BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT) || \
- ((DATASIZE) == SPI_DATASIZE_7BIT) || \
- ((DATASIZE) == SPI_DATASIZE_6BIT) || \
- ((DATASIZE) == SPI_DATASIZE_5BIT) || \
- ((DATASIZE) == SPI_DATASIZE_4BIT))
+/** @brief Checks if SPI Direction Mode parameter is 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
+/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
+ * @param __MODE__ specifies the SPI Direction Mode.
+ * @retval None
+ */
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
+ ((__MODE__) == SPI_DIRECTION_1LINE))
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
+/** @brief Checks if SPI Data Size parameter is in allowed range.
+ * @param __DATASIZE__ specifies the SPI Data Size.
+ * This parameter can be a value of @ref SPI_Data_Size
+ * @retval None
+ */
+#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
+ ((__DATASIZE__) == SPI_DATASIZE_4BIT))
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
+/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
+ * @param __CPOL__ specifies the SPI serial clock steady state.
+ * This parameter can be a value of @ref SPI_Clock_Polarity
+ * @retval None
+ */
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
+ ((__CPOL__) == SPI_POLARITY_HIGH))
-#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
- ((NSSP) == SPI_NSS_PULSE_DISABLE))
+/** @brief Checks if SPI Clock Phase parameter is in allowed range.
+ * @param __CPHA__ specifies the SPI Clock Phase.
+ * This parameter can be a value of @ref SPI_Clock_Phase
+ * @retval None
+ */
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
+ ((__CPHA__) == SPI_PHASE_2EDGE))
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+/** @brief Checks if SPI Slave Select parameter is in allowed range.
+ * @param __NSS__ specifies the SPI Slave Select management parameter.
+ * This parameter can be a value of @ref SPI_Slave_Select_management
+ * @retval None
+ */
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
+ ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+ ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
+/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
+ * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
+ * This parameter can be a value of @ref SPI_NSSP_Mode
+ * @retval None
+ */
+#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
+ ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
- ((MODE) == SPI_TIMODE_ENABLE))
+/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
+ * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
+ * This parameter can be a value of @ref SPI_BaudRate_Prescaler
+ * @retval None
+ */
+#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
+ ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
+ * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
+ * This parameter can be a value of @ref SPI_MSB_LSB_transmission
+ * @retval None
+ */
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
+ ((__BIT__) == SPI_FIRSTBIT_LSB))
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
- ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
- ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+/** @brief Checks if SPI TI mode parameter is in allowed range.
+ * @param __MODE__ specifies the SPI TI mode.
+ * This parameter can be a value of @ref SPI_TI_mode
+ * @retval None
+ */
+#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
+ ((__MODE__) == SPI_TIMODE_ENABLE))
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
+/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
+ * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
+ * This parameter can be a value of @ref SPI_CRC_Calculation
+ * @retval None
+ */
+#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
+ ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-#define IS_SPI_DMA_HANDLE(HANDLE) ((HANDLE) != NULL)
+/** @brief Checks if SPI CRC length is in allowed range.
+ * @param __LENGTH__ specifies the SPI CRC length.
+ * This parameter can be a value of @ref SPI_CRC_length
+ * @retval None
+ */
+#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
+ ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
+ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
-#define IS_SPI_16BIT_ALIGNED_ADDRESS(DATA) (((uint32_t)(DATA) % 2U) == 0U)
+/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
+ * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
+ * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
+ * @retval None
+ */
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
+
+/** @brief Checks if DMA handle is valid.
+ * @param __HANDLE__ specifies a DMA Handle.
+ * @retval None
+ */
+#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
+
+/** @brief Checks if a data address is 16bit aligned.
+ * @param __DATA__ specifies a data address.
+ * @retval None
+ */
+#define IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U)
/**
* @}
@@ -633,6 +777,12 @@
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -699,6 +849,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_SPI_H */
+#endif /* STM32F0xx_HAL_SPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_spi_ex.h b/Inc/stm32f0xx_hal_spi_ex.h
index 7764476..b65c152 100644
--- a/Inc/stm32f0xx_hal_spi_ex.h
+++ b/Inc/stm32f0xx_hal_spi_ex.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_SPI_EX_H
-#define __STM32F0xx_HAL_SPI_EX_H
+#ifndef STM32F0xx_HAL_SPI_EX_H
+#define STM32F0xx_HAL_SPI_EX_H
#ifdef __cplusplus
extern "C" {
@@ -86,6 +70,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_SPI_EX_H */
+#endif /* STM32F0xx_HAL_SPI_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_tim.h b/Inc/stm32f0xx_hal_tim.h
index 410138a..18c8515 100644
--- a/Inc/stm32f0xx_hal_tim.h
+++ b/Inc/stm32f0xx_hal_tim.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_TIM_H
-#define __STM32F0xx_HAL_TIM_H
+#ifndef STM32F0xx_HAL_TIM_H
+#define STM32F0xx_HAL_TIM_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -56,8 +40,9 @@
/** @defgroup TIM_Exported_Types TIM Exported Types
* @{
*/
+
/**
- * @brief TIM Time base Configuration Structure definition
+ * @brief TIM Time base Configuration Structure definition
*/
typedef struct
{
@@ -80,15 +65,15 @@
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
+ GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+ Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;
/**
- * @brief TIM Output Compare Configuration Structure definition
+ * @brief TIM Output Compare Configuration Structure definition
*/
typedef struct
{
@@ -103,24 +88,24 @@
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
+ uint32_t OCFastMode; /*!< Specifies the Fast mode state.
This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
} TIM_OC_InitTypeDef;
/**
- * @brief TIM One Pulse Mode Configuration Structure definition
+ * @brief TIM One Pulse Mode Configuration Structure definition
*/
typedef struct
{
@@ -135,15 +120,15 @@
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
+ @note This parameter is valid only for timer instances supporting break feature. */
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
@@ -155,14 +140,13 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef;
-
/**
- * @brief TIM Input Capture Configuration Structure definition
+ * @brief TIM Input Capture Configuration Structure definition
*/
typedef struct
{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t ICSelection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -175,7 +159,7 @@
} TIM_IC_InitTypeDef;
/**
- * @brief TIM Encoder Configuration Structure definition
+ * @brief TIM Encoder Configuration Structure definition
*/
typedef struct
{
@@ -183,7 +167,7 @@
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -195,7 +179,7 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -207,59 +191,100 @@
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef;
-
/**
- * @brief TIM Clock Configuration Handle Structure definition
- */
+ * @brief Clock Configuration Handle Structure definition
+ */
typedef struct
{
- uint32_t ClockSource; /*!< TIM clock sources
+ uint32_t ClockSource; /*!< TIM clock sources
This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
+ uint32_t ClockPolarity; /*!< TIM clock polarity
This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
+ uint32_t ClockPrescaler; /*!< TIM clock prescaler
This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
+ uint32_t ClockFilter; /*!< TIM clock filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClockConfigTypeDef;
/**
* @brief TIM Clear Input Configuration Handle Structure definition
- */
+ */
typedef struct
{
- uint32_t ClearInputState; /*!< TIM clear Input state
+ uint32_t ClearInputState; /*!< TIM clear Input state
This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIMEx_Clock_Clear_Input_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
+ uint32_t ClearInputSource; /*!< TIM clear Input sources
+ This parameter can be a value of @ref TIM_ClearInput_Source */
+ uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
+ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
+ This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ uint32_t ClearInputFilter; /*!< TIM Clear Input filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+} TIM_ClearInputConfigTypeDef;
/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct {
- uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-}TIM_SlaveConfigTypeDef;
+ * @brief TIM Master configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
+ This parameter can be a value of @ref TIM_Master_Mode_Selection */
+ uint32_t MasterSlaveMode; /*!< Master/slave mode selection
+ This parameter can be a value of @ref TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the effect of
+ an event on the trigger input (TRGI) is delayed to allow a
+ perfect synchronization between the current timer and its
+ slaves (through TRGO). It is not mandatory in case of timer
+ synchronization mode. */
+} TIM_MasterConfigTypeDef;
/**
- * @brief HAL State structures definition
- */
+ * @brief TIM Slave configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t SlaveMode; /*!< Slave mode selection
+ This parameter can be a value of @ref TIM_Slave_Mode */
+ uint32_t InputTrigger; /*!< Input Trigger source
+ This parameter can be a value of @ref TIM_Trigger_Selection */
+ uint32_t TriggerPolarity; /*!< Input Trigger polarity
+ This parameter can be a value of @ref TIM_Trigger_Polarity */
+ uint32_t TriggerPrescaler; /*!< Input trigger prescaler
+ This parameter can be a value of @ref TIM_Trigger_Prescaler */
+ uint32_t TriggerFilter; /*!< Input trigger filter
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+} TIM_SlaveConfigTypeDef;
+
+/**
+ * @brief TIM Break input(s) and Dead time configuration Structure definition
+ * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
+ * filter and polarity.
+ */
+typedef struct
+{
+ uint32_t OffStateRunMode; /*!< TIM off state in run mode
+ This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+ uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
+ This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+ uint32_t LockLevel; /*!< TIM Lock level
+ This parameter can be a value of @ref TIM_Lock_level */
+ uint32_t DeadTime; /*!< TIM dead Time
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+ uint32_t BreakState; /*!< TIM Break State
+ This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+ uint32_t BreakPolarity; /*!< TIM Break input polarity
+ This parameter can be a value of @ref TIM_Break_Polarity */
+ uint32_t BreakFilter; /*!< Specifies the break input filter.
+ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+ uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BreakDeadTimeConfigTypeDef;
+
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
@@ -267,48 +292,178 @@
HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_TIM_StateTypeDef;
+} HAL_TIM_StateTypeDef;
/**
- * @brief HAL Active channel structures definition
- */
+ * @brief HAL Active channel structures definition
+ */
typedef enum
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
+} HAL_TIM_ActiveChannel;
/**
- * @brief TIM Time Base Handle Structure definition
- */
+ * @brief TIM Time Base Handle Structure definition
+ */
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+typedef struct __TIM_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref TIM_DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
+ This array is accessed by a @ref DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
-}TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
+ void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
+ void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
+ void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
+ void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
+ void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
+ void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
+ void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
+ void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
+ void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
+ void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
+ void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
+ void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
+ void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
+ void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
+ void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
+ void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
+ void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
+ void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
+ void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
+ void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
+ void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
+ void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
+ void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
+ void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
+ void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
+ void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+} TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+
+ ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+} HAL_TIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
+/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_Exported_Constants TIM Exported Constants
* @{
*/
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
-#define TIM_INPUTCHANNELPOLARITY_RISING (0x00000000U) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
+#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
+ * @{
+ */
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_DCR 0x00000012U
+#define TIM_DMABASE_DMAR 0x00000013U
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Event_Source TIM Event Source
+ * @{
+ */
+#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
+ * @{
+ */
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
* @}
@@ -317,8 +472,8 @@
/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED (0x0000U) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
/**
* @}
*/
@@ -326,10 +481,10 @@
/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
-#define TIM_ETRPRESCALER_DIV1 (0x0000U) /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
+#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
+#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
/**
* @}
*/
@@ -337,11 +492,11 @@
/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-#define TIM_COUNTERMODE_UP (0x0000U)
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
+#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
+#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
+#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
+#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
+#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
/**
* @}
*/
@@ -349,9 +504,18 @@
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
-#define TIM_CLOCKDIVISION_DIV1 (0x0000U)
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
+#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_State TIM Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
+#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
/**
* @}
*/
@@ -359,23 +523,9 @@
/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
* @{
*/
-#define TIM_AUTORELOAD_PRELOAD_DISABLE (0x0000U) /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
-/**
- * @}
- */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
- * @{
- */
-#define TIM_OCMODE_TIMING (0x0000U)
-#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
/**
* @}
*/
@@ -383,8 +533,17 @@
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
-#define TIM_OCFAST_DISABLE (0x0000U)
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
+#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
+#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
+ * @{
+ */
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
+#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
/**
* @}
*/
@@ -392,8 +551,8 @@
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-#define TIM_OCPOLARITY_HIGH (0x0000U)
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
+#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
+#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
/**
* @}
*/
@@ -401,8 +560,8 @@
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
-#define TIM_OCNPOLARITY_HIGH (0x0000U)
-#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
+#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
+#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
/**
* @}
*/
@@ -410,8 +569,8 @@
/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
* @{
*/
-#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET (0x0000U)
+#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
+#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
/**
* @}
*/
@@ -419,20 +578,8 @@
/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
* @{
*/
-#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET (0x0000U)
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel TIM Channel
- * @{
- */
-#define TIM_CHANNEL_1 (0x0000U)
-#define TIM_CHANNEL_2 (0x0004U)
-#define TIM_CHANNEL_3 (0x0008U)
-#define TIM_CHANNEL_4 (0x000CU)
-#define TIM_CHANNEL_ALL (0x0018U)
+#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
+#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
/**
* @}
*/
@@ -440,9 +587,18 @@
/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
+#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
+#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
+#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+ * @{
+ */
+#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
+#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
@@ -450,11 +606,11 @@
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
+#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
+ connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
*/
@@ -462,10 +618,10 @@
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
-#define TIM_ICPSC_DIV1 (0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
+#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
+#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
/**
* @}
*/
@@ -473,8 +629,8 @@
/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
-#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE (0x0000U)
+#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
+#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
@@ -482,24 +638,24 @@
/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
*/
-#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
+#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
+#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
/**
* @}
*/
-/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
* @{
*/
-#define TIM_IT_UPDATE (TIM_DIER_UIE)
-#define TIM_IT_CC1 (TIM_DIER_CC1IE)
-#define TIM_IT_CC2 (TIM_DIER_CC2IE)
-#define TIM_IT_CC3 (TIM_DIER_CC3IE)
-#define TIM_IT_CC4 (TIM_DIER_CC4IE)
-#define TIM_IT_COM (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER (TIM_DIER_TIE)
-#define TIM_IT_BREAK (TIM_DIER_BIE)
+#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
+#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
+#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
+#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
+#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
+#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
+#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
+#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
/**
* @}
*/
@@ -507,9 +663,8 @@
/** @defgroup TIM_Commutation_Source TIM Commutation Source
* @{
*/
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE (0x0000U)
-
+#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
/**
* @}
*/
@@ -517,28 +672,13 @@
/** @defgroup TIM_DMA_sources TIM DMA Sources
* @{
*/
-#define TIM_DMA_UPDATE (TIM_DIER_UDE)
-#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
-#define TIM_DMA_COM (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIM Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
+#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
+#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
+#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
+#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
+#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
+#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
+#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
/**
* @}
*/
@@ -546,18 +686,30 @@
/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
-#define TIM_FLAG_UPDATE (TIM_SR_UIF)
-#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
-#define TIM_FLAG_COM (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
-#define TIM_FLAG_BREAK (TIM_SR_BIF)
-#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
+#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
+#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
+#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
+#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
+#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
+#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
+#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
+#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
+#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
+#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
+#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
+#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Channel TIM Channel
+ * @{
+ */
+#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
+#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
+#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
+#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
+#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
/**
* @}
*/
@@ -565,16 +717,16 @@
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 (0x0000U)
-#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
-#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
+#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
+#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
+#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
/**
* @}
*/
@@ -582,9 +734,9 @@
/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
/**
@@ -594,10 +746,10 @@
/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
*/
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
+#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
+#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
+#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
* @}
*/
@@ -605,8 +757,8 @@
/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
* @}
*/
@@ -614,48 +766,47 @@
/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
*/
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
+#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
/**
* @}
*/
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE (0x0000U)
+#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE (0x0000U)
+#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
+#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
+/**
+ * @}
+ */
+/** @defgroup TIM_Lock_level TIM Lock level
+ * @{
+ */
+#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
+#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
/**
* @}
*/
-/** @defgroup TIM_Lock_level TIM Lock level
+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
* @{
*/
-#define TIM_LOCKLEVEL_OFF (0x0000U)
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
- * @{
- */
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE (0x0000U)
+#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
+#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
/**
* @}
*/
@@ -663,16 +814,18 @@
/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
-#define TIM_BREAKPOLARITY_LOW (0x0000U)
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
+#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
/**
* @}
*/
+
/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
* @{
*/
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE (0x0000U)
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+ (if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/
@@ -680,35 +833,50 @@
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
-#define TIM_TRGO_RESET (0x0000U)
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
+#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
+#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
+#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
+#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
+#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
+#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
/**
* @}
*/
-/** @defgroup TIM_Slave_Mode TIM Slave Mode
+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
* @{
*/
-#define TIM_SLAVEMODE_DISABLE (0x0000U)
-#define TIM_SLAVEMODE_RESET (0x0004U)
-#define TIM_SLAVEMODE_GATED (0x0005U)
-#define TIM_SLAVEMODE_TRIGGER (0x0006U)
-#define TIM_SLAVEMODE_EXTERNAL1 (0x0007U)
+#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
/**
* @}
*/
-/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
+/** @defgroup TIM_Slave_Mode TIM Slave mode
* @{
*/
-#define TIM_MASTERSLAVEMODE_ENABLE (0x0080U)
-#define TIM_MASTERSLAVEMODE_DISABLE (0x0000U)
+#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
+#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
+#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
+#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
+#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
+ * @{
+ */
+#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
+#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
+#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
+#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
+#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
+#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
+#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
+#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
/**
* @}
*/
@@ -716,15 +884,15 @@
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
-#define TIM_TS_ITR0 (0x0000U)
-#define TIM_TS_ITR1 (0x0010U)
-#define TIM_TS_ITR2 (0x0020U)
-#define TIM_TS_ITR3 (0x0030U)
-#define TIM_TS_TI1F_ED (0x0040U)
-#define TIM_TS_TI1FP1 (0x0050U)
-#define TIM_TS_TI2FP2 (0x0060U)
-#define TIM_TS_ETRF (0x0070U)
-#define TIM_TS_NONE (0xFFFFU)
+#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
+#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
+#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
+#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
+#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
+#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
+#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
+#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
+#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
/**
* @}
*/
@@ -732,8 +900,8 @@
/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
+#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
@@ -744,10 +912,10 @@
/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
* @{
*/
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
+#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
+#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
+#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
+#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
/**
* @}
*/
@@ -755,35 +923,8 @@
/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
-#define TIM_TI1SELECTION_CH1 (0x0000U)
-#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 (0x00000000)
-#define TIM_DMABASE_CR2 (0x00000001)
-#define TIM_DMABASE_SMCR (0x00000002)
-#define TIM_DMABASE_DIER (0x00000003)
-#define TIM_DMABASE_SR (0x00000004)
-#define TIM_DMABASE_EGR (0x00000005)
-#define TIM_DMABASE_CCMR1 (0x00000006)
-#define TIM_DMABASE_CCMR2 (0x00000007)
-#define TIM_DMABASE_CCER (0x00000008)
-#define TIM_DMABASE_CNT (0x00000009)
-#define TIM_DMABASE_PSC (0x0000000A)
-#define TIM_DMABASE_ARR (0x0000000B)
-#define TIM_DMABASE_RCR (0x0000000C)
-#define TIM_DMABASE_CCR1 (0x0000000D)
-#define TIM_DMABASE_CCR2 (0x0000000E)
-#define TIM_DMABASE_CCR3 (0x0000000F)
-#define TIM_DMABASE_CCR4 (0x00000010)
-#define TIM_DMABASE_BDTR (0x00000011)
-#define TIM_DMABASE_DCR (0x00000012)
-#define TIM_DMABASE_OR (0x00000013)
+#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
+#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
/**
* @}
*/
@@ -791,49 +932,49 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
-#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
-#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
-#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
-#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
-#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
-#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
-#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
-#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
-#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
-#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
-#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
-#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
-#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
-#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
-#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
-#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
-#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
-/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
+/** @defgroup DMA_Handle_index TIM DMA Handle Index
* @{
*/
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
+#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
-/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
-#define TIM_CCx_ENABLE (0x0001U)
-#define TIM_CCx_DISABLE (0x0000U)
-#define TIM_CCxN_ENABLE (0x0004U)
-#define TIM_CCxN_DISABLE (0x0000U)
+#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
+#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
+#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
+#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
/**
* @}
*/
@@ -841,343 +982,44 @@
/**
* @}
*/
-
-/* Private Constants -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
-/**
- * @}
- */
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
- ((MODE) == TIM_COUNTERMODE_DOWN) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
- ((STATE) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
- ((STATE) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
- ((STATE) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
- ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
- ((MODE) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
- ((MODE) == TIM_ENCODERMODE_TI2) || \
- ((MODE) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_TRIGGER) || \
- ((FLAG) == TIM_FLAG_BREAK) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
- ((BASE) == TIM_DMABASE_CR2) || \
- ((BASE) == TIM_DMABASE_SMCR) || \
- ((BASE) == TIM_DMABASE_DIER) || \
- ((BASE) == TIM_DMABASE_SR) || \
- ((BASE) == TIM_DMABASE_EGR) || \
- ((BASE) == TIM_DMABASE_CCMR1) || \
- ((BASE) == TIM_DMABASE_CCMR2) || \
- ((BASE) == TIM_DMABASE_CCER) || \
- ((BASE) == TIM_DMABASE_CNT) || \
- ((BASE) == TIM_DMABASE_PSC) || \
- ((BASE) == TIM_DMABASE_ARR) || \
- ((BASE) == TIM_DMABASE_RCR) || \
- ((BASE) == TIM_DMABASE_CCR1) || \
- ((BASE) == TIM_DMABASE_CCR2) || \
- ((BASE) == TIM_DMABASE_CCR3) || \
- ((BASE) == TIM_DMABASE_CCR4) || \
- ((BASE) == TIM_DMABASE_BDTR) || \
- ((BASE) == TIM_DMABASE_DCR) || \
- ((BASE) == TIM_DMABASE_OR))
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
-
-/** @brief Set TIM IC prescaler
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @param __ICPSC__ specifies the prescaler value.
- * @retval None
- */
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-/** @brief Reset TIM IC prescaler
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @retval None
- */
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-
-/** @brief Set TIM IC polarity
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @param __POLARITY__ specifies TIM Channel Polarity
- * @retval None
- */
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 12U)))
-
-/** @brief Reset TIM IC polarity
- * @param __HANDLE__ TIM handle
- * @param __CHANNEL__ specifies TIM Channel
- * @retval None
- */
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
-
-/**
- * @}
- */
-
-/* Private Functions --------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-/**
- * @}
- */
+/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM_Exported_Macros TIM Exported Macros
* @{
*/
-/** @brief Reset TIM handle state
+/** @brief Reset TIM handle state.
* @param __HANDLE__ TIM handle.
* @retval None
*/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
+ (__HANDLE__)->Base_MspInitCallback = NULL; \
+ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
+ (__HANDLE__)->IC_MspInitCallback = NULL; \
+ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OC_MspInitCallback = NULL; \
+ (__HANDLE__)->OC_MspDeInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspInitCallback = NULL; \
+ (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
+ (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspInitCallback = NULL; \
+ (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
+ (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
+ } while(0)
+#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @brief Enable the TIM peripheral.
* @param __HANDLE__ TIM handle
* @retval None
- */
+ */
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
/**
@@ -1193,17 +1035,16 @@
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0)
-/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
+ } \
+ } \
+ } while(0)
+
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
@@ -1211,27 +1052,25 @@
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0)
+ do { \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
+ { \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
+ { \
+ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
+ } \
+ } \
+ } while(0)
-/* The Main Output Enable of a timer instance is disabled unconditionally */
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
- * @note The Main Output Enable of a timer instance is disabled uncondiotionally
+ * @note The Main Output Enable of a timer instance is disabled unconditionally
*/
#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
-/**
- * @brief Enables the specified TIM interrupt.
+/** @brief Enable the specified TIM interrupt.
* @param __HANDLE__ specifies the TIM Handle.
* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
* This parameter can be one of the following values:
@@ -1247,8 +1086,7 @@
*/
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-/**
- * @brief Disables the specified TIM interrupt.
+/** @brief Disable the specified TIM interrupt.
* @param __HANDLE__ specifies the TIM Handle.
* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
* This parameter can be one of the following values:
@@ -1264,8 +1102,7 @@
*/
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-/**
- * @brief Enables the specified DMA request.
+/** @brief Enable the specified DMA request.
* @param __HANDLE__ specifies the TIM Handle.
* @param __DMA__ specifies the TIM DMA request to enable.
* This parameter can be one of the following values:
@@ -1280,8 +1117,7 @@
*/
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
-/**
- * @brief Disables the specified DMA request.
+/** @brief Disable the specified DMA request.
* @param __HANDLE__ specifies the TIM Handle.
* @param __DMA__ specifies the TIM DMA request to disable.
* This parameter can be one of the following values:
@@ -1296,8 +1132,7 @@
*/
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-/**
- * @brief Checks whether the specified TIM interrupt flag is set or not.
+/** @brief Check whether the specified TIM interrupt flag is set or not.
* @param __HANDLE__ specifies the TIM Handle.
* @param __FLAG__ specifies the TIM interrupt flag to check.
* This parameter can be one of the following values:
@@ -1308,7 +1143,7 @@
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
@@ -1317,8 +1152,7 @@
*/
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-/**
- * @brief Clears the specified TIM interrupt flag.
+/** @brief Clear the specified TIM interrupt flag.
* @param __HANDLE__ specifies the TIM Handle.
* @param __FLAG__ specifies the TIM interrupt flag to clear.
* This parameter can be one of the following values:
@@ -1329,7 +1163,7 @@
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
@@ -1339,70 +1173,58 @@
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/**
- * @brief Checks whether the specified TIM interrupt has occurred or not.
+ * @brief Check whether the specified TIM interrupt source is enabled or not.
* @param __HANDLE__ TIM handle
* @param __INTERRUPT__ specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
+ == (__INTERRUPT__)) ? SET : RESET)
-/**
- * @brief Clear the TIM interrupt pending bits
+/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
*/
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
/**
- * @brief Sets the TIM active prescaler register value on update event.
+ * @brief Set the TIM Prescaler on runtime.
* @param __HANDLE__ TIM handle.
- * @param __PRESC__ specifies the active prescaler register new value.
+ * @param __PRESC__ specifies the Prescaler new value.
* @retval None
*/
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
/**
- * @brief Sets the TIM Capture Compare Register value on runtime without
- * calling another time ConfigChannel function.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __COMPARE__ specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
-
-/**
- * @brief Gets the TIM Capture Compare Register value on runtime
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
-
-/**
- * @brief Sets the TIM Counter Register value on runtime.
+ * @brief Set the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
@@ -1410,37 +1232,33 @@
#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
- * @brief Gets the TIM Counter Register value on runtime.
+ * @brief Get the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
- ((__HANDLE__)->Instance->CNT)
+#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
- * @brief Sets the TIM Autoreload Register value on runtime without calling
- * another time any Init function.
+ * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __AUTORELOAD__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
+ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
+ } while(0)
/**
- * @brief Gets the TIM Autoreload Register value on runtime
+ * @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
- ((__HANDLE__)->Instance->ARR)
+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
- * @brief Sets the TIM Clock Division value on runtime without calling
- * another time any Init function.
+ * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __CKD__ specifies the clock division value.
* This parameter can be one of the following value:
@@ -1450,61 +1268,24 @@
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
+ } while(0)
/**
- * @brief Gets the TIM Clock Division value on runtime
+ * @brief Get the TIM Clock Division value on runtime.
* @param __HANDLE__ TIM handle.
* @retval The clock division can be one of the following values:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
- * @brief Sets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
-
-/**
- * @brief Resets the TIM Output compare preload.
- * @param __HANDLE__ TIM handle.
- * @param __CHANNEL__ TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
-
-
-/**
- * @brief Sets the TIM Input Capture prescaler on runtime without calling
- * another time HAL_TIM_IC_ConfigChannel() function.
+ * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@@ -1521,13 +1302,13 @@
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ do{ \
+ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
+ } while(0)
/**
- * @brief Gets the TIM Input Capture prescaler on runtime
+ * @brief Get the TIM Input Capture prescaler on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@@ -1548,32 +1329,7 @@
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__ TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
-
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__ TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * (+) Counter overflow/underflow
- * (+) Setting the UG bit
- * (+) Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-/**
- * @brief Sets the TIM Capture x input polarity on runtime.
+ * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
@@ -1581,34 +1337,449 @@
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__ Polarity for TIx source
+ * @param __COMPARE__ specifies the Capture Compare register new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
+ ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
+
+/**
+ * @brief Get the TIM Capture Compare Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: get capture/compare 1 register value
+ * @arg TIM_CHANNEL_2: get capture/compare 2 register value
+ * @arg TIM_CHANNEL_3: get capture/compare 3 register value
+ * @arg TIM_CHANNEL_4: get capture/compare 4 register value
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
+ */
+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
+ ((__HANDLE__)->Instance->CCR4))
+
+/**
+ * @brief Set the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Reset the TIM Output compare preload.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
+
+/**
+ * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is set, only counter
+ * overflow/underflow generates an update interrupt or DMA request (if
+ * enabled)
+ * @retval None
+ */
+#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
+
+/**
+ * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
+ * @param __HANDLE__ TIM handle.
+ * @note When the URS bit of the TIMx_CR1 register is reset, any of the
+ * following events generate an update interrupt or DMA request (if
+ * enabled):
+ * _ Counter overflow underflow
+ * _ Setting the UG bit
+ * _ Update generation through the slave mode controller
+ * @retval None
+ */
+#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
+
+/**
+ * @brief Set the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @param __POLARITY__ Polarity for TIx source
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
+ do{ \
+ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
+ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
+ }while(0)
/**
* @}
*/
+/* End of exported macros ----------------------------------------------------*/
-/* Include TIM HAL Extension module */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
+ ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
+
+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
+ ((__BASE__) == TIM_DMABASE_CR2) || \
+ ((__BASE__) == TIM_DMABASE_SMCR) || \
+ ((__BASE__) == TIM_DMABASE_DIER) || \
+ ((__BASE__) == TIM_DMABASE_SR) || \
+ ((__BASE__) == TIM_DMABASE_EGR) || \
+ ((__BASE__) == TIM_DMABASE_CCMR1) || \
+ ((__BASE__) == TIM_DMABASE_CCMR2) || \
+ ((__BASE__) == TIM_DMABASE_CCER) || \
+ ((__BASE__) == TIM_DMABASE_CNT) || \
+ ((__BASE__) == TIM_DMABASE_PSC) || \
+ ((__BASE__) == TIM_DMABASE_ARR) || \
+ ((__BASE__) == TIM_DMABASE_RCR) || \
+ ((__BASE__) == TIM_DMABASE_CCR1) || \
+ ((__BASE__) == TIM_DMABASE_CCR2) || \
+ ((__BASE__) == TIM_DMABASE_CCR3) || \
+ ((__BASE__) == TIM_DMABASE_CCR4) || \
+ ((__BASE__) == TIM_DMABASE_BDTR))
+
+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
+ ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
+ ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
+
+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
+ ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
+
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
+#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
+ ((__STATE__) == TIM_OCFAST_ENABLE))
+
+#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCPOLARITY_LOW))
+
+#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
+ ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
+
+#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCIDLESTATE_RESET))
+
+#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
+ ((__STATE__) == TIM_OCNIDLESTATE_RESET))
+
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
+#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
+
+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
+ ((__SELECTION__) == TIM_ICSELECTION_TRC))
+
+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
+ ((__PRESCALER__) == TIM_ICPSC_DIV8))
+
+#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
+ ((__MODE__) == TIM_OPMODE_REPETITIVE))
+
+#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI2) || \
+ ((__MODE__) == TIM_ENCODERMODE_TI12))
+
+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
+
+#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \
+ ((__CHANNEL__) == TIM_CHANNEL_ALL))
+
+#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2))
+
+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \
+ ((__CHANNEL__) == TIM_CHANNEL_3))
+
+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+
+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
+ ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
+
+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
+
+#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
+ ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
+
+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
+
+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
+ ((__STATE__) == TIM_OSSR_DISABLE))
+
+#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
+ ((__STATE__) == TIM_OSSI_DISABLE))
+
+#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
+ ((__LEVEL__) == TIM_LOCKLEVEL_3))
+
+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
+
+
+#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
+ ((__STATE__) == TIM_BREAK_DISABLE))
+
+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
+ ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
+
+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
+ ((__SOURCE__) == TIM_TRGO_ENABLE) || \
+ ((__SOURCE__) == TIM_TRGO_UPDATE) || \
+ ((__SOURCE__) == TIM_TRGO_OC1) || \
+ ((__SOURCE__) == TIM_TRGO_OC1REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC2REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC3REF) || \
+ ((__SOURCE__) == TIM_TRGO_OC4REF))
+
+#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
+ ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
+
+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
+ ((__MODE__) == TIM_SLAVEMODE_RESET) || \
+ ((__MODE__) == TIM_SLAVEMODE_GATED) || \
+ ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
+ ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
+
+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_PWM2))
+
+#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
+ ((__MODE__) == TIM_OCMODE_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_INACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_TOGGLE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
+ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
+
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_TI1F_ED) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_ETRF))
+
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
+ ((__SELECTION__) == TIM_TS_NONE))
+
+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
+ ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
+
+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
+ ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
+
+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
+ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
+
+#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
+ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
+#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
+
+#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
+
+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
+
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
+
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
+
+/* Include TIM HAL Extended module */
#include "stm32f0xx_hal_tim_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
+/** @addtogroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @addtogroup TIM_Exported_Functions_Group1
- * @{
- */
+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ * @{
+ */
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
@@ -1627,10 +1798,11 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group2
- * @{
- */
-/* Timer Output Compare functions **********************************************/
+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ * @{
+ */
+/* Timer Output Compare functions *********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
@@ -1644,15 +1816,15 @@
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group3
- * @{
- */
-/* Timer PWM functions *********************************************************/
+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ * @{
+ */
+/* Timer PWM functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
@@ -1670,10 +1842,11 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group4
- * @{
- */
-/* Timer Input Capture functions ***********************************************/
+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ * @{
+ */
+/* Timer Input Capture functions **********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
@@ -1691,10 +1864,11 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group5
- * @{
- */
-/* Timer One Pulse functions ***************************************************/
+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ * @{
+ */
+/* Timer One Pulse functions **************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
@@ -1709,92 +1883,111 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group6
- * @{
- */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ * @{
+ */
+/* Timer Encoder functions ****************************************************/
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group7
- * @{
- */
-/* Interrupt Handler functions **********************************************/
+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief IRQ handler management
+ * @{
+ */
+/* Interrupt Handler functions ***********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group8
- * @{
- */
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel);
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group9
- * @{
- */
+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
+ * @brief TIM Callbacks functions
+ * @{
+ */
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group10
- * @{
- */
-/* Peripheral State functions **************************************************/
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief Peripheral State functions
+ * @{
+ */
+/* Peripheral State functions ************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
/**
* @}
*/
@@ -1802,16 +1995,33 @@
/**
* @}
*/
+/* End of exported functions -------------------------------------------------*/
-/* Private Functions --------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIM_Private_Functions TIM Private Functions
+ * @{
+ */
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+
+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMAError(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
+/* End of private functions --------------------------------------------------*/
/**
* @}
@@ -1825,6 +2035,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_TIM_H */
+#endif /* STM32F0xx_HAL_TIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_tim_ex.h b/Inc/stm32f0xx_hal_tim_ex.h
index a504794..3df9a02 100644
--- a/Inc/stm32f0xx_hal_tim_ex.h
+++ b/Inc/stm32f0xx_hal_tim_ex.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_TIM_EX_H
-#define __STM32F0xx_HAL_TIM_EX_H
+#ifndef STM32F0xx_HAL_TIM_EX_H
+#define STM32F0xx_HAL_TIM_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -53,94 +37,45 @@
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
-
/**
- * @brief TIM Hall sensor Configuration Structure definition
+ * @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+ uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
-
-/**
- * @brief TIM Master configuration Structure definition
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
- * @brief TIM Break and Dead time configuration Structure definition
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
/**
* @}
*/
+/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
-/** @defgroup TIMEx_Remap TIMEx Remap
+/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
-
-#define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */
-#define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */
-#define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */
-#define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Clock_Clear_Input_Source TIMEx Clear Input Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_NONE (0x00000000U)
-#define TIM_CLEARINPUTSOURCE_ETR (0x00000001U)
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined (STM32F098xx)
-#define TIM_CLEARINPUTSOURCE_OCREFCLR (0x00000002U)
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || defined (STM32F098xx) */
+#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
+#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
+#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
+#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
/**
* @}
*/
@@ -148,53 +83,47 @@
/**
* @}
*/
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\
- ((TIM_REMAP) == TIM_TIM14_RTC) ||\
- ((TIM_REMAP) == TIM_TIM14_HSE) ||\
- ((TIM_REMAP) == TIM_TIM14_MCO))
-
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */
-
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined (STM32F098xx)
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR))
-#else
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || defined (STM32F098xx) */
-/**
- * @}
- */
+/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
-/** @addtogroup TIMEx_Exported_Functions_Group1
- * @{
- */
+/**
+ * @}
+ */
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+ * @{
+ */
+#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
+ (((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))
+
+/**
+ * @}
+ */
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+ * @{
+ */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ * @{
+ */
/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
@@ -207,9 +136,10 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group2
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ * @{
+ */
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -226,9 +156,10 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group3
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ * @{
+ */
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -244,9 +175,10 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group4
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ * @{
+ */
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@@ -259,34 +191,43 @@
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group5
- * @{
- */
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
/* Extended Control functions ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
+ TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group6
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
* @{
*/
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
/**
* @}
*/
-/** @addtogroup TIMEx_Exported_Functions_Group7
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
* @{
*/
-/* Extension Peripheral State functions **************************************/
+/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/**
* @}
@@ -298,13 +239,14 @@
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
-* @{
-*/
+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+ * @{
+ */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
-* @}
-*/
+ * @}
+ */
/* End of private functions --------------------------------------------------*/
/**
@@ -320,6 +262,6 @@
#endif
-#endif /* __STM32F0xx_HAL_TIM_EX_H */
+#endif /* STM32F0xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_hal_tsc.h b/Inc/stm32f0xx_hal_tsc.h
index 8972469..974c030 100644
--- a/Inc/stm32f0xx_hal_tsc.h
+++ b/Inc/stm32f0xx_hal_tsc.h
@@ -2,110 +2,102 @@
******************************************************************************
* @file stm32f0xx_hal_tsc.h
* @author MCD Application Team
- * @brief This file contains all the functions prototypes for the TSC firmware
- * library.
+ * @brief Header file of TSC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_TSC_H
-#define __STM32F0xx_TSC_H
+#ifndef STM32F0xx_HAL_TSC_H
+#define STM32F0xx_HAL_TSC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
- defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
- defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal_def.h"
+#if defined(TSC)
+
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @addtogroup TSC
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
-
/** @defgroup TSC_Exported_Types TSC Exported Types
* @{
*/
-/**
- * @brief TSC state structure definition
- */
+
+/**
+ * @brief TSC state structure definition
+ */
typedef enum
{
- HAL_TSC_STATE_RESET = 0x00U, /*!< TSC registers have their reset value */
- HAL_TSC_STATE_READY = 0x01U, /*!< TSC registers are initialized or acquisition is completed with success */
- HAL_TSC_STATE_BUSY = 0x02U, /*!< TSC initialization or acquisition is on-going */
- HAL_TSC_STATE_ERROR = 0x03U /*!< Acquisition is completed with max count error */
+ HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */
+ HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */
+ HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */
+ HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */
} HAL_TSC_StateTypeDef;
-/**
- * @brief TSC group status structure definition
- */
+/**
+ * @brief TSC group status structure definition
+ */
typedef enum
{
- TSC_GROUP_ONGOING = 0x00U, /*!< Acquisition on group is on-going or not started */
- TSC_GROUP_COMPLETED = 0x01U /*!< Acquisition on group is completed with success (no max count error) */
+ TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */
+ TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */
} TSC_GroupStatusTypeDef;
-/**
- * @brief TSC init structure definition
- */
+/**
+ * @brief TSC init structure definition
+ */
typedef struct
{
- uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length */
- uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length */
- uint32_t SpreadSpectrum; /*!< Spread spectrum activation */
- uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation */
- uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler */
- uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler */
- uint32_t MaxCountValue; /*!< Max count value */
- uint32_t IODefaultMode; /*!< IO default mode */
- uint32_t SynchroPinPolarity; /*!< Synchro pin polarity */
- uint32_t AcquisitionMode; /*!< Acquisition mode */
- uint32_t MaxCountInterrupt; /*!< Max count interrupt activation */
+ uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
+ This parameter can be a value of @ref TSC_CTPulseHL_Config */
+ uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
+ This parameter can be a value of @ref TSC_CTPulseLL_Config */
+ FunctionalState SpreadSpectrum; /*!< Spread spectrum activation
+ This parameter can be set to ENABLE or DISABLE. */
+ uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
+ This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
+ uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
+ This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
+ uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
+ This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
+ uint32_t MaxCountValue; /*!< Max count value
+ This parameter can be a value of @ref TSC_MaxCount_Value */
+ uint32_t IODefaultMode; /*!< IO default mode
+ This parameter can be a value of @ref TSC_IO_Default_Mode */
+ uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
+ This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
+ uint32_t AcquisitionMode; /*!< Acquisition mode
+ This parameter can be a value of @ref TSC_Acquisition_Mode */
+ FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation
+ This parameter can be set to ENABLE or DISABLE. */
uint32_t ChannelIOs; /*!< Channel IOs mask */
uint32_t ShieldIOs; /*!< Shield IOs mask */
uint32_t SamplingIOs; /*!< Sampling IOs mask */
} TSC_InitTypeDef;
-/**
- * @brief TSC IOs configuration structure definition
- */
+/**
+ * @brief TSC IOs configuration structure definition
+ */
typedef struct
{
uint32_t ChannelIOs; /*!< Channel IOs mask */
@@ -113,390 +105,349 @@
uint32_t SamplingIOs; /*!< Sampling IOs mask */
} TSC_IOConfigTypeDef;
-/**
- * @brief TSC handle Structure definition
- */
+/**
+ * @brief TSC handle Structure definition
+ */
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+typedef struct __TSC_HandleTypeDef
+#else
typedef struct
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
{
- TSC_TypeDef *Instance; /*!< Register base address */
- TSC_InitTypeDef Init; /*!< Initialization parameters */
- __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
- HAL_LockTypeDef Lock; /*!< Lock feature */
+ TSC_TypeDef *Instance; /*!< Register base address */
+ TSC_InitTypeDef Init; /*!< Initialization parameters */
+ __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
+ HAL_LockTypeDef Lock; /*!< Lock feature */
+ __IO uint32_t ErrorCode; /*!< TSC Error code */
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */
+ void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */
+
+ void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */
+ void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */
+
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
} TSC_HandleTypeDef;
+enum
+{
+ TSC_GROUP1_IDX = 0x00UL,
+ TSC_GROUP2_IDX,
+ TSC_GROUP3_IDX,
+ TSC_GROUP4_IDX,
+ TSC_GROUP5_IDX,
+ TSC_GROUP6_IDX,
+ TSC_GROUP7_IDX,
+ TSC_GROUP8_IDX,
+ TSC_NB_OF_GROUPS
+};
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TSC Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */
+ HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */
+
+ HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */
+ HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */
+
+} HAL_TSC_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TSC Callback pointer definition
+ */
+typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
+
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup TSC_Exported_Constants TSC Exported Constants
* @{
- */
-
-/** @defgroup TSC_CTPH_Cycles TSC Charge Transfer Pulse High
- * @{
- */
-#define TSC_CTPH_1CYCLE ((uint32_t)( 0U << 28))
-#define TSC_CTPH_2CYCLES ((uint32_t)( 1U << 28))
-#define TSC_CTPH_3CYCLES ((uint32_t)( 2U << 28))
-#define TSC_CTPH_4CYCLES ((uint32_t)( 3U << 28))
-#define TSC_CTPH_5CYCLES ((uint32_t)( 4U << 28))
-#define TSC_CTPH_6CYCLES ((uint32_t)( 5U << 28))
-#define TSC_CTPH_7CYCLES ((uint32_t)( 6U << 28))
-#define TSC_CTPH_8CYCLES ((uint32_t)( 7U << 28))
-#define TSC_CTPH_9CYCLES ((uint32_t)( 8U << 28))
-#define TSC_CTPH_10CYCLES ((uint32_t)( 9U << 28))
-#define TSC_CTPH_11CYCLES ((uint32_t)(10U << 28))
-#define TSC_CTPH_12CYCLES ((uint32_t)(11U << 28))
-#define TSC_CTPH_13CYCLES ((uint32_t)(12U << 28))
-#define TSC_CTPH_14CYCLES ((uint32_t)(13U << 28))
-#define TSC_CTPH_15CYCLES ((uint32_t)(14U << 28))
-#define TSC_CTPH_16CYCLES ((uint32_t)(15U << 28))
-#define IS_TSC_CTPH(VAL) (((VAL) == TSC_CTPH_1CYCLE) || \
- ((VAL) == TSC_CTPH_2CYCLES) || \
- ((VAL) == TSC_CTPH_3CYCLES) || \
- ((VAL) == TSC_CTPH_4CYCLES) || \
- ((VAL) == TSC_CTPH_5CYCLES) || \
- ((VAL) == TSC_CTPH_6CYCLES) || \
- ((VAL) == TSC_CTPH_7CYCLES) || \
- ((VAL) == TSC_CTPH_8CYCLES) || \
- ((VAL) == TSC_CTPH_9CYCLES) || \
- ((VAL) == TSC_CTPH_10CYCLES) || \
- ((VAL) == TSC_CTPH_11CYCLES) || \
- ((VAL) == TSC_CTPH_12CYCLES) || \
- ((VAL) == TSC_CTPH_13CYCLES) || \
- ((VAL) == TSC_CTPH_14CYCLES) || \
- ((VAL) == TSC_CTPH_15CYCLES) || \
- ((VAL) == TSC_CTPH_16CYCLES))
-/**
- * @}
*/
-/** @defgroup TSC_CTPL_Cycles TSC Charge Transfer Pulse Low
- * @{
- */
-#define TSC_CTPL_1CYCLE ((uint32_t)( 0U << 24))
-#define TSC_CTPL_2CYCLES ((uint32_t)( 1U << 24))
-#define TSC_CTPL_3CYCLES ((uint32_t)( 2U << 24))
-#define TSC_CTPL_4CYCLES ((uint32_t)( 3U << 24))
-#define TSC_CTPL_5CYCLES ((uint32_t)( 4U << 24))
-#define TSC_CTPL_6CYCLES ((uint32_t)( 5U << 24))
-#define TSC_CTPL_7CYCLES ((uint32_t)( 6U << 24))
-#define TSC_CTPL_8CYCLES ((uint32_t)( 7U << 24))
-#define TSC_CTPL_9CYCLES ((uint32_t)( 8U << 24))
-#define TSC_CTPL_10CYCLES ((uint32_t)( 9U << 24))
-#define TSC_CTPL_11CYCLES ((uint32_t)(10U << 24))
-#define TSC_CTPL_12CYCLES ((uint32_t)(11U << 24))
-#define TSC_CTPL_13CYCLES ((uint32_t)(12U << 24))
-#define TSC_CTPL_14CYCLES ((uint32_t)(13U << 24))
-#define TSC_CTPL_15CYCLES ((uint32_t)(14U << 24))
-#define TSC_CTPL_16CYCLES ((uint32_t)(15U << 24))
-#define IS_TSC_CTPL(VAL) (((VAL) == TSC_CTPL_1CYCLE) || \
- ((VAL) == TSC_CTPL_2CYCLES) || \
- ((VAL) == TSC_CTPL_3CYCLES) || \
- ((VAL) == TSC_CTPL_4CYCLES) || \
- ((VAL) == TSC_CTPL_5CYCLES) || \
- ((VAL) == TSC_CTPL_6CYCLES) || \
- ((VAL) == TSC_CTPL_7CYCLES) || \
- ((VAL) == TSC_CTPL_8CYCLES) || \
- ((VAL) == TSC_CTPL_9CYCLES) || \
- ((VAL) == TSC_CTPL_10CYCLES) || \
- ((VAL) == TSC_CTPL_11CYCLES) || \
- ((VAL) == TSC_CTPL_12CYCLES) || \
- ((VAL) == TSC_CTPL_13CYCLES) || \
- ((VAL) == TSC_CTPL_14CYCLES) || \
- ((VAL) == TSC_CTPL_15CYCLES) || \
- ((VAL) == TSC_CTPL_16CYCLES))
-/**
- * @}
- */
-
-/** @defgroup TSC_SS_Prescaler_definition TSC Spread spectrum prescaler definition
+/** @defgroup TSC_Error_Code_definition TSC Error Code definition
+ * @brief TSC Error Code definition
* @{
*/
-#define TSC_SS_PRESC_DIV1 (0U)
-#define TSC_SS_PRESC_DIV2 (TSC_CR_SSPSC)
-#define IS_TSC_SS_PRESC(VAL) (((VAL) == TSC_SS_PRESC_DIV1) || ((VAL) == TSC_SS_PRESC_DIV2))
-
+#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
-
-/** @defgroup TSC_PG_Prescaler_definition TSC Pulse Generator prescaler definition
+
+/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{
*/
-#define TSC_PG_PRESC_DIV1 ((uint32_t)(0 << 12))
-#define TSC_PG_PRESC_DIV2 ((uint32_t)(1 << 12))
-#define TSC_PG_PRESC_DIV4 ((uint32_t)(2 << 12))
-#define TSC_PG_PRESC_DIV8 ((uint32_t)(3 << 12))
-#define TSC_PG_PRESC_DIV16 ((uint32_t)(4 << 12))
-#define TSC_PG_PRESC_DIV32 ((uint32_t)(5 << 12))
-#define TSC_PG_PRESC_DIV64 ((uint32_t)(6 << 12))
-#define TSC_PG_PRESC_DIV128 ((uint32_t)(7 << 12))
-#define IS_TSC_PG_PRESC(VAL) (((VAL) == TSC_PG_PRESC_DIV1) || \
- ((VAL) == TSC_PG_PRESC_DIV2) || \
- ((VAL) == TSC_PG_PRESC_DIV4) || \
- ((VAL) == TSC_PG_PRESC_DIV8) || \
- ((VAL) == TSC_PG_PRESC_DIV16) || \
- ((VAL) == TSC_PG_PRESC_DIV32) || \
- ((VAL) == TSC_PG_PRESC_DIV64) || \
- ((VAL) == TSC_PG_PRESC_DIV128))
+#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
+#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
+#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
+#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
+#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
+#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
+#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
+#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
+#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
+#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
+#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
+#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
+#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
+#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
+#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
+#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
/**
* @}
*/
-/** @defgroup TSC_MCV_definition TSC Max Count Value definition
- * @{
- */
-#define TSC_MCV_255 ((uint32_t)(0 << 5))
-#define TSC_MCV_511 ((uint32_t)(1 << 5))
-#define TSC_MCV_1023 ((uint32_t)(2 << 5))
-#define TSC_MCV_2047 ((uint32_t)(3 << 5))
-#define TSC_MCV_4095 ((uint32_t)(4 << 5))
-#define TSC_MCV_8191 ((uint32_t)(5 << 5))
-#define TSC_MCV_16383 ((uint32_t)(6 << 5))
-#define IS_TSC_MCV(VAL) (((VAL) == TSC_MCV_255) || \
- ((VAL) == TSC_MCV_511) || \
- ((VAL) == TSC_MCV_1023) || \
- ((VAL) == TSC_MCV_2047) || \
- ((VAL) == TSC_MCV_4095) || \
- ((VAL) == TSC_MCV_8191) || \
- ((VAL) == TSC_MCV_16383))
-/**
- * @}
- */
-
-/** @defgroup TSC_IO_default_mode_definition TSC I/O default mode definition
- * @{
- */
-#define TSC_IODEF_OUT_PP_LOW (0U)
-#define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF)
-#define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT))
-/**
- * @}
- */
-
-/** @defgroup TSC_Synchronization_pin_polarity TSC Synchronization pin polarity
- * @{
- */
-#define TSC_SYNC_POLARITY_FALLING (0U)
-#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL)
-#define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POLARITY_FALLING) || ((VAL) == TSC_SYNC_POLARITY_RISING))
-/**
- * @}
- */
-
-/** @defgroup TSC_Acquisition_mode TSC Acquisition mode
- * @{
- */
-#define TSC_ACQ_MODE_NORMAL (0U)
-#define TSC_ACQ_MODE_SYNCHRO (TSC_CR_AM)
-#define IS_TSC_ACQ_MODE(VAL) (((VAL) == TSC_ACQ_MODE_NORMAL) || ((VAL) == TSC_ACQ_MODE_SYNCHRO))
-/**
- * @}
- */
-
-/** @defgroup TSC_IO_mode_definition TSC I/O mode definition
+/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{
*/
-#define TSC_IOMODE_UNUSED (0U)
-#define TSC_IOMODE_CHANNEL (1U)
-#define TSC_IOMODE_SHIELD (2U)
-#define TSC_IOMODE_SAMPLING (3U)
-#define IS_TSC_IOMODE(VAL) (((VAL) == TSC_IOMODE_UNUSED) || \
- ((VAL) == TSC_IOMODE_CHANNEL) || \
- ((VAL) == TSC_IOMODE_SHIELD) || \
- ((VAL) == TSC_IOMODE_SAMPLING))
+#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
+#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
+#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
+#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
+#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
+#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
+#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
+#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
+#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
+#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
+#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
+#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
+#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
+#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
+#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
+#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
/**
* @}
*/
-/** @defgroup TSC_interrupts_definition TSC interrupts definition
+/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
* @{
*/
-#define TSC_IT_EOA ((uint32_t)TSC_IER_EOAIE)
-#define TSC_IT_MCE ((uint32_t)TSC_IER_MCEIE)
-#define IS_TSC_MCE_IT(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
-/**
- * @}
- */
-
-/** @defgroup TSC_flags_definition TSC Flags Definition
- * @{
- */
-#define TSC_FLAG_EOA ((uint32_t)TSC_ISR_EOAF)
-#define TSC_FLAG_MCE ((uint32_t)TSC_ISR_MCEF)
+#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */
+#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */
/**
* @}
*/
-/** @defgroup TSC_groups_definition TSC groups definition
+/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
* @{
- */
-#define TSC_NB_OF_GROUPS (8)
-
-#define TSC_GROUP1 (0x00000001U)
-#define TSC_GROUP2 (0x00000002U)
-#define TSC_GROUP3 (0x00000004U)
-#define TSC_GROUP4 (0x00000008U)
-#define TSC_GROUP5 (0x00000010U)
-#define TSC_GROUP6 (0x00000020U)
-#define TSC_GROUP7 (0x00000040U)
-#define TSC_GROUP8 (0x00000080U)
-#define TSC_ALL_GROUPS (0x000000FFU)
-
-#define TSC_GROUP1_IDX (0U)
-#define TSC_GROUP2_IDX (1U)
-#define TSC_GROUP3_IDX (2U)
-#define TSC_GROUP4_IDX (3U)
-#define TSC_GROUP5_IDX (4U)
-#define TSC_GROUP6_IDX (5U)
-#define TSC_GROUP7_IDX (6U)
-#define TSC_GROUP8_IDX (7U)
-#define IS_GROUP_INDEX(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < TSC_NB_OF_GROUPS)))
-
-#define TSC_GROUP1_IO1 (0x00000001U)
-#define TSC_GROUP1_IO2 (0x00000002U)
-#define TSC_GROUP1_IO3 (0x00000004U)
-#define TSC_GROUP1_IO4 (0x00000008U)
-#define TSC_GROUP1_ALL_IOS (0x0000000FU)
-
-#define TSC_GROUP2_IO1 (0x00000010U)
-#define TSC_GROUP2_IO2 (0x00000020U)
-#define TSC_GROUP2_IO3 (0x00000040U)
-#define TSC_GROUP2_IO4 (0x00000080U)
-#define TSC_GROUP2_ALL_IOS (0x000000F0U)
-
-#define TSC_GROUP3_IO1 (0x00000100U)
-#define TSC_GROUP3_IO2 (0x00000200U)
-#define TSC_GROUP3_IO3 (0x00000400U)
-#define TSC_GROUP3_IO4 (0x00000800U)
-#define TSC_GROUP3_ALL_IOS (0x00000F00U)
-
-#define TSC_GROUP4_IO1 (0x00001000U)
-#define TSC_GROUP4_IO2 (0x00002000U)
-#define TSC_GROUP4_IO3 (0x00004000U)
-#define TSC_GROUP4_IO4 (0x00008000U)
-#define TSC_GROUP4_ALL_IOS (0x0000F000U)
-
-#define TSC_GROUP5_IO1 (0x00010000U)
-#define TSC_GROUP5_IO2 (0x00020000U)
-#define TSC_GROUP5_IO3 (0x00040000U)
-#define TSC_GROUP5_IO4 (0x00080000U)
-#define TSC_GROUP5_ALL_IOS (0x000F0000U)
-
-#define TSC_GROUP6_IO1 (0x00100000U)
-#define TSC_GROUP6_IO2 (0x00200000U)
-#define TSC_GROUP6_IO3 (0x00400000U)
-#define TSC_GROUP6_IO4 (0x00800000U)
-#define TSC_GROUP6_ALL_IOS (0x00F00000U)
-
-#define TSC_GROUP7_IO1 (0x01000000U)
-#define TSC_GROUP7_IO2 (0x02000000U)
-#define TSC_GROUP7_IO3 (0x04000000U)
-#define TSC_GROUP7_IO4 (0x08000000U)
-#define TSC_GROUP7_ALL_IOS (0x0F000000U)
-
-#define TSC_GROUP8_IO1 (0x10000000U)
-#define TSC_GROUP8_IO2 (0x20000000U)
-#define TSC_GROUP8_IO3 (0x40000000U)
-#define TSC_GROUP8_IO4 (0x80000000U)
-#define TSC_GROUP8_ALL_IOS (0xF0000000U)
-
-#define TSC_ALL_GROUPS_ALL_IOS (0xFFFFFFFFU)
+ */
+#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */
+#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */
+#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */
+#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */
+#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */
+#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */
+#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */
+#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */
/**
* @}
*/
-
+
+/** @defgroup TSC_MaxCount_Value Max Count Value
+ * @{
+ */
+#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */
+#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */
+#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */
+#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */
+#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */
+#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */
+#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */
/**
* @}
- */
+ */
-/* Private macros -----------------------------------------------------------*/
-/** @defgroup TSC_Private_Macros TSC Private Macros
- * @{
- */
-/** @defgroup TSC_Spread_Spectrum TSC Spread Spectrum
+/** @defgroup TSC_IO_Default_Mode IO Default Mode
* @{
- */
-#define IS_TSC_SS(VAL) (((VAL) == DISABLE) || ((VAL) == ENABLE))
+ */
+#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */
+#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */
+/**
+ * @}
+ */
-#define IS_TSC_SSD(VAL) (((VAL) == 0U) || (((VAL) > 0U) && ((VAL) < 128U)))
+/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
+ * @{
+ */
+#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */
+#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Acquisition_Mode Acquisition Mode
+ * @{
+ */
+#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
+#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_interrupts_definition Interrupts definition
+ * @{
+ */
+#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
+#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_flags_definition Flags definition
+ * @{
+ */
+#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */
+#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */
+/**
+ * @}
+ */
+
+/** @defgroup TSC_Group_definition Group definition
+ * @{
+ */
+#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
+#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
+#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
+#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
+#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
+#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
+#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
+#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX)
+
+#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
+#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
+#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
+#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
+
+#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
+#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
+#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
+#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
+
+#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
+#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
+#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
+#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
+
+#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
+#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
+#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
+#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
+
+#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
+#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
+#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
+#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
+
+#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
+#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
+#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
+#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
+
+#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
+#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
+#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
+#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
+
+#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
+#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */
+#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */
+#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */
/**
* @}
*/
/**
* @}
- */
+ */
/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TSC_Exported_Macros TSC Exported Macros
- * @{
- */
-/** @brief Reset TSC handle state
- * @param __HANDLE__ TSC handle.
+/** @defgroup TSC_Exported_Macros TSC Exported Macros
+ * @{
+ */
+
+/** @brief Reset TSC handle state.
+ * @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
+#endif
/**
* @brief Enable the TSC peripheral.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
+#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
/**
* @brief Disable the TSC peripheral.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_TSCE))
+#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
/**
- * @brief Start acquisition
+ * @brief Start acquisition.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
+#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
/**
- * @brief Stop acquisition
+ * @brief Stop acquisition.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_START))
+#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
/**
- * @brief Set IO default mode to output push-pull low
+ * @brief Set IO default mode to output push-pull low.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_IODEF))
+#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
/**
- * @brief Set IO default mode to input floating
+ * @brief Set IO default mode to input floating.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
+#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
/**
- * @brief Set synchronization polarity to falling edge
+ * @brief Set synchronization polarity to falling edge.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (uint32_t)(~TSC_CR_SYNCPOL))
+#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
/**
- * @brief Set synchronization polarity to rising edge and high level
+ * @brief Set synchronization polarity to rising edge and high level.
* @param __HANDLE__ TSC handle
* @retval None
*/
-#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
+#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
/**
* @brief Enable TSC interrupt.
@@ -504,7 +455,7 @@
* @param __INTERRUPT__ TSC interrupt
* @retval None
*/
-#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disable TSC interrupt.
@@ -512,22 +463,22 @@
* @param __INTERRUPT__ TSC interrupt
* @retval None
*/
-#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (uint32_t)(~(__INTERRUPT__)))
+#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
-/** @brief Check if the specified TSC interrupt source is enabled or disabled.
+/** @brief Check whether the specified TSC interrupt source is enabled or not.
* @param __HANDLE__ TSC Handle
* @param __INTERRUPT__ TSC interrupt
* @retval SET or RESET
*/
-#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
- * @brief Get the selected TSC's flag status.
+ * @brief Check whether the specified TSC flag is set or not.
* @param __HANDLE__ TSC handle
* @param __FLAG__ TSC flag
* @retval SET or RESET
*/
-#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/**
* @brief Clear the TSC's pending flag.
@@ -535,34 +486,34 @@
* @param __FLAG__ TSC flag
* @retval None
*/
-#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
- * @brief Enable schmitt trigger hysteresis on a group of IOs
+ * @brief Enable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
+#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
/**
- * @brief Disable schmitt trigger hysteresis on a group of IOs
+ * @brief Disable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR &= (~(__GX_IOY_MASK__)))
/**
- * @brief Open analog switch on a group of IOs
+ * @brief Open analog switch on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR &= (~(__GX_IOY_MASK__)))
/**
- * @brief Close analog switch on a group of IOs
+ * @brief Close analog switch on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
@@ -570,39 +521,39 @@
#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
/**
- * @brief Enable a group of IOs in channel mode
+ * @brief Enable a group of IOs in channel mode.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
+#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
/**
- * @brief Disable a group of channel IOs
+ * @brief Disable a group of channel IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR &= (~(__GX_IOY_MASK__)))
/**
- * @brief Enable a group of IOs in sampling mode
+ * @brief Enable a group of IOs in sampling mode.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
+#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
/**
- * @brief Disable a group of sampling IOs
+ * @brief Disable a group of sampling IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
-#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (uint32_t)(~(__GX_IOY_MASK__)))
+#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
/**
- * @brief Enable acquisition groups
+ * @brief Enable acquisition groups.
* @param __HANDLE__ TSC handle
* @param __GX_MASK__ Groups mask
* @retval None
@@ -610,113 +561,220 @@
#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
/**
- * @brief Disable acquisition groups
+ * @brief Disable acquisition groups.
* @param __HANDLE__ TSC handle
* @param __GX_MASK__ Groups mask
* @retval None
*/
-#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (uint32_t)(~(__GX_MASK__)))
+#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
-/** @brief Gets acquisition group status
+/** @brief Gets acquisition group status.
* @param __HANDLE__ TSC Handle
* @param __GX_INDEX__ Group index
* @retval SET or RESET
*/
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
-((((__HANDLE__)->Instance->IOGCSR & (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) == (uint32_t)((uint32_t)1 << ((__GX_INDEX__) + (uint32_t)16))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
+((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
/**
* @}
*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TSC_Exported_Functions TSC Exported Functions
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup TSC_Private_Macros TSC Private Macros
* @{
*/
-/** @addtogroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
-void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc);
-void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc);
+#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \
+ ((__VALUE__) == TSC_CTPH_2CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_3CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_4CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_5CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_6CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_7CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_8CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_9CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_10CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_11CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_12CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_13CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_14CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_15CYCLES) || \
+ ((__VALUE__) == TSC_CTPH_16CYCLES))
+
+#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \
+ ((__VALUE__) == TSC_CTPL_2CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_3CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_4CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_5CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_6CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_7CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_8CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_9CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_10CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_11CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_12CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_13CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_14CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_15CYCLES) || \
+ ((__VALUE__) == TSC_CTPL_16CYCLES))
+
+#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
+
+#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
+
+#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
+
+#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV2) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV4) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV8) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV16) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV32) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV64) || \
+ ((__VALUE__) == TSC_PG_PRESC_DIV128))
+
+#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
+ ((__VALUE__) == TSC_MCV_511) || \
+ ((__VALUE__) == TSC_MCV_1023) || \
+ ((__VALUE__) == TSC_MCV_2047) || \
+ ((__VALUE__) == TSC_MCV_4095) || \
+ ((__VALUE__) == TSC_MCV_8191) || \
+ ((__VALUE__) == TSC_MCV_16383))
+
+#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
+
+#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING) || ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
+
+#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
+
+#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE) || ((FunctionalState)(__VALUE__) == ENABLE))
+
+#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
+
+#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\
+ (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
+ (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
+ (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
+ (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
+ (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
+ (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
+ (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
+ (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
+ (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
+ (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
+ (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
+ (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
+ (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
+ (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
+ (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
+ (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
+ (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
+ (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
+ (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
+ (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
+ (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
+ (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
+ (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
+ (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
+ (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
+ (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
+ (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
+ (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
+ (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
+ (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
+ (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
+ (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))
/**
* @}
*/
-/** @addtogroup TSC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions * @{
- */
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TSC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
+void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
+
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc);
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index);
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index);
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
/**
* @}
*/
/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
- * @{
- */
+ * @{
+ */
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config);
-HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice);
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
/**
* @}
*/
-/** @addtogroup TSC_Exported_Functions_Group4 State functions
- * @brief State functions
- * @{
- */
+/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @{
+ */
/* Peripheral State and Error functions ***************************************/
-HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc);
-HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc);
-void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc);
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
/**
* @}
*/
-
-/** @addtogroup TSC_Exported_Functions_Group5 Callback functions
- * @brief Callback functions
- * @{
+
+/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
*/
-/* Callback functions *********************************************************/
-void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc);
-void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc);
+/******* TSC IRQHandler and Callbacks used in Interrupt mode */
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
+void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
+void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
/**
* @}
*/
/**
* @}
- */
-
-/**
- * @}
- */
+ */
/**
* @}
*/
-#endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */
- /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || */
- /* defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */
-
+/**
+ * @}
+ */
+#endif /* TSC */
#ifdef __cplusplus
}
#endif
-#endif /*__STM32F0xx_TSC_H */
+#endif /* STM32F0xx_HAL_TSC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_uart.h b/Inc/stm32f0xx_hal_uart.h
index b6ac309..8844f91 100644
--- a/Inc/stm32f0xx_hal_uart.h
+++ b/Inc/stm32f0xx_hal_uart.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_UART_H
-#define __STM32F0xx_HAL_UART_H
+#ifndef STM32F0xx_HAL_UART_H
+#define STM32F0xx_HAL_UART_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -64,12 +48,13 @@
{
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
The baud rate register is computed using the following formula:
- - If oversampling is 16 or in LIN mode (LIN mode not available on F030xx devices),
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
+ - If oversampling is 16 or in LIN mode,
+ Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate)))
- If oversampling is 8,
- Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1U */
+ Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1
+ where uart_ker_ck is the UART input clock */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref UARTEx_Word_Length. */
@@ -97,10 +82,12 @@
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
Selecting the single sample method increases the receiver tolerance to clock
deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
-}UART_InitTypeDef;
+
+
+} UART_InitTypeDef;
/**
- * @brief UART Advanced Features initalization structure definition
+ * @brief UART Advanced Features initialization structure definition
*/
typedef struct
{
@@ -109,10 +96,10 @@
This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
- This parameter can be a value of @ref UART_Tx_Inv. */
+ This parameter can be a value of @ref UART_Tx_Inv. */
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
- This parameter can be a value of @ref UART_Rx_Inv. */
+ This parameter can be a value of @ref UART_Rx_Inv. */
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
vs negative/inverted logic).
@@ -128,37 +115,35 @@
This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
- This parameter can be a value of @ref UART_AutoBaudRate_Enable */
+ This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
detection is carried out.
- This parameter can be a value of @ref UARTEx_AutoBaud_Rate_Mode. */
+ This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref UART_MSB_First. */
} UART_AdvFeatureInitTypeDef;
-
-
/**
- * @brief HAL UART State structures definition
- * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
- * - gState contains UART state information related to global Handle management
+ * @brief HAL UART State definition
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
+ * - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
- * b7-b6 Error information
+ * b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL UART Init function already called)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
+ * 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@@ -168,9 +153,9 @@
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
+ * b5 Peripheral initialization status
+ * 0 : Reset (Peripheral not initialized)
+ * 1 : Init done (Peripheral not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@@ -179,80 +164,108 @@
* b0 (not used)
* x : Should be set to 0.
*/
-typedef enum
-{
- HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
- HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_UART_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
+typedef uint32_t HAL_UART_StateTypeDef;
/**
* @brief UART clock sources definition
*/
typedef enum
{
- UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
- UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
- UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
+ UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
+ UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
+ UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}UART_ClockSourceTypeDef;
+} UART_ClockSourceTypeDef;
/**
* @brief UART handle Structure definition
*/
-typedef struct
+typedef struct __UART_HandleTypeDef
{
- USART_TypeDef *Instance; /*!< UART registers base address */
+ USART_TypeDef *Instance; /*!< UART registers base address */
- UART_InitTypeDef Init; /*!< UART communication parameters */
+ UART_InitTypeDef Init; /*!< UART communication parameters */
- UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
+ UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
- uint16_t TxXferSize; /*!< UART Tx Transfer size */
+ uint16_t TxXferSize; /*!< UART Tx Transfer size */
- __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
- uint16_t RxXferSize; /*!< UART Rx Transfer size */
+ uint16_t RxXferSize; /*!< UART Rx Transfer size */
- __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
- uint16_t Mask; /*!< UART Rx RDR register mask */
+ uint16_t Mask; /*!< UART Rx RDR register mask */
- DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
+ void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
- DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
+ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
- __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
- __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ HAL_LockTypeDef Lock; /*!< Locking object */
- __IO uint32_t ErrorCode; /*!< UART Error code */
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
-}UART_HandleTypeDef;
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< UART Error code */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */
+ void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */
+ void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */
+ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */
+ void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
+
+ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
+ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL UART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */
+ HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */
+ HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */
+ HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */
+ HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */
+ HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */
+ HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */
+ HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */
+ HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */
+
+ HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */
+ HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL UART Callback pointer definition
+ */
+typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@@ -263,32 +276,55 @@
* @{
*/
-/** @defgroup UART_Error UART Error
+/** @defgroup UART_State_Definition UART State Code Definition
* @{
*/
-#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_UART_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
-#define HAL_UART_ERROR_BUSY (0x00000020U) /*!< Busy Error */
+#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
+ Value is allowed for gState only */
+#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
+ Value is allowed for gState only */
/**
* @}
- */
+ */
+
+/** @defgroup UART_Error_Definition UART Error Definition
+ * @{
+ */
+#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
+#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
-#ifdef USART_SMARTCARD_SUPPORT
-#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
-#define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */
-#define UART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< UART frame with 1.5 stop bits */
-#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */
-#else
-#define UART_STOPBITS_1 (0x00000000U) /*!< UART frame with 1 stop bit */
-#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< UART frame with 2 stop bits */
-#endif
+#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */
+#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */
+#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */
/**
* @}
*/
@@ -296,9 +332,9 @@
/** @defgroup UART_Parity UART Parity
* @{
*/
-#define UART_PARITY_NONE (0x00000000U) /*!< No parity */
-#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+#define UART_PARITY_NONE 0x00000000U /*!< No parity */
+#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
@@ -306,10 +342,10 @@
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
*/
-#define UART_HWCONTROL_NONE (0x00000000U) /*!< No hardware control */
-#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /*!< Request To Send */
-#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /*!< Clear To Send */
-#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< Request and Clear To Send */
+#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */
+#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */
+#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */
+#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */
/**
* @}
*/
@@ -317,9 +353,9 @@
/** @defgroup UART_Mode UART Transfer Mode
* @{
*/
-#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+#define UART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define UART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
@@ -327,8 +363,8 @@
/** @defgroup UART_State UART State
* @{
*/
-#define UART_STATE_DISABLE (0x00000000U) /*!< UART disabled */
-#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< UART enabled */
+#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */
+#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */
/**
* @}
*/
@@ -336,8 +372,8 @@
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
-#define UART_OVERSAMPLING_16 (0x00000000U) /*!< Oversampling by 16 */
-#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /*!< Oversampling by 8 */
+#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
@@ -345,17 +381,46 @@
/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
* @{
*/
-#define UART_ONE_BIT_SAMPLE_DISABLE (0x00000000U) /*!< One-bit sampling disable */
-#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enable */
+#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */
/**
* @}
*/
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
* @{
*/
-#define UART_RECEIVER_TIMEOUT_DISABLE (0x00000000U) /*!< UART receiver timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /*!< UART receiver timeout enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+ * @{
+ */
+#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN UART Local Interconnection Network mode
+ * @{
+ */
+#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */
+/**
+ * @}
+ */
+
+/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
+ * @{
+ */
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */
/**
* @}
*/
@@ -363,8 +428,8 @@
/** @defgroup UART_DMA_Tx UART DMA Tx
* @{
*/
-#define UART_DMA_TX_DISABLE (0x00000000U) /*!< UART DMA TX disabled */
-#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< UART DMA TX enabled */
+#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */
/**
* @}
*/
@@ -372,8 +437,8 @@
/** @defgroup UART_DMA_Rx UART DMA Rx
* @{
*/
-#define UART_DMA_RX_DISABLE (0x00000000U) /*!< UART DMA RX disabled */
-#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< UART DMA RX enabled */
+#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */
/**
* @}
*/
@@ -381,17 +446,8 @@
/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
* @{
*/
-#define UART_HALF_DUPLEX_DISABLE (0x00000000U) /*!< UART half-duplex disabled */
-#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /*!< UART half-duplex enabled */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_Address_Length UART WakeUp Address Length
- * @{
- */
-#define UART_ADDRESS_DETECT_4B (0x00000000U) /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
+#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */
/**
* @}
*/
@@ -399,26 +455,20 @@
/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
* @{
*/
-#define UART_WAKEUPMETHOD_IDLELINE (0x00000000U) /*!< UART wake-up on idle line */
-#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /*!< UART wake-up on address mark */
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */
+#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */
/**
* @}
*/
-/** @defgroup UART_IT UART IT
- * Elements values convention: 0000ZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZ : Flag position in the ISR register(4bits)
+/** @defgroup UART_Request_Parameters UART Request Parameters
* @{
*/
-#define UART_IT_ERR (0x0060U) /*!< UART error interruption */
-#define UART_IT_ORE (0x0300U) /*!< UART overrun error interruption */
-#define UART_IT_NE (0x0200U) /*!< UART noise error interruption */
-#define UART_IT_FE (0x0100U) /*!< UART frame error interruption */
+#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
+#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */
+#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */
+#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
@@ -426,15 +476,15 @@
/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
* @{
*/
-#define UART_ADVFEATURE_NO_INIT (0x00000000U) /*!< No advanced feature initialization */
-#define UART_ADVFEATURE_TXINVERT_INIT (0x00000001U) /*!< TX pin active level inversion */
-#define UART_ADVFEATURE_RXINVERT_INIT (0x00000002U) /*!< RX pin active level inversion */
-#define UART_ADVFEATURE_DATAINVERT_INIT (0x00000004U) /*!< Binary data inversion */
-#define UART_ADVFEATURE_SWAP_INIT (0x00000008U) /*!< TX/RX pins swap */
-#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT (0x00000010U) /*!< RX overrun disable */
-#define UART_ADVFEATURE_DMADISABLEONERROR_INIT (0x00000020U) /*!< DMA disable on Reception Error */
-#define UART_ADVFEATURE_AUTOBAUDRATE_INIT (0x00000040U) /*!< Auto Baud rate detection initialization */
-#define UART_ADVFEATURE_MSBFIRST_INIT (0x00000080U) /*!< Most significant bit sent/received first */
+#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
+#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
+#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
+#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
+#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */
+#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
/**
* @}
*/
@@ -442,8 +492,8 @@
/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_TXINV_DISABLE (0x00000000U) /*!< TX pin active level inversion disable */
-#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /*!< TX pin active level inversion enable */
+#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
/**
* @}
*/
@@ -451,8 +501,8 @@
/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
* @{
*/
-#define UART_ADVFEATURE_RXINV_DISABLE (0x00000000U) /*!< RX pin active level inversion disable */
-#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /*!< RX pin active level inversion enable */
+#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
/**
* @}
*/
@@ -460,8 +510,8 @@
/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
* @{
*/
-#define UART_ADVFEATURE_DATAINV_DISABLE (0x00000000U) /*!< Binary data inversion disable */
-#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /*!< Binary data inversion enable */
+#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
/**
* @}
*/
@@ -469,8 +519,8 @@
/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
* @{
*/
-#define UART_ADVFEATURE_SWAP_DISABLE (0x00000000U) /*!< TX/RX pins swap disable */
-#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /*!< TX/RX pins swap enable */
+#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
/**
* @}
*/
@@ -478,8 +528,8 @@
/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
* @{
*/
-#define UART_ADVFEATURE_OVERRUN_ENABLE (0x00000000U) /*!< RX overrun enable */
-#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /*!< RX overrun disable */
+#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
+#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
/**
* @}
*/
@@ -487,8 +537,8 @@
/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
* @{
*/
-#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE (0x00000000U) /*!< RX Auto Baud rate detection enable */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /*!< RX Auto Baud rate detection disable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */
/**
* @}
*/
@@ -496,8 +546,8 @@
/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
* @{
*/
-#define UART_ADVFEATURE_DMA_ENABLEONRXERROR (0x00000000U) /*!< DMA enable on Reception Error */
-#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /*!< DMA disable on Reception Error */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
/**
* @}
*/
@@ -505,17 +555,28 @@
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
-#define UART_ADVFEATURE_MSBFIRST_DISABLE (0x00000000U) /*!< Most significant bit sent/received first disable */
-#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /*!< Most significant bit sent/received first enable */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
/**
* @}
*/
+#if defined(USART_CR1_UESM)
+
+/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
+ * @{
+ */
+#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */
+/**
+ * @}
+ */
+#endif /* USART_CR1_UESM */
/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
* @{
*/
-#define UART_ADVFEATURE_MUTEMODE_DISABLE (0x00000000U) /*!< UART mute mode disable */
-#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /*!< UART mute mode enable */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */
/**
* @}
*/
@@ -523,16 +584,28 @@
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
* @{
*/
-#define UART_CR2_ADDRESS_LSB_POS ( 24U) /*!< UART address-matching LSB position in CR2 register */
+#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
/**
* @}
*/
+#if defined(USART_CR1_UESM)
+
+/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
+ * @{
+ */
+#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
+#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
+/**
+ * @}
+ */
+#endif /* USART_CR1_UESM */
/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
* @{
*/
-#define UART_DE_POLARITY_HIGH (0x00000000U) /*!< Driver enable signal is active high */
-#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /*!< Driver enable signal is active low */
+#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */
/**
* @}
*/
@@ -540,7 +613,7 @@
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEAT_ADDRESS_LSB_POS ( 21U) /*!< UART Driver Enable assertion time LSB position in CR1 register */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */
/**
* @}
*/
@@ -548,7 +621,7 @@
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
-#define UART_CR1_DEDT_ADDRESS_LSB_POS ( 16U) /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
/**
* @}
*/
@@ -556,7 +629,7 @@
/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
* @{
*/
-#define UART_IT_MASK (0x001FU) /*!< UART interruptions flags mask */
+#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */
/**
* @}
*/
@@ -564,7 +637,99 @@
/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
* @{
*/
-#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
+#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Flags UART Status Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */
+#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */
+#if defined(USART_CR1_UESM)
+#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */
+#endif /* USART_CR1_UESM */
+#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */
+#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */
+#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */
+#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */
+#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */
+#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */
+#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */
+#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */
+#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */
+#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */
+#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */
+#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */
+#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */
+#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */
+#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */
+#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */
+#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */
+/**
+ * @}
+ */
+
+/** @defgroup UART_Interrupt_definition UART Interrupts Definition
+ * Elements values convention: 000ZZZZZ0XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * - ZZZZZ : Flag position in the ISR register(5bits)
+ * Elements values convention: 000000000XXYYYYYb
+ * - YYYYY : Interrupt source position in the XX register (5bits)
+ * - XX : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
+ * Elements values convention: 0000ZZZZ00000000b
+ * - ZZZZ : Flag position in the ISR register(4bits)
+ * @{
+ */
+#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
+#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
+#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
+#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
+#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
+#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
+#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
+#define UART_IT_CM 0x112EU /*!< UART character match interruption */
+#if defined(USART_CR1_UESM)
+#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
+#endif /* USART_CR1_UESM */
+#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
+
+#define UART_IT_ERR 0x0060U /*!< UART error interruption */
+
+#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
+#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
+#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
+/**
+ * @}
+ */
+
+/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
+ * @{
+ */
+#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
+#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
+#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */
+#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
+#if defined(USART_CR1_UESM)
+#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
+#endif /* USART_CR1_UESM */
+#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */
/**
* @}
*/
@@ -583,48 +748,47 @@
* @param __HANDLE__ UART handle.
* @retval None
*/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while(0)
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief Flush the UART Data registers.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
+ do{ \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+ SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+ } while(0U)
/** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
- * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
- * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on all devices)
- @endif
- * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
- * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag (not available on all devices)
- @endif
- * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on all devices)
- @endif
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+#endif
* @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
@@ -659,54 +823,28 @@
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
/** @brief Check whether the specified UART flag is set or not.
* @param __HANDLE__ specifies the UART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
* @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
- @endif
* @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_FLAG_WUF Wake up from stop mode flag (not available on F030xx devices)
- @endif
- * @arg @ref UART_FLAG_RWU Receiver wake up flag (not available on F030xx devices)
+ #if defined(USART_CR1_UESM)
+ * @arg @ref UART_FLAG_WUF Wake up from stop mode flag
+ #endif
+ * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
* @arg @ref UART_FLAG_SBKF Send Break flag
* @arg @ref UART_FLAG_CMF Character match flag
* @arg @ref UART_FLAG_BUSY Busy flag
* @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
* @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_FLAG_EOBF End of block flag (not available on F030xx devices)
- @endif
- * @arg @ref UART_FLAG_RTOF Receiver timeout flag
* @arg @ref UART_FLAG_CTS CTS Change flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_FLAG_LBDF LIN Break detection flag (not available on F030xx devices)
- @endif
+ * @arg @ref UART_FLAG_LBDF LIN Break detection flag
* @arg @ref UART_FLAG_TXE Transmit data register empty flag
* @arg @ref UART_FLAG_TC Transmission Complete flag
* @arg @ref UART_FLAG_RXNE Receive data register not empty flag
+ * @arg @ref UART_FLAG_RTOF Receiver Timeout flag
* @arg @ref UART_FLAG_IDLE Idle Line detection flag
* @arg @ref UART_FLAG_ORE Overrun Error flag
* @arg @ref UART_FLAG_NE Noise Error flag
@@ -720,30 +858,19 @@
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
@@ -755,30 +882,19 @@
* @param __HANDLE__ specifies the UART Handle.
* @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
@@ -787,109 +903,67 @@
/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__ specifies the UART Handle.
- * @param __IT__ specifies the UART interrupt to check.
+ * @param __INTERRUPT__ specifies the UART interrupt to check.
* This parameter can be one of the following values:
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_ORE Overrun Error interrupt
- * @arg @ref UART_IT_NE Noise Error interrupt
- * @arg @ref UART_IT_FE Framing Error interrupt
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
- * @param __IT__ specifies the UART interrupt source to check.
+ * @param __INTERRUPT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_CM Character match interrupt
- * @arg @ref UART_IT_CTS CTS change interrupt
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_IT_LBD LIN Break detection interrupt (not available on F030xx devices)
- @endif
- * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref UART_IT_TC Transmission complete interrupt
- * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref UART_IT_IDLE Idle line detection interrupt
- * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
- * @arg @ref UART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+#if defined(USART_CR1_UESM)
+ * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
+#endif
+ * @arg @ref UART_IT_CM Character match interrupt
+ * @arg @ref UART_IT_CTS CTS change interrupt
+ * @arg @ref UART_IT_LBD LIN Break detection interrupt
+ * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref UART_IT_TC Transmission complete interrupt
+ * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref UART_IT_RTO Receive Timeout interrupt
+ * @arg @ref UART_IT_IDLE Idle line detection interrupt
+ * @arg @ref UART_IT_PE Parity Error interrupt
+ * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__IT__)) & UART_IT_MASK)))
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
- * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
- * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag (not available on F030xx devices)
- @endif
- * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
- * @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
- @endif
- * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag (not available on F030xx devices)
- @endif
+ * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag
+ * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
+ * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
+ * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref UART_CLEAR_CMF Character Match Clear Flag
+ #if defined(USART_CR1_UESM)
+ * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
+#endif
* @retval None
*/
#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
@@ -902,51 +976,44 @@
* @arg @ref UART_SENDBREAK_REQUEST Send Break Request
* @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
* @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
- * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request (not available on F030xx devices)
- @endif
+ * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
-#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the UART one bit sample method.
- * @param __HANDLE__ specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
- */
+ */
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the UART one bit sample method.
- * @param __HANDLE__ specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
/** @brief Enable UART.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART.
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
-#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Enable CTS flow control.
- * @note This macro allows to enable CTS hardware flow control for a given UART instance,
+ * @note This macro allows to enable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -954,17 +1021,17 @@
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0)
+ } while(0U)
/** @brief Disable CTS flow control.
- * @note This macro allows to disable CTS hardware flow control for a given UART instance,
+ * @note This macro allows to disable CTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -972,17 +1039,17 @@
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0)
+ } while(0U)
/** @brief Enable RTS flow control.
- * @note This macro allows to enable RTS hardware flow control for a given UART instance,
+ * @note This macro allows to enable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -990,17 +1057,17 @@
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0)
+ } while(0U)
/** @brief Disable RTS flow control.
- * @note This macro allows to disable RTS hardware flow control for a given UART instance,
+ * @note This macro allows to disable RTS hardware flow control for a given UART instance,
* without need to call HAL_UART_Init() function.
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+ * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@@ -1008,8 +1075,7 @@
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0)
-
+ } while(0U)
/**
* @}
*/
@@ -1019,6 +1085,7 @@
* @{
*/
+
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock.
* @param __BAUD__ Baud rate set by the user.
@@ -1033,9 +1100,10 @@
*/
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
+
/** @brief Check UART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
- * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
+ * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
*/
@@ -1045,99 +1113,120 @@
* @param __TIME__ 5-bit value assertion time.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
/** @brief Check UART deassertion time.
* @param __TIME__ 5-bit value deassertion time.
* @retval Test result (TRUE or FALSE).
*/
-#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
/**
* @brief Ensure that UART frame number of stop bits is valid.
- * @param __STOPBITS__ UART frame number of stop bits.
+ * @param __STOPBITS__ UART frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
-#ifdef USART_SMARTCARD_SUPPORT
#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
((__STOPBITS__) == UART_STOPBITS_1) || \
((__STOPBITS__) == UART_STOPBITS_1_5) || \
((__STOPBITS__) == UART_STOPBITS_2))
-#else
-#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
- ((__STOPBITS__) == UART_STOPBITS_2))
-#endif
+
/**
* @brief Ensure that UART frame parity is valid.
- * @param __PARITY__ UART frame parity.
+ * @param __PARITY__ UART frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
+ */
#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
((__PARITY__) == UART_PARITY_EVEN) || \
((__PARITY__) == UART_PARITY_ODD))
/**
* @brief Ensure that UART hardware flow control is valid.
- * @param __CONTROL__ UART hardware flow control.
+ * @param __CONTROL__ UART hardware flow control.
* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
- */
+ */
#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
- (((__CONTROL__) == UART_HWCONTROL_NONE) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS) || \
- ((__CONTROL__) == UART_HWCONTROL_CTS) || \
- ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+ (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_CTS) || \
+ ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
/**
* @brief Ensure that UART communication mode is valid.
- * @param __MODE__ UART communication mode.
+ * @param __MODE__ UART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
+ */
#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that UART state is valid.
- * @param __STATE__ UART state.
+ * @param __STATE__ UART state.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
- */
+ */
#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
((__STATE__) == UART_STATE_ENABLE))
/**
* @brief Ensure that UART oversampling is valid.
- * @param __SAMPLING__ UART oversampling.
+ * @param __SAMPLING__ UART oversampling.
* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
- */
+ */
#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
((__SAMPLING__) == UART_OVERSAMPLING_8))
/**
* @brief Ensure that UART frame sampling is valid.
- * @param __ONEBIT__ UART frame sampling.
+ * @param __ONEBIT__ UART frame sampling.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
*/
#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
/**
- * @brief Ensure that Address Length detection parameter is valid.
- * @param __ADDRESS__ UART Adress length value.
- * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+ * @brief Ensure that UART auto Baud rate detection mode is valid.
+ * @param __MODE__ UART auto Baud rate detection mode.
+ * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
-#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
- ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
+ ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
/**
* @brief Ensure that UART receiver timeout setting is valid.
- * @param __TIMEOUT__ UART receiver timeout setting.
+ * @param __TIMEOUT__ UART receiver timeout setting.
* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
*/
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
- ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+ ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief Check the receiver timeout value.
+ * @note The maximum UART receiver timeout value is 0xFFFFFF.
+ * @param __TIMEOUTVALUE__ receiver timeout value.
+ * @retval Test result (TRUE or FALSE)
+ */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+ * @brief Ensure that UART LIN state is valid.
+ * @param __LIN__ UART LIN state.
+ * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+ */
+#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
+ ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+ * @brief Ensure that UART LIN break detection length is valid.
+ * @param __LENGTH__ UART LIN break detection length.
+ * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+ */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
/**
* @brief Ensure that UART DMA TX state is valid.
- * @param __DMATX__ UART DMA TX state.
+ * @param __DMATX__ UART DMA TX state.
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
*/
#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \
@@ -1145,7 +1234,7 @@
/**
* @brief Ensure that UART DMA RX state is valid.
- * @param __DMARX__ UART DMA RX state.
+ * @param __DMARX__ UART DMA RX state.
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
*/
#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \
@@ -1153,7 +1242,7 @@
/**
* @brief Ensure that UART half-duplex state is valid.
- * @param __HDSEL__ UART half-duplex state.
+ * @param __HDSEL__ UART half-duplex state.
* @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
*/
#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
@@ -1161,15 +1250,26 @@
/**
* @brief Ensure that UART wake-up method is valid.
- * @param __WAKEUP__ UART wake-up method .
+ * @param __WAKEUP__ UART wake-up method .
* @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
*/
#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
/**
+ * @brief Ensure that UART request parameter is valid.
+ * @param __PARAM__ UART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
+ ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
+ ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
+ ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
* @brief Ensure that UART advanced features initialization is valid.
- * @param __INIT__ UART advanced features initialization.
+ * @param __INIT__ UART advanced features initialization.
* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
*/
#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \
@@ -1184,7 +1284,7 @@
/**
* @brief Ensure that UART frame TX inversion setting is valid.
- * @param __TXINV__ UART frame TX inversion setting.
+ * @param __TXINV__ UART frame TX inversion setting.
* @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
*/
#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
@@ -1192,7 +1292,7 @@
/**
* @brief Ensure that UART frame RX inversion setting is valid.
- * @param __RXINV__ UART frame RX inversion setting.
+ * @param __RXINV__ UART frame RX inversion setting.
* @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
*/
#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
@@ -1200,7 +1300,7 @@
/**
* @brief Ensure that UART frame data inversion setting is valid.
- * @param __DATAINV__ UART frame data inversion setting.
+ * @param __DATAINV__ UART frame data inversion setting.
* @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
*/
#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
@@ -1208,7 +1308,7 @@
/**
* @brief Ensure that UART frame RX/TX pins swap setting is valid.
- * @param __SWAP__ UART frame RX/TX pins swap setting.
+ * @param __SWAP__ UART frame RX/TX pins swap setting.
* @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
*/
#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
@@ -1216,7 +1316,7 @@
/**
* @brief Ensure that UART frame overrun setting is valid.
- * @param __OVERRUN__ UART frame overrun setting.
+ * @param __OVERRUN__ UART frame overrun setting.
* @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
*/
#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
@@ -1224,7 +1324,7 @@
/**
* @brief Ensure that UART auto Baud rate state is valid.
- * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+ * @param __AUTOBAUDRATE__ UART auto Baud rate state.
* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
*/
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
@@ -1232,7 +1332,7 @@
/**
* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
- * @param __DMA__ UART DMA enabling or disabling on error setting.
+ * @param __DMA__ UART DMA enabling or disabling on error setting.
* @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
*/
#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
@@ -1240,28 +1340,50 @@
/**
* @brief Ensure that UART frame MSB first setting is valid.
- * @param __MSBFIRST__ UART frame MSB first setting.
+ * @param __MSBFIRST__ UART frame MSB first setting.
* @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
*/
#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+#if defined(USART_CR1_UESM)
+/**
+ * @brief Ensure that UART stop mode state is valid.
+ * @param __STOPMODE__ UART stop mode state.
+ * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+ */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+ ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+#endif /* USART_CR1_UESM */
/**
* @brief Ensure that UART mute mode state is valid.
- * @param __MUTE__ UART mute mode state.
+ * @param __MUTE__ UART mute mode state.
* @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
*/
#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+#if defined(USART_CR1_UESM)
+
+/**
+ * @brief Ensure that UART wake-up selection is valid.
+ * @param __WAKE__ UART wake-up selection.
+ * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+ */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
+ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
+ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+#endif /* USART_CR1_UESM */
/**
* @brief Ensure that UART driver enable polarity is valid.
- * @param __POLARITY__ UART driver enable polarity.
+ * @param __POLARITY__ UART driver enable polarity.
* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
*/
#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
((__POLARITY__) == UART_DE_POLARITY_LOW))
+
/**
* @}
*/
@@ -1269,6 +1391,7 @@
/* Include UART HAL Extended module */
#include "stm32f0xx_hal_uart_ex.h"
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
@@ -1281,11 +1404,21 @@
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+#if defined(USART_CR2_LINEN)
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+#endif /* USART_CR2_LINEN */
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1313,14 +1446,14 @@
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
/**
* @}
@@ -1331,6 +1464,13 @@
*/
/* Peripheral Control functions ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+#if defined(USART_CR2_LINEN)
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+#endif /* USART_CR2_LINEN */
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
@@ -1361,13 +1501,14 @@
/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
/**
* @}
@@ -1385,7 +1526,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_UART_H */
+#endif /* STM32F0xx_HAL_UART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_uart_ex.h b/Inc/stm32f0xx_hal_uart_ex.h
index 916a98e..4a5ed23 100644
--- a/Inc/stm32f0xx_hal_uart_ex.h
+++ b/Inc/stm32f0xx_hal_uart_ex.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_UART_EX_H
-#define __STM32F0xx_HAL_UART_EX_H
+#ifndef STM32F0xx_HAL_UART_EX_H
+#define STM32F0xx_HAL_UART_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -53,31 +37,31 @@
*/
/* Exported types ------------------------------------------------------------*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
+#if defined(USART_CR1_UESM)
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
- uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
+ uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
- This parameter can be a value of @ref UART_WakeUp_Address_Length. */
+ This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
+#endif /* USART_CR1_UESM */
/**
* @}
*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
@@ -87,215 +71,80 @@
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */
+#if defined(USART_CR1_M1)
+#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
+#endif /* USART_CR1_M1 */
+#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
+#if defined (USART_CR1_M0)
+#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
#else
-#define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long UART frame */
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+#define UART_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long UART frame */
+#endif /* USART_CR1_M0 */
/**
* @}
*/
-/** @defgroup UARTEx_AutoBaud_Rate_Mode UARTEx Advanced Feature AutoBaud Rate Mode
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
-#else
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */
-#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-/** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode
- * @{
- */
-#define UART_LIN_DISABLE (0x00000000U) /*!< Local Interconnect Network disable */
-#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
-/**
- * @}
- */
-
-/** @defgroup UARTEx_LIN_Break_Detection UARTEx LIN Break Detection
- * @{
- */
-#define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /*!< LIN 10-bit break detection length */
-#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
-/**
- * @}
- */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
-/** @defgroup UART_Flags UARTEx Status Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_FLAG_REACK (0x00400000U) /*!< UART receive enable acknowledge flag */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define UART_FLAG_TEACK (0x00200000U) /*!< UART transmit enable acknowledge flag */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_FLAG_WUF (0x00100000U) /*!< UART wake-up from stop mode flag */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define UART_FLAG_RWU (0x00080000U) /*!< UART receiver wake-up from mute mode flag */
-#define UART_FLAG_SBKF (0x00040000U) /*!< UART send break flag */
-#define UART_FLAG_CMF (0x00020000U) /*!< UART character match flag */
-#define UART_FLAG_BUSY (0x00010000U) /*!< UART busy flag */
-#define UART_FLAG_ABRF (0x00008000U) /*!< UART auto Baud rate flag */
-#define UART_FLAG_ABRE (0x00004000U) /*!< UART auto Baud rate error */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_FLAG_EOBF (0x00001000U) /*!< UART end of block flag */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define UART_FLAG_RTOF (0x00000800U) /*!< UART receiver timeout flag */
-#define UART_FLAG_CTS (0x00000400U) /*!< UART clear to send flag */
-#define UART_FLAG_CTSIF (0x00000200U) /*!< UART clear to send interrupt flag */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_FLAG_LBDF (0x00000100U) /*!< UART LIN break detection flag (not available on F030xx devices)*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define UART_FLAG_TXE (0x00000080U) /*!< UART transmit data register empty */
-#define UART_FLAG_TC (0x00000040U) /*!< UART transmission complete */
-#define UART_FLAG_RXNE (0x00000020U) /*!< UART read data register not empty */
-#define UART_FLAG_IDLE (0x00000010U) /*!< UART idle flag */
-#define UART_FLAG_ORE (0x00000008U) /*!< UART overrun error */
-#define UART_FLAG_NE (0x00000004U) /*!< UART noise error */
-#define UART_FLAG_FE (0x00000002U) /*!< UART frame error */
-#define UART_FLAG_PE (0x00000001U) /*!< UART parity error */
-/**
- * @}
- */
-
-/** @defgroup UART_Interrupt_definition UARTEx Interrupts Definition
- * Elements values convention: 000ZZZZZ0XXYYYYYb
- * - YYYYY : Interrupt source position in the XX register (5bits)
- * - XX : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * - ZZZZZ : Flag position in the ISR register(5bits)
- * @{
- */
-#define UART_IT_PE (0x0028U) /*!< UART parity error interruption */
-#define UART_IT_TXE (0x0727U) /*!< UART transmit data register empty interruption */
-#define UART_IT_TC (0x0626U) /*!< UART transmission complete interruption */
-#define UART_IT_RXNE (0x0525U) /*!< UART read data register not empty interruption */
-#define UART_IT_IDLE (0x0424U) /*!< UART idle interruption */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_IT_LBD (0x0846U) /*!< UART LIN break detection interruption */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define UART_IT_CTS (0x096AU) /*!< UART CTS interruption */
-#define UART_IT_CM (0x112EU) /*!< UART character match interruption */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_IT_WUF (0x1476U) /*!< UART wake-up from stop mode interruption */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-/**
- * @}
- */
-
-
-/** @defgroup UART_IT_CLEAR_Flags UARTEx Interruption Clear Flags
- * @{
- */
-#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
-#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag (not available on F030xx devices)*/
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
-#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-/**
- * @}
- */
-
-/** @defgroup UART_Request_Parameters UARTEx Request Parameters
- * @{
- */
-#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
-#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
-#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
-#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-#else
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-/**
- * @}
- */
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-/** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable
- * @{
- */
-#define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /*!< UART stop mode disable */
-#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
-/**
- * @}
- */
-
-/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
- * @{
- */
-#define UART_WAKEUP_ON_ADDRESS (0x00000000U) /*!< UART wake-up on address */
-#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */
-#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */
-/**
- * @}
- */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
/**
* @}
*/
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
* @{
*/
-/** @brief Flush the UART Data registers.
- * @param __HANDLE__ specifies the UART Handle.
- * @retval None
+/** @addtogroup UARTEx_Exported_Functions_Group1
+ * @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
- } while(0)
-#else
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
- } while(0)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
+
+/* Initialization and de-initialization functions ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime);
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+#if defined(USART_CR1_UESM)
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+#endif /* USART_CR1_UESM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+ * @{
+ */
+
+/* Peripheral Control functions **********************************************/
+#if defined(USART_CR1_UESM)
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+#endif/* USART_CR1_UESM */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+
+/**
+ * @}
+ */
/**
* @}
@@ -311,6 +160,7 @@
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
+
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -333,9 +183,7 @@
break; \
} \
} while(0)
-#elif defined (STM32F030x8) || defined (STM32F070x6) || \
- defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F051x8) || defined (STM32F058xx)
+#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -609,9 +457,8 @@
} while(0)
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
-
-/** @brief Compute the UART mask to apply to retrieve the received data
+/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
@@ -620,220 +467,102 @@
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#if defined (USART_CR1_M1)
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x007FU; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x003FU; \
- } \
- } \
-} while(0)
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x003FU ; \
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+
#else
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x01FFU; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x00FFU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
- { \
- (__HANDLE__)->Mask = 0x00FFU; \
- } \
- else \
- { \
- (__HANDLE__)->Mask = 0x007FU; \
- } \
- } \
-} while(0)
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x01FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
+ { \
+ (__HANDLE__)->Mask = 0x00FFU ; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x007FU ; \
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+
+#endif /* USART_CR1_M1 */
/**
* @brief Ensure that UART frame length is valid.
- * @param __LENGTH__ UART frame length.
+ * @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#if defined (USART_CR1_M1)
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
#else
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+#endif /* USART_CR1_M1 */
/**
- * @brief Ensure that UART auto Baud rate detection mode is valid.
- * @param __MODE__ UART auto Baud rate detection mode.
- * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+ * @brief Ensure that UART wake-up address length is valid.
+ * @param __ADDRESS__ UART wake-up address length.
+ * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
-#else
-#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
- ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
-
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-/**
- * @brief Ensure that UART LIN state is valid.
- * @param __LIN__ UART LIN state.
- * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
- */
-#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
- ((__LIN__) == UART_LIN_ENABLE))
-
-/**
- * @brief Ensure that UART LIN break detection length is valid.
- * @param __LENGTH__ UART LIN break detection length.
- * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
- */
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
-/**
- * @brief Ensure that UART request parameter is valid.
- * @param __PARAM__ UART request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
- ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
- ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
- ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
-#else
-#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
- ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
- ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
- ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST))
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-/**
- * @brief Ensure that UART stop mode state is valid.
- * @param __STOPMODE__ UART stop mode state.
- * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
- */
-#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
- ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
-
-/**
- * @brief Ensure that UART wake-up selection is valid.
- * @param __WAKE__ UART wake-up selection.
- * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
- */
-#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
- ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
- ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UARTEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group1
- * @brief Extended Initialization and Configuration Functions
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-/**
- * @}
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group2
- * @brief Extended UART Interrupt handling function
- * @{
- */
-
-/* IO operation functions ***************************************************/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
-void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-/**
- * @}
- */
-
-/** @addtogroup UARTEx_Exported_Functions_Group3
- * @brief Extended Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions **********************************************/
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6) && !defined(STM32F030xC)
-HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-/**
- * @}
- */
-/* Peripheral State functions ************************************************/
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+ ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @}
@@ -853,7 +582,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_UART_EX_H */
+#endif /* STM32F0xx_HAL_UART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_usart.h b/Inc/stm32f0xx_hal_usart.h
index 30a6e59..e0f1dba 100644
--- a/Inc/stm32f0xx_hal_usart.h
+++ b/Inc/stm32f0xx_hal_usart.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_USART_H
-#define __STM32F0xx_HAL_USART_H
+#ifndef STM32F0xx_HAL_USART_H
+#define STM32F0xx_HAL_USART_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -64,7 +48,11 @@
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
+ Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[3] = 0
+ Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
+ where fclk_pres is the USART input clock frequency
+ @note Oversampling by 8 is systematically applied to achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
@@ -91,7 +79,8 @@
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit. */
-}USART_InitTypeDef;
+
+} USART_InitTypeDef;
/**
* @brief HAL USART State structures definition
@@ -106,7 +95,7 @@
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
-}HAL_USART_StateTypeDef;
+} HAL_USART_StateTypeDef;
/**
* @brief USART clock sources definitions
@@ -118,43 +107,85 @@
USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
-}USART_ClockSourceTypeDef;
-
+} USART_ClockSourceTypeDef;
/**
* @brief USART handle Structure definition
*/
-typedef struct
+typedef struct __USART_HandleTypeDef
{
- USART_TypeDef *Instance; /*!< USART registers base address */
+ USART_TypeDef *Instance; /*!< USART registers base address */
- USART_InitTypeDef Init; /*!< USART communication parameters */
+ USART_InitTypeDef Init; /*!< USART communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
+ uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
- uint16_t TxXferSize; /*!< USART Tx Transfer size */
+ uint16_t TxXferSize; /*!< USART Tx Transfer size */
- __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
+ uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
- uint16_t RxXferSize; /*!< USART Rx Transfer size */
+ uint16_t RxXferSize; /*!< USART Rx Transfer size */
- __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
- uint16_t Mask; /*!< USART Rx RDR register mask */
+ uint16_t Mask; /*!< USART Rx RDR register mask */
- DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
+ void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
- DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
+ void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
- __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
+ DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
- __IO uint32_t ErrorCode; /*!< USART Error code */
+ HAL_LockTypeDef Lock; /*!< Locking object */
-}USART_HandleTypeDef;
+ __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code */
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
+ void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
+ void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
+ void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
+ void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
+ void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
+ void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
+
+ void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
+ void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+} USART_HandleTypeDef;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL USART Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
+ HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
+ HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
+ HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
+ HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
+ HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
+ HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
+
+ HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
+ HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
+
+} HAL_USART_CallbackIDTypeDef;
+
+/**
+ * @brief HAL USART Callback pointer definition
+ */
+typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
+
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
@@ -165,31 +196,34 @@
* @{
*/
-/** @defgroup USART_Error USART Error
+/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
-#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
-#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
-#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
-#define HAL_USART_ERROR_FE (0x00000004U) /*!< frame error */
-#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
+#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
+#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
+#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
+#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
- */
+ */
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
-#ifdef USART_SMARTCARD_SUPPORT
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
-#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
+#if defined(USART_SMARTCARD_SUPPORT)
+#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */
+#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */
+#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
+#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */
#else
#define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
/**
* @}
*/
@@ -197,9 +231,9 @@
/** @defgroup USART_Parity USART Parity
* @{
*/
-#define USART_PARITY_NONE (0x00000000U) /*!< No parity */
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
+#define USART_PARITY_NONE 0x00000000U /*!< No parity */
+#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
+#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
@@ -207,9 +241,18 @@
/** @defgroup USART_Mode USART Mode
* @{
*/
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
+#define USART_MODE_RX USART_CR1_RE /*!< RX mode */
+#define USART_MODE_TX USART_CR1_TE /*!< TX mode */
+#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Over_Sampling USART Over Sampling
+ * @{
+ */
+#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
@@ -217,8 +260,8 @@
/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLE (0x00000000U) /*!< USART clock disable */
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
+#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */
+#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */
/**
* @}
*/
@@ -226,8 +269,8 @@
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
-#define USART_POLARITY_LOW (0x00000000U) /*!< USART Clock signal is steady Low */
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
+#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */
+#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */
/**
* @}
*/
@@ -235,8 +278,8 @@
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
-#define USART_PHASE_1EDGE (0x00000000U) /*!< USART frame phase on first clock transition */
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
+#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */
+#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */
/**
* @}
*/
@@ -244,8 +287,40 @@
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
-#define USART_LASTBIT_DISABLE (0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
+#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */
+#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */
+/**
+ * @}
+ */
+
+
+/** @defgroup USART_Request_Parameters USART Request Parameters
+ * @{
+ */
+#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
+#if defined(USART_RQR_TXFRQ)
+#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
+#endif /* USART_RQR_TXFRQ */
+/**
+ * @}
+ */
+
+/** @defgroup USART_Flags USART Flags
+ * Elements values convention: 0xXXXX
+ * - 0xXXXX : Flag mask in the ISR register
+ * @{
+ */
+#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
+#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
+#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
+#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
+#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
+#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
+#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
+#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
+#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
+#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
+#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
/**
* @}
*/
@@ -261,15 +336,16 @@
* @{
*/
-#define USART_IT_PE ((uint16_t)0x0028U) /*!< USART parity error interruption */
-#define USART_IT_TXE ((uint16_t)0x0727U) /*!< USART transmit data register empty interruption */
-#define USART_IT_TC ((uint16_t)0x0626U) /*!< USART transmission complete interruption */
-#define USART_IT_RXNE ((uint16_t)0x0525U) /*!< USART read data register not empty interruption */
-#define USART_IT_IDLE ((uint16_t)0x0424U) /*!< USART idle interruption */
-#define USART_IT_ERR ((uint16_t)0x0060U) /*!< USART error interruption */
-#define USART_IT_ORE ((uint16_t)0x0300U) /*!< USART overrun error interruption */
-#define USART_IT_NE ((uint16_t)0x0200U) /*!< USART noise error interruption */
-#define USART_IT_FE ((uint16_t)0x0100U) /*!< USART frame error interruption */
+#define USART_IT_PE 0x0028U /*!< USART parity error interruption */
+#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
+#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
+#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
+#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
+#define USART_IT_ERR 0x0060U /*!< USART error interruption */
+#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
+#define USART_IT_NE 0x0200U /*!< USART noise error interruption */
+#define USART_IT_FE 0x0100U /*!< USART frame error interruption */
+
/**
* @}
*/
@@ -277,13 +353,13 @@
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
* @{
*/
-#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
-#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
-#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
-#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
-#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
-#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
-#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
+#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
+#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
+#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
+#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
+#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
+#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
+#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
/**
* @}
*/
@@ -291,7 +367,11 @@
/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
* @{
*/
-#define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */
+#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */
+#define USART_CR_MASK 0x00E0U /*!< USART control register mask */
+#define USART_CR_POS 5U /*!< USART control register position */
+#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */
+#define USART_ISR_POS 8U /*!< USART ISR register position */
/**
* @}
*/
@@ -305,24 +385,25 @@
* @{
*/
-/** @brief Reset USART handle state.
+/** @brief Reset USART handle state.
* @param __HANDLE__ USART handle.
* @retval None
*/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
+#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
* @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
- @endif
* @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref USART_FLAG_BUSY Busy flag
* @arg @ref USART_FLAG_CTS CTS Change flag
@@ -342,12 +423,12 @@
* @param __HANDLE__ specifies the USART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
- * @arg @ref USART_CLEAR_PEF
- * @arg @ref USART_CLEAR_FEF
- * @arg @ref USART_CLEAR_NEF
- * @arg @ref USART_CLEAR_OREF
- * @arg @ref USART_CLEAR_IDLEF
- * @arg @ref USART_CLEAR_TCF
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_CTSF
* @retval None
*/
@@ -383,72 +464,75 @@
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
+
+
/** @brief Enable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
- * @param __IT__ specifies the USART interrupt source to check.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_ORE OverRun Error interrupt
- * @arg @ref USART_IT_NE Noise Error interrupt
- * @arg @ref USART_IT_FE Framing Error interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+ & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
- * @param __IT__ specifies the USART interrupt source to check.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
- * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
- * @arg @ref USART_IT_TC Transmission complete interrupt
- * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
- * @arg @ref USART_IT_IDLE Idle line detection interrupt
- * @arg @ref USART_IT_ORE OverRun Error interrupt
- * @arg @ref USART_IT_NE Noise Error interrupt
- * @arg @ref USART_IT_FE Framing Error interrupt
- * @arg @ref USART_IT_PE Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
+ * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
+ * @arg @ref USART_IT_TC Transmission complete interrupt
+ * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
+ * @arg @ref USART_IT_IDLE Idle line detection interrupt
+ * @arg @ref USART_IT_ORE OverRun Error interrupt
+ * @arg @ref USART_IT_NE Noise Error interrupt
+ * @arg @ref USART_IT_FE Framing Error interrupt
+ * @arg @ref USART_IT_PE Parity Error interrupt
+ * @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
- (((uint16_t)(__IT__)) & USART_IT_MASK)))
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
@@ -456,13 +540,12 @@
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt.
* This parameter can be one of the following values:
- * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
- * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
- * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
- * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
- * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
- * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
- * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
+ * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
+ * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
+ * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
+ * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
+ * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
+ * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
@@ -472,42 +555,37 @@
* @param __REQ__ specifies the request flag to set.
* This parameter can be one of the following values:
* @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
- @if STM32F030x6
- @elseif STM32F030x8
- @elseif STM32F030xC
- @elseif STM32F070x6
- @elseif STM32F070xB
- @else
+#if defined(USART_RQR_TXFRQ)
* @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
- @endif
+#endif
*
* @retval None
*/
-#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the USART one bit sample method.
- * @param __HANDLE__ specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the USART one bit sample method.
- * @param __HANDLE__ specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
-#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
/** @brief Enable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
-#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
-#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
@@ -518,20 +596,26 @@
* @{
*/
+/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
+ * @param __PCLK__ USART clock.
+ * @param __BAUD__ Baud rate set by the user.
+ * @retval Division result
+ */
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+
/** @brief Check USART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U)
+ * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */
+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 6000000U)
/**
* @brief Ensure that USART frame number of stop bits is valid.
- * @param __STOPBITS__ USART frame number of stop bits.
+ * @param __STOPBITS__ USART frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
-#ifdef USART_SMARTCARD_SUPPORT
+#if defined(USART_SMARTCARD_SUPPORT)
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
((__STOPBITS__) == USART_STOPBITS_1) || \
((__STOPBITS__) == USART_STOPBITS_1_5) || \
@@ -539,55 +623,75 @@
#else
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
((__STOPBITS__) == USART_STOPBITS_2))
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
/**
* @brief Ensure that USART frame parity is valid.
- * @param __PARITY__ USART frame parity.
+ * @param __PARITY__ USART frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
- */
+ */
#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
((__PARITY__) == USART_PARITY_EVEN) || \
((__PARITY__) == USART_PARITY_ODD))
/**
* @brief Ensure that USART communication mode is valid.
- * @param __MODE__ USART communication mode.
+ * @param __MODE__ USART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
- */
+ */
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
+ * @brief Ensure that USART oversampling is valid.
+ * @param __SAMPLING__ USART oversampling.
+ * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+ */
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+ ((__SAMPLING__) == USART_OVERSAMPLING_8))
+
+/**
* @brief Ensure that USART clock state is valid.
- * @param __CLOCK__ USART clock state.
+ * @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
- */
+ */
#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
((__CLOCK__) == USART_CLOCK_ENABLE))
/**
* @brief Ensure that USART frame polarity is valid.
- * @param __CPOL__ USART frame polarity.
+ * @param __CPOL__ USART frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
- */
+ */
#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
/**
* @brief Ensure that USART frame phase is valid.
- * @param __CPHA__ USART frame phase.
+ * @param __CPHA__ USART frame phase.
* @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
*/
#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
/**
* @brief Ensure that USART frame last bit clock pulse setting is valid.
- * @param __LASTBIT__ USART frame last bit clock pulse setting.
+ * @param __LASTBIT__ USART frame last bit clock pulse setting.
* @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
*/
#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
((__LASTBIT__) == USART_LASTBIT_ENABLE))
/**
+ * @brief Ensure that USART request parameter is valid.
+ * @param __PARAM__ USART request parameter.
+ * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+ */
+#if defined(USART_RQR_TXFRQ)
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
+ ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
+#else
+#define IS_USART_REQUEST_PARAMETER(__PARAM__) ((__PARAM__) == USART_RXDATA_FLUSH_REQUEST)
+#endif /* USART_RQR_TXFRQ */
+
+/**
* @}
*/
@@ -609,6 +713,13 @@
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -620,13 +731,16 @@
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
@@ -635,21 +749,19 @@
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
-/* Peripheral Control functions ***********************************************/
-
-/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
@@ -677,7 +789,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_USART_H */
+#endif /* STM32F0xx_HAL_USART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_usart_ex.h b/Inc/stm32f0xx_hal_usart_ex.h
index 942fe1e..9625c13 100644
--- a/Inc/stm32f0xx_hal_usart_ex.h
+++ b/Inc/stm32f0xx_hal_usart_ex.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_USART_EX_H
-#define __STM32F0xx_HAL_USART_EX_H
+#ifndef STM32F0xx_HAL_USART_EX_H
+#define STM32F0xx_HAL_USART_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -61,83 +45,18 @@
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
-#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
-#else
+#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
+#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
+#elif defined(USART_CR1_M)
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long USART frame */
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+#endif
/**
* @}
*/
-/** @defgroup USART_Request_Parameters USARTEx Request Parameters
- * @{
- */
-#define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
-#else
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-/**
- * @}
- */
-
-/** @defgroup USART_Flags USART Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the ISR register
- * @{
- */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-#define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */
-#define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */
-#define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */
-#define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */
-#define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */
-#define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */
-#define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */
-#define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */
-#define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */
-#define USART_FLAG_NE (0x00000004U) /*!< USART noise error */
-#define USART_FLAG_FE (0x00000002U) /*!< USART frame error */
-#define USART_FLAG_PE (0x00000001U) /*!< USART parity error */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup USARTEx_Exported_Macros USARTEx Exported Macros
- * @{
- */
-
-/** @brief Flush the USART Data registers.
- * @param __HANDLE__ specifies the USART Handle.
- * @retval None
- */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
- SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
- } while(0)
-#else
-#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
- } while(0)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
* @}
@@ -153,6 +72,12 @@
* @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
+/** @brief Report the UART clock source.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __CLOCKSOURCE__ output variable.
+ * @retval UART clocking source, written in __CLOCKSOURCE__.
+ */
+
#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
@@ -175,9 +100,7 @@
break; \
} \
} while(0)
-#elif defined (STM32F030x8) || defined (STM32F070x6) || \
- defined (STM32F042x6) || defined (STM32F048xx) || \
- defined (STM32F051x8) || defined (STM32F058xx)
+#elif defined (STM32F030x8) || defined (STM32F070x6) || defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F051x8) || defined (STM32F058xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -450,8 +373,6 @@
} \
} while(0)
#endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
-
-
/** @brief Compute the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
@@ -461,111 +382,126 @@
* @param __HANDLE__ specifies the USART Handle.
* @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x007FU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x003FU; \
- } \
- } \
-} while(0)
-#else
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+#elif defined(USART_CR1_M)
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU; \
- } \
- } \
-} while(0)
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
-
+ } \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Mask = 0x0000U; \
+ } \
+ } while(0U)
+#endif
/**
* @brief Ensure that USART frame length is valid.
- * @param __LENGTH__ USART frame length.
+ * @param __LENGTH__ USART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
-#if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
+#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
-#else
+#elif defined(USART_CR1_M)
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
-#endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || defined (STM32F070xB) || \
- defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
+#endif
-/**
- * @brief Ensure that USART request parameter is valid.
- * @param __PARAM__ USART request parameter.
- * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
- */
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
- ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
-#else
-#define IS_USART_REQUEST_PARAMETER(__PARAM__) ((__PARAM__) == USART_RXDATA_FLUSH_REQUEST)
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USARTEx_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USARTEx_Exported_Functions_Group1
+ * @{
+ */
+
+/* IO operation functions *****************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup USARTEx_Exported_Functions_Group2
+ * @{
+ */
+
+/* Peripheral Control functions ***********************************************/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/**
* @}
@@ -579,7 +515,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_USART_EX_H */
+#endif /* STM32F0xx_HAL_USART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/Inc/stm32f0xx_hal_wwdg.h b/Inc/stm32f0xx_hal_wwdg.h
index a164d85..7293ba3 100644
--- a/Inc/stm32f0xx_hal_wwdg.h
+++ b/Inc/stm32f0xx_hal_wwdg.h
@@ -6,39 +6,23 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_HAL_WWDG_H
-#define __STM32F0xx_HAL_WWDG_H
+#ifndef STM32F0xx_HAL_WWDG_H
+#define STM32F0xx_HAL_WWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -58,7 +42,7 @@
* @{
*/
-/**
+/**
* @brief WWDG Init structure definition
*/
typedef struct
@@ -75,18 +59,44 @@
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
-}WWDG_InitTypeDef;
+} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+typedef struct __WWDG_HandleTypeDef
+#else
typedef struct
+#endif
{
- WWDG_TypeDef *Instance; /*!< Register base address */
+ WWDG_TypeDef *Instance; /*!< Register base address */
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
-}WWDG_HandleTypeDef;
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
+
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif
+} WWDG_HandleTypeDef;
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL WWDG common Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
+} HAL_WWDG_CallbackIDTypeDef;
+
+/**
+ * @brief HAL WWDG Callback pointer definition
+ */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
+
+#endif
/**
* @}
*/
@@ -117,10 +127,10 @@
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
@@ -128,7 +138,7 @@
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
-#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
+#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}
@@ -143,9 +153,9 @@
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
@@ -174,7 +184,7 @@
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__ WWDG handle
+ * @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
@@ -229,7 +239,8 @@
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
@@ -247,6 +258,12 @@
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
+#endif
+
/**
* @}
*/
@@ -257,7 +274,7 @@
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
@@ -278,6 +295,6 @@
}
#endif
-#endif /* __STM32F0xx_HAL_WWDG_H */
+#endif /* STM32F0xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_ll_adc.h b/Inc/stm32f0xx_ll_adc.h
index 2a7f519..7adf13b 100644
--- a/Inc/stm32f0xx_ll_adc.h
+++ b/Inc/stm32f0xx_ll_adc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_bus.h b/Inc/stm32f0xx_ll_bus.h
index 4059159..0468a19 100644
--- a/Inc/stm32f0xx_ll_bus.h
+++ b/Inc/stm32f0xx_ll_bus.h
@@ -23,29 +23,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_comp.h b/Inc/stm32f0xx_ll_comp.h
index ceb1a5d..faaae83 100644
--- a/Inc/stm32f0xx_ll_comp.h
+++ b/Inc/stm32f0xx_ll_comp.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_cortex.h b/Inc/stm32f0xx_ll_cortex.h
index 4044db1..7b7cfd8 100644
--- a/Inc/stm32f0xx_ll_cortex.h
+++ b/Inc/stm32f0xx_ll_cortex.h
@@ -19,29 +19,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_crc.h b/Inc/stm32f0xx_ll_crc.h
index 949201e..4883242 100644
--- a/Inc/stm32f0xx_ll_crc.h
+++ b/Inc/stm32f0xx_ll_crc.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_LL_CRC_H
-#define __STM32F0xx_LL_CRC_H
+#ifndef STM32F0xx_LL_CRC_H
+#define STM32F0xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
@@ -65,7 +49,7 @@
* @{
*/
-#if defined(CRC_PROG_POLYNOMIAL_SUPPORT)
+#if defined(CRC_POL_POL)
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
* @{
*/
@@ -76,7 +60,7 @@
/**
* @}
*/
-#endif
+#endif /* CRC_POL_POL */
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
* @{
@@ -98,7 +82,7 @@
* @}
*/
-#if defined(CRC_PROG_POLYNOMIAL_SUPPORT)
+#if defined(CRC_POL_POL)
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
* @brief Normal representation of this polynomial value is
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
@@ -108,7 +92,7 @@
/**
* @}
*/
-#endif
+#endif /* CRC_POL_POL */
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
* @{
@@ -138,7 +122,7 @@
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
@@ -179,11 +163,9 @@
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
-#if defined(CRC_PROG_POLYNOMIAL_SUPPORT)
+#if defined(CRC_POL_POL)
/**
* @brief Configure size of the polynomial.
- * @note This function is available only on devices supporting
- * Programmable Polynomial feature.
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
* @param CRCx CRC Instance
* @param PolySize This parameter can be one of the following values:
@@ -200,8 +182,6 @@
/**
* @brief Return size of the polynomial.
- * @note This function is available only on devices supporting
- * Programmable Polynomial feature.
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
@@ -214,7 +194,7 @@
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
-#endif
+#endif /* CRC_POL_POL */
/**
* @brief Configure the reversal of the bit order of the input data
@@ -302,12 +282,10 @@
return (uint32_t)(READ_REG(CRCx->INIT));
}
-#if defined(CRC_PROG_POLYNOMIAL_SUPPORT)
+#if defined(CRC_POL_POL)
/**
* @brief Initialize the Programmable polynomial value
* (coefficients of the polynomial to be used for CRC calculation).
- * @note This function is available only on devices supporting
- * Programmable Polynomial feature.
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
@@ -324,8 +302,6 @@
/**
* @brief Return current Programmable polynomial value
- * @note This function is available only on devices supporting
- * Programmable Polynomial feature.
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
@@ -337,7 +313,7 @@
{
return (uint32_t)(READ_REG(CRCx->POL));
}
-#endif
+#endif /* CRC_POL_POL */
/**
* @}
@@ -368,7 +344,10 @@
*/
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
- *(uint16_t __IO *)(&CRCx->DR) = (uint16_t) InData;
+ __IO uint16_t *pReg;
+
+ pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = InData;
}
/**
@@ -394,12 +373,10 @@
return (uint32_t)(READ_REG(CRCx->DR));
}
-#if defined(CRC_PROG_POLYNOMIAL_SUPPORT)
+#if defined(CRC_POL_POL)
/**
* @brief Return current CRC calculation result. 16 bits value is returned.
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
- * @note This function is available only on devices supporting
- * Programmable Polynomial feature.
* @rmtoll DR DR LL_CRC_ReadData16
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
@@ -412,8 +389,6 @@
/**
* @brief Return current CRC calculation result. 8 bits value is returned.
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
- * @note This function is available only on devices supporting
- * Programmable Polynomial feature.
* @rmtoll DR DR LL_CRC_ReadData8
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
@@ -426,8 +401,6 @@
/**
* @brief Return current CRC calculation result. 7 bits value is returned.
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
- * @note This function is available only on devices supporting
- * Programmable Polynomial feature.
* @rmtoll DR DR LL_CRC_ReadData7
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
@@ -436,7 +409,7 @@
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
-#endif
+#endif /* CRC_POL_POL */
/**
* @brief Return data stored in the Independent Data(IDR) register.
@@ -455,7 +428,7 @@
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
- * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+ * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
@@ -496,6 +469,6 @@
}
#endif
-#endif /* __STM32F0xx_LL_CRC_H */
+#endif /* STM32F0xx_LL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_ll_crs.h b/Inc/stm32f0xx_ll_crs.h
index 4f154c1..b44e4be 100644
--- a/Inc/stm32f0xx_ll_crs.h
+++ b/Inc/stm32f0xx_ll_crs.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_dac.h b/Inc/stm32f0xx_ll_dac.h
index cb01e26..4040522 100644
--- a/Inc/stm32f0xx_ll_dac.h
+++ b/Inc/stm32f0xx_ll_dac.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_dma.h b/Inc/stm32f0xx_ll_dma.h
index 9d9eb97..ebd74e1 100644
--- a/Inc/stm32f0xx_ll_dma.h
+++ b/Inc/stm32f0xx_ll_dma.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_exti.h b/Inc/stm32f0xx_ll_exti.h
index 647409c..f488959 100644
--- a/Inc/stm32f0xx_ll_exti.h
+++ b/Inc/stm32f0xx_ll_exti.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_gpio.h b/Inc/stm32f0xx_ll_gpio.h
index 2782b06..42fdd87 100644
--- a/Inc/stm32f0xx_ll_gpio.h
+++ b/Inc/stm32f0xx_ll_gpio.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_i2c.h b/Inc/stm32f0xx_ll_i2c.h
index fbe9e01..b581d85 100644
--- a/Inc/stm32f0xx_ll_i2c.h
+++ b/Inc/stm32f0xx_ll_i2c.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_LL_I2C_H
-#define __STM32F0xx_LL_I2C_H
+#ifndef STM32F0xx_LL_I2C_H
+#define STM32F0xx_LL_I2C_H
#ifdef __cplusplus
extern "C" {
@@ -281,14 +265,14 @@
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
-#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
-#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
+#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
@@ -431,7 +415,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
}
/**
@@ -513,7 +497,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
}
/**
@@ -546,7 +530,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -579,7 +563,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -594,7 +578,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
{
- register uint32_t data_reg_addr = 0U;
+ register uint32_t data_reg_addr;
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{
@@ -642,7 +626,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
}
/**
@@ -675,7 +659,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
}
#if defined(I2C_CR1_WUPEN)
@@ -716,7 +700,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
}
#endif
@@ -752,7 +736,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}
/**
@@ -829,7 +813,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
+ return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
}
/**
@@ -885,7 +869,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
+ return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
}
/**
@@ -1040,7 +1024,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
}
/**
@@ -1079,7 +1063,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
}
/**
@@ -1244,7 +1228,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
- return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
+ return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
}
/**
@@ -1285,7 +1269,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
}
/**
@@ -1318,7 +1302,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
}
/**
@@ -1351,7 +1335,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
}
/**
@@ -1384,7 +1368,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
}
/**
@@ -1417,7 +1401,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
}
/**
@@ -1456,7 +1440,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
}
/**
@@ -1507,7 +1491,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
+ return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
}
/**
@@ -1528,7 +1512,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
}
/**
@@ -1541,7 +1525,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
}
/**
@@ -1554,7 +1538,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
}
/**
@@ -1567,7 +1551,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
}
/**
@@ -1580,7 +1564,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
}
/**
@@ -1593,7 +1577,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
}
/**
@@ -1606,7 +1590,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
}
/**
@@ -1619,7 +1603,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
}
/**
@@ -1632,7 +1616,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
}
/**
@@ -1645,7 +1629,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
}
/**
@@ -1658,7 +1642,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
}
/**
@@ -1673,7 +1657,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
}
/**
@@ -1688,7 +1672,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
}
/**
@@ -1704,7 +1688,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
}
/**
@@ -1717,7 +1701,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
}
/**
@@ -1878,7 +1862,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
}
/**
@@ -1913,7 +1897,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
}
/**
@@ -2012,7 +1996,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
}
/**
@@ -2108,9 +2092,9 @@
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
- SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
+ SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
}
/**
@@ -2165,7 +2149,7 @@
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
+ return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
}
/**
@@ -2213,8 +2197,8 @@
* @{
*/
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
@@ -2241,6 +2225,6 @@
}
#endif
-#endif /* __STM32F0xx_LL_I2C_H */
+#endif /* STM32F0xx_LL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_ll_iwdg.h b/Inc/stm32f0xx_ll_iwdg.h
index 7a2086e..9934247 100644
--- a/Inc/stm32f0xx_ll_iwdg.h
+++ b/Inc/stm32f0xx_ll_iwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_LL_IWDG_H
-#define __STM32F0xx_LL_IWDG_H
+#ifndef STM32F0xx_LL_IWDG_H
+#define STM32F0xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
@@ -61,12 +45,10 @@
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
-
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
-
/**
* @}
*/
@@ -86,7 +68,6 @@
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
-
/**
* @}
*/
@@ -160,7 +141,7 @@
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
@@ -171,7 +152,7 @@
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
@@ -182,7 +163,7 @@
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
@@ -193,7 +174,7 @@
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+ WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
@@ -230,7 +211,7 @@
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->PR));
+ return (READ_REG(IWDGx->PR));
}
/**
@@ -253,7 +234,7 @@
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->RLR));
+ return (READ_REG(IWDGx->RLR));
}
/**
@@ -276,7 +257,7 @@
*/
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
{
- return (uint32_t)(READ_REG(IWDGx->WINR));
+ return (READ_REG(IWDGx->WINR));
}
/**
@@ -295,7 +276,7 @@
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
@@ -306,7 +287,7 @@
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
/**
@@ -317,7 +298,7 @@
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
}
/**
@@ -330,7 +311,7 @@
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
+ return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
}
/**
@@ -346,7 +327,7 @@
* @}
*/
-#endif /* IWDG) */
+#endif /* IWDG */
/**
* @}
@@ -356,6 +337,6 @@
}
#endif
-#endif /* __STM32F0xx_LL_IWDG_H */
+#endif /* STM32F0xx_LL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_ll_pwr.h b/Inc/stm32f0xx_ll_pwr.h
index 3a6449d..d50b86a 100644
--- a/Inc/stm32f0xx_ll_pwr.h
+++ b/Inc/stm32f0xx_ll_pwr.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_rcc.h b/Inc/stm32f0xx_ll_rcc.h
index 50bba6b..0206b9d 100644
--- a/Inc/stm32f0xx_ll_rcc.h
+++ b/Inc/stm32f0xx_ll_rcc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -468,6 +452,7 @@
/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
* @{
*/
+#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */
#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
@@ -1649,9 +1634,28 @@
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
/**
+ * @brief Configure PLL clock source
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
+ * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLSOURCE_HSI48 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
+}
+
+/**
* @brief Get the oscillator used as PLL clock source.
* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
* @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI (*)
* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
* @arg @ref LL_RCC_PLLSOURCE_HSE
diff --git a/Inc/stm32f0xx_ll_rtc.h b/Inc/stm32f0xx_ll_rtc.h
index b7cfbe6..8bfb830 100644
--- a/Inc/stm32f0xx_ll_rtc.h
+++ b/Inc/stm32f0xx_ll_rtc.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -103,19 +87,19 @@
{
uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
-
+
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetHourFormat(). */
uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
-
+
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetAsynchPrescaler(). */
uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
-
+
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetSynchPrescaler(). */
} LL_RTC_InitTypeDef;
@@ -551,7 +535,7 @@
* @}
*/
-/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
* @{
*/
#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
@@ -849,14 +833,14 @@
* @arg @ref LL_RTC_PIN_PC15
* @retval None
*/
-__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask)
+__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask)
{
CLEAR_BIT(RTCx->TAFCR, PinMask);
}
/**
* @brief Set PC14 and/or PC15 to high level.
- * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
* @rmtoll TAFCR PC14VALUE LL_RTC_SetOutputPin\n
* TAFCR PC15VALUE LL_RTC_SetOutputPin
* @param RTCx RTC Instance
@@ -865,14 +849,14 @@
* @arg @ref LL_RTC_PIN_PC15
* @retval None
*/
-__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef *RTCx, uint32_t PinMask)
{
SET_BIT(RTCx->TAFCR, (PinMask >> 1));
}
/**
* @brief Set PC14 and/or PC15 to low level.
- * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
+ * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode)
* @rmtoll TAFCR PC14VALUE LL_RTC_ResetOutputPin\n
* TAFCR PC15VALUE LL_RTC_ResetOutputPin
* @param RTCx RTC Instance
@@ -881,7 +865,7 @@
* @arg @ref LL_RTC_PIN_PC15
* @retval None
*/
-__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask)
+__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef *RTCx, uint32_t PinMask)
{
CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1));
}
@@ -1143,10 +1127,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
- return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
}
/**
@@ -1181,10 +1162,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
- return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))) >> RTC_TR_MNU_Pos);
}
/**
@@ -1219,10 +1197,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU))) >> RTC_TR_SU_Pos);
}
/**
@@ -1277,7 +1252,7 @@
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
register uint32_t temp = 0U;
-
+
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
(((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
@@ -1415,10 +1390,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
}
/**
@@ -1511,10 +1483,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
- return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
}
/**
@@ -1544,10 +1513,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
- return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
}
/**
@@ -1616,7 +1582,7 @@
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
register uint32_t temp = 0U;
-
+
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
(((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
@@ -1744,10 +1710,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
- return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
}
/**
@@ -1839,10 +1802,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
- return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
}
/**
@@ -1870,10 +1830,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
- return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
}
/**
@@ -1901,10 +1858,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
{
- register uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
+ return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
}
/**
@@ -2258,10 +2212,10 @@
* TAFCR TAMP3E LL_RTC_TAMPER_Enable
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_1
- * @arg @ref LL_RTC_TAMPER_2
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2
* @arg @ref LL_RTC_TAMPER_3 (*)
- *
+ *
* (*) value not defined in all devices.
* @retval None
*/
@@ -2277,10 +2231,10 @@
* TAFCR TAMP3E LL_RTC_TAMPER_Disable
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_1
- * @arg @ref LL_RTC_TAMPER_2
+ * @arg @ref LL_RTC_TAMPER_1
+ * @arg @ref LL_RTC_TAMPER_2
* @arg @ref LL_RTC_TAMPER_3 (*)
- *
+ *
* (*) value not defined in all devices.
* @retval None
*/
@@ -2427,10 +2381,10 @@
* TAFCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
- *
+ *
* (*) value not defined in all devices.
* @retval None
*/
@@ -2446,10 +2400,10 @@
* TAFCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
- *
+ *
* (*) value not defined in all devices.
* @retval None
*/
diff --git a/Inc/stm32f0xx_ll_spi.h b/Inc/stm32f0xx_ll_spi.h
index d3a6381..537c954 100644
--- a/Inc/stm32f0xx_ll_spi.h
+++ b/Inc/stm32f0xx_ll_spi.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_LL_SPI_H
-#define __STM32F0xx_LL_SPI_H
+#ifndef STM32F0xx_LL_SPI_H
+#define STM32F0xx_LL_SPI_H
#ifdef __cplusplus
extern "C" {
@@ -397,7 +381,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
/**
@@ -738,7 +722,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+ return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
}
/**
@@ -902,7 +886,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
}
/**
@@ -921,7 +905,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
}
/**
@@ -932,7 +916,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
}
/**
@@ -943,7 +927,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
}
/**
@@ -954,7 +938,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+ return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
/**
@@ -965,7 +949,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
/**
@@ -983,7 +967,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+ return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
}
/**
@@ -994,7 +978,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
}
/**
@@ -1048,11 +1032,10 @@
*/
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
- tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
- (void) tmpreg;
+ __IO uint32_t tmpreg_sr;
+ tmpreg_sr = SPIx->SR;
+ (void) tmpreg_sr;
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
@@ -1170,7 +1153,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
}
/**
@@ -1181,7 +1164,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
}
/**
@@ -1192,7 +1175,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
}
/**
@@ -1233,7 +1216,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -1266,7 +1249,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+ return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
}
/**
@@ -1331,7 +1314,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
- return (uint32_t) & (SPIx->DR);
+ return (uint32_t) &(SPIx->DR);
}
/**
@@ -1373,7 +1356,12 @@
*/
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
+#if defined (__GNUC__)
+ __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
*((__IO uint8_t *)&SPIx->DR) = TxData;
+#endif /* __GNUC__ */
}
/**
@@ -1385,7 +1373,12 @@
*/
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
- *((__IO uint16_t *)&SPIx->DR) = TxData;
+#if defined (__GNUC__)
+ __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+ *spidr = TxData;
+#else
+ SPIx->DR = TxData;
+#endif /* __GNUC__ */
}
/**
@@ -1666,7 +1659,7 @@
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
}
/**
@@ -1875,7 +1868,7 @@
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+ return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
}
#if defined(SPI_I2SCFGR_ASTRTEN)
@@ -1909,7 +1902,7 @@
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
+ return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
}
#endif /* SPI_I2SCFGR_ASTRTEN */
@@ -1973,7 +1966,7 @@
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+ return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
/**
@@ -1998,7 +1991,7 @@
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
{
- return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+ return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
}
/**
@@ -2288,6 +2281,6 @@
}
#endif
-#endif /* __STM32F0xx_LL_SPI_H */
+#endif /* STM32F0xx_LL_SPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_ll_system.h b/Inc/stm32f0xx_ll_system.h
index 65af161..5f101d8 100644
--- a/Inc/stm32f0xx_ll_system.h
+++ b/Inc/stm32f0xx_ll_system.h
@@ -18,29 +18,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_tim.h b/Inc/stm32f0xx_ll_tim.h
index 7fc8713..a490cc2 100644
--- a/Inc/stm32f0xx_ll_tim.h
+++ b/Inc/stm32f0xx_ll_tim.h
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -117,7 +101,6 @@
* @}
*/
-
/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Constants TIM Private Constants
* @{
@@ -129,16 +112,16 @@
#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7FU)
-#define DT_DELAY_2 ((uint8_t)0x3FU)
-#define DT_DELAY_3 ((uint8_t)0x1FU)
-#define DT_DELAY_4 ((uint8_t)0x1FU)
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00U)
-#define DT_RANGE_2 ((uint8_t)0x80U)
-#define DT_RANGE_3 ((uint8_t)0xC0U)
-#define DT_RANGE_4 ((uint8_t)0xE0U)
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
/**
@@ -161,12 +144,12 @@
* @retval none
*/
#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+ (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+ ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
/** @brief Calculate the deadtime sampling period(in ps).
* @param __TIMCLK__ timer input clock frequency (in Hz).
@@ -177,9 +160,9 @@
* @retval none
*/
#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
/**
* @}
*/
@@ -619,7 +602,7 @@
#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
@@ -659,7 +642,7 @@
/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
* @{
*/
-#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
@@ -704,7 +687,7 @@
* @{
*/
#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
/**
* @}
@@ -713,9 +696,9 @@
/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
* @{
*/
-#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
+#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
/**
* @}
*/
@@ -750,14 +733,14 @@
/** @defgroup TIM_LL_EC_TS Trigger Selection
* @{
*/
-#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
/**
* @}
*/
@@ -858,8 +841,6 @@
#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-
-
/**
* @}
*/
@@ -924,7 +905,7 @@
* @param __VALUE__ Value to be written in the register
* @retval None
*/
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in TIM register.
@@ -932,7 +913,7 @@
* @param __REG__ Register to be read
* @retval Register value
*/
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
@@ -953,11 +934,11 @@
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
- 0U)
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ 0U)
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
@@ -967,7 +948,7 @@
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+ (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -978,7 +959,7 @@
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+ ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
@@ -989,8 +970,8 @@
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
-((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
- / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+ ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
@@ -1002,8 +983,8 @@
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
- + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro retrieving the ratio of the input capture prescaler
@@ -1016,7 +997,7 @@
* @retval Input capture prescaler ratio (1, 2, 4 or 8)
*/
#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
/**
@@ -1066,7 +1047,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
/**
@@ -1099,7 +1080,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
}
/**
@@ -1165,9 +1146,12 @@
/**
* @brief Set the timer counter counting mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
* CR1 CMS LL_TIM_SetCounterMode
* @param TIMx Timer instance
@@ -1181,12 +1165,12 @@
*/
__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
{
- MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+ MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
}
/**
* @brief Get actual counter mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
@@ -1234,12 +1218,12 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+ return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
}
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
@@ -1257,7 +1241,7 @@
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
@@ -1274,7 +1258,7 @@
/**
* @brief Set the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
@@ -1288,7 +1272,7 @@
/**
* @brief Get the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
@@ -1342,7 +1326,7 @@
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* @rmtoll ARR ARR LL_TIM_SetAutoReload
@@ -1358,7 +1342,7 @@
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @param TIMx Timer instance
* @retval Auto-reload value
@@ -1370,7 +1354,7 @@
/**
* @brief Set the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
@@ -1384,7 +1368,7 @@
/**
* @brief Get the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
@@ -1407,7 +1391,7 @@
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
@@ -1420,7 +1404,7 @@
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
@@ -1433,7 +1417,7 @@
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
@@ -1477,7 +1461,7 @@
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
@@ -1565,7 +1549,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
- return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+ return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
/**
@@ -1667,7 +1651,7 @@
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -1731,7 +1715,7 @@
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
- * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
@@ -1851,9 +1835,9 @@
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
@@ -1915,15 +1899,15 @@
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
@@ -1946,7 +1930,7 @@
/**
* @brief Disable clearing the output channel on an external event.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
@@ -1971,7 +1955,7 @@
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
@@ -1988,14 +1972,14 @@
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
+ return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
@@ -2011,9 +1995,9 @@
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
@@ -2028,9 +2012,9 @@
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
@@ -2045,9 +2029,9 @@
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
@@ -2062,9 +2046,9 @@
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
@@ -2079,9 +2063,9 @@
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
@@ -2095,9 +2079,9 @@
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
@@ -2111,9 +2095,9 @@
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
@@ -2127,9 +2111,9 @@
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
@@ -2237,7 +2221,7 @@
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2288,7 +2272,7 @@
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2363,7 +2347,7 @@
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2426,7 +2410,7 @@
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
@@ -2439,7 +2423,7 @@
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
@@ -2452,7 +2436,7 @@
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
@@ -2460,15 +2444,15 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
@@ -2482,9 +2466,9 @@
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
@@ -2498,9 +2482,9 @@
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
@@ -2514,9 +2498,9 @@
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
@@ -2537,7 +2521,7 @@
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
@@ -2550,7 +2534,7 @@
/**
* @brief Disable external clock mode 2.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
@@ -2563,7 +2547,7 @@
/**
* @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
@@ -2571,7 +2555,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
}
/**
@@ -2580,9 +2564,9 @@
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
@@ -2600,7 +2584,7 @@
/**
* @brief Set the encoder interface mode.
- * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
@@ -2624,7 +2608,7 @@
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
@@ -2646,7 +2630,7 @@
/**
* @brief Set the synchronization mode of a slave timer.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
@@ -2664,7 +2648,7 @@
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
@@ -2686,7 +2670,7 @@
/**
* @brief Enable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
@@ -2699,7 +2683,7 @@
/**
* @brief Disable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
@@ -2712,7 +2696,7 @@
/**
* @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
@@ -2720,12 +2704,12 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+ return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
}
/**
* @brief Configure the external trigger (ETR) input.
- * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
@@ -2773,7 +2757,7 @@
*/
/**
* @brief Enable the break function.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
@@ -2781,10 +2765,8 @@
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
- __IO uint32_t tmpreg;
-
+ __IO uint32_t tmpreg;
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
@@ -2794,16 +2776,14 @@
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
__IO uint32_t tmpreg;
-
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-
/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
@@ -2811,7 +2791,7 @@
/**
* @brief Configure the break input.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK
* @param TIMx Timer instance
@@ -2823,17 +2803,15 @@
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
{
__IO uint32_t tmpreg;
-
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
-
- /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
+ /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */
tmpreg = READ_REG(TIMx->BDTR);
(void)(tmpreg);
}
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
@@ -2853,7 +2831,7 @@
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
@@ -2866,7 +2844,7 @@
/**
* @brief Disable automatic output (MOE can be set only by software).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
@@ -2879,7 +2857,7 @@
/**
* @brief Indicate whether automatic output is enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
@@ -2887,14 +2865,14 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
}
/**
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
@@ -2909,7 +2887,7 @@
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
@@ -2922,7 +2900,7 @@
/**
* @brief Indicates whether outputs are enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
@@ -2930,7 +2908,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+ return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
}
/**
@@ -2942,7 +2920,7 @@
*/
/**
* @brief Configures the timer DMA burst feature.
- * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
@@ -2989,7 +2967,7 @@
*/
__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
{
- MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+ MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
}
/**
@@ -3001,7 +2979,7 @@
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
- * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
* @param TIMx Timer instance
@@ -3066,7 +3044,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
/**
@@ -3088,7 +3066,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
/**
@@ -3110,7 +3088,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
/**
@@ -3132,7 +3110,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
/**
@@ -3154,7 +3132,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
/**
@@ -3176,7 +3154,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
}
/**
@@ -3198,7 +3176,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
}
/**
@@ -3220,7 +3198,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
/**
@@ -3242,7 +3220,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
}
/**
@@ -3264,7 +3242,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
}
/**
@@ -3286,7 +3264,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
}
/**
@@ -3308,7 +3286,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+ return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
}
/**
@@ -3348,7 +3326,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
}
/**
@@ -3381,7 +3359,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
}
/**
@@ -3414,7 +3392,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
}
/**
@@ -3447,7 +3425,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
}
/**
@@ -3480,7 +3458,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
}
/**
@@ -3513,7 +3491,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
}
/**
@@ -3546,7 +3524,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
}
/**
@@ -3579,7 +3557,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
}
/**
@@ -3619,7 +3597,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
}
/**
@@ -3652,7 +3630,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
}
/**
@@ -3685,7 +3663,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
}
/**
@@ -3718,7 +3696,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
}
/**
@@ -3751,7 +3729,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
}
/**
@@ -3784,7 +3762,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
}
/**
@@ -3817,7 +3795,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+ return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
}
/**
diff --git a/Inc/stm32f0xx_ll_usart.h b/Inc/stm32f0xx_ll_usart.h
index e8f00fb..1a1810c 100644
--- a/Inc/stm32f0xx_ll_usart.h
+++ b/Inc/stm32f0xx_ll_usart.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_LL_USART_H
-#define __STM32F0xx_LL_USART_H
+#ifndef STM32F0xx_LL_USART_H
+#define STM32F0xx_LL_USART_H
#ifdef __cplusplus
extern "C" {
@@ -48,7 +32,7 @@
* @{
*/
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) || defined (USART7) || defined (USART8)
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) || defined (USART6) || defined (USART7) || defined (USART8)
/** @defgroup USART_LL USART
* @{
@@ -58,13 +42,6 @@
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
- * @{
- */
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@@ -86,6 +63,7 @@
*/
typedef struct
{
+
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
@@ -171,22 +149,22 @@
*/
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */
-#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise detected flag */
+#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */
-#if defined(USART_LIN_SUPPORT)
+#if defined USART_LIN_SUPPORT
#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */
-#endif
+#endif /* USART_LIN_SUPPORT */
#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */
#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */
-#if defined(USART_SMARTCARD_SUPPORT)
+#if defined USART_SMARTCARD_SUPPORT
#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */
-#endif
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -203,26 +181,26 @@
#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */
#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */
-#if defined(USART_LIN_SUPPORT)
+#if defined USART_LIN_SUPPORT
#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
-#endif
+#endif /* USART_LIN_SUPPORT */
#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
-#if defined(USART_SMARTCARD_SUPPORT)
+#if defined USART_SMARTCARD_SUPPORT
#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
+#endif /* USART_CR1_UESM */
#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
-#endif
/**
* @}
*/
@@ -240,15 +218,15 @@
#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
#if defined(USART_SMARTCARD_SUPPORT)
#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#if defined(USART_LIN_SUPPORT)
#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
-#endif
+#endif /* USART_LIN_SUPPORT */
#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
-#endif
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -293,7 +271,7 @@
#else
#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-#endif
+#endif/* USART_7BITS_SUPPORT */
/**
* @}
*/
@@ -351,11 +329,11 @@
*/
#if defined(USART_SMARTCARD_SUPPORT)
#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
#if defined(USART_SMARTCARD_SUPPORT)
#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
@@ -414,7 +392,7 @@
#if defined(USART_FABR_SUPPORT)
#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
-#endif
+#endif /* USART_FABR_SUPPORT */
/**
* @}
*/
@@ -439,7 +417,7 @@
* @}
*/
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
* @{
*/
@@ -449,8 +427,8 @@
/**
* @}
*/
-#endif
+#endif /* USART_CR1_UESM */
#if defined(USART_IRDA_SUPPORT)
/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
* @{
@@ -460,7 +438,7 @@
/**
* @}
*/
-#endif
+#endif /* USART_IRDA_SUPPORT */
#if defined(USART_LIN_SUPPORT)
/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
@@ -471,7 +449,7 @@
/**
* @}
*/
-#endif
+#endif /* USART_LIN_SUPPORT */
/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
@@ -535,7 +513,8 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@@ -544,7 +523,7 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
@@ -597,10 +576,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/**
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
@@ -640,10 +619,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_CR1_UESM*/
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_USART_EnableDirectionRx
@@ -848,7 +827,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
/**
@@ -1036,7 +1015,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
}
/**
@@ -1287,7 +1266,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
}
/**
@@ -1359,7 +1338,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
}
/**
@@ -1538,7 +1517,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
}
/**
@@ -1571,10 +1550,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS);
+ return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
@@ -1607,8 +1586,8 @@
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
}
-#endif
+#endif /* USART_CR1_UESM */
/**
* @brief Configure USART BRR register for achieving expected Baud Rate value.
* @note Compute and set USARTDIV value in BRR Register (full BRR content)
@@ -1628,8 +1607,8 @@
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
uint32_t BaudRate)
{
- register uint32_t usartdiv = 0x0U;
- register uint32_t brrtemp = 0x0U;
+ uint32_t usartdiv;
+ register uint32_t brrtemp;
if (OverSampling == LL_USART_OVERSAMPLING_8)
{
@@ -1659,16 +1638,20 @@
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
{
- register uint32_t usartdiv = 0x0U;
+ register uint32_t usartdiv;
register uint32_t brrresult = 0x0U;
usartdiv = USARTx->BRR;
- if (OverSampling == LL_USART_OVERSAMPLING_8)
+ if (usartdiv == 0U)
{
- if ((usartdiv & 0xFFF7U) != 0U)
+ /* Do not perform a division by 0 */
+ }
+ else if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ if (usartdiv != 0U)
{
- usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
brrresult = (PeriphClk * 2U) / usartdiv;
}
}
@@ -1728,7 +1711,7 @@
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
}
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
/**
* @}
@@ -1775,7 +1758,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
}
/**
@@ -1821,7 +1804,7 @@
*/
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -1841,7 +1824,7 @@
/**
* @}
*/
-#endif
+#endif /* USART_IRDA_SUPPORT */
#if defined(USART_SMARTCARD_SUPPORT)
/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
@@ -1884,7 +1867,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
}
/**
@@ -1923,7 +1906,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
}
/**
@@ -1970,7 +1953,7 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
@@ -1999,7 +1982,7 @@
*/
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
+ MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
}
/**
@@ -2019,7 +2002,7 @@
/**
* @}
*/
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
* @{
@@ -2061,7 +2044,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
/**
@@ -2140,13 +2123,13 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
}
/**
* @}
*/
-#endif
+#endif /* USART_LIN_SUPPORT */
/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
* @{
@@ -2242,7 +2225,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
/**
@@ -2313,25 +2296,26 @@
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported), CLKEN bits in the USART_CR2 register,
- - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.*/
+ - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.
+ */
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
#else
CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-#endif
+#endif /* USART_LIN_SUPPORT */
#if defined(USART_SMARTCARD_SUPPORT)
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-#endif
+#endif /* USART_IRDA_SUPPORT */
#else
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-#endif
-#endif
+#endif /* USART_IRDA_SUPPORT */
+#endif /* USART_SMARTCARD_SUPPORT */
}
/**
@@ -2365,23 +2349,24 @@
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported) bit in the USART_CR2 register,
- - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.*/
+ - SCEN (if Smartcard feature is supported), IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.
+ */
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-#endif
+#endif /* USART_LIN_SUPPORT */
#if defined(USART_SMARTCARD_SUPPORT)
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-#endif
+#endif /* USART_IRDA_SUPPORT */
#else
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-#endif
-#endif
+#endif /* USART_IRDA_SUPPORT */
+#endif /* USART_SMARTCARD_SUPPORT */
/* set the UART/USART in Synchronous mode */
SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
}
@@ -2420,25 +2405,26 @@
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- - IREN (if Irda feature is supported), SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.*/
+ - IREN (if Irda feature is supported) , SCEN (if Smartcard feature is supported)and HDSEL bits in the USART_CR3 register.
+ */
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
#if defined(USART_SMARTCARD_SUPPORT)
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-#endif
+#endif /* USART_IRDA_SUPPORT */
#else
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-#endif
-#endif
+#endif /* USART_IRDA_SUPPORT */
+#endif /* USART_SMARTCARD_SUPPORT */
/* Set the UART/USART in LIN mode */
SET_BIT(USARTx->CR2, USART_CR2_LINEN);
}
-#endif
+#endif /* USART_LIN_SUPPORT */
/**
* @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
@@ -2470,24 +2456,25 @@
__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
{
/* In Half Duplex mode, the following bits must be kept cleared:
- - LINEN (if LIN feature is supported), CLKEN bits in the USART_CR2 register,
- - SCEN (if Smartcard feature is supported) and IREN (if Irda feature is supported) bits in the USART_CR3 register.*/
+ - LINEN (if LIN feature is supported) and CLKEN bits in the USART_CR2 register,
+ - SCEN (if Smartcard feature is supported) and IREN (if Irda feature is supported) bits in the USART_CR3 register.
+ */
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
#else
CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-#endif
+#endif /* USART_LIN_SUPPORT */
#if defined(USART_SMARTCARD_SUPPORT)
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN));
-#endif
+#endif /* USART_IRDA_SUPPORT */
#else
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN));
-#endif
-#endif
+#endif /* USART_IRDA_SUPPORT */
+#endif /* USART_SMARTCARD_SUPPORT */
/* set the UART/USART in Half Duplex mode */
SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
}
@@ -2526,22 +2513,23 @@
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported) bit in the USART_CR2 register,
- - IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.*/
+ - IREN (if Irda feature is supported) and HDSEL bits in the USART_CR3 register.
+ */
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-#endif
+#endif /* USART_LIN_SUPPORT */
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL));
-#endif
+#endif /* USART_IRDA_SUPPORT */
/* Configure Stop bits to 1.5 bits */
/* Synchronous mode is activated by default */
SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
/* set the UART/USART in Smartcard mode */
SET_BIT(USARTx->CR3, USART_CR3_SCEN);
}
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#if defined(USART_IRDA_SUPPORT)
/**
@@ -2577,21 +2565,22 @@
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported), STOP and CLKEN bits in the USART_CR2 register,
- - SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.*/
+ - SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.
+ */
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
#else
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
-#endif
+#endif /* USART_LIN_SUPPORT */
#if defined(USART_SMARTCARD_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL));
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
/* set the UART/USART in IRDA mode */
SET_BIT(USARTx->CR3, USART_CR3_IREN);
}
-#endif
+#endif /* USART_IRDA_SUPPORT */
/**
* @brief Perform basic configuration of USART for enabling use in Multi processor Mode
@@ -2624,25 +2613,26 @@
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN (if LIN feature is supported) and CLKEN bits in the USART_CR2 register,
- - IREN (if Irda feature is supported), SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.*/
+ - IREN (if Irda feature is supported), SCEN (if Smartcard feature is supported) and HDSEL bits in the USART_CR3 register.
+ */
#if defined(USART_LIN_SUPPORT)
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
#else
CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-#endif
+#endif /* USART_LIN_SUPPORT */
#if defined(USART_SMARTCARD_SUPPORT)
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-#endif
+#endif /* USART_IRDA_SUPPORT */
#else
#if defined(USART_IRDA_SUPPORT)
CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
#else
CLEAR_BIT(USARTx->CR3, (USART_CR3_HDSEL));
-#endif
-#endif
+#endif /* USART_IRDA_SUPPORT */
+#endif /* USART_SMARTCARD_SUPPORT*/
}
/**
@@ -2661,7 +2651,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
/**
@@ -2672,18 +2662,18 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Noise error detected Flag is set or not
- * @rmtoll ISR NF LL_USART_IsActiveFlag_NE
+ * @rmtoll ISR NE LL_USART_IsActiveFlag_NE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
/**
@@ -2694,7 +2684,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
/**
@@ -2705,7 +2695,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
/**
@@ -2716,7 +2706,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL);
}
/**
@@ -2727,7 +2717,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
/**
@@ -2738,7 +2728,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL);
}
#if defined(USART_LIN_SUPPORT)
@@ -2752,9 +2742,9 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_LIN_SUPPORT */
/**
* @brief Check if the USART CTS interrupt Flag is set or not
@@ -2766,7 +2756,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
/**
@@ -2779,7 +2769,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
/**
@@ -2790,7 +2780,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
}
#if defined(USART_SMARTCARD_SUPPORT)
@@ -2804,9 +2794,9 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
/**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
@@ -2818,7 +2808,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
}
/**
@@ -2831,7 +2821,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
}
/**
@@ -2842,7 +2832,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
/**
@@ -2853,7 +2843,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
/**
@@ -2864,7 +2854,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
/**
@@ -2875,10 +2865,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/**
* @brief Check if the USART Wake Up from stop mode Flag is set or not
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
@@ -2889,10 +2879,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_CR1_UESM */
/**
* @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
@@ -2901,7 +2891,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
/**
@@ -2912,10 +2902,9 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK));
+ return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
-
/**
* @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_USART_ClearFlag_PE
@@ -2939,7 +2928,7 @@
}
/**
- * @brief Clear Noise detected Flag
+ * @brief Clear Noise Error detected Flag
* @rmtoll ICR NCF LL_USART_ClearFlag_NE
* @param USARTx USART Instance
* @retval None
@@ -2996,7 +2985,7 @@
{
WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
}
-#endif
+#endif /* USART_LIN_SUPPORT */
/**
* @brief Clear CTS Interrupt Flag
@@ -3035,7 +3024,7 @@
{
WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
}
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
/**
* @brief Clear Character Match Flag
@@ -3048,7 +3037,7 @@
WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
}
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/**
* @brief Clear Wake Up from stop mode Flag
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
@@ -3061,8 +3050,8 @@
{
WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
}
-#endif
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -3161,7 +3150,7 @@
{
SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#if defined(USART_LIN_SUPPORT)
/**
@@ -3176,8 +3165,8 @@
{
SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
}
-#endif
+#endif/* USART_LIN_SUPPORT */
/**
* @brief Enable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
@@ -3206,7 +3195,7 @@
SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/**
* @brief Enable Wake Up from Stop Mode Interrupt
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
@@ -3219,8 +3208,8 @@
{
SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
-#endif
+#endif /* USART_CR1_UESM */
/**
* @brief Disable IDLE Interrupt
@@ -3312,7 +3301,7 @@
{
CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#if defined(USART_LIN_SUPPORT)
/**
@@ -3327,7 +3316,7 @@
{
CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
}
-#endif
+#endif /* USART_LIN_SUPPORT */
/**
* @brief Disable Error Interrupt
@@ -3357,7 +3346,7 @@
CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/**
* @brief Disable Wake Up from Stop Mode Interrupt
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
@@ -3370,8 +3359,8 @@
{
CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
-#endif
+#endif /* USART_CR1_UESM */
/**
* @brief Check if the USART IDLE Interrupt source is enabled or disabled.
@@ -3381,7 +3370,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
/**
@@ -3392,7 +3381,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U);
}
/**
@@ -3403,7 +3392,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
/**
@@ -3414,7 +3403,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U);
}
/**
@@ -3425,7 +3414,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
/**
@@ -3436,7 +3425,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
/**
@@ -3447,7 +3436,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
}
#if defined(USART_SMARTCARD_SUPPORT)
@@ -3461,10 +3450,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE));
+ return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_SMARTCARD_SUPPORT */
#if defined(USART_LIN_SUPPORT)
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
@@ -3476,9 +3465,9 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+ return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_LIN_SUPPORT */
/**
* @brief Check if the USART Error Interrupt is enabled or disabled.
@@ -3488,7 +3477,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
/**
@@ -3501,10 +3490,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
-#if defined(USART_WUSM_SUPPORT)
+#if defined(USART_CR1_UESM)
/**
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
* @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
@@ -3515,10 +3504,10 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
-#endif
+#endif /* USART_CR1_UESM */
/**
* @}
@@ -3558,7 +3547,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
/**
@@ -3591,7 +3580,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
/**
@@ -3624,7 +3613,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
{
- return (READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE));
+ return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
/**
@@ -3639,7 +3628,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
- register uint32_t data_reg_addr = 0U;
+ register uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
@@ -3671,7 +3660,7 @@
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
- return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+ return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
@@ -3706,7 +3695,7 @@
*/
__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
{
- USARTx->TDR = Value & 0x1FFU;
+ USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
}
/**
@@ -3727,7 +3716,7 @@
*/
__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_ABRRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
}
/**
@@ -3738,7 +3727,7 @@
*/
__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_SBKRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
}
/**
@@ -3749,18 +3738,20 @@
*/
__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_MMRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
}
/**
* @brief Request a Receive Data flush
+ * @note Allows to discard the received data without reading them, and avoid an overrun
+ * condition.
* @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_RXFRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
}
#if defined(USART_SMARTCARD_SUPPORT)
@@ -3774,9 +3765,9 @@
*/
__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
{
- SET_BIT(USARTx->RQR, USART_RQR_TXFRQ);
+ SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
}
-#endif
+#endif /*USART_SMARTCARD_SUPPORT*/
/**
* @}
@@ -3804,7 +3795,7 @@
* @}
*/
-#endif /* USART1 || USART2|| USART3 || USART4 || USART5 || USART6 || USART7 || USART8 */
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || USART7 || USART8 */
/**
* @}
@@ -3814,6 +3805,6 @@
}
#endif
-#endif /* __STM32F0xx_LL_USART_H */
+#endif /* STM32F0xx_LL_USART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_ll_usb.h b/Inc/stm32f0xx_ll_usb.h
new file mode 100644
index 0000000..0c9ce89
--- /dev/null
+++ b/Inc/stm32f0xx_ll_usb.h
@@ -0,0 +1,237 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_ll_usb.h
+ * @author MCD Application Team
+ * @brief Header file of USB Low Layer HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F0xx_LL_USB_H
+#define STM32F0xx_LL_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal_def.h"
+
+#if defined (USB)
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup USB_LL
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief USB Mode definition
+ */
+
+
+
+typedef enum
+{
+ USB_DEVICE_MODE = 0
+} USB_ModeTypeDef;
+
+/**
+ * @brief USB Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t dev_endpoints; /*!< Device Endpoints number.
+ This parameter depends on the used USB core.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint32_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref USB_Core_Speed */
+
+ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+
+ uint32_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref USB_Core_PHY */
+
+ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+
+ uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
+
+ uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
+
+ uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+} USB_CfgTypeDef;
+
+typedef struct
+{
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_EP_Type */
+
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
+
+ uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral
+ This parameter is added to ensure compatibility across USB peripherals */
+
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+
+ uint32_t xfer_len; /*!< Current transfer length */
+
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+
+} USB_EPTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+ * @{
+ */
+
+
+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
+ * @{
+ */
+#define DEP0CTL_MPS_64 0U
+#define DEP0CTL_MPS_32 1U
+#define DEP0CTL_MPS_16 2U
+#define DEP0CTL_MPS_8 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
+ * @{
+ */
+#define EP_TYPE_CTRL 0U
+#define EP_TYPE_ISOC 1U
+#define EP_TYPE_BULK 2U
+#define EP_TYPE_INTR 3U
+#define EP_TYPE_MSK 3U
+/**
+ * @}
+ */
+
+/** @defgroup USB_LL Device Speed
+ * @{
+ */
+#define USBD_FS_SPEED 2U
+/**
+ * @}
+ */
+
+#define BTABLE_ADDRESS 0x000U
+#define PMA_ACCESS 1U
+
+#define EP_ADDR_MSK 0x7U
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
+ * @{
+ */
+
+
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
+void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
+uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
+void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32F0xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f0xx_ll_utils.h b/Inc/stm32f0xx_ll_utils.h
index ca5ed3e..f047ba2 100644
--- a/Inc/stm32f0xx_ll_utils.h
+++ b/Inc/stm32f0xx_ll_utils.h
@@ -18,29 +18,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Inc/stm32f0xx_ll_wwdg.h b/Inc/stm32f0xx_ll_wwdg.h
index 3a6d707..2095991 100644
--- a/Inc/stm32f0xx_ll_wwdg.h
+++ b/Inc/stm32f0xx_ll_wwdg.h
@@ -6,36 +6,20 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_LL_WWDG_H
-#define __STM32F0xx_LL_WWDG_H
+#ifndef STM32F0xx_LL_WWDG_H
+#define STM32F0xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
@@ -56,34 +40,30 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-
/* Private constants ---------------------------------------------------------*/
-
/* Private macros ------------------------------------------------------------*/
-
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
-
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
-#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
-#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+ * @{
+ */
+#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
@@ -119,7 +99,6 @@
* @}
*/
-
/**
* @}
*/
@@ -155,7 +134,7 @@
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+ return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
@@ -182,7 +161,7 @@
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+ return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
@@ -215,7 +194,7 @@
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
@@ -247,7 +226,7 @@
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
@@ -268,7 +247,7 @@
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+ return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
@@ -310,7 +289,7 @@
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{
- return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+ return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
@@ -335,6 +314,6 @@
}
#endif
-#endif /* __STM32F0xx_LL_WWDG_H */
+#endif /* STM32F0xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/README.md b/README.md
index d19721d..932c34c 100644
--- a/README.md
+++ b/README.md
@@ -35,6 +35,7 @@
HAL Driver F0 | CMSIS Device F0 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
Tag v1.7.2 | Tag v2.3.3 | Tag v4.5_cm0 | Tag v1.10.1 (and following, if any, till next new tag)
+Tag v1.7.3 | Tag v2.3.4 | Tag v5.4.0_cm0 | Tag v1.11.0 (and following, if any, till next new tag)
The full **STM32CubeF0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF0).
diff --git a/Release_Notes.html b/Release_Notes.html
index 85d0ced..0c87fb8 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -1,972 +1,1555 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"><head><meta http-equiv="Content-Type" content="text/html; charset=windows-1252"><link rel="File-List" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/filelist.xml"><link rel="Edit-Time-Data" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/editdata.mso"><title>Release Notes for STM32F0xx HAL Drivers</title><link rel="themeData" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/themedata.thmx"><link rel="colorSchemeMapping" href="Release_Notes_for_STM32F0xx_HAL_Drivers_files/colorschememapping.xml"><style>
-<!--
-/* Font Definitions */
-@font-face
-{font-family:"Cambria Math";
-panose-1:2 4 5 3 5 4 6 3 2 4;
-mso-font-charset:1;
-mso-generic-font-family:roman;
-mso-font-format:other;
-mso-font-pitch:variable;
-mso-font-signature:0 0 0 0 0 0;}
-@font-face
-{font-family:Calibri;
-panose-1:2 15 5 2 2 2 4 3 2 4;
-mso-font-charset:0;
-mso-generic-font-family:swiss;
-mso-font-pitch:variable;
-mso-font-signature:-1610611985 1073750139 0 0 159 0;}
-@font-face
-{font-family:Tahoma;
-panose-1:2 11 6 4 3 5 4 4 2 4;
-mso-font-charset:0;
-mso-generic-font-family:swiss;
-mso-font-pitch:variable;
-mso-font-signature:1627400839 -2147483648 8 0 66047 0;}
-@font-face
-{font-family:Verdana;
-panose-1:2 11 6 4 3 5 4 4 2 4;
-mso-font-charset:0;
-mso-generic-font-family:swiss;
-mso-font-pitch:variable;
-mso-font-signature:536871559 0 0 0 415 0;}
-/* Style Definitions */
-p.MsoNormal, li.MsoNormal, div.MsoNormal
-{mso-style-unhide:no;
-mso-style-qformat:yes;
-mso-style-parent:"";
-margin:0in;
-margin-bottom:.0001pt;
-mso-pagination:widow-orphan;
-font-size:12.0pt;
-font-family:"Times New Roman","serif";
-mso-fareast-font-family:"Times New Roman";}
-h1
-{mso-style-unhide:no;
-mso-style-qformat:yes;
-mso-style-link:"Heading 1 Char";
-mso-margin-top-alt:auto;
-margin-right:0in;
-mso-margin-bottom-alt:auto;
-margin-left:0in;
-mso-pagination:widow-orphan;
-mso-outline-level:1;
-font-size:24.0pt;
-font-family:"Times New Roman","serif";
-mso-fareast-font-family:"Times New Roman";
-mso-fareast-theme-font:minor-fareast;
-font-weight:bold;}
-h2
-{mso-style-unhide:no;
-mso-style-qformat:yes;
-mso-style-link:"Heading 2 Char";
-mso-style-next:Normal;
-margin-top:12.0pt;
-margin-right:0in;
-margin-bottom:3.0pt;
-margin-left:0in;
-mso-pagination:widow-orphan;
-page-break-after:avoid;
-mso-outline-level:2;
-font-size:14.0pt;
-font-family:"Arial","sans-serif";
-mso-fareast-font-family:"Times New Roman";
-mso-fareast-theme-font:minor-fareast;
-font-weight:bold;
-font-style:italic;}
-h3
-{mso-style-unhide:no;
-mso-style-qformat:yes;
-mso-style-link:"Heading 3 Char";
-mso-margin-top-alt:auto;
-margin-right:0in;
-mso-margin-bottom-alt:auto;
-margin-left:0in;
-mso-pagination:widow-orphan;
-mso-outline-level:3;
-font-size:13.5pt;
-font-family:"Times New Roman","serif";
-mso-fareast-font-family:"Times New Roman";
-mso-fareast-theme-font:minor-fareast;
-font-weight:bold;}
-a:link, span.MsoHyperlink
-{mso-style-unhide:no;
-color:blue;
-text-decoration:underline;
-text-underline:single;}
-a:visited, span.MsoHyperlinkFollowed
-{mso-style-unhide:no;
-color:blue;
-text-decoration:underline;
-text-underline:single;}
-p
-{mso-style-unhide:no;
-mso-margin-top-alt:auto;
-margin-right:0in;
-mso-margin-bottom-alt:auto;
-margin-left:0in;
-mso-pagination:widow-orphan;
-font-size:12.0pt;
-font-family:"Times New Roman","serif";
-mso-fareast-font-family:"Times New Roman";}
-p.MsoAcetate, li.MsoAcetate, div.MsoAcetate
-{mso-style-unhide:no;
-mso-style-link:"Balloon Text Char";
-margin:0in;
-margin-bottom:.0001pt;
-mso-pagination:widow-orphan;
-font-size:8.0pt;
-font-family:"Tahoma","sans-serif";
-mso-fareast-font-family:"Times New Roman";}
-span.Heading1Char
-{mso-style-name:"Heading 1 Char";
-mso-style-unhide:no;
-mso-style-locked:yes;
-mso-style-link:"Heading 1";
-mso-ansi-font-size:14.0pt;
-mso-bidi-font-size:14.0pt;
-font-family:"Cambria","serif";
-mso-ascii-font-family:Cambria;
-mso-ascii-theme-font:major-latin;
-mso-fareast-font-family:"Times New Roman";
-mso-fareast-theme-font:major-fareast;
-mso-hansi-font-family:Cambria;
-mso-hansi-theme-font:major-latin;
-mso-bidi-font-family:"Times New Roman";
-mso-bidi-theme-font:major-bidi;
-color:#365F91;
-mso-themecolor:accent1;
-mso-themeshade:191;
-font-weight:bold;}
-span.Heading2Char
-{mso-style-name:"Heading 2 Char";
-mso-style-unhide:no;
-mso-style-locked:yes;
-mso-style-link:"Heading 2";
-mso-ansi-font-size:13.0pt;
-mso-bidi-font-size:13.0pt;
-font-family:"Cambria","serif";
-mso-ascii-font-family:Cambria;
-mso-ascii-theme-font:major-latin;
-mso-fareast-font-family:"Times New Roman";
-mso-fareast-theme-font:major-fareast;
-mso-hansi-font-family:Cambria;
-mso-hansi-theme-font:major-latin;
-mso-bidi-font-family:"Times New Roman";
-mso-bidi-theme-font:major-bidi;
-color:#4F81BD;
-mso-themecolor:accent1;
-font-weight:bold;}
-span.Heading3Char
-{mso-style-name:"Heading 3 Char";
-mso-style-unhide:no;
-mso-style-locked:yes;
-mso-style-link:"Heading 3";
-mso-ansi-font-size:12.0pt;
-mso-bidi-font-size:12.0pt;
-font-family:"Cambria","serif";
-mso-ascii-font-family:Cambria;
-mso-ascii-theme-font:major-latin;
-mso-fareast-font-family:"Times New Roman";
-mso-fareast-theme-font:major-fareast;
-mso-hansi-font-family:Cambria;
-mso-hansi-theme-font:major-latin;
-mso-bidi-font-family:"Times New Roman";
-mso-bidi-theme-font:major-bidi;
-color:#4F81BD;
-mso-themecolor:accent1;
-font-weight:bold;}
-span.BalloonTextChar
-{mso-style-name:"Balloon Text Char";
-mso-style-unhide:no;
-mso-style-locked:yes;
-mso-style-link:"Balloon Text";
-mso-ansi-font-size:8.0pt;
-mso-bidi-font-size:8.0pt;
-font-family:"Tahoma","sans-serif";
-mso-ascii-font-family:Tahoma;
-mso-hansi-font-family:Tahoma;
-mso-bidi-font-family:Tahoma;}
-.MsoChpDefault
-{mso-style-type:export-only;
-mso-default-props:yes;
-font-size:10.0pt;
-mso-ansi-font-size:10.0pt;
-mso-bidi-font-size:10.0pt;}
-@page WordSection1
-{size:8.5in 11.0in;
-margin:1.0in 1.25in 1.0in 1.25in;
-mso-header-margin:.5in;
-mso-footer-margin:.5in;
-mso-paper-source:0;}
-div.WordSection1
-{page:WordSection1;}
-/* List Definitions */
-@list l0
-{mso-list-id:62067358;
-mso-list-template-ids:-174943062;}
-@list l0:level1
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l0:level2
-{mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l0:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l0:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l0:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l0:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l0:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l0:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l0:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1
-{mso-list-id:128015942;
-mso-list-template-ids:-90681214;}
-@list l1:level1
-{mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level2
-{mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l1:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l2
-{mso-list-id:216556000;
-mso-list-template-ids:925924412;}
-@list l2:level1
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l2:level2
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l2:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l2:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l2:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l2:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l2:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l2:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l2:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3
-{mso-list-id:562446694;
-mso-list-template-ids:913898366;}
-@list l3:level1
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l3:level2
-{mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l3:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4
-{mso-list-id:797802132;
-mso-list-template-ids:-1971191336;}
-@list l4:level1
-{mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level2
-{mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l4:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5
-{mso-list-id:907304066;
-mso-list-template-ids:1969781532;}
-@list l5:level1
-{mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level2
-{mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l5:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l6
-{mso-list-id:1050613616;
-mso-list-template-ids:-1009886748;}
-@list l6:level1
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l6:level2
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l6:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l6:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l6:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l6:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l6:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l6:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l6:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l7
-{mso-list-id:1234970193;
-mso-list-template-ids:2055904002;}
-@list l7:level1
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l7:level2
-{mso-level-number-format:bullet;
-mso-level-text:\F0B7;
-mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;
-mso-ansi-font-size:10.0pt;
-font-family:Symbol;}
-@list l7:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l7:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l7:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l7:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l7:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l7:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l7:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8
-{mso-list-id:1846092290;
-mso-list-template-ids:-768590846;}
-@list l8:level1
-{mso-level-start-at:2;
-mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level2
-{mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l8:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9
-{mso-list-id:1894656566;
-mso-list-template-ids:1199983812;}
-@list l9:level1
-{mso-level-start-at:2;
-mso-level-tab-stop:.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level2
-{mso-level-tab-stop:1.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level3
-{mso-level-tab-stop:1.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level4
-{mso-level-tab-stop:2.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level5
-{mso-level-tab-stop:2.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level6
-{mso-level-tab-stop:3.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level7
-{mso-level-tab-stop:3.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level8
-{mso-level-tab-stop:4.0in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-@list l9:level9
-{mso-level-tab-stop:4.5in;
-mso-level-number-position:left;
-text-indent:-.25in;}
-ol
-{margin-bottom:0in;}
-ul
-{margin-bottom:0in;}
--->
-</style><meta content="MCD Application Team" name="author"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>Patrice LE FLOCH</o:LastAuthor> <o:Revision>39</o:Revision> <o:TotalTime>137</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2010-10-15T11:07:00Z</o:LastSaved> <o:Pages>3</o:Pages> <o:Words>973</o:Words> <o:Characters>5548</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>46</o:Lines> <o:Paragraphs>13</o:Paragraphs> <o:CharactersWithSpaces>6508</o:CharactersWithSpaces> <o:Version>12.00</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:TrackMoves>false</w:TrackMoves> <w:TrackFormatting/> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:DoNotPromoteQF/> <w:LidThemeOther>EN-US</w:LidThemeOther> <w:LidThemeAsian>X-NONE</w:LidThemeAsian> <w:LidThemeComplexScript>X-NONE</w:LidThemeComplexScript> <w:Compatibility> <w:BreakWrappedTables/> <w:SnapToGridInCell/> <w:WrapTextWithPunct/> <w:UseAsianBreakRules/> <w:DontGrowAutofit/> <w:SplitPgBreakAndParaMark/> <w:DontVertAlignCellWithSp/> <w:DontBreakConstrainedForcedTables/> <w:DontVertAlignInTxbx/> <w:Word11KerningPairs/> <w:CachedColBalance/> </w:Compatibility> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> <m:mathPr> <m:mathFont m:val="Cambria Math"/> <m:brkBin m:val="before"/> <m:brkBinSub m:val="--"/> <m:smallFrac m:val="off"/> <m:dispDef/> <m:lMargin m:val="0"/> <m:rMargin m:val="0"/> <m:defJc m:val="centerGroup"/> <m:wrapIndent m:val="1440"/> <m:intLim m:val="subSup"/> <m:naryLim m:val="undOvr"/> </m:mathPr></w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" DefUnhideWhenUsed="false" DefSemiHidden="false" DefQFormat="false" LatentStyleCount="267"> <w:LsdException Locked="false" QFormat="true" Name="Normal"/> <w:LsdException Locked="false" QFormat="true" Name="heading 1"/> <w:LsdException Locked="false" QFormat="true" Name="heading 2"/> <w:LsdException Locked="false" QFormat="true" Name="heading 3"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 4"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 5"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 6"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 7"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 8"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="heading 9"/> <w:LsdException Locked="false" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="caption"/> <w:LsdException Locked="false" QFormat="true" Name="Title"/> <w:LsdException Locked="false" Priority="1" Name="Default Paragraph Font"/> <w:LsdException Locked="false" QFormat="true" Name="Subtitle"/> <w:LsdException Locked="false" QFormat="true" Name="Strong"/> <w:LsdException Locked="false" QFormat="true" Name="Emphasis"/> <w:LsdException Locked="false" Priority="99" Name="No List"/> <w:LsdException Locked="false" Priority="99" SemiHidden="true" Name="Placeholder Text"/> <w:LsdException Locked="false" Priority="1" QFormat="true" Name="No Spacing"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading"/> <w:LsdException Locked="false" Priority="61" Name="Light List"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3"/> <w:LsdException Locked="false" Priority="70" Name="Dark List"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 1"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 1"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 1"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 1"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 1"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 1"/> <w:LsdException Locked="false" Priority="99" SemiHidden="true" Name="Revision"/> <w:LsdException Locked="false" Priority="34" QFormat="true" Name="List Paragraph"/> <w:LsdException Locked="false" Priority="29" QFormat="true" Name="Quote"/> <w:LsdException Locked="false" Priority="30" QFormat="true" Name="Intense Quote"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 1"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 1"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 1"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 1"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 1"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 1"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 1"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 1"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 2"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 2"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 2"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 2"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 2"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 2"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 2"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 2"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 2"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 2"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 2"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 2"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 2"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 2"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 3"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 3"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 3"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 3"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 3"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 3"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 3"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 3"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 3"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 3"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 3"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 3"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 3"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 3"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 4"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 4"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 4"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 4"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 4"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 4"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 4"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 4"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 4"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 4"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 4"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 4"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 4"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 4"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 5"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 5"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 5"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 5"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 5"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 5"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 5"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 5"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 5"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 5"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 5"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 5"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 5"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 5"/> <w:LsdException Locked="false" Priority="60" Name="Light Shading Accent 6"/> <w:LsdException Locked="false" Priority="61" Name="Light List Accent 6"/> <w:LsdException Locked="false" Priority="62" Name="Light Grid Accent 6"/> <w:LsdException Locked="false" Priority="63" Name="Medium Shading 1 Accent 6"/> <w:LsdException Locked="false" Priority="64" Name="Medium Shading 2 Accent 6"/> <w:LsdException Locked="false" Priority="65" Name="Medium List 1 Accent 6"/> <w:LsdException Locked="false" Priority="66" Name="Medium List 2 Accent 6"/> <w:LsdException Locked="false" Priority="67" Name="Medium Grid 1 Accent 6"/> <w:LsdException Locked="false" Priority="68" Name="Medium Grid 2 Accent 6"/> <w:LsdException Locked="false" Priority="69" Name="Medium Grid 3 Accent 6"/> <w:LsdException Locked="false" Priority="70" Name="Dark List Accent 6"/> <w:LsdException Locked="false" Priority="71" Name="Colorful Shading Accent 6"/> <w:LsdException Locked="false" Priority="72" Name="Colorful List Accent 6"/> <w:LsdException Locked="false" Priority="73" Name="Colorful Grid Accent 6"/> <w:LsdException Locked="false" Priority="19" QFormat="true" Name="Subtle Emphasis"/> <w:LsdException Locked="false" Priority="21" QFormat="true" Name="Intense Emphasis"/> <w:LsdException Locked="false" Priority="31" QFormat="true" Name="Subtle Reference"/> <w:LsdException Locked="false" Priority="32" QFormat="true" Name="Intense Reference"/> <w:LsdException Locked="false" Priority="33" QFormat="true" Name="Book Title"/> <w:LsdException Locked="false" Priority="37" SemiHidden="true" UnhideWhenUsed="true" Name="Bibliography"/> <w:LsdException Locked="false" Priority="39" SemiHidden="true" UnhideWhenUsed="true" QFormat="true" Name="TOC Heading"/> </w:LatentStyles> </xml><![endif]--><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman","serif";} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="7170"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--></head>
-<body style="" link="blue" vlink="blue">
-<div class="WordSection1">
-<p class="MsoNormal"><span style="font-family: "Arial","sans-serif";"><o:p> </o:p></span></p>
-<div align="center">
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
-<tbody>
-<tr style="">
-<td style="padding: 0in;" valign="top">
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
-<tbody>
-<tr style="">
-<td style="padding: 0in 5.4pt;" valign="top">
-<p class="MsoNormal"><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
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+<!DOCTYPE html>
+<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
+<head>
+ <meta charset="utf-8" />
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+ <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
+ <title>Release Notes for STM32F0xx HAL Drivers</title>
+ <style type="text/css">
+ code{white-space: pre-wrap;}
+ span.smallcaps{font-variant: small-caps;}
+ span.underline{text-decoration: underline;}
+ div.column{display: inline-block; vertical-align: top; width: 50%;}
+ </style>
+ <link rel="stylesheet" href="_htmresc/mini-st.css" />
+ <!--[if lt IE 9]>
+ <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
+ <![endif]-->
+</head>
+<body>
+<div class="row">
+<div class="col-sm-12 col-lg-4">
+<div class="card fluid">
+<div class="sectione dark">
+<center>
+<h1 id="release-notes-for-stm32f0xx-hal-drivers"><strong>Release Notes for STM32F0xx HAL Drivers</strong></h1>
+<p>Copyright © 2016 STMicroelectronics<br />
+</p>
+<a href="https://www.st.com" class="logo"><img src="../../_htmresc/st_logo.png" alt="ST logo" /></a>
+</center>
+</div>
+</div>
+<h1 id="license"><strong>License</strong></h1>
+This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
+<center>
+<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
+</center>
+</div>
+<div class="col-sm-12 col-lg-8">
+<h1 id="update-history"><strong>Update History</strong></h1>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_7_3" aria-hidden="true"> <label for="collapse-section1_7_3" aria-hidden="true"><strong>V1.7.3 / 12-September-2019</strong></label>
+<div>
+<h2 id="main-changes">Main Changes</h2>
+<ul>
+<li>General updates to fix known defects and enhancements implementation</li>
+<li>Add support of HAL callback registration feature</li>
+<li>Add new <strong>HAL EXTI</strong> driver</li>
+<li><strong>The following changes done on the HAL drivers require an update on the application code based on older HAL versions</strong>
+<ul>
+<li><strong>HAL/LL Generic</strong> update
+<ul>
+<li>Add support of <strong>HAL callback registration</strong> feature
+<ul>
+<li>The feature disabled by default is available for the following HAL drivers:
+<ul>
+<li><strong>ADC, CAN, COMP, CEC, DAC, I2C, SMBUS, UART, USART, WWDG, RTC, SPI, SMARTCARD, IrDA, I2S, TIM, TSC and PCD</strong></li>
+</ul></li>
+<li>The feature may be enabled individually per HAL PPP driver by setting the corresponding definition USE_HAL_PPP_REGISTER_CALLBACKS to 1U in stm32f0xx_hal_conf.h project configuration file (template file stm32f0xx_hal_conf_template.h available from Drivers/STM32F0xx_HAL_Driver/Inc)</li>
+<li>Once enabled , the user application may resort to HAL_PPP_RegisterCallback() to register specific callback function(s) and unregister it(them) with HAL_PPP_UnRegisterCallback()</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL Generic</strong> update
+<ul>
+<li>Update HAL driver to allow user to change systick period to 1ms, 10 ms or 100 ms :
+<ul>
+<li>Add the following API’s :
+<ul>
+<li>HAL_GetTickPrio(): Returns a tick priority.</li>
+<li>HAL_SetTickFreq(): Sets new tick frequency.</li>
+<li>HAL_GetTickFreq(): Returns tick frequency.</li>
+</ul></li>
+<li>Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies: 10 Hz, 100 Hz and 1KHz (default).</li>
+</ul></li>
+<li>Add UNUSED() macro implementation to avoid GCC warning
+<ul>
+<li>The warning is detected when the UNUSED() macro is called from C++ file</li>
+</ul></li>
+<li>General updates to fix MISRA 2012 compilation errors
+<ul>
+<li>HAL_IS_BIT_SET()/HAL_IS_BIT_CLR() macros implementation update</li>
+<li>stdio.h include updated with stddef.h</li>
+<li>Update assert_failed() API prototype to use pointer on uint8_t instead of char</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL CRC</strong> update
+<ul>
+<li>Remove extended initialization HAL_CRCEx_Init() API
+<ul>
+<li>HAL_CRC_Init() call HAL_CRCEx_Polynomial_Set() to initialize the CRC polynomial</li>
+</ul></li>
+<li>Remove extra call to HAL_LOCK/HAL_UNLOCK from the followings APIs:
+<ul>
+<li>HAL_CRC_Accumulate()</li>
+<li>HAL_CRC_Calculate()</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL DAC</strong> update
+<ul>
+<li>Update to check on DAC_CHANNEL2_SUPPORT instead of device part number</li>
+</ul></li>
+<li><strong>HAL DMA</strong> update
+<ul>
+<li>Add clean of callbacks in HAL_DMA_DeInit() API</li>
+<li>Update HAL_DMA_Abort() API to
+<ul>
+<li>Be able to return HAL_ERROR when DMA is already busy</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL RTC</strong> update
+<ul>
+<li>HAL/LL drivers optimization
+<ul>
+<li>HAL driver: remove unused variables to fix CodeSonar warnings</li>
+<li>LL driver: getter APIs optimization</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL GPIO</strong> update
+<ul>
+<li>HAL_GPIO_TogglePin() API implementation update: to improve robustness</li>
+<li>HAL_GPIO_DeInit() API update to ensure clear all GPIO EXTI pending interrupts.</li>
+</ul></li>
+<li><strong>HAL CEC</strong> update
+<ul>
+<li>update CEC states definition</li>
+</ul></li>
+<li><strong>HAL COMP</strong> update
+<ul>
+<li>Add HAL_COMP_GetError() API to return the COMP error code</li>
+</ul></li>
+<li><strong>HAL I2C</strong> update
+<ul>
+<li>I2C API changes for MISRA-C 2012 compliance:
+<ul>
+<li>Rename HAL_I2C_Master_Sequential_Transmit_IT() to HAL_I2C_Master_Seq_Transmit_IT()</li>
+<li>Rename HAL_I2C_Master_Sequentiel_Receive_IT() to HAL_I2C_Master_Seq_Receive_IT()</li>
+<li>Rename HAL_I2C_Slave_Sequentiel_Transmit_IT() to HAL_I2C_Slave_Seq_Transmit_IT()</li>
+<li>Rename HAL_I2C_Slave_Sequentiel_Receive_DMA() to HAL_I2C_Slave_Seq_Receive_DMA()</li>
+</ul></li>
+<li>Add support of I2C repeated start feature in DMA Mode With the following new APIs
+<ul>
+<li>HAL_I2C_Master_Seq_Transmit_DMA()</li>
+<li>HAL_I2C_Master_Seq_Receive_DMA()</li>
+<li>HAL_I2C_Slave_Seq_Transmit_DMA()</li>
+<li>HAL_I2C_Slave_Seq_Receive_DMA()</li>
+</ul></li>
+<li>Add new I2C transfer options to easy manage the sequential transfers
+<ul>
+<li>I2C_OTHER_FRAME</li>
+<li>I2C_OTHER_AND_LAST_FRAME</li>
+</ul></li>
+<li>Fix I2C send break issue in IT processes
+<ul>
+<li>Add additional check on hi2c->hdmatx and hi2c->hdmarx to avoid the DMA request enable when ITmode is used.</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SPI</strong> update
+<ul>
+<li>General update to enhance robustness for HAL SPI driver</li>
+</ul></li>
+<li><strong>HAL I2S</strong> update
+<ul>
+<li>General update to enhance robustness for HAL I2S driver</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> update
+<ul>
+<li>General update to enhance robustness for HAL SMBUS driver</li>
+</ul></li>
+<li><strong>HAL TIM</strong> update
+<ul>
+<li>Move the following TIM structures from stm32f0xx_hal_tim_ex.h into stm32f0xx_hal_tim.h
+<ul>
+<li>TIM_MasterConfigTypeDef()</li>
+<li>TIM_BreakDeadTimeConfigTypeDef()</li>
+</ul></li>
+<li>TIM API changes for MISRA-C 2012 compliance:
+<ul>
+<li>Rename HAL_TIM_SlaveConfigSynchronization to HAL_TIM_SlaveConfigSynchro</li>
+<li>Rename HAL_TIM_SlaveConfigSynchronization_IT to HAL_TIM_SlaveConfigSynchro_IT</li>
+<li>Rename HAL_TIMEx_ConfigCommutationEvent to HAL_TIMEx_ConfigCommutEvent</li>
+<li>Rename HAL_TIMEx_ConfigCommutationEvent_IT to HAL_TIMEx_ConfigCommutEvent_IT</li>
+<li>Rename HAL_TIMEx_ConfigCommutationEvent_DMA to HAL_TIMEx_ConfigCommutEvent_DMA</li>
+<li>Rename HAL_TIMEx_CommutationCallback to HAL_TIMEx_CommutCallback</li>
+</ul></li>
+<li>Add a call to HAL_DMA_Abort_IT from HAL_TIM_XXX_Stop_DMA</li>
+</ul></li>
+<li><strong>HAL TSC</strong> update
+<ul>
+<li>HAL_TSC_IODischarge() API: update choice parameter to be on FunctionalState instead of uint32_t.</li>
+<li>Add new field ErrorCode in TSC_HandleTypeDef structure</li>
+<li>HAL_TSC_Init() API add new assert_param() on ChannelIOs, ShieldIOs and SamplingIOs fields.</li>
+</ul></li>
+<li><strong>HAL UART</strong> update
+<ul>
+<li>Update to manage UART LIN and UART wakeUp features in stm32f0xx_hal_uart.c/.h instead of stm32f0_hal_uart_ex.c/.h</li>
+<li>General update to enhance robustness for HAL UART driver</li>
+<li>Major Update to improve performance in polling/interrupt mode to reach max frequency:
+<ul>
+<li>Polling mode :
+<ul>
+<li>Use API data pointer instead of UART handle data pointer.</li>
+</ul></li>
+<li>Interrupt mode
+<ul>
+<li>Minimize access on UART registers.</li>
+<li>Split the UART modes into dedicated static functions to minimize checking statements under HAL_IRQHandler():
+<ul>
+<li>8 bit/ 16 bits data formats</li>
+</ul></li>
+</ul></li>
+<li>All modes:
+<ul>
+<li>Update Timeout management to check on global process.</li>
+<li>Update Error code management in all processes.</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL USART</strong> update
+<ul>
+<li>General update to enhance robustness for HAL USART driver</li>
+<li>Major Update to improve performance in polling/interrupt mode to reach max frequency:
+<ul>
+<li>Polling mode :
+<ul>
+<li>Use API data pointer instead of USART handle data pointer.</li>
+<li>Update HAL USART Transmit/Receive processes to support Word Length 9 Bits with/No parity transfer</li>
+</ul></li>
+<li>Interrupt mode
+<ul>
+<li>Minimize access on USART registers.</li>
+<li>Split the USART modes into dedicated static functions to minimize checking statements under HAL_IRQHandler():
+<ul>
+<li>8 bit/ 16 bits data formats</li>
+</ul></li>
+</ul></li>
+<li>All modes:
+<ul>
+<li>Update Timeout management to check on global process.</li>
+<li>Update Error code management in all processes.</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong> update
+<ul>
+<li>General update to enhance robustness for HAL SMARTCARD driver</li>
+<li>Major Update to improve performance in polling/interrupt mode to reach max frequency:
+<ul>
+<li>Polling mode :
+<ul>
+<li>Use API data pointer instead of SMARTCARD handle data pointer.</li>
+<li>Update HAL SMARTCARD Transmit/Receive processes to support Word Length 9 Bits with/No parity transfer</li>
+</ul></li>
+<li>Interrupt mode
+<ul>
+<li>Minimize access on SMARTCARD registers.</li>
+<li>Split the SMARTCARD modes into dedicated static functions to minimize checking statements under HAL_IRQHandler():
+<ul>
+<li>8 bit/ 16 bits data formats</li>
+</ul></li>
+</ul></li>
+<li>All modes:
+<ul>
+<li>Update Timeout management to check on global process.</li>
+<li>Update Error code management in all processes.</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL IrDA</strong> update
+<ul>
+<li>General update to enhance robustness for HAL IrDA driver</li>
+<li>Update HAL IrDA Transmit/Receive processes to support Word Length 9 Bits with/No parity transfer</li>
+<li>Remove unused IRDA_ControlTypeDef() enumeration</li>
+</ul></li>
+<li><strong>LL/HAL RCC</strong> update
+<ul>
+<li>Add new LL/HAL macros
+<ul>
+<li>LL_RCC_PLL_SetMainSource() allowing to configure PLL main clock source</li>
+<li>__HAL_RCC_GET_RTC_SOURCE() allowing to get the RTC clock source</li>
+</ul></li>
+<li>Update HAL_RCC_ClockConfig() API to:
+<ul>
+<li>update to use __HAL_FLASH_GET_LATENCY() flash macro instead of using direct register access to LATENCY bits in FLASH ACR register.</li>
+</ul></li>
+<li>Update HAL_RCC_DeInit() and LL_RCC_DeInit() APIs to
+<ul>
+<li>Add checks for HSI and PLL ready before modifying RCC CFGR registers</li>
+<li>Clear all interrupt falgs</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL/LL USB</strong> update
+<ul>
+<li>Add stm32f0xx_ll_usb.c/h driver</li>
+<li>cleanup reference to low speed in device mode</li>
+<li>Software Quality improvement with a fix of CodeSonar warning on PCD_Port_IRQHandler() interrupt handlers</li>
+<li>Remove wrongly coded PCD_GET6_DB_DIR macro</li>
+<li>Improve software quality to be MISRA-C 2012 and CodeSonar compliant</li>
+<li>STM32F0 Fix USB Exti Wakeup signal by removing non used macro</li>
+<li>Ensure 16bits access to USB PMA</li>
+<li>Make sure to set correct count for receive fifo</li>
+<li>Rework USB BCD driver and fix required timing to initiate primary and secondary detection</li>
+<li>Prevent clearing CTR_RX and CTR_TX flags when setting the EP type</li>
+<li>Add error check during USB init</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_7_2" aria-hidden="true"> <label for="collapse-section1_7_2" aria-hidden="true"><strong>V1.7.2 / 09-May-2019</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Maintenance release to fix known defects and enhancements implementation</li>
+<li><strong>HAL Drivers changes</strong></li>
+<li><strong>HAL PCD</strong> update
+<ul>
+<li>Update Memory-mapped peripheral registers definition to be volatile to avoid unwanted optimization with GCC compiler.</li>
+</ul></li>
+<li><strong>LL TIM</strong> Update
+<ul>
+<li>Update Memory-mapped peripheral registers definition to be volatile to avoid unwanted optimization with GCC compiler.</li>
+</ul></li>
+<li><strong>LL DAC</strong> Update
+<ul>
+<li>Update Memory-mapped peripheral registers definition to be volatile to avoid unwanted optimization with GCC compiler.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_7_1" aria-hidden="true"> <label for="collapse-section1_7_1" aria-hidden="true"><strong>V1.7.1 / 02-April-2019</strong></label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
+<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
+<li><strong>The following changes done on the HAL drivers require an update on the application code based on older HAL versions</strong>
+<ul>
+<li><strong>Rework of HAL CAN driver (compatibility break)</strong>
+<ul>
+<li>A new HAL CAN driver has been redesigned with new APIs, to bypass limitations on CAN Tx/Rx FIFO management present with previous HAL CAN driver version.</li>
+<li>The new HAL CAN driver is the recommended version. It is located as usual in Drivers/STM32F0xx_HAL_Driver/Src and Drivers/STM32f0xx_HAL_Driver/Inc folders. It can be enabled through switch HAL_CAN_MODULE_ENABLED in stm32f0xx_hal_conf.h</li>
+<li>The legacy HAL CAN driver is also present in the release in Drivers/STM32F0xx_HAL_Driver/Src/Legacy and Drivers/STM32F0xx_HAL_Driver/Inc/Legacy folders for software compatibility reasons. Its usage is not recommended as deprecated. It can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in stm32f0xx_hal_conf.h</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL Drivers changes</strong></li>
+<li><strong>HAL CAN</strong> update
+<ul>
+<li>Fields of CAN_InitTypeDef structure are reworked:
+<ul>
+<li>SJW to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to TransmitFifoPriority</li>
+</ul></li>
+<li>HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() APIs</li>
+<li>HAL_CAN_Transmit() is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.</li>
+<li>HAL_CAN_Transmit_IT() is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then HAL_CAN_AddTxMessage() for place Tx request.</li>
+<li>HAL_CAN_Receive() is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until reception, then HAL_CAN_GetRxMessage() to get Rx message.</li>
+<li>HAL_CAN_Receive_IT() is replaced by HAL_CAN_ActivateNotification() to enable receive IT, then HAL_CAN_GetRxMessage() in the receive callback to get Rx message</li>
+<li>HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()</li>
+<li>HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), HAL_CAN_TxMailbox1CompleteCallback() and HAL_CAN_TxMailbox2CompleteCallback().</li>
+<li>HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and HAL_CAN_RxFifo1MsgPendingCallback().</li>
+<li>More complete “How to use the new driver” is detailed in the driver header section itself.</li>
+</ul></li>
+<li><strong>HAL FLASH</strong> update
+<ul>
+<li>Update the FLASH_OB_GetRDP() API to return the correct RDP level</li>
+</ul></li>
+<li><strong>HAL PCD</strong> update
+<ul>
+<li>PCD_SET_EPTYPE() macro update to prevent clearing USB_EP_CTR_TX and USB_EP_CTR_RX flags.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_7_0" aria-hidden="true"> <label for="collapse-section1_7_0" aria-hidden="true"><strong>V1.7.0 / 25-August-2017</strong></label>
+<div>
+<h2 id="main-changes-3">Main Changes</h2>
+<ul>
+<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
+<li><strong>Generic drivers changes</strong></li>
+<li>MISRA C 2004 rule 11.4 (A cast should not be performed between a pointer to object type and a different pointer to object type).</li>
+<li>MISRA C 2004 rule 12.4 (The right-hand operand of a logical or I I operator shall not contain side effects).</li>
+<li>Minor improvement of Doxygen Tags for CHM UM generation.</li>
+<li><strong>HAL Drivers changes</strong></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Add definition of GPIO_AF0_TIM3 for STM32F030x6 and STM32F030x8 devices.</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Editorial modification : astyle clean-up</li>
+</ul></li>
+<li><strong>HAL PCD</strong>
+<ul>
+<li>Remove lock/unlock from USB receive and transmit endpoints.</li>
+</ul></li>
+<li><strong>LL Drivers changes</strong></li>
+<li><strong>LL_TIM</strong>
+<ul>
+<li>Ensure write operation of BKE and BKP bits is effective by adding fake read operation to garantee 1 APB clock cycle before function exit.</li>
+<li>Exchange behavior between LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent().</li>
+</ul></li>
+<li><strong>LL_RCC</strong>
+<ul>
+<li>Fix issue in RCC_GetSystemClockFreq() when HSI48 oscillator is selected as system clock.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_6_0" aria-hidden="true"> <label for="collapse-section1_6_0" aria-hidden="true"><strong>V1.6.0 / 07-April-2017</strong></label>
+<div>
+<h2 id="main-changes-4">Main Changes</h2>
+<ul>
+<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
+<li><strong>HAL Drivers changes</strong></li>
+<li><strong>HAL Generic</strong>
+<ul>
+<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type).</li>
+<li>Remove useless cast (uint32_t ) cast in case of U suffix.</li>
+<li>Fix Code Sonar warnings (useless assignment, cast alters value, empty while statement).</li>
+</ul></li>
+<li><strong>HAL</strong>
+<ul>
+<li>Modify HAL_Delay to guarantee the minimum Delay provided as parameter.</li>
+<li>Add definition of USE_SPI_CRC to activate CRC feature inside HAL SPI driver.</li>
+<li>New API : HAL_GetUID() read the unique device identifier.</li>
+<li>Correct RTC_ASYNCH_PREDIV and RTC_SYNCH_PREDIV definition when LSI configured as RTC clock source.</li>
+</ul></li>
+<li><strong>HAL CAN</strong>
+<ul>
+<li>Add transmission abort when timeout is reached in HAL_CAN_Transmit().</li>
+<li>Add management of overrun error.</li>
+<li>Store missing FIFO number in received message.</li>
+<li>Extend SET_BIT, CLEAR_BIT macro usage.</li>
+<li>Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.</li>
+<li>Fix message lost issue with specific sequence of transmit requests.</li>
+</ul></li>
+<li><strong>HAL ADC</strong>
+<ul>
+<li>DMA transfer must be disabled during calibration to avoid ADC calibration factor insertion among ADC conversion data.</li>
+<li>Remove unused literal ADC_EOC_SINGLE_SEQ_CONV.</li>
+</ul></li>
+<li><strong>HAL COMP</strong>
+<ul>
+<li>Rename LL_COMP_DELAY_STARTUP_US in COMP_DELAY_STARTUP_US.</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Replace hard coded values by CMSIS define.</li>
+<li>Extend SET_BIT, CLEAR_BIT macro usage.</li>
+<li>Add timeout management in HAL_SPI_Abort() and HAL_SPI_Abort_IT().</li>
+<li>Add IS_SPI_DMA_HANDLE macro to check handle validity.</li>
+<li>Add IS_SPI_16BIT_ALIGNED_ADDRESS macro to check if data buffer address are 16 bits aligned when transferring more than 1 byte (there is no support for unaligned accesses on the Cortex-M0 processor).</li>
+<li>In 2 lines transmission configuration, ensure RXFIFO is empty at the end of transmission. Add SPI_WaitFifoStateUntilTimeout (SPI_FLAG_FRLVL) call.</li>
+</ul></li>
+<li><strong>HAL RTC</strong>
+<ul>
+<li>add a wait for synchronization on HAL_RTC_Init function to avoid re-entering in initialization state before previous exit of initialization state.</li>
+</ul></li>
+<li><strong>HAL TIM</strong>
+<ul>
+<li>New API to disable unconditionally the Main Output Enable of a timer instance : __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY().
+<ul>
+<li>DMA burst mode enhancement. Add 2 new API in order to manage serape parameters for burst length and data length:
+<ul>
+<li>HAL_TIM_DMABurst_MultiWriteStart()</li>
+<li>HAL_TIM_DMABurst_MultiReadStart()</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li>Add new feature “ZONE READ/WRITE” : The ZONE_READ and ZONE_WRITE protocols are used to simultaneously read from or write to some or all of the devices on a bus. New options defined (SMBUS_OTHER_FRAME_NO_PEC, SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC, SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC).</li>
+<li>New API : Digital/Analog filter configuration with HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter().</li>
+</ul></li>
+<li><strong>HAL PCD</strong>
+<ul>
+<li>Modify PCD_ReadPMA() to avoid HardFault when buffers not aligned on 16 bits address.</li>
+</ul></li>
+<li><strong>LL Drivers changes</strong></li>
+<li><strong>LL Generic</strong>
+<ul>
+<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type).</li>
+<li>MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).</li>
+<li>Remove useless cast (uint32_t ) cast in case of U suffix.</li>
+<li>Replace hard coded POSITION definition in driver by the associated PPP_xxx_pos CMSIS define (PPP could be I2C, USART …).</li>
+</ul></li>
+<li><strong>LL GPIO</strong>
+<ul>
+<li>Rename GPIO_AFRH and GPIO_AFRL bit fields for alignment with all STM32 series.</li>
+</ul></li>
+<li><strong>LL DMA</strong>
+<ul>
+<li>For better performances, use WRITE_REQ() and READ_REG() when accessing CPAR and CMAR registers.</li>
+<li>Replace SET_BIT by WRITE_REG macro to clear flags in DMA_ICFR register (register is write only).</li>
+</ul></li>
+<li><strong>LL USART</strong>
+<ul>
+<li>Add IS_LL_USART_BRR macro : In case of oversampling by 16 and 8, Baud Rate Register content must be greater than or equal to 16.</li>
+</ul></li>
+<li><strong>LL I2C</strong></li>
+<li>OA1EN bit of OAR1 register should be set only when own address different from 0 (0 reserved for General Call address).</li>
+<li><strong>LL CRS</strong>
+<ul>
+<li>Add missing shift of HSI48CalibrationValue parameter value in LL_CRS_ConfigSynchronization().</li>
+</ul></li>
+<li><strong>LL RTC</strong>
+<ul>
+<li>For better performances, simplify implementation of LL_RTC_TIME_Get() and LL_RTC_DATE_Get().</li>
+</ul></li>
+<li><strong>LL USART</strong>
+<ul>
+<li>Add ((void)(temp)) to Prevent unused argument(s) compilation warning when USE_FULL_ASSERT not defined.</li>
+</ul></li>
+<li><strong>LL_TIM</strong>
+<ul>
+<li>New API : In order to program BDTR register in a single write operation add :
+<ul>
+<li>LL_TIM_BDTR_StructInit(), LL_TIM_BDTR_Init().</li>
+<li>LL_TIM_BDTR_InitTypeDef structure definition with associated macro : IS_LL_TIM_OSSR_STATE, IS_LL_TIM_OSSI_STATE, IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE.</li>
+</ul></li>
+<li>Add initialization of AutomaticOuput field in LL_TIM_BDTR_StructInit().</li>
+</ul></li>
+<li><strong>LL UTILS</strong>
+<ul>
+<li>Use current AHB prescaler valuer instead of the one selected by the user to calculate SYSCLK frequency.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_5_0" aria-hidden="true"> <label for="collapse-section1_5_0" aria-hidden="true"><strong>V1.5.0 / 04-November-2016</strong></label>
+<div>
+<h2 id="main-changes-5">Main Changes</h2>
+<ul>
+<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
+<li><strong>HAL Drivers changes</strong></li>
+<li>Enhance HAL delay and time base implementation:
+<ul>
+<li>Add new templates stm32f0xx_hal_timebase_rtc_alarm_template.c, stm32f0xx_hal_timebase_rtc_wakeup_template.c and stm32f0xx_hal_timebase_tim_template.c which can be used to override the native HAL time base functions (defined as weak) to use either RTC or Timer as time base tick source. For more details about the usage of these drivers, please refer to HAL_TimeBase examples and FreeRTOS-based applications</li>
+</ul></li>
+<li><strong>The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0</strong></li>
+<li>HAL IWDG driver: Overall driver rework for better implementation
+<ul>
+<li>Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs</li>
+</ul></li>
+<li>HAL WWDG driver: Overall driver rework for better implementation
+<ul>
+<li>Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs</li>
+<li>Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter) function and API by removing the counter parameter</li>
+</ul></li>
+<li>HAL CEC driver: Overall driver rework with compatibility break versus previous HAL version
+<ul>
+<li>Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</li>
+<li>Remove HAL CEC receive interrupt process function HAL_CEC_Receive_IT() and enable the “receive” mode during the Init phase</li>
+<li>Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()</li>
+<li>Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</li>
+<li>Remove the InitiatorAddress field from the CEC_InitTypeDef structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function</li>
+<li>Add new parameter RxFrameSize in HAL_CEC_RxCpltCallback() function</li>
+<li>Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</li>
+</ul></li>
+<li>HAL TIM driver : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure</li>
+<li><strong>HAL Generic</strong>
+<ul>
+<li>Update HAL Driver compliancy with:
+<ul>
+<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type)</li>
+<li>MISRA C 2004 rule 14.8 (the statement forming the body of a switch, while, do … while, or for statement shall be a compound statement)</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL IWDG</strong>
+<ul>
+<li>New simplified HAL IWDG driver: remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs</li>
+<li>API functions are:
+<ul>
+<li>HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter</li>
+<li>HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter</li>
+</ul></li>
+<li>Refer to the following example to identify the changes : IWDG_Reset, IWDG_WidowMode</li>
+</ul></li>
+<li><strong>HAL WWDG</strong>
+<ul>
+<li>New simplified HAL WWDG driver: remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs
+<ul>
+<li>Update HAL_WWDG_Refresh() API to remove counter parameter</li>
+<li>New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt</li>
+<li>API functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(), HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()</li>
+</ul></li>
+<li>Refer to the following example to identify the changes: WWDG_Example</li>
+</ul></li>
+<li><strong>HAL CEC</strong>
+<ul>
+<li>Overall driver rework with break of compatibility with HAL V1.4.0
+<ul>
+<li>Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</li>
+<li>Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the “Receive” mode enable within the Init phase</li>
+<li>Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function</li>
+<li>Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</li>
+<li>Remove the InitiatorAddress field from the CEC_InitTypeDef structure and manage it as a parameter in the HAL_CEC_Transmit_IT() function</li>
+<li>Add new parameter RxFrameSize in HAL_CEC_RxCpltCallback() function</li>
+<li>Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</li>
+</ul></li>
+<li>Update driver to implement the new CEC state machine:
+<ul>
+<li>Add new rxState field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations</li>
+<li>Rename state field in CEC_HandleTypeDef structure to gstate: CEC state information related to global Handle management and Tx Operations</li>
+<li>Update CEC process to manage the new CEC states.</li>
+<li>Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL UART/USART/IRDA/SMARTCARD</strong>
+<ul>
+<li>IRQ Handler global optimization</li>
+<li>New abort API: HAL_PPP_Abort(), HAL_PPP_Abort_IT()</li>
+<li>Add error management in case of DMA transfer through HAL_DMA_Abort_IT() and DMA XferAbortCallback()</li>
+<li>Polling management update:
+<ul>
+<li>The user Timeout value must be estimated for the overall process duration</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency
+<ul>
+<li>Polling mode:
+<ul>
+<li>Replace the use of SPI_WaitOnFlagUnitTimeout() function by “if” statement to check on RXNE/TXE flage while transferring data</li>
+</ul></li>
+<li>Interrupt mode:</li>
+<li>Minimize access on SPI registers</li>
+<li>All modes:
+<ul>
+<li>Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</li>
+<li>Update timeout management to check on global processes</li>
+<li>Update error code management in all processes</li>
+</ul></li>
+</ul></li>
+<li>Fix regression in polling mode:
+<ul>
+<li>Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()</li>
+</ul></li>
+<li>Fix regression in interrupt mode:
+<ul>
+<li>Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()</li>
+<li>Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()</li>
+</ul></li>
+<li>Prevent data packing mode in reception for STM32F030x6, STM32F030x8, STM32F031x6, STM32F038xx, STM32F051x8 and STM32F058xx</li>
+</ul></li>
+<li><strong>HAL DMA</strong>
+<ul>
+<li>Global driver code optimization to reduce memory footprint</li>
+<li>Add new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to register/unregister the different callbacks identified by the enum typedef HAL_DMA_CallbackIDTypeDef</li>
+<li>Add new Error Code HAL_DMA_ERROR_NOT_SUPPORTED</li>
+<li>Remove DMA HAL_DMA_STATE_READY_HALF & HAL_DMA_STATE_ERROR states in HAL_DMA_StateTypeDef</li>
+</ul></li>
+<li><strong>HAL RTC</strong>
+<ul>
+<li>Interrupt flag cleared before enabling the interrupt in HAL_RTCEx_SetWakeUpTimer_IT()</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Disable I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init()</li>
+<li>Move I2C_NO_OPTION_FRAME in private section</li>
+<li>Use CMSIS bit for compilation switch instead of product switch</li>
+<li>Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)</li>
+<li>Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer</li>
+<li>On slave, reset LISTEN_TX state in case of direction change</li>
+<li>Remove GCC warnings</li>
+</ul></li>
+<li><strong>HAL TIM</strong>
+<ul>
+<li>API update : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure in order to set ARPE bit from TIMx_CR1 register</li>
+<li>New API : add 2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and __HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit from TIMx_CCMR1, TIMx_CCMR2 and TIMx_CCMR3 registers</li>
+<li>Update TIM_SET_CAPTUREPOLARITY and TIM_RESET_CAPTUREPOLARITY definition to take into account CC4NP bit</li>
+<li>Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li>Update SMBUS_Master_ISR() and SMBUS_Slave_ISR() to ensure storage of last receive data</li>
+</ul></li>
+<li><strong>HAL PCD</strong>
+<ul>
+<li>Update HAL_PCD_ActivateRemoteWakeup() and HAL_PCD_DeActivateRemoteWakeup() APIs to add condition if LPM activated.</li>
+</ul></li>
+<li><strong>LL Drivers changes</strong></li>
+<li><strong>LL GPIO</strong>
+<ul>
+<li>Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F0xx serie)</li>
+</ul></li>
+<li><strong>LL_TIM</strong>
+<ul>
+<li>Remove TIM_SMCR_OCCS compilation switch (useless for STM32F0xx serie)</li>
+</ul></li>
+<li><strong>LL_CRS</strong>
+<ul>
+<li>Update CRS_POSITION_XXX definitions to use CMSIS definition instead of hardcoded values</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_4_0" aria-hidden="true"> <label for="collapse-section1_4_0" aria-hidden="true"><strong>V1.4.0 / 27-May-2016</strong></label>
+<div>
+<h2 id="main-changes-6">Main Changes</h2>
+<ul>
+<li><strong>First official release supporting the Low Level drivers for the STM32F0xx family:</strong>
+<ul>
+<li>Low Layer drivers APIs provide register level programming:</li>
+<li>they require deep knowledge of peripherals described in STM32F0xx Reference Manual.</li>
+<li>Low Layer drivers are available for ADC, COMP, Cortex, CRC, CRS, DAC, DMA, EXTI, GPIO, I2C, IWDG, PWR,</li>
+<li>RCC, RTC, SPI, TIM, USART and WWDG peripherals and additional Low Level Bus, System and Utilities APIs.</li>
+<li>Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f0xx_ll_ppp.h files for PPP peripherals,</li>
+<li>there is no configuration file and each stm32f0xx_ll_ppp.h file must be included in user code.</li>
+</ul></li>
+<li><strong>Maintenance release to fix known defects and enhancements implementation.</strong></li>
+<li><strong>HAL generic</strong>
+<ul>
+<li>Updated HAL Driver compliancy with MISRA C 2004 rules:
+<ul>
+<li>MISRA C 2004 rule 5.2 (tmpreg variable shall not be used inside MACRO)</li>
+<li>MISRA C 2004 rule 10.3 (illegal explicit conversion from type unsigned int to uint16_t).</li>
+<li>MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</li>
+<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type).</li>
+<li>MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).</li>
+<li>MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators).</li>
+<li>MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</li>
+<li>MISRA C 2004 rule 14.3 (a null statement shall only occur on a line by itself).</li>
+<li>MISRA C 2004 rule 14.9 (if {expression} / else construct shall be followed by a compound statement).</li>
+<li>MISRA C 2004 rule 15.3 (all switch statements shall contain a final default clause).</li>
+<li>MISRA C 2004 rule 16.3 (identifiers shall be given for all of the parameters in a function prototype declaration).</li>
+<li>MISRA C 2004 rule 16.4 (identifiers used in the declaration and definition shall be identical).</li>
+<li>MISRA C 2004 rule 19.10 (in function-like macro definition, each instance of a parameter shall be enclosed in parenthesis).</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL</strong>
+<ul>
+<li>Changed uwTick to global to allow overwrite of HAL_IncTick().</li>
+</ul></li>
+<li><strong>HAL COMP</strong>
+<ul>
+<li>Added delay in COMP startup time required to reach propagation delay specification.</li>
+</ul></li>
+<li><strong>HAL CRC</strong>
+<ul>
+<li>Updated devices supporting Programmable Polynomial features: defines and functions prototypes are available only for</li>
+<li>STM32F071xB, STM32F072xB, STM32F078xx, STM32F091xC, STM32F098x devices.</li>
+<li>Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).</li>
+</ul></li>
+<li><strong>HAL DMA</strong>
+<ul>
+<li>Added __HAL_DMA_GET_COUNTER() macro returning the number of remaining data units in the current DMA Channel transfer.</li>
+<li>Provided new function HAL_DMA_Abort_IT() to abort current DMA transfer under interrupt mode without polling for DMA enable bit.</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Updated IS_GPIO_PIN() macro to cover full u32 bits.</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Used macro definition for I2C instances supporting Wakeup from Stop mode.</li>
+<li>Updated polling flags management within I2C slave DMA drivers.</li>
+<li>Added support of repeated start feature in case of multimaster mode (allow master to keep I2C communication with slave).</li>
+<li>Updated WaitOnFlag management (timeout measurement should be always cumulative).</li>
+<li>Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).</li>
+<li>Reworked DMA end process and I2C error management during DMA transfer.</li>
+</ul></li>
+<li><strong>HAL PWR</strong>
+<ul>
+<li>Aligned EWUPx pins and PWR functions with CMSIS definitions.</li>
+</ul></li>
+<li><strong>HAL IRDA</strong>
+<ul>
+<li>Modified IRDA_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</li>
+<li>Modified EIE bit setting in Tx and Rx transfers (Interrupt mode).</li>
+<li>Updated IRDA_SetConfig() function following UART Baudrate calculation update.</li>
+<li>Reviewed IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ.</li>
+<li>Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.</li>
+</ul></li>
+<li><strong>HAL RCC</strong>
+<ul>
+<li>Performed optimizations for HAL_RCC_ClockConfig(), HAL_RCCEx_PeriphCLKConfig functions.</li>
+<li>Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).</li>
+<li>Updated HAL_RCC_OscConfig() function to enable PWR only if necessary for LSE configuration.</li>
+<li>Corrected CRS interrupt sources.</li>
+<li>Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.</li>
+<li>Added missing HAL IRQHandler and callbacks API for CRS management.</li>
+<li>Added missing RCC_CFGR_PLLNODIV definition for STM32F030x4/6 devices.</li>
+<li>Removed HSI48State from structure RCC_OscInitTypeDef when device does not support HSI48.</li>
+<li>Removed RCC_HSI48_OFF.</li>
+<li>Removed flag RCC_FLAG_RMV which is write only.</li>
+<li>Modified AHBPrescTable and APBPrescTable in HAL.</li>
+<li>Renamed RCC_CRS_SYNCWARM to RCC_CRS_SYNCWARN.</li>
+<li>Renamed RCC_CRS_TRIMOV to RCC_CRS_TRIMOVF.</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Updated HAL_SPI_TransmitReceive() function in slave mode to receive correctly the CRC when NSS pulse activated.</li>
+<li>Added missing __IO in SPI_HandleTypeDef definition.</li>
+<li>Updated IS_SPI_CRC_POLYNOMIAL macro definition as polynomial value should be odd only.</li>
+<li>Updated SPI_2linesTxISR_8BIT() and SPI_2linesTxISR_16BIT() functions: added return so that SPI_2linesTxISR_8BITCRC() or SPI_2linesTxISR_16BITCRC() function is called from HAL_SPI_TransmitReceive_IT() when CRC is activated.</li>
+</ul></li>
+<li><strong>HAL TIM</strong>
+<ul>
+<li>Used IS_TIM_HALL_INTERFACE_INSTANCE macro instead of IS_TIM_XOR_INSTANCE macro in</li>
+<li>HAL_TIMEx_HallSensor_xxx() functions.</li>
+<li>Updated HAL_TIM_ConfigOCrefClear() function to allow TIM_CLEARINPUTSOURCE_OCREFCLR as new ClearInputSource.</li>
+</ul></li>
+<li><strong>HAL UART-USART</strong>
+<ul>
+<li>Updated UART Baudrate calculation (UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros).</li>
+<li>Updated USART_SetConfig() function following UART Baudrate calculation update.</li>
+<li>Aligned UART-USART Stop Bits with others STM32 series.</li>
+<li>Renamed IS_UART_WAKEUP_INSTANCE to IS_UART_WAKEUP_FROMSTOP_INSTANCE.</li>
+<li>Modified UART_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</li>
+<li>Reviewed UART state machine to avoid cases where UART state is overwritten by UART IRQ.</li>
+<li>Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.</li>
+</ul></li>
+<li><strong>HAL USB</strong>
+<ul>
+<li>Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.</li>
+<li>Added missing USB_CNTR_SOFM when setting wInterrupt_Mask global variable used in HAL_PCD_Init.</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong>
+<ul>
+<li>Aligned SMARTCARD Stop Bits with others STM32 series.</li>
+<li>Modified SMARTCARD_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</li>
+<li>Updated SMARTCARD_SetConfig() function following UART Baudrate calculation update.</li>
+<li>Reviewed SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_3_1" aria-hidden="true"> <label for="collapse-section1_3_1" aria-hidden="true"><strong>V1.3.1 / 29-January-2016</strong></label>
+<div>
+<h2 id="main-changes-7">Main Changes</h2>
+<ul>
+<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
+<li><strong>HAL Generic</strong>
+<ul>
+<li>Updated HAL Driver compliancy with:
+<ul>
+<li>MISRA C 2004 rule 10.6 (U suffix applied to all constants of unsigned type).</li>
+<li>MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</li>
+<li>MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</li>
+</ul></li>
+<li>Updated HAL weak empty callbacks to prevent unused argument compilation warnings.</li>
+<li>Updated stm32f3xx_hal_msp.c files:
+<ul>
+<li>Removed reference to MicroXplorer.</li>
+</ul></li>
+<li>Updated stm32f3xx_hal_conf.h files:
+<ul>
+<li>Set HSE_STARTUP_TIMEOUT value to 100ms instead of 5000ms</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL ADC</strong>
+<ul>
+<li>Corrected ADC_CHANNEL_VREFINT enabling in the CCR register.</li>
+<li>Corrected assert param of nb of discontinuous conversions when discontinuous mode is enabled.</li>
+<li>Removed Flag EOS in HAL_ADC_GetValue().</li>
+</ul></li>
+<li><strong>HAL CAN</strong>
+<ul>
+<li>Corrected missing __HAL_UNLOCK when all Mailboxes are busy.</li>
+<li>Added ERRI bit clear besides to clearing LEC bits in CAN_ESR register, in case of Error interrupt.</li>
+</ul></li>
+<li><strong>HAL CORTEX</strong>
+<ul>
+<li>Removed __HAL_CORTEX_SYSTICKCLK_CONFIG macro, replaced by HAL_SYSTICK_CLKSourceConfig() function.</li>
+</ul></li>
+<li><strong>HAL CRC</strong>
+<ul>
+<li>Updated CRC HAL_CRC_Calculate() and HAL_CRC_Accumulate() comments, handling input data pointers that are not * uint32_t.</li>
+</ul></li>
+<li><strong>HAL FLASH</strong>
+<ul>
+<li>Added FLASH API HAL_FLASHEx_OBGetUserData() to get the value saved in User data option byte.</li>
+<li>Aligned Return value of HAL_FLASH_EndOfOperationCallback function (0xFFFFFFF) when process is finished.</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Updated GPIO Output Speed literals naming to ensure HAL full compatibility.</li>
+<li>Added GPIOD support for STM32070x6 devices.</li>
+<li>Modified ADC poll for event to return timeout instead of error.</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Corrected wrong management of AF after NACK.</li>
+<li>Aligned I2C driver with new state machine definition.</li>
+<li>Corrected interrupt disabling in I2C_SlaveReceive_ISR() function.</li>
+<li>Modified HAL_I2C_Master_Transmit to handle sending data of size 0.</li>
+<li>Renamed I2C_CR1_DFN to I2C_CR1_DNF.</li>
+</ul></li>
+<li><strong>HAL PCD</strong>
+<ul>
+<li>Updated call to Double Buffering Counter Function.</li>
+</ul></li>
+<li><strong>HAL PWR</strong>
+<ul>
+<li>Added do { } while(0) in __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() multi statement macro.</li>
+</ul></li>
+<li><strong>HAL RCC</strong>
+<ul>
+<li>Performed optimizations for HAL_RCC_ClockConfig() function.</li>
+<li>Corrected inversion in LSE drive capability Bit definition.</li>
+<li>Performed optimizations for internal oscillators and PLL startup time.</li>
+<li>Added GPIOD support for STM32070x6 devices.</li>
+<li>Removed GPIOE support for STM32F030xC devices.</li>
+<li>Add RCC_USBCLKSOURCE_NONE when HSI48 is not present.</li>
+<li>Corrected definition for flag RCC_FLAG_V18PWRRST.</li>
+<li>Added missing macro __HAL_RCC_LSEDRIVE_CONFIG.</li>
+<li>Aligned naming of macros related to CRS_CFGR register.</li>
+<li>Corrected __HAL_RCC_CRS_CLEAR_IT()/__HAL_RCC_CRS_CLEAR_FLAG() macros.</li>
+<li>Removed Bit PLLNODIV for STM32F030x6 devices.</li>
+<li>Review implementation to automatically enable backup domain.</li>
+<li>Added RCC_IT_HSI48RDY definition.</li>
+<li>Renamed __HAL_RCC_MCO_CONFIG() to __HAL_RCC_MCO1_CONFIG().</li>
+</ul></li>
+<li><strong>HAL RTC</strong>
+<ul>
+<li>Aligned different HAL_RTC_XXIRQHandler() implementations.</li>
+<li>Check the behavior of flag WUTWF and corrected update of wakeup counter registers.</li>
+<li>Added subsecond fration formula in HAL_RTC_GetTime() function.</li>
+<li>Updated Bits mask literals used in macros definition.</li>
+</ul></li>
+<li><strong>HAL TIM</strong>
+<ul>
+<li>Corrected __HAL_TIM_SET_PRESCALER timer prescaler definition.</li>
+<li>Protected SMCR register of possible overwrite in HAL_TIM_ConfigOCrefClear().</li>
+<li>Corrected assert checks in HAL_TIM_ConfigClockSource().</li>
+</ul></li>
+<li><strong>HAL TSC</strong>
+<ul>
+<li>Updated IO default state management.</li>
+</ul></li>
+<li><strong>HAL UART-USART</strong>
+<ul>
+<li>Corrected behavior of HAL_UART_IRQ_Handler() (removed enabling/disabling of ERR IT source).</li>
+<li>Corrected UART_FLAG_SBKF definition.</li>
+<li>Corrected values used for max allowed baudrates constant definitions.</li>
+<li>Removed USART_CR2_LINEN/USART_CR3_IREN/USART_CR3_SCEN/USART_CR1_UESM bits definitions for STM32F030x6, STM32F030x8, STM32F070xB, STM32F070x6, STM32F030xC.</li>
+</ul></li>
+<li><strong>HAL WWDG</strong>
+<ul>
+<li>Aligned WWDG registers Bits naming between all families.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_3_0" aria-hidden="true"> <label for="collapse-section1_3_0" aria-hidden="true"><strong>V1.3.0 / 26-June-2015</strong></label>
+<div>
+<h2 id="main-changes-8">Main Changes</h2>
+<ul>
+<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
+<li><strong>Complete HAL API alignment (macro/function renaming)</strong></li>
+<li><strong>HAL Generic</strong>
+<ul>
+<li>Update HAL drivers to be MISRA/C++ compliant.</li>
+<li>Initialized handle lock in HAL_PPP_Init().</li>
+<li>Add SYSCFG define macros to manage FM+ on GPIOs.</li>
+<li>Use uint32_t instead of uint8_t/uint_16.</li>
+</ul></li>
+<li><strong>HAL ADC</strong>
+<ul>
+<li>Update ADC state machine. Missing state in function HAL_ADCEx_Calibration_Start().</li>
+<li>Align ADC_SOFTWARE_START literal on STM32L0xx.</li>
+<li>HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.</li>
+<li>HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.</li>
+<li>ADC_ConversionStop(): correct wrong timeout value.</li>
+<li>HAL_ADC_AnalogWDGConfig(): Add missing assert param.</li>
+<li>Remove channel for monitoring VBAT power supply pin on F0 Value line devices.</li>
+<li>Move sampling time setting into ADC init stucture (keep setting into ADC channel init stucture with comments of obsolete setting).</li>
+<li>Move __HAL_UNLOCK() before peripheral activation because if an interruption occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be executed while HAL still locked.</li>
+<li>ADC_DMAConvCplt(): Add call to ADC error callback in case of error.</li>
+<li>Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).</li>
+<li>Simplify __HAL_ADC_GET_IT_SOURCE().</li>
+<li>Add use of POSITION_VAL.</li>
+<li>Add optimization of ADC stabilization delays.</li>
+</ul></li>
+<li><strong>HAL CAN</strong>
+<ul>
+<li>Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().</li>
+<li>Unlock the CAN process when communication error occurred.</li>
+<li>Replace uint32_t Data[8] by uint8_t Data[8] in structures CanTxMsgTypeDef and CanRxMsgTypeDef.</li>
+</ul></li>
+<li><strong>HAL CEC</strong>
+<ul>
+<li>Add new API HAL_CEC_GetReceivedFrameSize() to get size of received frame</li>
+<li>HAL CORTEX</li>
+<li>Add new macro IS_NVIC_DEVICE_IRQ() to check on negative values of IRQn parameter</li>
+</ul></li>
+<li><strong>HAL CRC</strong>
+<ul>
+<li>Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().</li>
+<li>Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).</li>
+</ul></li>
+<li><strong>HAL DAC</strong>
+<ul>
+<li>HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and DAC_FLAG_DMAUDR2.</li>
+</ul></li>
+<li><strong>HAL DMA</strong>
+<ul>
+<li>Correct __HAL_DMA_GET_IT_SOURCE brief comments.</li>
+</ul></li>
+<li>**HAL FLASH*
+<ul>
+<li>FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).</li>
+<li>FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).</li>
+<li>Add missing macro __HAL_FLASH_GET_LATENCY.</li>
+<li>Disable WRP not compliant with other family.</li>
+<li>Add FLASH_BANK1_END defines.</li>
+<li>Remove WRP defines for few defines under devices swicthes.</li>
+<li>Add switch to handle option bits BOOT_SEL & nBOOT1 not present on STM32F030xC & STM32F070x6.</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.</li>
+</ul></li>
+<li><strong>HAL I2S</strong>
+<ul>
+<li>HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.</li>
+</ul></li>
+<li><strong>HAL IRDA</strong>
+<ul>
+<li>HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.</li>
+</ul></li>
+<li><strong>HAL PWR</strong>
+<ul>
+<li>Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.</li>
+<li>Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.</li>
+</ul></li>
+<li><strong>HAL RCC</strong>
+<ul>
+<li>Implement workaround to cover RCC limitation regarding Peripheral enable delay.</li>
+<li>HAL_RCC_OscConfig(): correct test on LSEState.</li>
+<li>Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.</li>
+<li>Add defines for RCC_System_Clock_Source_Status.</li>
+<li>Follow specific procedure to enable HSE.</li>
+<li>Add macros to get the enable or disable status of peripheral clock.</li>
+<li>HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.</li>
+<li>Add interface HAL_RCCEx_GetPeriphCLKFreq.</li>
+</ul></li>
+<li><strong>HAL RTC</strong>
+<ul>
+<li>Add missing RTC_FLAG_INIT in flag list.</li>
+<li>HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).</li>
+<li>Remove RTC_FLAG_INIT as currently unused.</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong>
+<ul>
+<li>Add missing IDLE flag management.</li>
+<li>Align SMARTCARD_Last_Bit defines.</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().</li>
+<li>In that case only RX callback are used and the call of TX callback can close the communication before the end of the RX processing.</li>
+<li>SPI_2linesRxISR_8BIT(): correct issue on RX 2lines with DataSize8bit, even buffer size and CRC 8bit (SPI_RXFIFO_THRESHOLD is not set).</li>
+<li>Fit bit update add BSY flag check for all the process.</li>
+<li>Add __IO (volatile) to the State member of the SPI_HandleTypeDef struct. to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().</li>
+</ul></li>
+<li><strong>HAL TIM</strong>
+<ul>
+<li>Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.</li>
+</ul></li>
+<li><strong>HAL UART</strong>
+<ul>
+<li>Add macro to control CTS and RTS from the customer applications.</li>
+<li>UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.</li>
+<li>Change DMA TX management to remove WaitOnFlag in ISR.</li>
+<li>Add DMA circular mode support for the communication peripherals.</li>
+<li>Add UART NVIC configuration in the HAL_UART_MspInit().</li>
+<li>Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.</li>
+<li>Modify UART DMA implementation issue (missed clear the TC bit in the SR).</li>
+<li>Add a OVR flag clear prior resuming DMA RX transfer.</li>
+<li>HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).</li>
+<li>HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.</li>
+<li>HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.</li>
+</ul></li>
+<li><strong>HAL USART</strong>
+<ul>
+<li>HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().</li>
+<li>Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.</li>
+<li>HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).</li>
+<li>HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.</li>
+<li>HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).</li>
+<li>HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true"><strong>V1.2.1 / 09-January-2015</strong></label>
+<div>
+<h2 id="main-changes-9">Main Changes</h2>
+<ul>
+<li><strong>HAL</strong>
+<ul>
+<li>stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 & channel2 for STM32F070xB only</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>stm32f0xx_hal_gpio_ex.h: add I2C1 as possible GPIO alternate function 3 for STM32F070xB</li>
+</ul></li>
+<li><strong>HAL RCC</strong>
+<ul>
+<li>stm32f0xx_hal_rcc_ex.h: add missing USART2_CLK_ENABLE/DISABLE() macros for STM32F070x6</li>
+</ul></li>
+<li><strong>HAL RTC</strong>
+<ul>
+<li>stm32f0xx_hal_rtc_ex.h/.c: Enable RTC periodic Wakeup timer feature on STM32F070xB & STM32F030xC</li>
+<li>stm32f0xx_hal_rtc_ex.c: remove HAL_RTCEx_Tamper3EventCallback() API for STM32F070xB & STM32F030xC, since there is no TAMPER3 on those products.</li>
+</ul></li>
+<li><strong>HAL UART</strong>
+<ul>
+<li>stm32f0xx_hal_uart_ex.c/.h: add HAL_RS485Ex_Init() API for STM32F0xx Value Line devices</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true"><strong>V1.2.0 / 05-December-2014</strong></label>
+<div>
+<h2 id="main-changes-10">Main Changes</h2>
+<ul>
+<li><strong>HAL generic</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>HandleTypeDef.ErrorCode must be typed uint32_t</li>
+<li>Update HAL drivers to ensure compliancy w/ C++</li>
+<li>Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h</li>
+<li>Case mismatch between #include typo and effective file name generating compiler errors under Linux</li>
+<li>Correct various issues for documentation generation (group name, doxygen tags, etc..)</li>
+<li>Missing support of I2C_PAx_FMP of F04xx devices</li>
+</ul></li>
+<li><strong>HAL ADC</strong>
+<ul>
+<li>Improve HAL ADC comments</li>
+<li>Correct issue observed with ADC start simultaneous commands</li>
+<li>Remove macro __HAL_ADC_OFR_CHANNEL() since OFRx register is not available on F0 devices.</li>
+</ul></li>
+<li><strong>HAL CAN</strong>
+<ul>
+<li><strong>ErrorCode</strong> field is now declared as __IO uint32 instead of <strong>enum HAL_CAN_ErrorTypeDef</strong> to fix C++ compilation issue</li>
+</ul></li>
+<li><strong>HAL CEC</strong>
+<ul>
+<li>change <strong>ErrorCode</strong> field declaration from uint32_t to __IO uint32_t</li>
+<li>correct CEC state: Ready to Receive state lost upon Transmission end</li>
+</ul></li>
+<li><strong>HAL COMP</strong>
+<ul>
+<li>State field is now declared as uint32_t instead of <strong>enum HAL_COMP_StateTypeDef</strong> to fix C++ compilation issue</li>
+<li>change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t to fix C++ compilation issue</li>
+</ul></li>
+<li><strong>HAL CRC</strong>
+<ul>
+<li>Wrong <span class="citation" data-cites="ref">@ref</span> in CRCLength field description for documentation generation</li>
+<li>Add support of new STM32F0 value line devices STM32F070xB/x6 and STM32F030xC.</li>
+</ul></li>
+<li><strong>HAL DAC</strong>
+<ul>
+<li>HAL_DAC_Stop_DMA() code clean up</li>
+<li>Use of internal macro MODIFY_REG() to update CR register</li>
+</ul></li>
+<li><strong>HAL DMA</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>DMA channel remap register renamed for compatibility with other STM32 devices.</li>
+<li>Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description</li>
+</ul></li>
+<li><strong>HAL FLASH</strong>
+<ul>
+<li>Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected</li>
+<li><strong>ErrorCode</strong> field is now declared as uint32 instead of <strong>enum FLASH_ErrorTypeDef</strong> to fix C++ compilation issue</li>
+<li>change HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t to fix C++ compilation issue</li>
+<li>Clean the error context to FLASH_ERROR_NONE before starting new Flash operation</li>
+<li>Put all the clear flags in the FLASH_SetSerrorCode()</li>
+<li>Stop the programming procedure in case of error detected in HAL_FLASH_Program()</li>
+<li>Check error before doing new procedure in HAL_FLASH_IRQhandler()</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>correct Typo in How to use this driver section & update comments</li>
+<li>Add assert on GPIO PIN in HAL_GPIO_DeInit()</li>
+<li>Add assert on GPIO AF instance to protect HAL_GPIO_Init() from impossible AF configuration</li>
+<li>Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()</li>
+<li>Reset Interrupt mode registers only in HAL_GPIO_DeInit()</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>ErrorCode field is now declared as uint32 instead of <strong>enum HAL_I2C_ErrorTypeDef</strong> to fix C++ compilation issue</li>
+</ul></li>
+<li><strong>HAL I2S</strong>
+<ul>
+<li><strong>ErrorCode</strong> field is now declared as uint32 instead of <strong>enum HAL_I2S_ErrorTypeDef</strong> to fix C++ compilation issue.</li>
+<li>Change <strong>HAL_I2S_GetError()</strong> type declaration from HAL_I2S_ErrorTypeDef to uint32_t to fix C++ compilation issue.</li>
+<li>Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to fix Unused variable warning w/ TrueSTUDIO.</li>
+<li>Typo in I2S HAL driver macros list section of stm32f0xx_hal_i2s.c</li>
+<li>Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)</li>
+</ul></li>
+<li><strong>HAL IRDA</strong>
+<ul>
+<li><strong>ErrorCode</strong> field is now declared as uint32 instead of <strong>enum HAL_IRDA_ErrorTypeDef</strong> to fix C++ compilation issue</li>
+<li>Missing doxygen tags for IRDA_HandleTypeDef fields description</li>
+</ul></li>
+<li><strong>HAL PWR</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>Add new API to manage SLEEPONEXIT and SEVONPEND bits of SCR register:
+<ul>
+<li>HAL_PWR_DisableSleepOnExit()</li>
+<li>HAL_PWR_EnableSleepOnExit()</li>
+<li>HAL_PWR_EnableSEVOnPend()</li>
+<li>HAL_PWR_DisableSEVOnPend()</li>
+</ul></li>
+<li>Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode()</li>
+</ul></li>
+<li><strong>HAL RCC</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>Add a comment in the How to use this driver section to mention the Peripheral enable delay</li>
+<li>Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to stm32f0xx_hal_rcc_ex.h since this feature is not supported on all F0 devices</li>
+<li>Change <strong>HAL_RCCEx_CRSWaitSynchronization()</strong> type declaration from RCC_CRSStatusTypeDef to uint32_t to fix C++ compilation issue</li>
+</ul></li>
+<li><strong>HAL RTC</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>Enhance <span class="citation" data-cites="note">@note</span> describing the use of HAL RTC APIs</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong>
+<ul>
+<li><strong>ErrorCode</strong> field is now declared as uint32 instead of <strong>enum HAL_SMARTCARD_ErrorTypeDef</strong> to fix C++ compilation issue</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li><strong>ErrorCode & PreviousState</strong> fields are now declared as uint32 instead of <strong>enum HAL_SMBUS_ErrorTypeDef</strong> & <strong>HAL_SMBUS_StateTypeDef</strong> to fix C++ compilation issue</li>
+<li>Change <strong>HAL_SMBUS_GetState()</strong> type declaration from HAL_SMBUS_StateTypeDef to uint32_t to fix C++ compilation issue</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li><strong>ErrorCode</strong> field is now declared as uint32 instead of <strong>enum HAL_SPI_ErrorTypeDef</strong> to fix C++ compilation issue</li>
+<li>Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to fix Unused variable warning w/ TrueSTUDIO.</li>
+<li>Add DMA circular mode support on SPI HAL driver.</li>
+<li>Internal fucntion renaming: HAL_SPI_DMATransmitCplt(), HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() & HAL_SPI_DMAError() renamed respectively into SPI_DMATransmitCplt(), SPI_DMAReceiveCplt(), SPI_DMATransmitReceiveCplt() & SPI_DMAError().</li>
+<li>Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype</li>
+<li>uint32_t driver alignment for compatibility with other STM32 devices</li>
+<li>Add new <strong>API HAL_SPI_GetError()</strong>, which was missing on STM32F0xx family</li>
+</ul></li>
+<li><strong>HAL UART/USART</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong> and <strong>STM32F030xC</strong>.</li>
+<li>structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.</li>
+<li><strong>ErrorCode</strong> field is now declared as uint32 instead of <strong>enum HAL_U(S)ART_ErrorTypeDef</strong> to fix C++ compilation issue</li>
+<li>unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h</li>
+<li>Add missing API HAL_StatusTypeDef <strong>HAL_LIN_SendBreak()</strong></li>
+<li>correct wrong USART_IT_CM value</li>
+<li>correct issue with Lin mode data length</li>
+<li>Add new value for Stop bit definition: UART_STOPBITS_1_5</li>
+</ul></li>
+<li><strong>HAL USB</strong>
+<ul>
+<li>Add support of new STM32F0 value line devices <strong>STM32F070xB/x6</strong>.</li>
+<li>Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description</li>
+<li>Correct _HAL_PCD_CLEAR_FLAG() macros definition</li>
+</ul></li>
+<li><strong>HAL WWDG</strong>
+<ul>
+<li>Add new macro to manage WWDG IT & correction:
+<ul>
+<li>__HAL_WWDG_DISABLE_IT()</li>
+<li>__HAL_WWDG_GET_IT()</li>
+<li>__HAL_WWDG_GET_IT_SOURCE()</li>
+</ul></li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true"><strong>V1.1.0 / 03-October-2014</strong></label>
+<div>
+<h2 id="main-changes-11">Main Changes</h2>
+<ul>
+<li><strong>HAL generic</strong>
+<ul>
+<li>general improvement of Doxygen Tags for CHM UM generation</li>
+<li>Add support of new devices <strong>STM32F091xC, STM32F098xx</strong> in STM32F0xx HAL drivers</li>
+<li>minor corrections for Pdf/Chm UM generation</li>
+<li>Correction for MISRA</li>
+<li>[F098xx] Remove PVD IT line wrapper</li>
+<li>FLAG&IT assert macros to be removed</li>
+<li>Bad macro name in stm32F0xx_hal.c/.h files</li>
+<li>uint32_t Alignement in HAL driver</li>
+</ul></li>
+<li><strong>HAL</strong> update (for STM32F091xC/STM32F098xx)
+<ul>
+<li>Add new define for HAL IRDA Enveloppe source Selection</li>
+<li>Add new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()</li>
+<li>Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)</li>
+<li>Add new macro __HAL_GET_PENDING_IT()</li>
+<li>Add new macro __HAL_SYSCFG_IRDA_ENV_SELECTION()</li>
+<li>Add new macro __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()</li>
+</ul></li>
+<li><strong>HAL COMP</strong>
+<ul>
+<li>Missing assert param IS_COMP_TRIGGERMODE</li>
+</ul></li>
+<li><strong>HAL Cortex</strong>
+<ul>
+<li>remove Macro not supported by cortex-M0 in stm32f0xx.h</li>
+</ul></li>
+<li><strong>HAL DMA</strong>
+<ul>
+<li>Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)</li>
+<li>Add new defines for DMAx channels remap bit field definition</li>
+<li>Add new macros: IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()</li>
+<li>Add new macro: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index</li>
+<li>Add new macro: __HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index</li>
+<li>Add new macro: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index</li>
+<li>Add new macro: __HAL_DMA_GET_FLAG()</li>
+<li>Add new macro: __HAL_DMA_CLEAR_FLAG()</li>
+<li>Add new macro: __HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()</li>
+<li>Bit definition name error for HAL_DMA1_CH2 remap on STM32F091xC</li>
+<li>HAL_DMA_PollForTransfer updated</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>BSRR regsiter should not be split in BSRRH/BSRRL</li>
+<li>rework GPIO_GET_SOURCE</li>
+<li>Add new defines for AF functions selection</li>
+</ul></li>
+<li><strong>HAL I2S</strong>
+<ul>
+<li>Supp ClockSource in Init</li>
+</ul></li>
+<li><strong>HAL IRDA</strong>
+<ul>
+<li>Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro</li>
+</ul></li>
+<li><strong>HAL IWDG</strong>
+<ul>
+<li>Use WRITE_REG instead of SET_BIT</li>
+</ul></li>
+<li><strong>HAL PWR</strong>
+<ul>
+<li>Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx</li>
+<li>PVD feature need falling/rising Event modes
+<ul>
+<li>Update defines name PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING to PWR_<strong>PVD</strong>_MODE_<strong>NORMAL</strong>/PWR_<strong>PVD</strong>_MODE_IT_RISING/PWR_<strong>PVD</strong>_MODE_IT_FALLING/PWR_<strong>PVD</strong>_MODE_IT_RISING_FALLING</li>
+<li>Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING</li>
+<li>Update macro IS_PWR_PVD_MODE()</li>
+<li>change macro name: __HAL_<strong>PWR</strong>_PVD_EXTI_ENABLE_IT(), __HAL_<strong>PWR</strong>_PVD_EXTI_DISABLE_IT(), __HAL_<strong>PWR</strong>_PVD_EXTI_GENERATE_SWIT(), __HAL_<strong>PWR</strong>_PVD_EXTI_GET_FLAG(), __HAL_<strong>PWR</strong>_PVD_EXTI_CLEAR_FLAG()</li>
+<li>Add new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(), __HAL_PWR_PVD_EXTI_DISABLE_EVENT(), __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(), __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL RCC</strong>
+<ul>
+<li>Defect correction:
+<ul>
+<li>HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode</li>
+<li>STM32F091xC/STM32F098xx
+<ul>
+<li>New structure RCC_PeriphCLKInitTypeDef</li>
+<li>Add defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1, RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC, RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3</li>
+<li>Add macro IS_RCC_PERIPHCLK()</li>
+<li>Add defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1, RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE, CC_USART3CLKSOURCE_HSI</li>
+<li>Add macro IS_RCC_USART3CLKSOURCE()</li>
+<li>Add macro __HAL_RCC_GET_USART3_SOURCE()</li>
+<li>Add macro __HAL_RCC_USART3_CONFIG()</li>
+<li>add clock enable macros for new UART: __USART5_CLK_ENABLE, __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE</li>
+<li>add clock disable macros for new UART: __USART5_CLK_DISABLE, __USART6_CLK_DISABLE, __USART7_CLK_DISABLE, __USART8_CLK_DISABLE</li>
+<li>add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET</li>
+<li>add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_RELEASE_RESET, __USART7_RELEASE_RESET, __USART8_RELEASE_RESET</li>
+</ul></li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong>
+<ul>
+<li>change SMARTCARD_AdvFeatureConfig() from exported to static private function</li>
+<li>STM32F091xC/STM32F098xx:
+<ul>
+<li>Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li>change SMARTCARD_AdvFeatureConfig() from exported to static private function</li>
+</ul></li>
+<li><strong>HAL SPI</strong>
+<ul>
+<li>Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC</li>
+<li>Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready</li>
+</ul></li>
+<li><strong>HAL TIM</strong>
+<ul>
+<li>Missed/Unused assert param to be added/removed</li>
+<li>Trigger interrupt should be activated when working with a slave mode</li>
+<li>Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT</li>
+<li>Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4</li>
+<li>missing assert in HAL_TIMEx_ConfigBreakDeadTime</li>
+<li>Add URS_ENABLE/ URS_DISABLE macros</li>
+</ul></li>
+<li><strong>HAL UART/USART</strong>
+<ul>
+<li>Change UART TX-IT implementation to remove WaitOnFlag in ISR</li>
+<li>STM32F091xC/STM32F098xx:
+<ul>
+<li>Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</li>
+<li>Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL USB</strong>
+<ul>
+<li>Bad IN/OUT EndPoint parameter array size</li>
+</ul></li>
+<li><strong>HAL WWDG</strong>
+<ul>
+<li>improvements from other families</li>
+</ul></li>
+</ul>
+<table>
+<thead>
+<tr class="header">
+<th style="text-align: left;">Driver</th>
+<th style="text-align: center;">Defect Correction</th>
</tr>
-<tr style="">
-<td style="padding: 1.5pt;">
-<h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release
-Notes for STM32F0xx HAL Drivers</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright
-2016 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;"><img id="_x0000_i1026" src="_htmresc/st_logo.png" border="0" height="65" width="86"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-family: "Arial","sans-serif"; display: none;"><o:p> </o:p></span></p>
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
+</thead>
<tbody>
-<tr style="">
-<td style="padding: 0in;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.2
-/ 09-May-2019</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Main changes</span></u></b></p><ul style="color: black;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Maintenance release to fix known defects and
-enhancements implementation</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> <span style="font-weight: bold;"><span style="text-decoration: underline;"></span></span></span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">HAL Drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: black;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; color: black; font-family: "Times New Roman",serif; font-size: 12pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD<span> </span></span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Memory-mapped peripheral registers definition </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to be volatile </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to avoid unwanted optimization with </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">GCC compiler.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL TIM </span>Update</span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Memory-mapped peripheral registers definition </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to be volatile </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to avoid unwanted optimization with </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">GCC compiler.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;">LL DAC </span>Update</span><span style="font-family: Verdana; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Memory-mapped peripheral registers definition </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to be volatile </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to avoid unwanted optimization with </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">GCC compiler.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.1
-/ 02-April-2019</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Main changes</span></u></b></p><ul style="color: black;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
-enhancements implementation<span style="text-decoration: underline;"></span></span></span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on older HAL versions</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">Rework of HAL CAN driver (compatibility break) </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">A
-new HAL CAN driver has been redesigned with new APIs, to bypass
-limitations on CAN Tx/Rx FIFO management present with previous HAL CAN
-driver version.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The
-new HAL CAN driver is the recommended version. It is located as usual
-in Drivers/STM32F0xx_HAL_Driver/Src and
-Drivers/STM32f0xx_HAL_Driver/Inc folders. It can be enabled through
-switch HAL_CAN_MODULE_ENABLED in stm32f0xx_hal_conf.h</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The
-legacy HAL CAN driver is also present in the release in
-Drivers/STM32F0xx_HAL_Driver/Src/Legacy and
-Drivers/STM32F0xx_HAL_Driver/Inc/Legacy folders for software
-compatibility reasons. Its usage is not recommended as
-deprecated. It can however be enabled through switch
-HAL_CAN_LEGACY_MODULE_ENABLED in stm32f0xx_hal_conf.h</span></li></ul></ul></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">HAL Drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: black;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fields of CAN_InitTypeDef structure are reworked:</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">SJW
-to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to
-TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to
-AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to
-TransmitFifoPriority</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Transmit()
-is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then
-HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Transmit_IT()
-is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then
-HAL_CAN_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">AddTxMessage</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">() for place Tx request.</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Receive()
-is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until
-reception, then HAL_CAN_GetRxMessage() <br>to get Rx message.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Receive_IT()
-is replaced by HAL_CAN_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">ActivateNotification</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">() </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">to enable receive IT, then
-HAL_CAN</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">_GetRxMessage()<br></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"> in the receivecallback to get Rx message</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxMailbox1CompleteCallback() and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxMailbox2CompleteCallback().</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_RxFifo1MsgPendingCallback().</span></li></ul><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">More complete "How to use the new driver" is detailed in the driver header section itself.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the FLASH_OB_GetRDP() API to return the correct RDP level</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">PCD_SET_EPTYPE() macro update to prevent clearing USB_EP_CTR_TX and </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">USB_EP_CTR_RX flags.</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.0
-/ 25-August-2017</span></h3><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Main changes</span></u></b></p><ul style="color: black;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
-enhancements implementation<span style="text-decoration: underline;"></span></span></span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;"></span></u></b></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">Generic drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: black;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">MISRA C 2004 rule 11.4 (A cast should not be performed between a pointer to object type and a different pointer to object type).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">MISRA C 2004 rule 12.4 (The right-hand operand of a logical or I I operator shall not <br>contain side effects).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">Minor </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">improvement of
- Doxygen Tags for CHM UM generation</span><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">.</span></li></ul><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"></p><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">HAL Drivers changes</span></u></b></p><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: black;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-style: normal; font-variant: normal; font-weight: normal; font-size: 13.33px; line-height: normal; font-size-adjust: none; font-stretch: normal; text-align: left; text-transform: none; text-indent: 0px; letter-spacing: normal; word-spacing: 0px; float: none; display: inline ! important; white-space: normal; widows: 1;">Add definition of GPIO_AF0_TIM3 for STM32F030x6 and STM32F030x8 devices.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Editorial modification : astyle clean-up</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL
- PCD </span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove lock/unlock from USB receive and transmit endpoints.</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"><br></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm; color: black;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_TIM</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Ensure
-write operation of BKE and BKP bits is effective by adding fake read
-operation to garantee 1 APB clock cycle before function exit.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Exchange behavior between LL_TIM_EnableUpdateEvent() and LL_TIM_DisableUpdateEvent().</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_RCC</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix issue in RCC_GetSystemClockFreq() when HSI48 oscillator is selected as system clock.<span style="font-family: monospace;"></span></span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.6.0
-/ 07-April-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
-enhancements implementation</span></span></li></ul><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span><br><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b><br></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL Generic</span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Remove uselesss cast (uint32_t ) cast in case of 'U' suffix.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Fix Code Sonar warnings (useless assignment, cast alters value, empty while statement).</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Modify HAL_Delay to guarantee the minimum Delay provided as parameter.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add definition of USE_SPI_CRC to activate CRC feature inside HAL SPI driver.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">New API : HAL_GetUID() read the unique device identifier.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Correct RTC_ASYNCH_PREDIV and RTC_SYNCH_PREDIV definition when LSI configured as RTC clock source.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">CAN</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add transmission abort when timeout is reached in HAL_CAN_Transmit().</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add managment of overrun error. </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Store missing FIFO number in received message.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Extend SET_BIT, CLEAR_BIT macro usage.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Allow possibility to receive messages from the 2 RX FIFOs in parallel via interrupt.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Fix message lost issue with specific sequence of transmit requests.</span> </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">ADC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DMA transfer must be disabled during calibration to avoid ADC calibration factor insertion among ADC conversion data.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove unused literal ADC_EOC_SINGLE_SEQ_CONV.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">COMP</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename LL_COMP_DELAY_STARTUP_US in </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">COMP_DELAY_STARTUP_US</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SPI</span></b><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"></span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li><ul style="margin-bottom: 0in; color: black;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Replace hard coded values by CMSIS define.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Extend SET_BIT, CLEAR_BIT macro usage.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add timeout managment in HAL_SPI_Abort() and HAL_SPI_Abort_IT().</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add IS_SPI_DMA_HANDLE macro to check handle validity.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
-IS_SPI_16BIT_ALIGNED_ADDRESS macro to check if data buffer
-address are 16 bits aligned when transferring more than 1 byte (there
-is no support for unaligned accesses on the Cortex-M0 processor).</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In 2
-lines transmission configuration, ensure RXFIFO is empty at
-the end of transmission. Add SPI_WaitFifoStateUntilTimeout
-(SPI_FLAG_FRLVL) call.</span></li></ul></ul><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: black;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RTC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">add
-a wait for synchronisation on HAL_RTC_Init function to avoid
-re-entering in initialisation state before previous exit of
-initialisation state.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span></span></li></ul><ul style="margin-bottom: 0in; font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm; color: black;" type="square"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New API to disable </span><span style="font-size: 10pt; font-family: Verdana;">unconditionally the </span><span style="font-size: 10pt; font-family: Verdana;">Main Output Enable of a timer instance : __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY().</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">DMA burst mode enhancement. Add 2 new API in order to manage separe parameters for burst length and data length:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HAL_TIM_DMABurst_MultiWriteStart()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">HAL_TIM_DMABurst_MultiReadStart()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SMBUS</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add new feature "ZONE READ/WRITE" : The ZONE_READ and ZONE_WRITE protocols are
-used to simultaneously read from or write to some or all of the devices
-on a bus. New options defined (SMBUS_OTHER_FRAME_NO_PEC,
-SMBUS_OTHER_FRAME_WITH_PEC, SMBUS_OTHER_AND_LAST_FRAME_NO_PEC,
-SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC).</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New API : Digital/Analog filter configuration with HAL_SMBUS_ConfigAnalogFilter() and HAL_SMBUS_ConfigDigitalFilter().<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL
- PCD </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Modify PCD_ReadPMA() to avoid HardFault when buffers not aligned on 16 bits address.</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span><br style="color: black;">
-<span style="font-size: 10pt; font-family: Verdana; color: black;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; color: black;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL Generic</span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Remove uselesss cast (uint32_t ) cast in case of 'U' suffix.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Replace hard coded POSITION definition in driver by the associated PPP_xxx_pos CMSIS define (PPP could be I2C, USART ...).</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL GPIO</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_AFRH and GPIO_AFRL bitfields for alignment with all STM32 series.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL DMA</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">For better performances, use WRITE_REQ() and READ_REG() when accessing CPAR and CMAR registers.</span></li></ul><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Replace SET_BIT by WRITE_REG macro to clear flags in DMA_ICFR register (register is write only).</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL USART</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
-IS_LL_USART_BRR macro : In case of oversampling by 16 and 8, Baud
-Rate Register content must be greater than or equal to 16.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL I2C</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">OA1EN bit of OAR1 register should be set only when own address different from 0 (0 reserved for General Call address).</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL CRS</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add missing shift of HSI48CalibrationValue parameter value in LL_CRS_ConfigSynchronization().</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL RTC</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">For better performances, simplify implementation of LL_RTC_TIME_Get() and LL_RTC_DATE_Get().</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL USART</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add ((void)(temp)) to Prevent unused argument(s) compilation warning when USE_FULL_ASSERT not defined.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_TIM</span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">New API : In order to program BDTR register in a single write operation add :</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_BDTR_StructInit(), LL_TIM_BDTR_Init().</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"> </span><span style="font-size: 10pt; font-family: Verdana;">LL_TIM_BDTR_InitTypeDef strcuture definition with associated macro </span><span style="font-size: 10pt; font-family: Verdana;">: IS_LL_TIM_OSSR_STATE,
-IS_LL_TIM_OSSI_STATE,
-IS_LL_TIM_LOCK_LEVEL, IS_LL_TIM_BREAK_STATE, IS_LL_TIM_BREAK_POLARITY, IS_LL_TIM_AUTOMATIC_OUTPUT_STATE.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add initialization of AutomaticOuput field in LL_TIM_BDTR_StructInit().</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL UTILS</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana; color: black;">Use current AHB prescaler valuer instead of the one selected by the user to calculate SYSCLK frequency.</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0
-/ 04-November-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
-enhancements implementation</span></span></li></ul><span style="font-size: 8pt; font-family: "Arial","sans-serif"; color: blue;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">HAL Drivers changes</span></u></b></p><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Enhance HAL delay and time base implementation</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">:</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
-new templates
-stm32f0xx_hal_timebase_rtc_alarm_template.c, stm32f0xx_hal_timebase_rtc_wakeup_template.c
-and stm32f0xx_hal_timebase_tim_template.c which can be used to override
-the native
-HAL time base functions (defined as weak) to use either RTC or
-Timer as time
-base tick source. For more details about the usage of these drivers,
-please refer to HAL\HAL_TimeBase examples </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">and FreeRTOS-based applications</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black; font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.0</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL IWDG</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space"> </span></span>driver: Overall driver rework for better implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_Start(),<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_MspInit() and<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_GetState() </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">APIs</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL WWDG</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space"> </span></span>driver: Overall driver rework for better implementation</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL_WWDG_Start(),<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_WWDG_Start_IT(),</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span class="Apple-converted-space"> </span>HAL_WWDG_MspDeInit() and<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_WWDG_GetState() APIs </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update the </span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US">HAL_WWDG_Refresh</span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US">(WWDG_HandleTypeDef *hwwdg, uint32_t counter) function and API by removing the "counter" parameter</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">HAL CEC </span>driver:<span class="Apple-converted-space"> </span> Overall driver rework with compatibility break versus previous HAL version</span><br><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove
-HAL CEC receive interrupt process function HAL_CEC_Receive_IT()
-and enable the "receive" mode during the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()<br></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
-field from the CEC_InitTypeDef structure and manage
-it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span></li></ul></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">HAL TIM driver </span>: add </span><span style="font-size: 10pt; font-family: Verdana;">one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure</span><br><br></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Update HAL Driver compliancy with:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type)</span></li><li><span style="font-size: 10pt; font-family: Verdana;">MISRA
-C 2004 rule 14.8 (the statement forming the body of a 'switch',
-'while', 'do ... while', or 'for' statement shall be a compound
-statement)<br></span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL IWDG</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL IWDG driver: r</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">emove HAL_IWDG_Start(), HAL_IWDG_MspInit()
-and HAL_IWDG_GetState() APIs</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API functions are: </span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Init(): </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">this function insures the configuration and the start of the IWDG
-counter</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">HAL_IWDG_Refresh(): </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">this function insures the reload of the IWDG counter</span></li></ul></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">Refer to the following example to identify the changes : IWDG_Reset, IWDG_WidowMode</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL WWDG</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New simplified HAL WWDG driver: remove </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit()
-and HAL_WWDG_GetState() APIs</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;"></span><span style="font-size: 11pt; font-family: "Calibri",sans-serif; color: black;">HAL_WWDG_Refresh</span><span style="font-size: 10pt; font-family: Verdana;">() API to remove counter parameter</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New field EWIMode in WWDG_InitTypeDef to specify need for Early Wakeup Interrupt</span></li></ul><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API
-functions are: HAL_WWDG_Init(), HAL_WWDG_MspInit(), HAL_WWDG_Refresh(),
-HAL_WWDG_IRQHandler() and HAL_WWDG_EarlyWakeupCallback()</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the following example to identify the changes: WWDG_Example</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL CEC</span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall driver rework with break of compatibility with HAL V1.4.0<br></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function<br></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
-field from the CEC_InitTypeDef structure and manage
-it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update driver to implement the new CEC state machine:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">"rxState"</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span class="Apple-converted-space"> </span>field in CEC_HandleTypeDef structure to provide the<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to Rx Operations</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to global Handle management and Tx Operations</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update CEC process to manage the new CEC states.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; color: black; font-size: 10pt;" lang="EN-US">Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">UART/USART</span></span><span style="font-size: 10pt; font-family: Verdana;">/</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">IRDA/SMARTCARD</span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="FR">IRQ Handler global optimization </span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="FR">New abort API: HAL_PPP_Abort(), HAL_PPP_Abort_IT() <br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add error management in case of DMA transfer through
- </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">HAL_DMA_Abort_IT() and DMA </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">XferAbortCallback()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="FR"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="FR">Polling management update:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;">The user Timeout value must be estimated for the overall process
-duration</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SPI</span></b><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"></span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Polling mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data</span></li></ul></ul></ul><ul style="margin-bottom: 0in;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> Interrupt mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Minimize access on SPI registers</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">All modes:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update timeout management to check on global processes</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update error code management in all processes</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in polling mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()<o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in interrupt mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Prevent data
-packing mode in reception for STM32F030x6, STM32F030x8,
-STM32F031x6, STM32F038xx, STM32F051x8 and STM32F058xx<br></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA</span></b></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Global
- driver code optimization to reduce memory footprint </span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
- new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to
- register/unregister the different callbacks identified by the enum
- typedef HAL_DMA_CallbackIDTypeDef</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
- new Error Code HAL_DMA_ERROR_NOT_SUPPORTED</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove
- DMA HAL_DMA_STATE_READY_HALF & HAL_DMA_STATE_ERROR states in
- HAL_DMA_StateTypeDef</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL RTC</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Interrupt flag cleared before enabling the interrupt in HAL_RTCEx_SetWakeUpTimer_IT()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL I2C</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Disable I2C_OARx_EN bit before any configuration in OAR1 or 2 in HAL_I2C_Init()</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Move I2C_NO_OPTION_FRAME in private section</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Use CMSIS bit for compilation switch instead of product switch</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update HAL_I2C_Master_Sequential_Transmit_IT() function (wrong state check)</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Add I2C_FIRST_AND_NEXT_FRAME option for I2C Sequential Transfer</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">On slave, reset LISTEN_TX state in case of direction change</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Remove GCC warnings<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL TIM</span></span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">API update : add one field (AutoReloadPreload) in TIM_Base_InitTypeDef structure in order to set ARPE
-bit from TIMx_CR1 register</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">New
-API : add 2 macros (__HAL_TIM_ENABLE_OCxPRELOAD() and
-__HAL_TIM_DISABLE_OCxPRELOAD()) in order to set OCxPE bit
-from TIMx_CCMR1, TIMx_CCMR2 and TIMx_CCMR3 registers</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Update TIM_SET_CAPTUREPOLARITY and TIM_RESET_CAPTUREPOLARITY definition to take into account CC4NP bit</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Use MODIFY_REG macro to avoid wrong initialisation in ConfigBreakDeadTime()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">HAL SMBUS</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">Update SMBUS_Master_ISR() and SMBUS_Slave_ISR() to ensure storage of last receive data</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; font-weight: bold;" lang="EN-US">HAL
- PCD </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
- HAL_PCD_ActivateRemoteWakeup() and HAL_PCD_DeActivateRemoteWakeup() APIs
- to add condition if LPM activated.</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul></ul>
-<span style="font-size: 10pt; font-family: Verdana;"></span><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">LL Drivers changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL GPIO</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove LL_GPIO_SPEED_FREQ_VERY_HIGH (GPIO_SPEED_FREQ_VERY_HIGH does not exist for STM32F0xx serie)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_TIM</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove TIM_SMCR_OCCS compilation switch (useless for STM32F0xx serie)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">LL_CRS</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update CRS_POSITION_XXX definitions </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">to use CMSIS definition instead of hardcoded values</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0
-/ 27-May-2016<o:p></o:p></span></h3><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">First official release supporting the Low Level drivers for the STM32F0xx family:</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Low Layer drivers APIs provide register level programming:</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">they require deep knowledge of peripherals described in STM32F0xx Reference Manual.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Low Layer drivers are available for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"> ADC, COMP, Cortex, CRC, CRS, DAC, DMA, EXTI,
-GPIO, I2C, IWDG, PWR,<br>RCC, RTC, SPI, TIM, USART and WWDG peripherals</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> and additional Low Level Bus, System and Utilities APIs.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f0xx_ll_ppp.h files for PPP peripherals,<br>there is no configuration file and each stm32f0xx_ll_ppp.h file must be included in user code.</span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">Maintenance release to fix known defects and enhancements implementation.</span></span></li></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Updated HAL Driver compliancy with </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rules</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">:</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 5.2 (tmpreg" variable shall not be used inside MACRO)</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.3 (illegal explicit conversion from type "unsigned int" to "uint16_t *).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 11.5 (no cast that removes any const or volatile qualification from the type addressed by a pointer).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 12.6 (logical operators should not be confused with bitwise operators).<br></span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.3 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(a null statement shall only occur on a line by itself).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 14.9 ('if {expression}' / 'else' construct shall be followed by a compound statement).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 15.3 (all switch statements shall contain a final default clause).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 16.3 (identifiers shall be given for all of the parameters in a function prototype declaration).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 16.4 (identifiers used in the declaration and definition shall be identical).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">MISRA C 2004 rule 19.10 (in function-like macro definition, each instance of a parameter shall be enclosed in parenthesis).</span></li></ul></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Changed uwTick to global to allow overwrite of HAL_IncTick().</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL COMP</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added delay in COMP startup time required to reach propagation delay specification</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL CRC</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated devices supporting Programmable Polynomial features: defines and functions prototypes are available only for<br>STM32F071xB, STM32F072xB, STM32F078xx, STM32F091xC, STM32F098x devices.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_CRC_DeInit() function (restored IDR Register to Reset value).<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL DMA</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added __HAL_DMA_GET_COUNTER</span><span style="font-size: 10pt; font-family: Verdana;">() macro returning the number of remaining data units in the current DMA Channel transfer.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Provided
-new function HAL_DMA_Abort_IT() to abort current DMA transfer
-under interrupt mode without polling for DMA enable bit.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL GPIO</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated IS_GPIO_PIN() macro to cover full u32 bits.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL I2C</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Used macro definition for I2C instances supporting Wakeup from Stop mode</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated polling flags management within I2C slave DMA drivers.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added support of repeated start feature in case of multimaster mode (allow master to keep I2C communication with slave).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated WaitOnFlag management (timeout measurement should be always cumulative).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Optimized HAL_I2C_XX_IRQHandler() functions (read status registers only once).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Reworked DMA end process and I2C error management during DMA transfer.<br></span></li></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL PWR</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Aligned EWUPx pins and PWR functions with CMSIS definitions</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL IRDA</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modified IRDA_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Modified EIE bit setting in Tx and Rx transfers (Interrupt mode).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated IRDA_SetConfig() function following UART Baudrate calculation update.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Reviewed IRDA state machine to avoid cases where IRDA state is overwritten by IRDA IRQ.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for HAL_RCC_ClockConfig(), HAL_RCCEx_PeriphCLKConfig functions.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_RCC_OscConfig() function to enable PWR only if necessary for LSE configuration.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Corrected CRS interrupt sources.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added missing HAL IRQHandler and callbacks API for CRS management.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added missing RCC_CFGR_PLLNODIV definition for STM32F030x4/6 devices.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed HSI48State from structure RCC_OscInitTypeDef when device does not support HSI48.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed RCC_HSI48_OFF.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Removed flag RCC_FLAG_RMV which is write only.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Modified AHBPrescTable and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">APBPrescTable in HAL.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">R</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">enamed </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_CRS_SYNCWARM to RCC_CRS_SYNCWARN.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">R</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">enamed </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">RCC_CRS_TRIMOV to RCC_CRS_TRIMOVF.</span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL SPI</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated HAL_SPI_TransmitReceive() function </span><span style="font-size: 10pt; font-family: Verdana;">in slave mode </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">to </span><span style="font-size: 10pt; font-family: Verdana;">receive correctly the CRC when NSS pulse activated.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Added missing __IO in SPI_HandleTypeDef definition.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated IS_SPI_CRC_POLYNOMIAL macro definition as polynomial value should be odd only.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Updated
-SPI_2linesTxISR_8BIT() and SPI_2linesTxISR_16BIT() functions: added
-return so that SPI_2linesTxISR_8BITCRC() or SPI_2linesTxISR_16BITCRC()
-function is called from HAL_SPI_TransmitReceive_IT() when CRC is
-activated.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL TIM</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Used </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IS_TIM_HALL_INTERFACE_INSTANCE </span><span style="font-size: 10pt; font-family: Verdana;">macro instead of </span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">IS_TIM_XOR_INSTANCE </span><span style="font-size: 10pt; font-family: Verdana;">macro in<br>HAL_TIMEx_HallSensor_xxx() functions.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated HAL_TIM_ConfigOCrefClear() function to allow TIM_CLEARINPUTSOURCE_OCREFCLR as new ClearInputSource.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL UART-USART</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated UART Baudrate calculation (UART_DIV_SAMPLING8() and UART_DIV_SAMPLING16() macros).</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated USART_SetConfig() function following UART Baudrate calculation update.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Aligned UART-USART Stop Bits with others STM32 series.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Renamed IS_UART_WAKEUP_INSTANCE to IS_UART_WAKEUP_FROMSTOP_INSTANCE.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Modified UART_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Reviewed UART state machine to avoid cases where UART state is overwritten by UART IRQ.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-size: 10pt; font-family: Verdana;">Ensure proper alignment of data pointer in Transmit and Receive functions to avoid toolchain compilation hardfault.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL USB</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Corrected double buffer implementation in PCD_SET_EP_DBUF1_CNT() macro.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Added missing USB_CNTR_SOFM when setting wInterrupt_Mask global variable used in HAL_PCD_Init.<br></span></li></ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal; font-weight: bold;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL SMARTCARD</span></li><ul><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Aligned </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> Stop Bits with others </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STM32 series</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Modified SMARTCARD_Receive_IT() to execute the RX flush request only in case no data is read from RDR.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Updated SMARTCARD_SetConfig() function following UART Baudrate calculation update.</span></li><li class="MsoNormal" style="color: windowtext; margin-top: 4.5pt; margin-bottom: 4.5pt; line-height: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Reviewed SMARTCARD state machine to avoid cases where SMARTCARD state is overwritten by SMARTCARD IRQ.</span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1
-/ 29-January-2016<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
-enhancements implementation</span></span></li></ul><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated HAL Driver compliancy with:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 ('U' suffix applied to all constants of 'unsigned' type).</span></li><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.5 (bitwise operators ~ and <<).</span></li><li><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 12.7 (bitwise operations not performed on signed integer types).</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated HAL weak empty callbacks to prevent unused argument compilation warnings.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated stm32f3xx_hal_msp.c files:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Removed reference to MicroXplorer.</span></li></ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated stm32f3xx_hal_conf.h files:</span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Set HSE_STARTUP_TIMEOUT value to 100ms instead of 5000ms</span></li></ul></ul></ul><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL ADC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected ADC_CHANNEL_VREFINT enabling in the CCR register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected assert param of nb of discontinuous conversions when discontinuous mode is enabled.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed Flag EOS in HAL_ADC_GetValue().</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CAN</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected missing __HAL_UNLOCK when all Mailboxes are busy.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added ERRI bit clear besides to clearing LEC bits in CAN_ESR register, in case of Error interrupt.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CORTEX</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Removed __HAL_CORTEX_SYSTICKCLK_CONFIG macro, replaced by HAL_SYSTICK_CLKSourceConfig() function.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CRC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated CRC HAL_CRC_Calculate() and HAL_CRC_Accumulate() comments, handling input data pointers that are not * uint32_t.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FLASH</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Added FLASH API HAL_FLASHEx_OBGetUserData() to get the value saved in User data option byte.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned Return value of HAL_FLASH_EndOfOperationCallback function (0xFFFFFFF) when process is finished.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated GPIO Output Speed literals naming to ensure HAL full compatibility.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added GPIOD support for STM32070x6 devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Modified ADC poll for event to return timeout instead of error.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2C</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected wrong management of AF after NACK.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned I2C driver with new state machine definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected interrupt disabling in I2C_SlaveReceive_ISR() function.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Modified HAL_I2C_Master_Transmit to handle sending data of size 0.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Renamed I2C_CR1_DFN to I2C_CR1_DNF.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PCD</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated call to Double Buffering Counter Function.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Added do { } while(0) in __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() multi statement macro.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for HAL_RCC_ClockConfig() function.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected invertion in LSE drive capability Bit definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Performed optimizations for internal oscillators and PLL startup time.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added GPIOD support for STM32070x6 devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed GPIOE support for STM32F030xC devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add RCC_USBCLKSOURCE_NONE when HSI48 is not present.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected definition for flag RCC_FLAG_V18PWRRST.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added missing macro __HAL_RCC_LSEDRIVE_CONFIG.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned naming of macros related to CRS_CFGR register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected __HAL_RCC_CRS_CLEAR_IT()/__HAL_RCC_CRS_CLEAR_FLAG() macros.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed Bit PLLNODIV for STM32F030x6 devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Review implementation to automatically enable backup domain.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added RCC_IT_HSI48RDY definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Renamed __HAL_RCC_MCO_CONFIG() to __HAL_RCC_MCO1_CONFIG().</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RTC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Aligned different HAL_RTC_XXIRQHandler() implementations.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Check the behavior of flag WUTWF and corrected update of wakeup counter registers.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added subsecond fration formula in HAL_RTC_GetTime() function.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated Bits mask literals used in macros definition.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TIM</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected __HAL_TIM_SET_PRESCALER timer prescaler definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Protected SMCR register of possible overwrite in HAL_TIM_ConfigOCrefClear().</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected assert checks in HAL_TIM_ConfigClockSource().</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TSC</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Updated IO default state management.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART-USART</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Corrected behavior of HAL_UART_IRQ_Handler() (removed enabling/disabling of ERR IT source).</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected UART_FLAG_SBKF definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected values used for max allowed baudrates constant definitions.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed
-USART_CR2_LINEN/USART_CR3_IREN/USART_CR3_SCEN/USART_CR1_UESM bits
-definitions for STM32F030x6, STM32F030x8, STM32F070xB, STM32F070x6,
-STM32F030xC.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL WWDG</span></span></li><ul><li><span style="font-size: 10pt; font-family: Verdana;">Aligned WWDG registers Bits naming between all families.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0
-/ 26-June-2015<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">Maintenance release to fix known defects and
-enhancements implementation</span></span></li></ul><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;"></span></span><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">Complete HAL API alignment (macro/function renaming)</span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL Generic</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update HAL drivers to be MISRA/C++ compliant.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Initialized handle lock in HAL_PPP_Init().</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add SYSCFG define macros to manage FM+ on GPIOs.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use uint32_t instead of uint8_t/uint_16.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL ADC</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update ADC state machine. Missing state in function "HAL_ADCEx_Calibration_Start().</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Align ADC_SOFTWARE_START literal on STM32L0xx.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_ADC_PollForConversion(): update to return error status in case of ADC-DMA mode.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_ADC_Init(): ADC resolution must be changed only when ADC is disabled.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">ADC_ConversionStop(): correct wrong timeout value.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_ADC_AnalogWDGConfig(): Add missing assert param.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove channel for monitoring VBAT power supply pin on F0 Value line devices.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Move
-sampling time setting into ADC init stucture (keep setting into ADC
-channel init stucture with comments of obsolete setting).</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Move
-__HAL_UNLOCK() before peripheral activation because if an interruption
-occurs between ADC enable & __HAL_UNLOCK(), IRQ handler will be
-executed while HAL still locked.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">ADC_DMAConvCplt(): Add call to ADC error callback in case of error.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename local variables for compliancy with coding rules (tmpHALstatus ==> tmp_hal_status).</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Simplify __HAL_ADC_GET_IT_SOURCE().</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add use of POSITION_VAL.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add optimization of ADC stabilization delays.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CAN</span> </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add management of CAN Slave start bank in HAL_CAN_ConfigFilter().</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Unlock the CAN process when communication error occurred.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Replace “uint32_t Data[8]” by “uint8_t Data[8]” in structures CanTxMsgTypeDef and CanRxMsgTypeDef.</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="color: black;"></span><o:p></o:p></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CEC</span> </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new API HAL_CEC_GetReceivedFrameSize() </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">to get size of received frame</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CORTEX</span> </span></li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macro <span style="font-style: italic;">IS_NVIC_DEVICE_IRQ()</span> to
-check on negative values of IRQn </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">parameter</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CRC</span> </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macros __HAL_CRC_GET_IDR() and __HAL_CRC_SET_IDR().</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update __HAL_CRC_SET_IDR macro in resorting to WRITE_REG instead of MODIFY_REG (cycles gain at execution).</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DAC</span> </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and
-</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">DAC_FLAG_DMAUDR</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">2.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Correct __HAL_DMA_GET_IT_SOURCE brief comments.</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FLASH</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">FLASH_OB_GetRDP(): update function to return the FLASH Read Protection level (OB_RDP_LEVEL_x).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">FLASH_OB_RDP_LevelConfig(): update function to set the FLASH Read Protection level (OB_RDP_LEVEL_x).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add missing macro __HAL_FLASH_GET_LATENCY.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Disable WRP not compliant with other family.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add FLASH_BANK1_END defines.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Remove WRP defines for few defines under devices swicthes.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add switch to handle option bits BOOT_SEL & nBOOT1 not present on STM32F030xC & STM32F070x6.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO</span> </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">stm32f0xx_hal_gpio_ex.h: add IR as possible GPIO alternate function 1 for STM32F030x6.</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2C</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2C_ER_IRQHandler(): handle NACK test during wait on flag treatment.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2S</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_DMAStop(): Correctt DMA Stop function which stops both Rx and Tx channels regardless which one was set-up.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_IRDA_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add macros __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() and __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() comments.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Implement workaround to cover RCC limitation regarding Peripheral enable delay.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RCC_OscConfig(): correct test on LSEState.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Rework __HAL_RCC_LSE_CONFIG macro to manage correctly LSE_Bypass.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add defines for RCC_System_Clock_Source_Status.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Follow specific procedure to enable HSE.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add macros to get the enable or disable status of peripheral clock.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RCCEx_PeriphCLKConfig(): reset backup domain only if RTC clock source has been changed.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add interface HAL_RCCEx_GetPeriphCLKFreq.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RTC</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add missing RTC_FLAG_INIT in flag list.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RTC_DeInit(): add switch products condition around WakeUp timer registers (WUTWF,WUTR).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Remove RTC_FLAG_INIT as currently unused.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add missing IDLE flag management.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Align SMARTCARD_Last_Bit defines.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SPI</span> </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix issue related to missing reset of the Dma Tx callback inside the function HAL_SPI_TransmitReceive_DMA().<br>In
-that case only RX callback are used and the call of TX callback can
-close the communication before the end of the RX processing.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SPI_2linesRxISR_8BIT():
-correct issue on RX 2lines with DataSize8bit, even buffer size and CRC
-8bit (SPI_RXFIFO_THRESHOLD is not set).</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fit bit update add BSY flag check for all the process.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-__IO (volatile) to the "State" member of the SPI_HandleTypeDef
-struct. to missing reset of the Dma Tx callback inside the
-function
-HAL_SPI_TransmitReceive_DMA().</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TIM</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add __HAL_TIM_SET_CAPTUREPOLARITY, TIM_SET_CAPTUREPOLARITY, TIM_RESET_CAPTUREPOLARITY macros.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add macro to control CTS and RTS from the customer applications.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">UART_DMATransmitCplt(): change implementation to remove WaitOnFlag in ISR.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Change DMA TX management to remove WaitOnFlag in ISR.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add DMA circular mode support for the communication peripherals.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add UART NVIC configuration in the HAL_UART_MspInit().</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the UARTx_IRQHandler() in the stm32fxxx_it.c and the prototype in the stm32fxxx_it.h.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Modify UART DMA implementation issue (missed clear the TC bit in the SR).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add a OVR flag clear prior resuming DMA RX transfer.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_UART_DMAResume(): Remove UART_CheckIdleState() call and replace it by unlock + return(HAL_OK).</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_UART_DMAStop(): remove LOCK/UNLOCK calls.</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_UART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USART</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_USART_IRQHandler(): Correct parameters values of __HAL_USART_CLEAR_IT().</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Replace xxxITxxx defines by xxxCLEARxxxF defines in __HAL_USART_CLEAR_IT calls.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_USART_Init(): update to reach max frequencies (enable oversampling by 8).</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_USART_DMAPause()/HAL_USART_DMAResume(): add of a OVR flag clear prior resuming DMA RX transfer.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_USART_DMAResume(): Remove UART_CheckIdleState() call and replace it by just an Unlock + ret(HAL_OK).</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_USART_DMAStop(): update comments regarding deletion of LOCK/UNLOCK mechanism.<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1
-/ 09-January-2015</span></h3><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">stm32f0xx_hal.h: add missing define for USART3_RX/TX DMA remap on channel3 & channel2 for STM32F070xB only</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">stm32f0xx_hal_gpio_ex.h: add I2C1 as possible GPIO alternate function 3 for STM32F070xB</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">stm32f0xx_hal_rcc_ex.h: add missing USART2_CLK_ENABLE/DISABLE() macros for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F070x6</span></li></ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC</span></span>
-<ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f0xx_hal_rtc_ex.h/.c:
-Enable RTC periodic Wakeup timer feature on </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F070xB
-& </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F030xC</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f0xx_hal_rtc_ex.c:
-remove </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_RTCEx_Tamper3EventCallback()
-API for </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F070xB
-& </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F030xC, since
-there is no TAMPER3 on those products.</span></li></ul>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL UART</span></span>
-<ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f0xx_hal_uart_ex.c/.h:
-add HAL_RS485Ex_Init() API for </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F0xx Value
-Line devices</span></li></ul></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0
-/ 05-December-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> </span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HandleTypeDef.ErrorCode must be typed uint32_t</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update HAL drivers to ensure compliancy w/ C++</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add some generic defines (__NOINLINE) in stm32f0xx_hal_def.h</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Case mismatch between #include typo and effective file name generating compiler errors under Linux</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Correct various issues for documentation generation (group name, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">doxygen tags, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">etc..)</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Missing support of I2C_PAx_FMP of F04xx devices<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL ADC </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Improve HAL ADC comments</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Correct issue observed with ADC start simultaneous commands</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove macro __HAL_ADC_OFR_CHANNEL() since </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">OFRx register</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> is not available on F0 devices.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CAN </span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as __IO uint32 instead of <span style="font-weight: bold;">enum HAL_CAN_ErrorTypeDef</span> to fix C++ compilation issue<span style="font-weight: bold;"><br></span></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CEC </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">change<span style="font-weight: bold;"> ErrorCode </span>field declaration from </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">uint32_t to</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> __IO uint32_t</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">correct CEC state: Ready to Receive state lost upon Transmission end</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL COMP </span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">State </span>field is now declared as uint32_t instead of <span style="font-weight: bold;">enum HAL_COMP_StateTypeDef</span> to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">change HAL_COMP_GetState() type declaration from HAL_COMP_StateTypeDef to uint32_t </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">to fix C++ compilation issue</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CRC </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Wrong @ref in CRCLength field description for documentation generation </span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DAC </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DAC_Stop_DMA() code clean up</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use of internal macro MODIFY_REG() to update CR register<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">DMA channel remap register renamed for compatibility with other STM32 devices.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Correct wrong comments in __HAL_DMA_GET_FLAG and __HAL_DMA_CLEAR_FLAG macros description</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL FLASH </span></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in macro IS_OPTIONBYTE(VALUE) when all option_OB are selected</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as uint32 instead of <span style="font-weight: bold;">enum FLASH_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">change HAL_FLASH_GetError() type declaration from FLASH_ErrorTypeDef to uint32_t </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Clean the error context to FLASH_ERROR_NONE before starting new Flash operation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Put all the clear flags in the FLASH_SetSerrorCode()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Stop </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">the programming procedure in case of error detected </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">in HAL_FLASH_Program()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Check error before doing new procedure in </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_FLASH_IRQhandler() </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">correct Typo in 'How to use this driver' section & update comments</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add assert on GPIO PIN in HAL_GPIO_DeInit()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add assert </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">on GPIO AF instance to protect HAL_GPIO_Init() </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">from impossible AF configuration</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename internal macro GET_GPIO_INDEX() into GPIO_GET_INDEX()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Reset </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Interrupt mode registers only in HAL_GPIO_DeInit()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2C</span></span><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as uint32 instead of <span style="font-weight: bold;">enum HAL_I2C_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2S </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as uint32 instead of <span style="font-weight: bold;">enum HAL_I2S_ErrorTypeDef</span> to fix C++ compilation issue.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change <span style="font-weight: bold;">HAL_I2S_GetError</span>() type declaration from </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_I2S_ErrorTypeDef </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> to uint32_t </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">to fix C++ compilation issue.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add use of UNUSED(tmpreg) in __HAL_I2S_CLEAR_OVRFLAG() & __HAL_I2S_CLEAR_UDRFLAG to </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">fix </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Unused variable" warning w/ TrueSTUDIO</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Typo in 'I2S HAL driver macros list' section of stm32f0xx_hal_i2s.c</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Missing doxygen tags for I2S_HandleTypeDef fields description (documentation generation)</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as uint32 instead of <span style="font-weight: bold;">enum HAL_IRDA_ErrorTypeDef</span> to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Missing doxygen tags for IRDA_HandleTypeDef fields description</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new API to manage </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SLEEPONEXIT and SEVONPEND bits of SCR register:</span></li></ul></ul><ul style="margin-left: 80px;"><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWR_DisableSleepOnExit()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWR_EnableSleepOnExit()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWR_EnableSEVOnPend()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWR_DisableSEVOnPend()</span></li></ul><ul style="margin-top: 0cm; list-style-type: square;"><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Removed useless regulator parameter setting for F0 family in core of HAL_PWR_EnterSLEEPMode()<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add a comment in the 'How to use this driver' section to mention the Peripheral enable delay</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Move __HAL_RCC_USART2_CONFIG() & __HAL_RCC_GET_USART2_SOURCE() from stm32f0xx_hal_rcc.h to </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">stm32f0xx_hal_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">rcc_ex.h since this feature is not supported on all F0 devices </span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change <span style="font-weight: bold;">HAL_RCCEx_CRSWaitSynchronization</span>() type declaration from </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_CRSStatusTypeDef</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> to uint32_t </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">to fix C++ compilation issue</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RTC </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Enhance @note describing the use of HAL RTC APIs </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span></span><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as uint32 instead of <span style="font-weight: bold;">enum HAL_SMARTCARD_ErrorTypeDef</span> to fix C++ compilation issue</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMBUS</span></span><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode & PreviousState </span>fields are now declared as uint32 instead of <span style="font-weight: bold;">enum HAL_SMBUS_ErrorTypeDef</span> & <span style="font-weight: bold;">HAL_SMBUS_StateTypeDef </span>to fix C++ compilation issue</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change <span style="font-weight: bold;">HAL_SMBUS_GetState</span>() type declaration from </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_SMBUS_StateTypeDef<span style="font-weight: bold;"> </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> to uint32_t </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">to fix C++ compilation issue</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SPI </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as uint32 instead of <span style="font-weight: bold;">enum HAL_SPI_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add use of UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(), __HAL_SPI_CLEAR_FREFLAG() to </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">fix </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"Unused variable" warning w/ TrueSTUDIO</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add DMA circular mode support on SPI HAL driver.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Internal
-fucntion renaming: HAL_SPI_DMATransmitCplt(),
-HAL_SPI_DMAReceiveCplt(), HAL_SPI_DMATransmitReceiveCplt() &
-HAL_SPI_DMAError() renamed respectively into </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SPI_DMATransmitCplt(), </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SPI_DMAReceiveCplt(), </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SPI_DMATransmitReceiveCplt() & </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">SPI_DMAError().</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove unused HAL_StatusTypeDef SPI_EndRxTxTransaction() prototype<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">uint32_t driver alignment for compatibility with other STM32 devices<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new API <span style="font-weight: bold;">HAL_SPI_GetError</span>(), which was missing on STM32F0xx family<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART/USART </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span> and <span style="font-weight: bold;">STM32F030xC</span>.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">structure UART_WakeUpTypeDef moved to stm32f0xx_hal_uart_ex.h since wakeup feature is not available on all F0 devices.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">ErrorCode </span>field is now declared as uint32 instead of <span style="font-weight: bold;">enum HAL_U(S)ART_ErrorTypeDef</span> to fix C++ compilation issue</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">unused HAL_USART_SetConfig() prototype to be removed from stm32f0xx_hal_usart.h</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add missing API HAL_StatusTypeDef <span style="font-weight: bold;">HAL_LIN_SendBreak</span>()<br></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">correct wrong USART_IT_CM value</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">correct issue with Lin mode data length</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new value for Stop bit definition: UART_STOPBITS_1_5<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USB </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new STM32F0 value line devices <span style="font-weight: bold;">STM32F070xB/x6</span><span style="font-weight: bold;"></span>.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Wrong comment in HAL_PCD_Dev(Connect/Disconnect) functions description</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Correct _HAL_PCD_CLEAR_FLAG() macros definition <br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL WWDG </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro to manage WWDG IT & correction:</span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_WWDG_DISABLE_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_WWDG_GET_IT()</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">__HAL_WWDG_GET_IT_SOURCE()</span><br></span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0
-/ 03-October-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> </span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">general improvement of Doxygen Tags for CHM UM generation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add support of new devices </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">STM32F091xC</span>, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">STM32F098xx</span> in </span><span style="font-size: 10pt; font-family: Verdana;">STM32F0xx HAL drivers</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">minor corrections for Pdf/Chm UM generation</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Correction for MISRA </span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">[F098xx] Remove PVD IT line wrapper</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">FLAG&IT assert macros to be removed</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Bad macro name in stm32F0xx_hal.c/.h files</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">uint32_t Alignement in HAL driver</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL </span>update </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">(for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F091xC/</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F098xx)</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new define for HAL IRDA Enveloppe source Selection</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro IS_HAL_SYSCFG_IRDA_ENV_SEL()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new defines for ISR Wrapper (HAL_SYSCFG_ITLINE0, etc..)</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_GET_PENDING_IT()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SYSCFG_IRDA_ENV_SELECTION()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_SYSCFG_GET_IRDA_ENV_SELECTION()</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL COMP </span></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Missing assert param IS_COMP_TRIGGERMODE</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL Cortex </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">remove Macro not supported by cortex-M0 in stm32f0xx.h</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA </span></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new defines for DMAx Channel remapping (DMAx_CHANNELx_RMP)</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new defines for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">DMAx channels </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">remap bit field definition</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macros: </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">IS_HAL_DMA1_REMAP(), IS_HAL_DMA2_REMAP()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">: __HAL_DMA_GET_TC_FLAG_INDEX(), that returns specified transfer complete flag index</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro: </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_DMA_GET_HT_FLAG_INDEX(), that returns specified half transfer complete flag index</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">: __HAL_DMA_GET_TE_FLAG_INDEX(), that returns specified transfer error flag index</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro: </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_DMA_GET_FLAG()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro: </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_DMA_CLEAR_FLAG()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">A</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">dd new macro: </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_DMA1_REMAP(), __HAL_DMA2_REMAP()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Bit definition name error for HAL_DMA1_CH2 remap on STM32F091xC</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_DMA_PollForTransfer updated</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL GPIO </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">BSRR regsiter should not be split in BSRRH/BSRRL</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">rework GPIO_GET_SOURCE</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new defines for AF functions selection</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2S </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Supp ClockSource in Init</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Incorrect definition for IS_IRDA_REQUEST_PARAMETER macro</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IWDG </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use WRITE_REG instead of SET_BIT</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Functions for VDDIO2 management missing in all F09xx, F07xx, F04xx</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-family: Calibri;">PVD feature need falling/rising Event modes</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update defines name PWR_MODE_EVT/PWR_MODE_IT_RISING/PWR_MODE_IT_FALLING/PWR_MODE_IT_RISING_FALLING to PWR_<span style="font-weight: bold;">PVD</span>_MODE_<span style="font-weight: bold;">NORMAL/</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">PWR_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">PVD</span>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">MODE_IT_RISING/PWR_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">PVD</span>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">MODE_IT_FALLING/PWR_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">PVD</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_MODE_IT_RISING_FALLING</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new defines PWR_PVD_MODE_EVENT_RISING, PWR_PVD_MODE_EVENT_FALLING, PWR_PVD_MODE_EVENT_RISING_FALLING<span style="font-weight: bold;"><br></span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update macro IS_PWR_PVD_MODE()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">change macro name: __HAL</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_PVD_EXTI_ENABLE_IT(), __HAL</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_PVD_EXTI_DISABLE_IT(), __HAL</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_PVD_EXTI_GENERATE_SWIT(), __HAL</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_PVD_EXTI_GET_FLAG(), __HAL</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_<span style="font-weight: bold;">PWR</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_PVD_EXTI_CLEAR_FLAG()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-new macro __HAL_PWR_PVD_EXTI_ENABLE_EVENT(),
-__HAL_PWR_PVD_EXTI_DISABLE_EVENT(),
-__HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER(),
-__HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC </span></span><ul><li><span style="font-family: Calibri;">Defect correction:</span><span style="font-family: Calibri;"></span></li><ul><li><span style="font-family: Calibri;">HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F091xC/</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F098xx</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">New structure RCC_PeriphCLKInitTypeDef</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-defines for RCC new peripheral clock selection: RCC_PERIPHCLK_USART1,
-RCC_PERIPHCLK_USART2, RCC_PERIPHCLK_I2C1, RCC_PERIPHCLK_CEC,
-RCC_PERIPHCLK_RTC, RCC_PERIPHCLK_USART3</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add macro IS_RCC_PERIPHCLK()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-defines for USART3 clock source selection (RCC_USART3CLKSOURCE_PCLK1,
-RCC_USART3CLKSOURCE_SYSCLK, CC_USART3CLKSOURCE_LSE,
-CC_USART3CLKSOURCE_HSI</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add macro IS_RCC_USART3CLKSOURCE()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add macro __HAL_RCC_GET_USART3_SOURCE()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add macro __HAL_RCC_USART3_CONFIG()<br></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">add clock enable macros for new UART: __USART5_CLK_ENABLE, __USART6_CLK_ENABLE, __USART7_CLK_ENABLE, __USART8_CLK_ENABLE</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">add clock disable macros for new UART: __USART5_CLK_DISABLE, __USART6_CLK_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">, __USART7_CLK_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">, __USART8_CLK_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">DISABLE</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">add Force reset macros for new UART: __USART5_FORCE_RESET, __USART6_FORCE_RESET, __USART7_FORCE_RESET, __USART8_FORCE_RESET</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">add Release reset macros for new UART: __USART5_RELEASE_RESET, __USART6_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RELEASE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_RESET, __USART7_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RELEASE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_RESET, __USART8_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RELEASE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">_RESET</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span></li></ul></ul></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">change SMARTCARD_AdvFeatureConfig() from exported to static private function</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F091xC/</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F098xx:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro __HAL_SMARTCARD_GETCLOCKSOURCE() for USART1, USART2, USART3, USAR</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMBUS </span> </span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">change SMARTCARD_AdvFeatureConfig() from exported to static private function</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SPI </span></span></p></li><ul style="font-family: Lucida Sans;" class="MsoChpDefault"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Function HAL_SPI_TransmitReceive muse use SPI_FLAG_RXNE to read CRC</span></p></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Function HAL_SPI_IRQHandler, in case of error the state must be reset to ready<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TIM </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Missed/Unused assert param to be added/removed</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Trigger interrupt should be activated when working with a slave mode</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Break interrupt should be activated in HAL_TIMEx_OCN_Start_IT</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Wrong CCMR register cleared in HAL_TIM_IRQHandler for Input Capture event Channel 3 and 4</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">missing assert in HAL_TIMEx_ConfigBreakDeadTime</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">URS_ENABLE/ URS_DISABLE macros</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART/USART </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change UART TX-IT implementation to remove WaitOnFlag in ISR</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F091xC/</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32F098xx:</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro __HAL_UART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro __HAL_USART_GETCLOCKSOURCE() for USART1, USART2, USART3, USART4</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USB </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Bad IN/OUT EndPoint parameter array size</span></p></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL WWDG </span></span></p></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">improvements from other families</span></p></li></ul></ul><div style="margin-left: 40px;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Defect Correction<br><br></span></u></b>
-
-<table class="MsoNormalTable" style="width: 652.45pt; border-collapse: collapse;" border="0" cellpadding="0" cellspacing="0" width="870">
- <tbody><tr style="height: 15pt;">
-
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
- <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
- <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
- <p class="MsoNormal"><span style="color: black;">PWR<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
- <p class="MsoNormal"><span style="color: black;">PVD feature need falling/rising Event modes<o:p></o:p></span></p>
- </td>
- </tr>
- <tr style="height: 15pt;">
-
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
- <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
- <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
- <p class="MsoNormal"><span style="color: black;">COMP<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
- <p class="MsoNormal"><span style="color: black;">Missing assert param IS_COMP_TRIGGERMODE <o:p></o:p></span></p>
- </td>
- </tr>
-
- <tr style="height: 15pt;">
-
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 124.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="166">
- <p class="MsoNormal"><span style="color: black;">STM32F0xx_HAL_Driver<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 49.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="66">
- <p class="MsoNormal"><span style="color: black;">Defect<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 68.8pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="92">
- <p class="MsoNormal"><span style="color: black;">RCC<o:p></o:p></span></p>
- </td>
- <td style="padding: 0cm 5.4pt; background: rgb(216, 228, 188) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; width: 366.75pt; height: 15pt;" nowrap="nowrap" valign="bottom" width="489">
- <p class="MsoNormal"><span style="color: black;">HAL_RCC_OscConfig: HSERDY has to be checked also in by
- pass mode<o:p></o:p></span></p>
- </td>
- </tr>
-</tbody></table>
-<br></div><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1
-/ 18-June-2014<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL generic</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix flag clear procedure: use atomic write operation </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">"=" </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">instead of ready-modify-write operation "|=" or "&="</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
-on Timeout management, Timeout value set to 0 passed to API
-automatically exits the function after checking the flag without any
-wait.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL CEC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span> </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL COMP</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add <span style="font-style: italic;">NonInvertingInput</span> field in the <span style="font-style: italic;">COMP_InitTypeDef</span> structure.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new defines <span style="font-style: italic;">COMP_NONINVERTINGINPUT_IO1</span> and <span style="font-style: italic;">COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED</span><br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in <span style="font-style: italic;">HAL_DMA_PollForTransfer()</span> to set error code <span style="font-style: italic;">HAL_DMA_ERROR_TE </span>in case of <span style="font-style: italic;">HAL_ERROR</span> status</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2C</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add
-management of NACK event in Master transmitter mode and Slave
-transmitter/receiver modes (only in polling mode), in that case the
-current transfer is stopped.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL I2S</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">I2S clock source change: new define <span style="font-style: italic;">I2S_CLOCK_SYSCLK</span>, remove<span style="font-style: italic;"> I2S_CLOCK_PLL</span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Improvement done in I2S transfer/receive processes <br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IRDA</span> update<br></span></p><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new enum typedef <span style="font-style: italic;">IRDA_ClockSourceTypeDef</span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro <span style="font-style: italic;">__HAL_IRDA_GETCLOCKSOURCE</span></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_IRDA_Transmit_IT()</span> to enable IRDA_IT_TXE instead of IRDA_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li></ul></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PCD </span>update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></p>
- </li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro <span style="font-style: italic;">__HAL_USB_EXTI_GENERATE_SWIT</span></span></p>
- </li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL PWR</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in <span style="font-style: italic;">HAL_PWR_EnterSTANDBYMode()</span> to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL RCC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add USB peripheral and clocking macros for STM32F078xx device.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix HSI Calibration issue when selected as SYSCLK </span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMARTCARD</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_SMARTCARD_Transmit_IT()</span> to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL SMBUS</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TIM</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix macro __HAL_TIM_PRESCALER</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL TSC</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix define <span style="font-style: italic;">TSC_ACQ_MODE_SYNCHRO</span></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
-
-
-
-
-
-
-
-<p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL UART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_LIN_Init()</span> parameter BreakDetectLength to uint32_t</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_UART_Transmit_IT()</span> to enable UART_IT_TXE instead of UART_IT_TC.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL USART</span> update<br></span></p></li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change <span style="font-style: italic;">USART_InitTypeDef</span> fields to uint32_t type</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename __USART_ENABLE and __USART_DISABLE macros to respectively </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USART_ENABLE and __HAL_USART_DISABLE</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_USART_Transmit_IT()</span> to enable USART_IT_TXE instead of USART_IT_TC.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Process no more locked during the transmission in interrupt mode.</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Change in <span style="font-style: italic;">HAL_USART_TransmitReceive_DMA()</span> to manage DMA half transfer mode</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
-/ 20-May-2014<o:p></o:p></span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official
-release of STM32F0xx HAL drivers for </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F030x4/x6, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F030x8, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F031x4/x6</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F051x4/x6/x8</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F071x8/xB, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F042x4/x6,
-</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F072x8/xB, </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F038xx,
-</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;"> STM32F048xx</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">, </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">STM32F058xx and STM32F078xx
-</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-weight: bold;">devices.</span></li></ul><br><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistribution
-and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:</span><br>
-</font>
-<ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
-of source code must retain the above copyright notice, this list of
-conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
-in binary form must reproduce the above copyright notice, this list of
-conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the
-documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the
-name of STMicroelectronics nor the names of its contributors may be
-used to endorse or promote products derived</span></font><small><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span></small><br></li></ol><font size="-1">
-<span style="font-family: "Verdana","sans-serif";"></span><br>
-<span style="font-family: "Verdana","sans-serif";"></span></font><font size="-1"><span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font><font size="-1"><span style="font-family: "Verdana","sans-serif";"></span></font> </div>
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32<span style="color: black;"> Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
+<tr class="odd">
+<td style="text-align: left;">PWR</td>
+<td style="text-align: center;">PVD feature need falling/rising Event modes</td>
</tr>
-<tr><td style="padding: 0in;" valign="top"></td></tr></tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
+<tr class="even">
+<td style="text-align: left;">COMP</td>
+<td style="text-align: center;">Missing assert param IS_COMP_TRIGGERMODE</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">RCC</td>
+<td style="text-align: center;">HAL_RCC_OscConfig: HSERDY has to be checked also in by pass mode</td>
</tr>
</tbody>
</table>
</div>
-<p class="MsoNormal"><o:p> </o:p></p>
</div>
-</body></html>
\ No newline at end of file
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_0_1" aria-hidden="true"> <label for="collapse-section1_0_1" aria-hidden="true"><strong>V1.0.1 / 18-June-2014</strong></label>
+<div>
+<h2 id="main-changes-12">Main Changes</h2>
+<ul>
+<li><strong>HAL generic</strong> update
+<ul>
+<li>Fix flag clear procedure: use atomic write operation = instead of ready-modify-write operation |= or &=</li>
+<li>Fix on Timeout management, Timeout value set to 0 passed to API automatically exits the function after checking the flag without any wait.</li>
+<li>Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state.</li>
+</ul></li>
+<li><strong>HAL CEC</strong> update
+<ul>
+<li>Process no more locked during the transmission in interrupt mode.</li>
+</ul></li>
+<li><strong>HAL COMP</strong> update
+<ul>
+<li>Add NonInvertingInput field in the COMP_InitTypeDef structure.</li>
+<li>Add new defines COMP_NONINVERTINGINPUT_IO1 and COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED</li>
+</ul></li>
+<li><strong>HAL DMA</strong> update
+<ul>
+<li>Fix in HAL_DMA_PollForTransfer() to set error code HAL_DMA_ERROR_TE in case of HAL_ERROR status</li>
+</ul></li>
+<li><strong>HAL I2C</strong> update
+<ul>
+<li>Add management of NACK event in Master transmitter mode and Slave transmitter/receiver modes (only in polling mode), in that case the current transfer is stopped.</li>
+</ul></li>
+<li><strong>HAL I2S</strong> update
+<ul>
+<li>I2S clock source change: new define I2S_CLOCK_SYSCLK, remove I2S_CLOCK_PLL</li>
+<li>Improvement done in I2S transfer/receive processes</li>
+</ul></li>
+<li><strong>HAL IRDA</strong> update
+<ul>
+<li>Add new enum typedef IRDA_ClockSourceTypeDef</li>
+<li>Add new macro __HAL_IRDA_GETCLOCKSOURCE</li>
+<li>Change in HAL_IRDA_Transmit_IT() to enable IRDA_IT_TXE instead of IRDA_IT_TC.</li>
+<li>Process no more locked during the transmission in interrupt mode.</li>
+</ul></li>
+<li><strong>HAL PCD</strong> update
+<ul>
+<li>Add new macro __HAL_USB_EXTI_GENERATE_SWIT</li>
+</ul></li>
+<li><strong>HAL PWR</strong> update
+<ul>
+<li>Fix in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which need to be cleared at application level before to call this function</li>
+</ul></li>
+<li><strong>HAL RCC</strong> update
+<ul>
+<li>Add USB peripheral and clocking macros for STM32F078xx device.</li>
+<li>Fix HSI Calibration issue when selected as SYSCLK</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong> update
+<ul>
+<li>Change in HAL_SMARTCARD_Transmit_IT() to enable SMARTCARD_IT_TXE instead of SMARTCARD_IT_TC.</li>
+<li>Process no more locked during the transmission in interrupt mode.</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> update
+<ul>
+<li>Fix Slave acknowledge issue: Slave should ack each bit and so stretch the line till the bit is not ack</li>
+</ul></li>
+<li><strong>HAL TIM</strong> update
+<ul>
+<li>Fix macro __HAL_TIM_PRESCALER</li>
+</ul></li>
+<li><strong>HAL TSC</strong> update
+<ul>
+<li>Fix define TSC_ACQ_MODE_SYNCHRO</li>
+</ul></li>
+<li><strong>HAL UART</strong> update
+<ul>
+<li>Change in HAL_LIN_Init() parameter BreakDetectLength to uint32_t</li>
+<li>Change in HAL_UART_Transmit_IT() to enable UART_IT_TXE instead of UART_IT_TC.</li>
+<li>Process no more locked during the transmission in interrupt mode.</li>
+</ul></li>
+<li><strong>HAL USART</strong> update
+<ul>
+<li>Change USART_InitTypeDef fields to uint32_t type</li>
+<li>Rename __USART_ENABLE and __USART_DISABLE macros to respectively __HAL_USART_ENABLE and __HAL_USART_DISABLE</li>
+<li>Change in HAL_USART_Transmit_IT() to enable USART_IT_TXE instead of USART_IT_TC.</li>
+<li>Process no more locked during the transmission in interrupt mode.</li>
+<li>Change in HAL_USART_TransmitReceive_DMA() to manage DMA half transfer mode</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true"><strong>V1.0.0 / 12-June-2018</strong></label>
+<div>
+<h2 id="main-changes-13">Main Changes</h2>
+<ul>
+<li>First official release of STM32F0xx HAL drivers for <strong>STM32F030x4/x6, STM32F030x8, STM32F031x4/x6, STM32F051x4/x6/x8, STM32F071x8/xB, STM32F042x4/x6, STM32F072x8/xB, STM32F038xx, STM32F048xx, STM32F058xx and STM32F078xx devices.</strong></li>
+</ul>
+</div>
+</div>
+</div>
+</div>
+<footer class="sticky">
+For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span> <em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em>
+</footer>
+</body>
+</html>
diff --git a/Src/stm32f0xx_hal.c b/Src/stm32f0xx_hal.c
index 501253a..79905fa 100644
--- a/Src/stm32f0xx_hal.c
+++ b/Src/stm32f0xx_hal.c
@@ -21,29 +21,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -68,12 +52,12 @@
* @{
*/
/**
- * @brief STM32F0xx HAL Driver version number V1.7.2
+ * @brief STM32F0xx HAL Driver version number V1.7.3
*/
-#define __STM32F0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F0xx_HAL_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
-#define __STM32F0xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
-#define __STM32F0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32F0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
+#define __STM32F0xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
+#define __STM32F0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\
|(__STM32F0xx_HAL_VERSION_SUB2 << 8U )\
@@ -92,11 +76,13 @@
* @}
*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
+/* Exported variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Exported Variables
* @{
*/
__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
@@ -116,12 +102,12 @@
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface, the NVIC allocation and initial clock
- configuration. It initializes the source of time base also when timeout
- is needed and the backup domain when enabled.
+ configuration. It initializes the systick also when timeout is needed
+ and the backup domain when enabled.
(+) de-Initializes common part of the HAL.
- (+) Configure The time base source to have 1ms time base with a dedicated
- Tick interrupt priority.
- (++) Systick timer is used by default as source of time base, but user
+ (+) Configure The time base source to have 1ms time base with a dedicated
+ Tick interrupt priority.
+ (++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
@@ -171,7 +157,7 @@
}
/**
- * @brief This function de-Initializes common part of the HAL and stops the source
+ * @brief This function de-Initialize common part of the HAL and stops the SysTick
* of time base.
* @note This function is optional.
* @retval HAL status
@@ -196,12 +182,12 @@
}
/**
- * @brief Initializes the MSP.
+ * @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
@@ -212,7 +198,7 @@
*/
__weak void HAL_MspDeInit(void)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
@@ -226,7 +212,7 @@
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The the SysTick interrupt must have higher priority (numerically lower)
+ * The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __Weak to be overwritten in case of other
* implementation in user file.
@@ -236,10 +222,21 @@
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000U);
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
- /*Configure the SysTick IRQ priority */
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
/* Return function status */
return HAL_OK;
@@ -276,14 +273,14 @@
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
- * in Systick ISR.
+ * in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
- uwTick++;
+ uwTick += uwTickFreq;
}
/**
@@ -298,6 +295,56 @@
}
/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ HAL_TickFreqTypeDef prevTickFreq;
+
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+
+ if (status != HAL_OK)
+ {
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * @brief return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
* @brief This function provides accurate delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
@@ -308,15 +355,15 @@
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
-__weak void HAL_Delay(__IO uint32_t Delay)
+__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
- /* Add a period to guarantee minimum wait */
+ /* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
- wait++;
+ wait += (uint32_t)(uwTickFreq);
}
while((HAL_GetTick() - tickstart) < wait)
@@ -359,7 +406,7 @@
/**
* @brief This method returns the HAL revision
- * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+ * @retval version 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
@@ -412,7 +459,7 @@
}
/**
- * @brief Enable the Debug Module during STOP mode
+ * @brief Enable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
@@ -421,7 +468,7 @@
}
/**
- * @brief Disable the Debug Module during STOP mode
+ * @brief Disable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
@@ -430,7 +477,7 @@
}
/**
- * @brief Enable the Debug Module during STANDBY mode
+ * @brief Enable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
@@ -439,7 +486,7 @@
}
/**
- * @brief Disable the Debug Module during STANDBY mode
+ * @brief Disable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
diff --git a/Src/stm32f0xx_hal_adc.c b/Src/stm32f0xx_hal_adc.c
index a94fe6d..8aff721 100644
--- a/Src/stm32f0xx_hal_adc.c
+++ b/Src/stm32f0xx_hal_adc.c
@@ -211,45 +211,92 @@
(#) Optionally, in case of usage of ADC with interruptions:
(++) Disable the NVIC for ADC
- using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+ using function HAL_NVIC_DisableIRQ(ADCx_IRQn)
(#) Optionally, in case of usage of DMA:
(++) Deinitialize the DMA
- using function HAL_DMA_Init().
+ using function HAL_DMA_DeInit().
(++) Disable the NVIC for DMA
- using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+ using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)
[..]
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_ADC_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : ADC conversion complete callback
+ (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
+ (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
+ (+) ErrorCallback : ADC error callback
+ (+) MspInitCallback : ADC Msp Init callback
+ (+) MspDeInitCallback : ADC Msp DeInit callback
+ [..]
+
+ By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+ or @ref HAL_ADC_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -399,8 +446,24 @@
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ /* Init the ADC Callback settings */
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
+
+ if (hadc->MspInitCallback == NULL)
+ {
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hadc->MspInitCallback(hadc);
+#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Configuration of ADC parameters if previous preliminary actions are */
@@ -467,13 +530,13 @@
ADC_CFGR1_SCANDIR |
ADC_CFGR1_DMACFG );
- tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
- ADC_CFGR1_AUTOOFF(hadc->Init.LowPowerAutoPowerOff) |
- ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) |
- ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
- hadc->Init.DataAlign |
- ADC_SCANDIR(hadc->Init.ScanConvMode) |
- ADC_CFGR1_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
+ tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
+ ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
+ ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
+ ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
+ hadc->Init.DataAlign |
+ ADC_SCANDIR(hadc->Init.ScanConvMode) |
+ ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
/* Enable discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
@@ -674,10 +737,20 @@
/* */
/* __HAL_RCC_ADC1_FORCE_RESET() */
/* __HAL_RCC_ADC1_RELEASE_RESET() */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ if (hadc->MspDeInitCallback == NULL)
+ {
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ }
/* DeInit the low level hardware */
+ hadc->MspDeInitCallback(hadc);
+#else
+ /* DeInit the low level hardware */
HAL_ADC_MspDeInit(hadc);
-
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
@@ -723,6 +796,202 @@
*/
}
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User ADC Callback
+ * To be used instead of the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = pCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a ADC Callback
+ * ADC callback is redirected to the weak predefined callback
+ * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
+ * the configuration information for the specified ADC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID
+ * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
+ * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
+ * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
+ * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if ((hadc->State & HAL_ADC_STATE_READY) != 0)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+ hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+ break;
+
+ case HAL_ADC_CONVERSION_HALF_CB_ID :
+ hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+ break;
+
+ case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+ hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+ break;
+
+ case HAL_ADC_ERROR_CB_ID :
+ hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+ break;
+
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_ADC_STATE_RESET == hadc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_ADC_MSPINIT_CB_ID :
+ hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_ADC_MSPDEINIT_CB_ID :
+ hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1444,11 +1713,14 @@
}
}
- /* Conversion complete callback */
/* Note: into callback, to determine if conversion has been triggered */
/* from EOC or EOS, possibility to use: */
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
- HAL_ADC_ConvCpltCallback(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
@@ -1465,8 +1737,11 @@
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
- /* Level out of window callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->LevelOutOfWindowCallback(hadc);
+#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear ADC Analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
@@ -1492,8 +1767,11 @@
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
- /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/* Clear the Overrun flag */
@@ -2126,7 +2404,11 @@
}
/* Conversion complete callback */
- HAL_ADC_ConvCpltCallback(hadc);
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvCpltCallback(hadc);
+#else
+ HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
else
{
@@ -2147,7 +2429,11 @@
ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ConvHalfCpltCallback(hadc);
+#else
HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
@@ -2167,7 +2453,11 @@
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
/* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+ hadc->ErrorCallback(hadc);
+#else
HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
/**
diff --git a/Src/stm32f0xx_hal_adc_ex.c b/Src/stm32f0xx_hal_adc_ex.c
index a3408d9..159a7c1 100644
--- a/Src/stm32f0xx_hal_adc_ex.c
+++ b/Src/stm32f0xx_hal_adc_ex.c
@@ -19,31 +19,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_hal_can.c b/Src/stm32f0xx_hal_can.c
index d576947..47bfa35 100644
--- a/Src/stm32f0xx_hal_can.c
+++ b/Src/stm32f0xx_hal_can.c
@@ -126,6 +126,74 @@
(++) When a start of Rx CAN frame is detected by the CAN peripheral,
if automatic wake up mode is enabled.
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks:
+ (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
+ (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
+ (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
+ (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
+ (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
+ (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
+ (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
+ (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
+ (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
+ (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
+ (+) SleepCallback : Sleep Callback.
+ (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : CAN MspInit.
+ (+) MspDeInitCallback : CAN MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback.
+ (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback.
+ (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback.
+ (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback.
+ (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback.
+ (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback.
+ (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback.
+ (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback.
+ (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback.
+ (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback.
+ (+) SleepCallback : Sleep Callback.
+ (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) MspInitCallback : CAN MspInit.
+ (+) MspDeInitCallback : CAN MspDeInit.
+
+ By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
+ all callbacks are set to the corresponding weak functions:
+ example @ref HAL_CAN_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit()
+ or @ref HAL_CAN_Init() function.
+
+ When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
@@ -227,11 +295,40 @@
assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Reset callbacks to legacy functions */
+ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */
+ hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */
+ hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */
+ hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */
+ hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
+ hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
+ hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
+ hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */
+ hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */
+ hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */
+ hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */
+ hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */
+ hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hcan->MspInitCallback == NULL)
+ {
+ hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware: CLOCK, NVIC */
+ hcan->MspInitCallback(hcan);
+ }
+
+#else
if (hcan->State == HAL_CAN_STATE_RESET)
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
@@ -373,8 +470,19 @@
/* Stop the CAN module */
(void)HAL_CAN_Stop(hcan);
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ if (hcan->MspDeInitCallback == NULL)
+ {
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
+ hcan->MspDeInitCallback(hcan);
+
+#else
/* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Reset the CAN peripheral */
SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
@@ -421,6 +529,284 @@
*/
}
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+ * @brief Register a CAN CallBack.
+ * To be used instead of the weak predefined callback
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for CAN module
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+ hcan->TxMailbox0CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+ hcan->TxMailbox1CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+ hcan->TxMailbox2CompleteCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+ hcan->TxMailbox0AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+ hcan->TxMailbox1AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+ hcan->TxMailbox2AbortCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+ hcan->RxFifo0MsgPendingCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+ hcan->RxFifo0FullCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+ hcan->RxFifo1MsgPendingCallback = pCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+ hcan->RxFifo1FullCallback = pCallback;
+ break;
+
+ case HAL_CAN_SLEEP_CB_ID :
+ hcan->SleepCallback = pCallback;
+ break;
+
+ case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+ hcan->WakeUpFromRxMsgCallback = pCallback;
+ break;
+
+ case HAL_CAN_ERROR_CB_ID :
+ hcan->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a CAN CallBack.
+ * CAN callabck is redirected to the weak predefined callback
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for CAN module
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID
+ * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID
+ * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID
+ * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID
+ * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID
+ * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID
+ * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+ hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+ hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+ hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+ hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+ hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
+ break;
+
+ case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+ hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+ hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+ hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+ hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
+ break;
+
+ case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+ hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
+ break;
+
+ case HAL_CAN_SLEEP_CB_ID :
+ hcan->SleepCallback = HAL_CAN_SleepCallback;
+ break;
+
+ case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+ hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
+ break;
+
+ case HAL_CAN_ERROR_CB_ID :
+ hcan->ErrorCallback = HAL_CAN_ErrorCallback;
+ break;
+
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = HAL_CAN_MspInit;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcan->State == HAL_CAN_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CAN_MSPINIT_CB_ID :
+ hcan->MspInitCallback = HAL_CAN_MspInit;
+ break;
+
+ case HAL_CAN_MSPDEINIT_CB_ID :
+ hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
@@ -1138,7 +1524,7 @@
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
- pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
@@ -1324,8 +1710,13 @@
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
{
/* Transmission Mailbox 0 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox0CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
@@ -1342,8 +1733,13 @@
else
{
/* Transmission Mailbox 0 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox0AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
@@ -1357,8 +1753,13 @@
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
{
/* Transmission Mailbox 1 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox1CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
@@ -1375,8 +1776,13 @@
else
{
/* Transmission Mailbox 1 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox1AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
@@ -1390,8 +1796,13 @@
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
{
/* Transmission Mailbox 2 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox2CompleteCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
@@ -1408,8 +1819,13 @@
else
{
/* Transmission Mailbox 2 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->TxMailbox2AbortCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
}
@@ -1437,8 +1853,13 @@
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
/* Receive FIFO 0 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo0FullCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1449,8 +1870,13 @@
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
{
/* Receive FIFO 0 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo0MsgPendingCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1476,8 +1902,13 @@
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
/* Receive FIFO 1 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo1FullCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1488,8 +1919,13 @@
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
{
/* Receive FIFO 1 mesage pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->RxFifo1MsgPendingCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1502,8 +1938,13 @@
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
/* Sleep Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->SleepCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1516,8 +1957,13 @@
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
/* WakeUp Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->WakeUpFromRxMsgCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
@@ -1606,8 +2052,13 @@
hcan->ErrorCode |= errorcode;
/* Call Error callback function */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+ /* Call registered callback*/
+ hcan->ErrorCallback(hcan);
+#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
diff --git a/Src/stm32f0xx_hal_cec.c b/Src/stm32f0xx_hal_cec.c
index 3c93dc5..dfbfdcb 100644
--- a/Src/stm32f0xx_hal_cec.c
+++ b/Src/stm32f0xx_hal_cec.c
@@ -3,94 +3,125 @@
* @file stm32f0xx_hal_cec.c
* @author MCD Application Team
* @brief CEC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the High Definition Multimedia Interface
+ * This file provides firmware functions to manage the following
+ * functionalities of the High Definition Multimedia Interface
* Consumer Electronics Control Peripheral (CEC).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
+ * + Initialization and de-initialization function
+ * + IO operation function
+ * + Peripheral Control function
*
- *
- @verbatim
+ *
+ @verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The CEC HAL driver can be used as follow:
-
+
(#) Declare a CEC_HandleTypeDef handle structure.
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
(##) Enable the CEC interface clock.
(##) CEC pins configuration:
- (+) Enable the clock for the CEC GPIOs.
- (+) Configure these CEC pins as alternate function pull-up.
+ (+++) Enable the clock for the CEC GPIOs.
+ (+++) Configure these CEC pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
- (+) Configure the CEC interrupt priority.
- (+) Enable the NVIC CEC IRQ handle.
- (@) The specific CEC interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
- and receive process.
+ (+++) Configure the CEC interrupt priority.
+ (+++) Enable the NVIC CEC IRQ handle.
+ (+++) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
in case of Bit Rising Error, Error-Bit generation conditions, device logical
address and Listen mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
-
- (@) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_CEC_MspInit() API.
+ [..]
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
+ to register an interrupt callback.
+
+ Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CEC MspInit.
+ (+) MspDeInitCallback : CEC MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
+ @ref HAL_CEC_RegisterRxCpltCallback().
+
+ Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Transfer completed callback.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : CEC MspInit.
+ (+) MspDeInitCallback : CEC MspDeInit.
+
+ For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
+ @ref HAL_CEC_UnRegisterRxCpltCallback().
+
+ By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
+ all callbacks are set to the corresponding weak functions :
+ examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
+ keep and use the user MspInit/MspDeInit functions (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
+ Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
+ in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
+ or @ref HAL_CEC_Init() function.
+
+ When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
-#ifdef HAL_CEC_MODULE_ENABLED
-
-#if defined(STM32F042x6) || defined(STM32F048xx) ||\
- defined(STM32F051x8) || defined(STM32F058xx) ||\
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||\
- defined(STM32F091xC) || defined (STM32F098xx)
-
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
-/** @defgroup CEC CEC
+/** @defgroup CEC CEC
* @brief HAL CEC module driver
* @{
*/
+#ifdef HAL_CEC_MODULE_ENABLED
+#if defined (CEC)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -100,7 +131,7 @@
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -110,7 +141,7 @@
/**
* @}
*/
-
+
/* Exported functions ---------------------------------------------------------*/
/** @defgroup CEC_Exported_Functions CEC Exported Functions
@@ -118,17 +149,17 @@
*/
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the CEC
- (+) The following parameters need to be configured:
+ (+) The following parameters need to be configured:
(++) SignalFreeTime
- (++) Tolerance
+ (++) Tolerance
(++) BRERxStop (RX stopped or not upon Bit Rising Error)
(++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
(++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
@@ -148,79 +179,101 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
-{
+{
/* Check the CEC handle allocation */
- if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
+ if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
- /* Check the parameters */
+ /* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
- assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
+ assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
- assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
+ assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
- assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
+ assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
- if(hcec->gState == HAL_CEC_STATE_RESET)
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcec->Lock = HAL_UNLOCKED;
+
+ hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hcec->MspInitCallback == NULL)
+ {
+ hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hcec->MspInitCallback(hcec);
+ }
+#else
+ if (hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
hcec->gState = HAL_CEC_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
-
+
/* Write to CEC Control Register */
- hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
- hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
- hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
+ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
+ hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
hcec->Init.ListenMode;
-
+
/* Enable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+ CEC_IER_TX_ALL_ERR);
+
/* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
-
+
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_READY;
hcec->RxState = HAL_CEC_STATE_READY;
-
+
return HAL_OK;
}
/**
- * @brief DeInitializes the CEC peripheral
+ * @brief DeInitializes the CEC peripheral
* @param hcec CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
- if(hcec == NULL)
+ if (hcec == NULL)
{
return HAL_ERROR;
}
@@ -229,46 +282,59 @@
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
hcec->gState = HAL_CEC_STATE_BUSY;
-
+
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+ if (hcec->MspDeInitCallback == NULL)
+ {
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware */
+ hcec->MspDeInitCallback(hcec);
+
+#else
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
-
+
/* Clear Flags */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
-
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR);
+
/* Disable the following CEC Transmission/Reception interrupts as
- * well as the following CEC Transmission/Reception Errors interrupts
- * Rx Byte Received IT
- * End of Reception IT
- * Rx overrun
- * Rx bit rising error
- * Rx short bit period error
- * Rx long bit period error
- * Rx missing acknowledge
- * Tx Byte Request IT
- * End of Transmission IT
- * Tx Missing Acknowledge IT
- * Tx-Error IT
- * Tx-Buffer Underrun IT
- * Tx arbitration lost */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
-
+ * well as the following CEC Transmission/Reception Errors interrupts
+ * Rx Byte Received IT
+ * End of Reception IT
+ * Rx overrun
+ * Rx bit rising error
+ * Rx short bit period error
+ * Rx long bit period error
+ * Rx missing acknowledge
+ * Tx Byte Request IT
+ * End of Transmission IT
+ * Tx Missing Acknowledge IT
+ * Tx-Error IT
+ * Tx-Buffer Underrun IT
+ * Tx arbitration lost */
+ __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND |
+ CEC_IER_TX_ALL_ERR);
+
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_RESET;
hcec->RxState = HAL_CEC_STATE_RESET;
-
+
/* Process Unlock */
__HAL_UNLOCK(hcec);
-
+
return HAL_OK;
}
/**
* @brief Initializes the Own Address of the CEC device
* @param hcec CEC handle
- * @param CEC_OwnAddress The CEC own address.
+ * @param CEC_OwnAddress The CEC own address.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
@@ -277,34 +343,34 @@
assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
- {
+ {
/* Process Locked */
- __HAL_LOCK(hcec);
-
+ __HAL_LOCK(hcec);
+
hcec->gState = HAL_CEC_STATE_BUSY;
-
+
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
-
- if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+
+ if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
{
- hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16U);
+ hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16);
}
else
{
hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
}
-
+
hcec->gState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
+ __HAL_UNLOCK(hcec);
+
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
-
- return HAL_OK;
+
+ return HAL_OK;
}
else
{
@@ -317,13 +383,13 @@
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspInit can be implemented in the user file
- */
+ */
}
/**
@@ -331,40 +397,278 @@
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspDeInit can be implemented in the user file
- */
+ */
}
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User CEC Callback
+ * To be used instead of the weak predefined callback
+ * @param hcec CEC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
+ pCEC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_TX_CPLT_CB_ID :
+ hcec->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_CEC_ERROR_CB_ID :
+ hcec->ErrorCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = pCallback;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an CEC Callback
+ * CEC callabck is redirected to the weak predefined callback
+ * @param hcec uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_TX_CPLT_CB_ID :
+ hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_CEC_ERROR_CB_ID :
+ hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = HAL_CEC_MspInit;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hcec->gState == HAL_CEC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_CEC_MSPINIT_CB_ID :
+ hcec->MspInitCallback = HAL_CEC_MspInit;
+ break;
+
+ case HAL_CEC_MSPDEINIT_CB_ID :
+ hcec->MspDeInitCallback = HAL_CEC_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+
+ return status;
+}
+
+/**
+ * @brief Register CEC RX complete Callback
+ * To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback
+ * @param hcec CEC handle
+ * @param pCallback pointer to the Rx transfer compelete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (HAL_CEC_STATE_READY == hcec->RxState)
+ {
+ hcec->RxCpltCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+ return status;
+}
+
+/**
+ * @brief UnRegister CEC RX complete Callback
+ * CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback
+ * @param hcec CEC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hcec);
+
+ if (HAL_CEC_STATE_READY == hcec->RxState)
+ {
+ hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcec);
+ return status;
+}
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
- * @brief CEC Transmit/Receive functions
+/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief CEC Transmit/Receive functions
*
-@verbatim
+@verbatim
===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
This subsection provides a set of functions allowing to manage the CEC data transfers.
-
+
(#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
- logical addresses (4-bit long addresses, 0x0F for broadcast messages destination)
-
- (#) The communication is performed using Interrupts.
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+
+ (#) The communication is performed using Interrupts.
These API's return the HAL status.
- The end of the data processing will be indicated through the
+ The end of the data processing will be indicated through the
dedicated CEC IRQ when using Interrupt mode.
- The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
- The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback() user callback will be executed when a communication
error is detected
-
+
(#) API's with Interrupt are :
(+) HAL_CEC_Transmit_IT()
(+) HAL_CEC_IRQHandler()
@@ -373,35 +677,36 @@
(+) HAL_CEC_TxCpltCallback()
(+) HAL_CEC_RxCpltCallback()
(+) HAL_CEC_ErrorCallback()
-
+
@endverbatim
* @{
*/
/**
- * @brief Send data in interrupt mode
- * @param hcec CEC handle
+ * @brief Send data in interrupt mode
+ * @param hcec CEC handle
* @param InitiatorAddress Initiator address
- * @param DestinationAddress destination logical address
+ * @param DestinationAddress destination logical address
* @param pData pointer to input byte data buffer
* @param Size amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+ */
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
+ uint8_t *pData, uint32_t Size)
{
/* if the IP isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
- if (hcec->gState == HAL_CEC_STATE_READY)
- {
- if((pData == NULL ) && (Size > 0U))
+ if (hcec->gState == HAL_CEC_STATE_READY)
+ {
+ if ((pData == NULL) && (Size > 0U))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
- assert_param(IS_CEC_ADDRESS(DestinationAddress));
- assert_param(IS_CEC_ADDRESS(InitiatorAddress));
+ assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_ADDRESS(InitiatorAddress));
assert_param(IS_CEC_MSGSIZE(Size));
/* Process Locked */
@@ -409,11 +714,11 @@
hcec->pTxBuffPtr = pData;
hcec->gState = HAL_CEC_STATE_BUSY_TX;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
+
/* initialize the number of bytes to send,
- * 0 means only one header is sent (ping operation) */
- hcec->TxXferCount = Size;
-
+ * 0 means only one header is sent (ping operation) */
+ hcec->TxXferCount = (uint16_t)Size;
+
/* in case of no payload (Size = 0), sender is only pinging the system;
Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
if (Size == 0U)
@@ -422,13 +727,14 @@
}
/* send header block */
- hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
+ hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress);
+
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
+ __HAL_UNLOCK(hcec);
+
return HAL_OK;
}
@@ -452,14 +758,14 @@
* @brief Change Rx Buffer.
* @param hcec CEC handle
* @param Rxbuffer Rx Buffer
- * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
+ * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size
*/
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer)
{
- hcec->Init.RxBuffer = Rxbuffer;
+ hcec->Init.RxBuffer = Rxbuffer;
}
-
+
/**
* @brief This function handles CEC interrupt requests.
* @param hcec CEC handle
@@ -467,102 +773,125 @@
*/
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
{
-
+
/* save interrupts register for further error or interrupts handling purposes */
- uint32_t reg = 0U;
+ uint32_t reg;
reg = hcec->Instance->ISR;
-
- /* ----------------------------Arbitration Lost Management----------------------------------*/
+
+ /* ----------------------------Arbitration Lost Management----------------------------------*/
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
- if((reg & CEC_FLAG_ARBLST) != RESET)
- {
+ if ((reg & CEC_FLAG_ARBLST) != 0U)
+ {
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
}
-
- /* ----------------------------Rx Management----------------------------------*/
+
+ /* ----------------------------Rx Management----------------------------------*/
/* CEC RX byte received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXBR) != RESET)
- {
- /* reception is starting */
+ if ((reg & CEC_FLAG_RXBR) != 0U)
+ {
+ /* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
hcec->RxXferSize++;
/* read received byte */
- *hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
+ *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR;
+ hcec->Init.RxBuffer++;
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
}
-
+
/* CEC RX end received interrupt ---------------------------------------------------*/
- if((reg & CEC_FLAG_RXEND) != RESET)
- {
+ if ((reg & CEC_FLAG_RXEND) != 0U)
+ {
/* clear IT */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
-
+
/* Rx process is completed, restore hcec->RxState to Ready */
- hcec->RxState = HAL_CEC_STATE_READY;
+ hcec->RxState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->Init.RxBuffer -= hcec->RxXferSize;
- HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
- hcec->RxXferSize = 0U;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->RxCpltCallback(hcec, hcec->RxXferSize);
+#else
+ HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+ hcec->RxXferSize = 0U;
}
-
- /* ----------------------------Tx Management----------------------------------*/
+
+ /* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXBR) != RESET)
+ if ((reg & CEC_FLAG_TXBR) != 0U)
{
if (hcec->TxXferCount == 0U)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+ hcec->pTxBuffPtr++;
}
else
- {
- hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
+ {
+ hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+ hcec->pTxBuffPtr++;
hcec->TxXferCount--;
- }
+ }
/* clear Tx-Byte request flag */
- __HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
- }
-
+ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
+ }
+
/* CEC TX end interrupt ------------------------------------------------*/
- if((reg & CEC_FLAG_TXEND) != RESET)
- {
+ if ((reg & CEC_FLAG_TXEND) != 0U)
+ {
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
-
- /* Tx process is ended, restore hcec->gState to Ready */
+
+ /* Tx process is ended, restore hcec->gState to Ready */
hcec->gState = HAL_CEC_STATE_READY;
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->TxCpltCallback(hcec);
+#else
HAL_CEC_TxCpltCallback(hcec);
- }
-
- /* ----------------------------Rx/Tx Error Management----------------------------------*/
- if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0U)
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
+ }
+
+ /* ----------------------------Rx/Tx Error Management----------------------------------*/
+ if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
+ CEC_ISR_TXACKE)) != 0U)
{
hcec->ErrorCode = reg;
- __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
+ __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
+ HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
-
- if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
+
+ if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
{
- hcec->Init.RxBuffer-=hcec->RxXferSize;
- hcec->RxXferSize = 0U;
+ hcec->Init.RxBuffer -= hcec->RxXferSize;
+ hcec->RxXferSize = 0U;
hcec->RxState = HAL_CEC_STATE_READY;
}
- else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
- {
+ else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
+ {
/* Set the CEC state ready to be able to start again the process */
hcec->gState = HAL_CEC_STATE_READY;
- }
-
- /* Error Call Back */
+ }
+ else
+ {
+ /* Nothing todo*/
+ }
+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U)
+ hcec->ErrorCallback(hcec);
+#else
+ /* Error Call Back */
HAL_CEC_ErrorCallback(hcec);
+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
}
-
+ else
+ {
+ /* Nothing todo*/
+ }
}
/**
@@ -570,13 +899,13 @@
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hcec);
+ UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_TxCpltCallback can be implemented in the user file
- */
+ */
}
/**
@@ -600,29 +929,29 @@
* @param hcec CEC handle
* @retval None
*/
- __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_ErrorCallback can be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
- * @brief CEC control functions
+/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
+ * @brief CEC control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control function #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the CEC.
- (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
+ (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
@endverbatim
* @{
*/
@@ -634,16 +963,16 @@
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
{
- uint32_t temp1 = 0x00U, temp2 = 0x00U;
+ uint32_t temp1, temp2;
temp1 = hcec->gState;
temp2 = hcec->RxState;
-
+
return (HAL_CEC_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the CEC error code
- * @param hcec pointer to a CEC_HandleTypeDef structure that contains
+ * @param hcec pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC.
* @retval CEC Error Code
*/
@@ -659,18 +988,14 @@
/**
* @}
*/
-
+#endif /* CEC */
+#endif /* HAL_CEC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
- */
-#endif /* defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || */
- /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
- /* defined(STM32F091xC) || defined (STM32F098xx) */
-
-#endif /* HAL_CEC_MODULE_ENABLED */
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_comp.c b/Src/stm32f0xx_hal_comp.c
index a2d9c2d..bd04bed 100644
--- a/Src/stm32f0xx_hal_comp.c
+++ b/Src/stm32f0xx_hal_comp.c
@@ -75,36 +75,79 @@
(#) For safety purposes comparator(s) can be locked using HAL_COMP_Lock() function.
Only a MCU reset can reset that protection.
-
+
+ *** Callback registration ***
+ =============================================
+ [..]
+
+ The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_COMP_RegisterCallback()
+ to register an interrupt callback.
+ [..]
+
+ Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
+ (+) OperationCpltCallback : callback for End of operation.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+
+ Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
+ weak function.
+ [..]
+
+ @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) OperationCpltCallback : callback for End of operation.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+
+ By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_COMP_OperationCpltCallback(), @ref HAL_COMP_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ [..]
+
+ If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+
+ Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ [..]
+
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
+ or @ref HAL_COMP_Init() function.
+ [..]
+
+ When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/*
@@ -161,9 +204,7 @@
#ifdef HAL_COMP_MODULE_ENABLED
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined (STM32F098xx)
+#if defined (COMP1) || defined (COMP2)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
@@ -264,9 +305,22 @@
/* Init SYSCFG and the low level hardware to access comparators */
__HAL_RCC_SYSCFG_CLK_ENABLE();
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ /* Init the COMP Callback settings */
+ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
+ if (hcomp->MspInitCallback == NULL)
+ {
+ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware */
+ hcomp->MspInitCallback(hcomp);
+#else
/* Init the low level hardware : SYSCFG to access comparators */
HAL_COMP_MspInit(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
if(hcomp->State == HAL_COMP_STATE_RESET)
{
@@ -340,9 +394,19 @@
MODIFY_REG(COMP->CSR,
COMP_CSR_RESET_PARAMETERS_MASK << regshift,
COMP_CSR_RESET_VALUE << regshift);
-
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ if (hcomp->MspDeInitCallback == NULL)
+ {
+ hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
+ hcomp->MspDeInitCallback(hcomp);
+#else
/* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
HAL_COMP_MspDeInit(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
hcomp->State = HAL_COMP_STATE_RESET;
@@ -383,6 +447,166 @@
*/
}
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User COMP Callback
+ * To be used instead of the weak predefined callback
+ * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
+ * the configuration information for the specified COMP.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
+ * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ if (HAL_COMP_STATE_READY == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_TRIGGER_CB_ID :
+ hcomp->TriggerCallback = pCallback;
+ break;
+
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_COMP_STATE_RESET == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = pCallback;
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Unregister a COMP Callback
+ * COMP callback is redirected to the weak predefined callback
+ * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
+ * the configuration information for the specified COMP.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
+ * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (HAL_COMP_STATE_READY == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_TRIGGER_CB_ID :
+ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
+ break;
+
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_COMP_STATE_RESET == hcomp->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_COMP_MSPINIT_CB_ID :
+ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_COMP_MSPDEINIT_CB_ID :
+ hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ return status;
+}
+
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -570,8 +794,12 @@
/* Clear COMP Exti pending bit */
WRITE_REG(EXTI->PR, extiline);
- /* COMP trigger user callback */
- HAL_COMP_TriggerCallback(hcomp);
+ /* COMP trigger callback */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+ hcomp->TriggerCallback(hcomp);
+#else
+ HAL_COMP_TriggerCallback(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
}
@@ -667,7 +895,7 @@
}
/**
- * @brief Comparator callback.
+ * @brief Comparator trigger callback.
* @param hcomp COMP handle
* @retval None
*/
@@ -719,6 +947,20 @@
return hcomp->State;
}
+
+/**
+ * @brief Return the COMP error code.
+ * @param hcomp COMP handle
+ * @retval COMP error code
+ */
+uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
+{
+ /* Check the parameters */
+ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+ return hcomp->ErrorCode;
+}
+
/**
* @}
*/
@@ -735,9 +977,7 @@
* @}
*/
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || defined (STM32F098xx) */
+#endif /* COMP1 || COMP2 */
#endif /* HAL_COMP_MODULE_ENABLED */
diff --git a/Src/stm32f0xx_hal_cortex.c b/Src/stm32f0xx_hal_cortex.c
index fba72d3..157426e 100644
--- a/Src/stm32f0xx_hal_cortex.c
+++ b/Src/stm32f0xx_hal_cortex.c
@@ -68,31 +68,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_hal_crc.c b/Src/stm32f0xx_hal_crc.c
index cd94ee2..a4b3d16 100644
--- a/Src/stm32f0xx_hal_crc.c
+++ b/Src/stm32f0xx_hal_crc.c
@@ -3,12 +3,12 @@
* @file stm32f0xx_hal_crc.c
* @author MCD Application Team
* @brief CRC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
===============================================================================
##### How to use this driver #####
@@ -16,44 +16,28 @@
[..]
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(+) Initialize CRC calculator
- (++)specify generating polynomial (IP default or non-default one)
- (++)specify initialization value (IP default or non-default one)
- (++)specify input data format
- (++)specify input or output data inversion mode if any
- (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
- input data buffer starting with the previously computed CRC as
+ (++) specify generating polynomial (peripheral default or non-default one)
+ (++) specify initialization value (peripheral default or non-default one)
+ (++) specify input data format
+ (++) specify input or output data inversion mode if any
+ (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
+ input data buffer starting with the previously computed CRC as
initialization value
- (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
- input data buffer starting with the defined initialization value
+ (+) Use HAL_CRC_Calculate() function to compute the CRC value of the
+ input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -78,8 +62,8 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
+ * @{
+ */
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/**
@@ -92,124 +76,133 @@
* @{
*/
-/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions.
+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions.
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Initialize the CRC according to the specified parameters
+ (+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP (MCU Specific Package)
(+) DeInitialize the CRC MSP
-
+
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
- * parameters in the CRC_InitTypeDef and initialize the associated handle.
+ * parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
- if(hcrc == NULL)
+ if (hcrc == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
- if(hcrc->State == HAL_CRC_STATE_RESET)
- {
+ if (hcrc->State == HAL_CRC_STATE_RESET)
+ {
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
-
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
-
- hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Extended initialization: if programmable polynomial feature is
- applicable to device, set default or non-default generating
- polynomial according to hcrc->Init parameters.
- If feature is non-applicable to device in use, HAL_CRCEx_Init straight
- away reports HAL_OK. */
- if (HAL_CRCEx_Init(hcrc) != HAL_OK)
+
+ hcrc->State = HAL_CRC_STATE_BUSY;
+
+#if defined(CRC_POL_POL)
+ /* check whether or not non-default generating polynomial has been
+ * picked up by user */
+ assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
+ if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
- return HAL_ERROR;
+ /* initialize peripheral with default generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
}
-
- /* check whether or not non-default CRC initial value has been
+ else
+ {
+ /* initialize CRC peripheral with generating polynomial defined by user */
+ if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+#endif /* CRC_POL_POL */
+
+ /* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
- WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
+ WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
}
-
+
/* set input data inversion mode */
- assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
-
+ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
+
/* set output data inversion mode */
- assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
-
+ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
+
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief DeInitialize the CRC peripheral.
+ * @brief DeInitialize the CRC peripheral.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
-{
+{
/* Check the CRC handle allocation */
- if(hcrc == NULL)
+ if (hcrc == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
+
/* Check the CRC peripheral state */
- if(hcrc->State == HAL_CRC_STATE_BUSY)
+ if (hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
-
+
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
-
+
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
-
+
/* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR) ;
+ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
@@ -258,32 +251,32 @@
* @}
*/
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions.
+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief management functions.
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
- (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
- using the combination of the previous CRC value and the new one
-
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
+ using combination of the previous CRC value and the new one.
+
[..] or
-
- (+) compute the 7U, 8U, 16 or 32-bit CRC value of an 8U, 16 or 32-bit data buffer
+
+ (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
-/**
+/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
- * provided by hcrc->InputDataFormat.
+ * provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
@@ -295,125 +288,111 @@
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0U; /* CRC input data buffer index */
+ uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
+
+ /* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
-
+
switch (hcrc->InputDataFormat)
{
- case CRC_INPUTDATA_FORMAT_WORDS:
+ case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
+ for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
-
- case CRC_INPUTDATA_FORMAT_BYTES:
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
-
- case CRC_INPUTDATA_FORMAT_HALFWORDS:
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
-
default:
- break;
+ break;
}
-
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
+
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return the CRC computed value */
return temp;
}
-
-/**
+/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer, exact input data format is
- * provided by hcrc->InputDataFormat.
+ * provided by hcrc->InputDataFormat.
* @param BufferLength input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
- * handle field hcrc->InputDataFormat.
+ * handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
+ */
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0U; /* CRC input data buffer index */
+ uint32_t index; /* CRC input data buffer index */
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
-
- /* Process locked */
- __HAL_LOCK(hcrc);
-
- /* Change CRC peripheral state */
+
+ /* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
-
- /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
+
+ /* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
-
+
switch (hcrc->InputDataFormat)
{
- case CRC_INPUTDATA_FORMAT_WORDS:
+ case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
- for(index = 0U; index < BufferLength; index++)
+ for (index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
-
- case CRC_INPUTDATA_FORMAT_BYTES:
+
+ case CRC_INPUTDATA_FORMAT_BYTES:
/* Specific 8-bit input data handling */
- temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
+ temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
break;
-
- case CRC_INPUTDATA_FORMAT_HALFWORDS:
+
+ case CRC_INPUTDATA_FORMAT_HALFWORDS:
/* Specific 16-bit input data handling */
- temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
+ temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
break;
-
+
default:
- break;
+ break;
}
- /* Change CRC peripheral state */
- hcrc->State = HAL_CRC_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcrc);
-
- /* Return the CRC computed value */
+ /* Change CRC peripheral state */
+ hcrc->State = HAL_CRC_STATE_READY;
+
+ /* Return the CRC computed value */
return temp;
}
-
+
/**
* @}
*/
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
+ * @brief Peripheral State functions.
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@@ -440,13 +419,13 @@
* @}
*/
-/** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
+/** @addtogroup CRC_Private_Functions
+ * @{
+ */
-/**
+/**
* @brief Enter 8-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
+ * Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
@@ -454,71 +433,81 @@
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
- uint32_t i = 0U; /* input data buffer index */
-
- /* Processing time optimization: 4 bytes are entered in a row with a single word write,
- * last bytes must be carefully fed to the CRC calculator to ensure a correct type
- * handling by the IP */
- for(i = 0U; i < (BufferLength/4U); i++)
- {
- hcrc->Instance->DR = ((uint32_t)pBuffer[4U*i]<<24U) | ((uint32_t)pBuffer[4U*i+1]<<16U) | ((uint32_t)pBuffer[4U*i+2]<<8U) | (uint32_t)pBuffer[4U*i+3];
- }
- /* last bytes specific handling */
- if ((BufferLength%4U) != 0U)
- {
- if (BufferLength%4U == 1U)
- {
- *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i];
- }
- if (BufferLength%4U == 2U)
- {
- *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
- }
- if (BufferLength%4U == 3U)
- {
- *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
- *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
- }
- }
-
- /* Return the CRC computed value */
+ uint32_t i; /* input data buffer index */
+ uint16_t data;
+ __IO uint16_t *pReg;
+
+ /* Processing time optimization: 4 bytes are entered in a row with a single word write,
+ * last bytes must be carefully fed to the CRC calculator to ensure a correct type
+ * handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 4U); i++)
+ {
+ hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
+ ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
+ ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
+ (uint32_t)pBuffer[(4U * i) + 3U];
+ }
+ /* last bytes specific handling */
+ if ((BufferLength % 4U) != 0U)
+ {
+ if ((BufferLength % 4U) == 1U)
+ {
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
+ }
+ if ((BufferLength % 4U) == 2U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+ }
+ if ((BufferLength % 4U) == 3U)
+ {
+ data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = data;
+
+ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
+ }
+ }
+
+ /* Return the CRC computed value */
return hcrc->Instance->DR;
}
-
-
-/**
+/**
* @brief Enter 16-bit input data to the CRC calculator.
- * Specific data handling to optimize processing time.
+ * Specific data handling to optimize processing time.
* @param hcrc CRC handle
* @param pBuffer pointer to the input data buffer
* @param BufferLength input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
- */
+ */
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
- uint32_t i = 0U; /* input data buffer index */
-
+ uint32_t i; /* input data buffer index */
+ __IO uint16_t *pReg;
+
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
- * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
- * a correct type handling by the IP */
- for(i = 0U; i < (BufferLength/2U); i++)
+ * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
+ * a correct type handling by the peripheral */
+ for (i = 0U; i < (BufferLength / 2U); i++)
{
- hcrc->Instance->DR = ((uint32_t)pBuffer[2U*i]<<16U) | (uint32_t)pBuffer[2U*i+1];
+ hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
}
- if ((BufferLength%2U) != 0U)
+ if ((BufferLength % 2U) != 0U)
{
- *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2*i];
+ pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
+ *pReg = pBuffer[2U * i];
}
-
- /* Return the CRC computed value */
+
+ /* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @}
*/
-
+
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
diff --git a/Src/stm32f0xx_hal_crc_ex.c b/Src/stm32f0xx_hal_crc_ex.c
index 0259170..08eaa62 100644
--- a/Src/stm32f0xx_hal_crc_ex.c
+++ b/Src/stm32f0xx_hal_crc_ex.c
@@ -3,48 +3,30 @@
* @file stm32f0xx_hal_crc_ex.c
* @author MCD Application Team
* @brief Extended CRC HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the CRC peripheral:
- * + Extended initialization functions
- *
+ * This file provides firmware functions to manage the extended
+ * functionalities of the CRC peripheral.
+ *
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
- (+) Extended initialization
- (+) Set or not user-defined generating
- polynomial other than default one
+ (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+ (+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -54,7 +36,7 @@
* @{
*/
-/** @defgroup CRCEx CRCEx
+/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
@@ -66,86 +48,129 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Functions CRCEx Exported Functions
+/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
* @brief Extended Initialization and Configuration functions.
*
-@verbatim
+@verbatim
===============================================================================
- ##### Initialization and Configuration functions #####
+ ##### Extended configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Initialize the CRC generating polynomial: if programmable polynomial
- feature is applicable to device, set default or non-default generating
- polynomial according to hcrc->Init.DefaultPolynomialUse parameter.
- If feature is non-applicable to device in use, HAL_CRCEx_Init straight
- away reports HAL_OK.
- (+) Set the generating polynomial
-
+ (+) Configure the generating polynomial
+ (+) Configure the input data inversion
+ (+) Configure the output data inversion
+
@endverbatim
* @{
*/
+#if defined(CRC_POL_POL)
/**
- * @brief Extended initialization to set generating polynomial
- * @param hcrc CRC handle
+ * @brief Initialize the CRC polynomial if different from default one.
+ * @param hcrc CRC handle
+ * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
+ * This parameter is written in normal representation, e.g.
+ * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
+ * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
+ * @param PolyLength CRC polynomial length.
+ * This parameter can be one of the following values:
+ * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
+ * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
+ * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
+ * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Init(CRC_HandleTypeDef *hcrc)
+ */
+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined (STM32F098xx)
- /* check whether or not non-default generating polynomial has been
- * picked up by user */
- assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
- if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
- {
- /* initialize IP with default generating polynomial */
- WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
- }
- else
- {
- /* initialize CRC IP with generating polynomial defined by user */
- if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
- {
- return HAL_ERROR;
- }
- }
-#endif /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined (STM32F098xx) */
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
- return HAL_OK;
+ /* Check the parameters */
+ assert_param(IS_CRC_POL_LENGTH(PolyLength));
+
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ {
+ }
+
+ switch (PolyLength)
+ {
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ if (status == HAL_OK)
+ {
+ /* set generating polynomial */
+ WRITE_REG(hcrc->Instance->POL, Pol);
+
+ /* set generating polynomial size */
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
+ }
+ /* Return function status */
+ return status;
}
+#endif /* CRC_POL_POL */
/**
* @brief Set the Reverse Input data mode.
* @param hcrc CRC handle
- * @param InputReverseMode Input Data inversion mode
+ * @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
- * @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
- * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
- * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
+ * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
+ * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
-{
+{
/* Check the parameters */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
-
+
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set input data inversion mode */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -153,100 +178,32 @@
/**
* @brief Set the Reverse Output data mode.
* @param hcrc CRC handle
- * @param OutputReverseMode Output Data inversion mode
+ * @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
- * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
- * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
+ * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
-
+
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set output data inversion mode */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
-
+ MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
+
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
-#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx)
-/**
- * @brief Initializes the CRC polynomial if different from default one.
- * @param hcrc CRC handle
- * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long)
- * This parameter is written in normal representation, e.g.
- * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
- * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
- * @param PolyLength CRC polynomial length
- * This parameter can be one of the following values:
- * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
- * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
- * @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
- * @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
-{
- uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
- /* Check the parameters */
- assert_param(IS_CRC_POL_LENGTH(PolyLength));
-
- /* check polynomial definition vs polynomial size:
- * polynomial length must be aligned with polynomial
- * definition. HAL_ERROR is reported if Pol degree is
- * larger than that indicated by PolyLength.
- * Look for MSB position: msb will contain the degree of
- * the second to the largest polynomial member. E.g., for
- * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while (((Pol & (1U << msb)) == 0U) && (msb-- > 0U))
- {}
- switch (PolyLength)
- {
- case CRC_POLYLENGTH_7B:
- if (msb >= HAL_CRC_LENGTH_7B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_8B:
- if (msb >= HAL_CRC_LENGTH_8B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_16B:
- if (msb >= HAL_CRC_LENGTH_16B)
- {
- return HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_32B:
- /* no polynomial definition vs. polynomial length issue possible */
- break;
- default:
- break;
- }
-
- /* set generating polynomial */
- WRITE_REG(hcrc->Instance->POL, Pol);
-
- /* set generating polynomial size */
- MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
-
- /* Return function status */
- return HAL_OK;
-}
-#endif /* #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F091xC) || defined (STM32F098xx) */
/**
* @}
diff --git a/Src/stm32f0xx_hal_dac.c b/Src/stm32f0xx_hal_dac.c
index f3b658d..a52c16a 100644
--- a/Src/stm32f0xx_hal_dac.c
+++ b/Src/stm32f0xx_hal_dac.c
@@ -148,7 +148,63 @@
HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+ (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
+ (+) DMAUnderrunCallbackCh1 : callback when an error occurs on Ch1.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) DMAUnderrunCallbackCh2 : callback when an error occurs on Ch2.
+ (+) MspInitCallback : DAC MspInit.
+ (+) MspDeInitCallback : DAC MspdeInit.
+ (+) All Callbacks
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+ By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
+ and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
+ or @ref HAL_DAC_Init function.
+
+ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
*** DAC HAL driver macros list ***
=============================================
[..]
@@ -166,32 +222,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
@@ -203,9 +243,7 @@
#ifdef HAL_DAC_MODULE_ENABLED
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined (STM32F098xx)
+#if defined (DAC1)
/** @defgroup DAC DAC
* @brief DAC driver modules
@@ -269,13 +307,36 @@
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
- if(hdac->State == HAL_DAC_STATE_RESET)
- {
+ if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the DAC Callback settings */
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+ if (hdac->MspInitCallback == NULL)
+ {
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ }
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ /* Init the low level hardware */
+ hdac->MspInitCallback(hdac);
+#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
@@ -311,8 +372,18 @@
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ if(hdac->MspDeInitCallback == NULL)
+ {
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hdac->MspDeInitCallback(hdac);
+
+#else
/* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
@@ -496,11 +567,9 @@
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
-#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined (STM32F098xx)
- /* Does not apply to STM32F051x8 & STM32F058xx */
+#if defined(DAC_CHANNEL2_SUPPORT)
- else /* Channel2 is used for */
+ else /* Channel2 is used */
{
/* Disable the DMA channel */
status = HAL_DMA_Abort(hdac->DMA_Handle2);
@@ -508,8 +577,7 @@
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
-#endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+#endif /* DAC_CHANNEL2_SUPPORT */
/* Check if DMA Channel effectively disabled */
if (status != HAL_OK)
@@ -768,12 +836,249 @@
* @}
*/
+/** @addtogroup DAC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+ * @{
+ */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User DAC Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
+ *
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+ pDAC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if (hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = pCallback;
+ break;
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = pCallback;
+ break;
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = pCallback;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+
+/**
+ * @brief Unregister a User DAC Callback
+ * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * @param hdac DAC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdac);
+
+ if (hdac->State == HAL_DAC_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_CH1_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ break;
+ case HAL_DAC_CH1_ERROR_ID :
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ break;
+ case HAL_DAC_CH1_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+ break;
+ case HAL_DAC_CH2_COMPLETE_CB_ID :
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ break;
+ case HAL_DAC_CH2_ERROR_ID :
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ break;
+ case HAL_DAC_CH2_UNDERRUN_CB_ID :
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ break;
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ case HAL_DAC_ALL_CB_ID :
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+ hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+ hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hdac->State == HAL_DAC_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DAC_MSPINIT_CB_ID :
+ hdac->MspInitCallback = HAL_DAC_MspInit;
+ break;
+ case HAL_DAC_MSPDEINIT_CB_ID :
+ hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdac);
+ return status;
+}
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
/**
* @}
*/
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+#endif /* DAC1 */
#endif /* HAL_DAC_MODULE_ENABLED */
diff --git a/Src/stm32f0xx_hal_dac_ex.c b/Src/stm32f0xx_hal_dac_ex.c
index 7ff936d..b95ea6e 100644
--- a/Src/stm32f0xx_hal_dac_ex.c
+++ b/Src/stm32f0xx_hal_dac_ex.c
@@ -22,32 +22,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
@@ -774,7 +758,11 @@
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvCpltCallbackCh2(hdac);
+#else
HAL_DACEx_ConvCpltCallbackCh2(hdac);
+#endif
hdac->State= HAL_DAC_STATE_READY;
}
@@ -788,8 +776,13 @@
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
/* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ConvHalfCpltCallbackCh2(hdac);
+#else
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+#endif
}
/**
@@ -805,8 +798,11 @@
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+ hdac->ErrorCallbackCh2(hdac);
+#else
HAL_DACEx_ErrorCallbackCh2(hdac);
-
+#endif
hdac->State= HAL_DAC_STATE_READY;
}
diff --git a/Src/stm32f0xx_hal_dma.c b/Src/stm32f0xx_hal_dma.c
index 9bd69a0..0b3ab97 100644
--- a/Src/stm32f0xx_hal_dma.c
+++ b/Src/stm32f0xx_hal_dma.c
@@ -63,32 +63,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -195,12 +179,6 @@
by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
DMA_CalcBaseAndBitshift(hdma);
- /* Clean callbacks */
- hdma->XferCpltCallback = NULL;
- hdma->XferHalfCpltCallback = NULL;
- hdma->XferErrorCallback = NULL;
- hdma->XferAbortCallback = NULL;
-
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -251,10 +229,16 @@
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
- /* Initialize the error code */
+ /* Clean callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
+ /* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- /* Initialize the DMA state */
+ /* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */
@@ -395,27 +379,39 @@
/**
* @brief Abort the DMA Transfer.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
- /* Disable DMA IT */
- hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
-
- /* Disable the channel */
- hdma->Instance->CCR &= ~DMA_CCR_EN;
-
- /* Clear all flags */
- hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
-
- /* Change the DMA state*/
- hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_OK;
+ if(hdma->State != HAL_DMA_STATE_BUSY)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Disable DMA IT */
+ hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
+
+ /* Disable the channel */
+ hdma->Instance->CCR &= ~DMA_CCR_EN;
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
+ }
+ /* Change the DMA state*/
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ return HAL_OK;
}
/**
diff --git a/Src/stm32f0xx_hal_exti.c b/Src/stm32f0xx_hal_exti.c
new file mode 100644
index 0000000..cb99ac9
--- /dev/null
+++ b/Src/stm32f0xx_hal_exti.c
@@ -0,0 +1,559 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_exti.c
+ * @author MCD Application Team
+ * @brief EXTI HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### EXTI Peripheral features #####
+ ==============================================================================
+ [..]
+ (+) Each Exti line can be configured within this driver.
+
+ (+) Exti line can be configured in 3 different modes
+ (++) Interrupt
+ (++) Event
+ (++) Both of them
+
+ (+) Configurable Exti lines can be configured with 3 different triggers
+ (++) Rising
+ (++) Falling
+ (++) Both of them
+
+ (+) When set in interrupt mode, configurable Exti lines have two different
+ interrupts pending registers which allow to distinguish which transition
+ occurs:
+ (++) Rising edge pending interrupt
+ (++) Falling
+
+ (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+ be selected through multiplexer.
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+
+ (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+ (++) Choose the interrupt line number by setting "Line" member from
+ EXTI_ConfigTypeDef structure.
+ (++) Configure the interrupt and/or event mode using "Mode" member from
+ EXTI_ConfigTypeDef structure.
+ (++) For configurable lines, configure rising and/or falling trigger
+ "Trigger" member from EXTI_ConfigTypeDef structure.
+ (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+ member from GPIO_InitTypeDef structure.
+
+ (#) Get current Exti configuration of a dedicated line using
+ HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+ (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (++) Provide exiting handle as parameter.
+
+ (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+ (++) Provide exiting handle as first parameter.
+ (++) Provide which callback will be registered using one value from
+ EXTI_CallbackIDTypeDef.
+ (++) Provide callback function pointer.
+
+ (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+ (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+ * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+ * of bounds [0,3] in following API :
+ * HAL_EXTI_SetConfigLine
+ * HAL_EXTI_GetConfigLine
+ * HAL_EXTI_ClearConfigLine
+ */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+ * @brief Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Set configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on EXTI configuration to be set.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+ assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+ /* Assign line number to handle */
+ hexti->Line = pExtiConfig->Line;
+
+ /* Compute line mask */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* Configure triggers for configurable lines */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ {
+ assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+ /* Configure rising trigger */
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+ {
+ EXTI->RTSR |= maskline;
+ }
+ else
+ {
+ EXTI->RTSR &= ~maskline;
+ }
+
+ /* Configure falling trigger */
+ /* Mask or set line */
+ if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+ {
+ EXTI->FTSR |= maskline;
+ }
+ else
+ {
+ EXTI->FTSR &= ~maskline;
+ }
+
+
+ /* Configure gpio port selection in case of gpio exti line */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ /* Configure interrupt mode : read current mode */
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+ {
+ EXTI->IMR |= maskline;
+ }
+ else
+ {
+ EXTI->IMR &= ~maskline;
+ }
+
+ /* Configure event mode : read current mode */
+ /* Mask or set line */
+ if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+ {
+ EXTI->EMR |= maskline;
+ }
+ else
+ {
+ EXTI->EMR &= ~maskline;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param pExtiConfig Pointer on structure to store Exti configuration.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
+ /* Check null pointer */
+ if ((hexti == NULL) || (pExtiConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* Store handle line number to configuration structure */
+ pExtiConfig->Line = hexti->Line;
+
+ /* Compute line mask */
+ linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* 1] Get core mode : interrupt */
+
+ /* Check if selected line is enable */
+ if ((EXTI->IMR & maskline) != 0x00u)
+ {
+ pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+ }
+ else
+ {
+ pExtiConfig->Mode = EXTI_MODE_NONE;
+ }
+
+ /* Get event mode */
+ /* Check if selected line is enable */
+ if ((EXTI->EMR & maskline) != 0x00u)
+ {
+ pExtiConfig->Mode |= EXTI_MODE_EVENT;
+ }
+
+ /* 2] Get trigger for configurable lines : rising */
+ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+ {
+ /* Check if configuration of selected line is enable */
+ if ((EXTI->RTSR & maskline) != 0x00u)
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+ }
+ else
+ {
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ }
+
+ /* Get falling configuration */
+ /* Check if configuration of selected line is enable */
+ if ((EXTI->FTSR & maskline) != 0x00u)
+ {
+ pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+ }
+
+ /* Get Gpio port selection for gpio lines */
+ if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+ }
+ else
+ {
+ pExtiConfig->GPIOSel = 0x00u;
+ }
+ }
+ else
+ {
+ /* No Trigger selected */
+ pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+ pExtiConfig->GPIOSel = 0x00u;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Clear whole configuration of a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameter */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+
+ /* compute line mask */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* 1] Clear interrupt mode */
+ EXTI->IMR = (EXTI->IMR & ~maskline);
+
+ /* 2] Clear event mode */
+ EXTI->EMR = (EXTI->EMR & ~maskline);
+
+ /* 3] Clear triggers in case of configurable lines */
+ if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+ {
+ EXTI->RTSR = (EXTI->RTSR & ~maskline);
+ EXTI->FTSR = (EXTI->FTSR & ~maskline);
+
+ /* Get Gpio port selection for gpio lines */
+ if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+ {
+ assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+ regval = SYSCFG->EXTICR[linepos >> 2u];
+ regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+ SYSCFG->EXTICR[linepos >> 2u] = regval;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Register callback for a dedicated Exti line.
+ * @param hexti Exti handle.
+ * @param CallbackID User callback identifier.
+ * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+ * @param pPendingCbfn function pointer to be stored as callback.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_EXTI_COMMON_CB_ID:
+ hexti->PendingCallback = pPendingCbfn;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Store line number as handle private field.
+ * @param hexti Exti handle.
+ * @param ExtiLine Exti line number.
+ * This parameter can be from 0 to @ref EXTI_LINE_NB.
+ * @retval HAL Status.
+ */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE(ExtiLine));
+
+ /* Check null pointer */
+ if (hexti == NULL)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Store line number as handle private field */
+ hexti->Line = ExtiLine;
+
+ return HAL_OK;
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+ * @brief EXTI IO functions.
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Handle EXTI interrupt request.
+ * @param hexti Exti handle.
+ * @retval none.
+ */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+ uint32_t regval;
+ uint32_t maskline;
+
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Get pending bit */
+ regval = (EXTI->PR & maskline);
+ if (regval != 0x00u)
+ {
+ /* Clear pending bit */
+ EXTI->PR = maskline;
+
+ /* Call callback */
+ if (hexti->PendingCallback != NULL)
+ {
+ hexti->PendingCallback();
+ }
+ }
+}
+
+/**
+ * @brief Get interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be checked.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING
+ * This parameter is kept for compatibility with other series.
+ * @retval 1 if interrupt is pending else 0.
+ */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ uint32_t regval;
+ uint32_t linepos;
+ uint32_t maskline;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* Compute line mask */
+ linepos = (hexti->Line & EXTI_PIN_MASK);
+ maskline = (1uL << linepos);
+
+ /* return 1 if bit is set else 0 */
+ regval = ((EXTI->PR & maskline) >> linepos);
+ return regval;
+}
+
+/**
+ * @brief Clear interrupt pending bit of a dedicated line.
+ * @param hexti Exti handle.
+ * @param Edge Specify which pending edge as to be clear.
+ * This parameter can be one of the following values:
+ * @arg @ref EXTI_TRIGGER_RISING_FALLING
+ * This parameter is kept for compatibility with other series.
+ * @retval None.
+ */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+ uint32_t maskline;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+ assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Clear Pending bit */
+ EXTI->PR = maskline;
+}
+
+/**
+ * @brief Generate a software interrupt for a dedicated line.
+ * @param hexti Exti handle.
+ * @retval None.
+ */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+ uint32_t maskline;
+
+ /* Check parameters */
+ assert_param(IS_EXTI_LINE(hexti->Line));
+ assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+ /* Compute line mask */
+ maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+ /* Generate Software interrupt */
+ EXTI->SWIER = maskline;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_flash.c b/Src/stm32f0xx_hal_flash.c
index 514fafe..a4a0821 100644
--- a/Src/stm32f0xx_hal_flash.c
+++ b/Src/stm32f0xx_hal_flash.c
@@ -69,31 +69,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -170,7 +154,7 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @note FLASH should be previously erased before new programmation (only exception to this
+ * @note FLASH should be previously erased before new programming (only exception to this
* is when 0x0000 is programmed)
*
* @param TypeProgram Indicate the way to program at a specified address.
@@ -223,7 +207,7 @@
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
- /* In case of error, stop programation procedure */
+ /* In case of error, stop programming procedure */
if (status != HAL_OK)
{
break;
diff --git a/Src/stm32f0xx_hal_flash_ex.c b/Src/stm32f0xx_hal_flash_ex.c
index bb6143d..87f0e17 100644
--- a/Src/stm32f0xx_hal_flash_ex.c
+++ b/Src/stm32f0xx_hal_flash_ex.c
@@ -28,31 +28,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_hal_gpio.c b/Src/stm32f0xx_hal_gpio.c
index 2890fcc..88646b6 100644
--- a/Src/stm32f0xx_hal_gpio.c
+++ b/Src/stm32f0xx_hal_gpio.c
@@ -96,31 +96,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -135,6 +119,13 @@
* @{
*/
+/** MISRA C:2012 deviation rule has been granted for following rules:
+ * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
+ * which may be out of array bounds [..,UNKNOWN] in following APIs:
+ * HAL_GPIO_Init
+ * HAL_GPIO_DeInit
+ */
+
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -185,118 +176,118 @@
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
- uint32_t position = 0x00U;
- uint32_t iocurrent = 0x00U;
- uint32_t temp = 0x00U;
+ uint32_t position = 0x00u;
+ uint32_t iocurrent;
+ uint32_t temp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
- assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
- while (((GPIO_Init->Pin) >> position) != RESET)
+ while (((GPIO_Init->Pin) >> position) != 0x00u)
{
/* Get current io position */
- iocurrent = (GPIO_Init->Pin) & (1U << position);
-
- if(iocurrent)
+ iocurrent = (GPIO_Init->Pin) & (1uL << position);
+
+ if (iocurrent != 0x00u)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
- if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-
- /* Configure Alternate function mapped with the current IO */
- temp = GPIOx->AFR[position >> 3];
- CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
- SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
- GPIOx->AFR[position >> 3U] = temp;
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3u];
+ temp &= ~(0xFu << ((position & 0x07u) * 4u));
+ temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
+ GPIOx->AFR[position >> 3u] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
- CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2U));
- SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
- if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
- temp = GPIOx->OSPEEDR;
- CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
- SET_BIT(temp, GPIO_Init->Speed << (position * 2U));
+ temp = GPIOx->OSPEEDR;
+ temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
+ temp |= (GPIO_Init->Speed << (position * 2u));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
- CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
- SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
- CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2U));
- SET_BIT(temp, (GPIO_Init->Pull) << (position * 2U));
+ temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
+ temp |= ((GPIO_Init->Pull) << (position * 2u));
GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
- if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
-
- temp = SYSCFG->EXTICR[position >> 2];
- CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
- SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
- SYSCFG->EXTICR[position >> 2] = temp;
-
+
+ temp = SYSCFG->EXTICR[position >> 2u];
+ temp &= ~(0x0FuL << (4u * (position & 0x03u)));
+ temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
+ SYSCFG->EXTICR[position >> 2u] = temp;
+
/* Clear EXTI line configuration */
temp = EXTI->IMR;
- CLEAR_BIT(temp, (uint32_t)iocurrent);
+ temp &= ~(iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
- SET_BIT(temp, iocurrent);
+ temp |= iocurrent;
}
EXTI->IMR = temp;
temp = EXTI->EMR;
- CLEAR_BIT(temp, (uint32_t)iocurrent);
+ temp &= ~(iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- {
- SET_BIT(temp, iocurrent);
+ {
+ temp |= iocurrent;
}
EXTI->EMR = temp;
-
+
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
- CLEAR_BIT(temp, (uint32_t)iocurrent);
+ temp &= ~(iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
- SET_BIT(temp, iocurrent);
+ temp |= iocurrent;
}
EXTI->RTSR = temp;
temp = EXTI->FTSR;
- CLEAR_BIT(temp, (uint32_t)iocurrent);
+ temp &= ~(iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
- SET_BIT(temp, iocurrent);
+ temp |= iocurrent;
}
EXTI->FTSR = temp;
}
}
-
+
position++;
}
}
@@ -310,58 +301,59 @@
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
- uint32_t position = 0x00U;
- uint32_t iocurrent = 0x00U;
- uint32_t tmp = 0x00U;
+ uint32_t position = 0x00u;
+ uint32_t iocurrent;
+ uint32_t tmp;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
- while ((GPIO_Pin >> position) != RESET)
+ while ((GPIO_Pin >> position) != 0x00u)
{
/* Get current io position */
- iocurrent = GPIO_Pin & (1U << position);
+ iocurrent = (GPIO_Pin) & (1uL << position);
- if (iocurrent)
+ if (iocurrent != 0x00u)
{
- /*------------------------- GPIO Mode Configuration --------------------*/
- /* Configure IO Direction in Input Floting Mode */
- CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2U));
-
- /* Configure the default Alternate Function in current IO */
- CLEAR_BIT(GPIOx->AFR[position >> 3U], 0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
-
- /* Configure the default value for IO Speed */
- CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
-
- /* Configure the default value IO Output Type */
- CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
-
- /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
- CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2U));
-
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
-
- tmp = SYSCFG->EXTICR[position >> 2U];
- tmp &= ((0x0FU) << (4U * (position & 0x03U)));
- if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
+
+ tmp = SYSCFG->EXTICR[position >> 2u];
+ tmp &= (0x0FuL << (4u * (position & 0x03u)));
+ if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
{
- tmp = (0x0FU) << (4U * (position & 0x03U));
- CLEAR_BIT(SYSCFG->EXTICR[position >> 2U], tmp);
-
/* Clear EXTI line configuration */
- CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
- CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
+ EXTI->IMR &= ~((uint32_t)iocurrent);
+ EXTI->EMR &= ~((uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
- CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
- CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
+ EXTI->FTSR &= ~((uint32_t)iocurrent);
+
+ /* Configure the External Interrupt or event for the current IO */
+ tmp = 0x0FuL << (4u * (position & 0x03u));
+ SYSCFG->EXTICR[position >> 2u] &= ~tmp;
}
+
+ /*------------------------- GPIO Mode Configuration --------------------*/
+ /* Configure IO Direction in Input Floating Mode */
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
+
+ /* Configure the default Alternate Function in current IO */
+ GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
+
+ /* Configure the default value for IO Speed */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
+
+ /* Configure the default value IO Output Type */
+ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+ /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
}
-
+
position++;
}
}
@@ -449,7 +441,14 @@
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- GPIOx->ODR ^= GPIO_Pin;
+ if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
+ }
+ else
+ {
+ GPIOx->BSRR = (uint32_t)GPIO_Pin;
+ }
}
/**
@@ -479,10 +478,11 @@
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
- /* Read LCKK bit*/
+ /* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR;
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+ /* read again in order to confirm lock is active */
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
{
return HAL_OK;
}
@@ -500,7 +500,7 @@
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
diff --git a/Src/stm32f0xx_hal_i2c.c b/Src/stm32f0xx_hal_i2c.c
index c64e0f0..4c8796a 100644
--- a/Src/stm32f0xx_hal_i2c.c
+++ b/Src/stm32f0xx_hal_i2c.c
@@ -19,7 +19,7 @@
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
- (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
+ (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
@@ -39,54 +39,54 @@
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
- (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
- (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
+ (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
+ (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
- (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
- (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
- (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
- (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
- (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
+ (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
+ (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
+ (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
+ (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
- (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
- (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
+ (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
+ (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
- *** Interrupt mode IO sequential operation ***
- ==============================================
+ *** Interrupt mode or DMA mode IO sequential operation ***
+ ==========================================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
@@ -98,97 +98,114 @@
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition, an then permit a call the same master sequential interface
- several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
+ several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
+ or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and with a final stop condition in both cases
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+ interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ without stopping the communication and so generate a restart condition.
+ (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+ interface.
+ Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
+ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
+ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
(+) Differents sequential I2C interfaces are listed below:
- (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
- (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
+ or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
+ or using @ref HAL_I2C_Master_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
- (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
- (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
- (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
- (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
+ or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
+ (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
+ or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
+ (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
- HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ @ref HAL_I2C_Mem_Write_IT()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
- HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ @ref HAL_I2C_Mem_Read_IT()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ @ref HAL_I2C_Master_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ @ref HAL_I2C_Master_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ @ref HAL_I2C_Slave_Transmit_DMA()
+ (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
- HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
- (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
- (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
+ @ref HAL_I2C_Slave_Receive_DMA()
+ (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+ (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
+ (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
- HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
+ @ref HAL_I2C_Mem_Write_DMA()
+ (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
- HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
- (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ @ref HAL_I2C_Mem_Read_DMA()
+ (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
+ (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
@@ -196,13 +213,78 @@
[..]
Below the list of most used macros in I2C HAL driver.
- (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
- (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
- (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
- (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
- (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
- (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+ (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
+ (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
+ (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+ (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+ (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+ (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+ to register an interrupt callback.
+ [..]
+ Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+ [..]
+ Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
+ (+) MemRxCpltCallback : callback for Memory reception end of transfer.
+ (+) ErrorCallback : callback for error detection.
+ (+) AbortCpltCallback : callback for abort completion process.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+ [..]
+ By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
+ or @ref HAL_I2C_Init() function.
+ [..]
+ When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@@ -211,29 +293,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -274,14 +340,14 @@
#define SlaveAddr_MSK 0x06U
/* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
-#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
/* Private define to centralize the enable/disable of Interrupts */
@@ -300,10 +366,6 @@
*/
/* Private macro -------------------------------------------------------------*/
-#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
- ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
- ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
-
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -320,8 +382,8 @@
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
@@ -345,14 +407,17 @@
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
-/* Private functions to flush TXDR register */
+/* Private function to flush TXDR register */
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
-/* Private functions to handle start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+/* Private function to handle start, restart or stop a transfer */
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
@@ -424,8 +489,30 @@
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ /* Init the I2C Callback settings */
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hi2c->MspInitCallback == NULL)
+ {
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hi2c->MspInitCallback(hi2c);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
@@ -504,8 +591,18 @@
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ if (hi2c->MspDeInitCallback == NULL)
+ {
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hi2c->MspDeInitCallback(hi2c);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_RESET;
@@ -550,6 +647,328 @@
*/
}
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User I2C Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2C Callback
+ * I2C callback is redirected to the weak predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
+ * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
+ * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
+ * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
+ hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
+ hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
+ hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
+ hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_I2C_LISTEN_COMPLETE_CB_ID :
+ hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
+ hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
+ break;
+
+ case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
+ hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
+ break;
+
+ case HAL_I2C_ERROR_CB_ID :
+ hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2C_ABORT_CB_ID :
+ hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2C_STATE_RESET == hi2c->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2C_MSPINIT_CB_ID :
+ hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2C_MSPDEINIT_CB_ID :
+ hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match I2C Callback
+ * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match I2C Callback
+ * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2c);
+
+ if (HAL_I2C_STATE_READY == hi2c->State)
+ {
+ hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2c);
+ return status;
+}
+
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -591,6 +1010,13 @@
(++) HAL_I2C_Slave_Receive_IT()
(++) HAL_I2C_Mem_Write_IT()
(++) HAL_I2C_Mem_Read_IT()
+ (++) HAL_I2C_Master_Seq_Transmit_IT()
+ (++) HAL_I2C_Master_Seq_Receive_IT()
+ (++) HAL_I2C_Slave_Seq_Transmit_IT()
+ (++) HAL_I2C_Slave_Seq_Receive_IT()
+ (++) HAL_I2C_EnableListen_IT()
+ (++) HAL_I2C_DisableListen_IT()
+ (++) HAL_I2C_Master_Abort_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2C_Master_Transmit_DMA()
@@ -599,15 +1025,22 @@
(++) HAL_I2C_Slave_Receive_DMA()
(++) HAL_I2C_Mem_Write_DMA()
(++) HAL_I2C_Mem_Read_DMA()
+ (++) HAL_I2C_Master_Seq_Transmit_DMA()
+ (++) HAL_I2C_Master_Seq_Receive_DMA()
+ (++) HAL_I2C_Slave_Seq_Transmit_DMA()
+ (++) HAL_I2C_Slave_Seq_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_I2C_MemTxCpltCallback()
- (++) HAL_I2C_MemRxCpltCallback()
(++) HAL_I2C_MasterTxCpltCallback()
(++) HAL_I2C_MasterRxCpltCallback()
(++) HAL_I2C_SlaveTxCpltCallback()
(++) HAL_I2C_SlaveRxCpltCallback()
+ (++) HAL_I2C_MemTxCpltCallback()
+ (++) HAL_I2C_MemRxCpltCallback()
+ (++) HAL_I2C_AddrCallback()
+ (++) HAL_I2C_ListenCpltCallback()
(++) HAL_I2C_ErrorCallback()
+ (++) HAL_I2C_AbortCpltCallback()
@endverbatim
* @{
@@ -618,7 +1051,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -626,7 +1059,7 @@
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -638,7 +1071,7 @@
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
@@ -655,12 +1088,12 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
@@ -668,37 +1101,34 @@
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
hi2c->XferSize--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -707,14 +1137,7 @@
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -742,7 +1165,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -750,7 +1173,7 @@
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -762,7 +1185,7 @@
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
@@ -779,12 +1202,12 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
@@ -792,38 +1215,35 @@
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -832,14 +1252,7 @@
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -873,12 +1286,13 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -904,7 +1318,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -918,7 +1332,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -930,7 +1344,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
while (hi2c->XferCount > 0U)
@@ -940,19 +1354,15 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
}
@@ -970,7 +1380,7 @@
}
else
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
@@ -982,7 +1392,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Disable Address Acknowledge */
@@ -1013,12 +1423,13 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1044,7 +1455,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear ADDR flag */
@@ -1055,7 +1466,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
while (hi2c->XferCount > 0U)
@@ -1070,22 +1481,23 @@
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
}
- if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
- {
- return HAL_TIMEOUT;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
}
@@ -1094,15 +1506,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
-
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
@@ -1113,7 +1517,7 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Disable Address Acknowledge */
@@ -1138,14 +1542,14 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1180,7 +1584,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1207,14 +1611,14 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1249,7 +1653,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1374,14 +1778,15 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1416,37 +1821,71 @@
if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1455,7 +1894,7 @@
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1482,14 +1921,15 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1524,37 +1964,71 @@
if (hi2c->XferSize > 0U)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Send Slave Address */
- /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1563,7 +2037,7 @@
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1576,6 +2050,7 @@
/* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
+
return HAL_OK;
}
else
@@ -1594,10 +2069,13 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1614,33 +2092,67 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -1660,10 +2172,13 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ HAL_StatusTypeDef dmaxferstatus;
+
if (hi2c->State == HAL_I2C_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
/* Process Locked */
@@ -1680,33 +2195,67 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Enable Address Acknowledge */
- hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR, STOP, NACK, ADDR interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -1720,7 +2269,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -1730,7 +2279,7 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1739,6 +2288,7 @@
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -1750,7 +2300,7 @@
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
@@ -1765,30 +2315,21 @@
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
do
@@ -1796,38 +2337,35 @@
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
hi2c->XferSize--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
@@ -1838,14 +2376,7 @@
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -1873,7 +2404,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -1883,7 +2414,7 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -1892,6 +2423,7 @@
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -1903,7 +2435,7 @@
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
@@ -1918,18 +2450,9 @@
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Send Slave Address */
@@ -1937,12 +2460,12 @@
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
do
@@ -1950,31 +2473,35 @@
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -1984,14 +2511,7 @@
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -2018,7 +2538,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2027,8 +2547,8 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2037,6 +2557,7 @@
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2075,22 +2596,13 @@
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2117,7 +2629,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2126,8 +2638,8 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2136,6 +2648,7 @@
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2174,22 +2687,13 @@
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2215,7 +2719,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2224,8 +2728,9 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2234,6 +2739,7 @@
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2272,51 +2778,77 @@
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -2331,7 +2863,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2340,8 +2872,9 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart = 0U;
- uint32_t xfermode = 0U;
+ uint32_t tickstart;
+ uint32_t xfermode;
+ HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2350,6 +2883,7 @@
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2388,50 +2922,75 @@
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
}
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmarx->XferHalfCpltCallback = NULL;
- hi2c->hdmarx->XferAbortCallback = NULL;
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
return HAL_OK;
}
@@ -2447,16 +3006,19 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
- __IO uint32_t I2C_Trials = 0U;
+ __IO uint32_t I2C_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -2479,19 +3041,31 @@
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
{
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- /* Device is ready */
+ /* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+
+ return HAL_ERROR;
}
}
+
+ tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
+ tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
}
/* Check if the NACKF flag has not been set */
@@ -2500,7 +3074,7 @@
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -2519,7 +3093,7 @@
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear NACK Flag */
@@ -2530,7 +3104,7 @@
}
/* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials++ == Trials)
+ if (I2C_Trials == Trials)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
@@ -2538,21 +3112,28 @@
/* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
+
+ /* Increment Trials */
+ I2C_Trials++;
}
while (I2C_Trials < Trials);
+ /* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
else
{
@@ -2566,15 +3147,15 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
/* Check the parameters */
@@ -2595,7 +3176,7 @@
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Master_ISR_IT;
- /* If size > MAX_NBYTE_SIZE, use reload mode */
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
@@ -2607,15 +3188,26 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
/* Send Slave Address and set NBYTES to write */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2634,20 +3226,182 @@
}
/**
- * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
- uint32_t xfermode = 0U;
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to write */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_READ;
/* Check the parameters */
@@ -2680,15 +3434,26 @@
xfermode = hi2c->XferOptions;
}
- /* If transfer direction not change, do not generate Restart Condition */
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
{
xferrequest = I2C_NO_STARTSTOP;
}
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
/* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2707,6 +3472,168 @@
}
/**
+ * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ uint32_t xfermode;
+ uint32_t xferrequest = I2C_GENERATE_START_READ;
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Master_ISR_DMA;
+
+ /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ xfermode = I2C_RELOAD_MODE;
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ xfermode = hi2c->XferOptions;
+ }
+
+ /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+ {
+ xferrequest = I2C_NO_STARTSTOP;
+ }
+ else
+ {
+ /* Convert OTHER_xxx XferOptions if any */
+ I2C_ConvertOtherXferOptions(hi2c);
+
+ /* Update xfermode accordingly if no reload is necessary */
+ if (hi2c->XferCount < MAX_NBYTE_SIZE)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ }
+
+ if (hi2c->XferSize > 0U)
+ {
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Send Slave Address and set NBYTES to read */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hi2c->XferISR = I2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2716,15 +3643,16 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2740,6 +3668,26 @@
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ /* Abort DMA Xfer if any */
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
}
hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
@@ -2781,6 +3729,185 @@
}
/**
+ * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave RX state to TX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
* @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2790,15 +3917,16 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
if ((pData == NULL) || (Size == 0U))
{
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
return HAL_ERROR;
}
@@ -2814,6 +3942,26 @@
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
}
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
@@ -2855,6 +4003,185 @@
}
/**
+ * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ HAL_StatusTypeDef dmaxferstatus;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
+ }
+
+ /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
+ /* and then toggle the HAL slave TX state to RX state */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ {
+ /* Disable associated Interrupts */
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ {
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ }
+ }
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ {
+ if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ {
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Abort DMA Xfer if any */
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferISR = I2C_Slave_ISR_DMA;
+
+ if (hi2c->hdmarx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Reset XferSize */
+ hi2c->XferSize = 0;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ {
+ /* Clear ADDR flag after prepare the transfer parameters */
+ /* This action will generate an acknowledge to the Master */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* REnable ADDR interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
+}
+
+/**
* @brief Enable the Address listen mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -2914,7 +4241,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
@@ -2990,9 +4317,10 @@
{
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmperror;
/* I2C Bus error interrupt occurred ------------------------------------*/
- if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
@@ -3001,7 +4329,7 @@
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
@@ -3010,7 +4338,7 @@
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
@@ -3018,10 +4346,13 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
}
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
/* Call the Error Callback in case of Error detected */
- if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
{
- I2C_ITError(hi2c, hi2c->ErrorCode);
+ I2C_ITError(hi2c, tmperror);
}
}
@@ -3263,12 +4594,13 @@
*/
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0U;
+ uint16_t devaddress;
+ uint32_t tmpITFlags = ITFlags;
/* Process Locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3281,41 +4613,52 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
- if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
}
else
{
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
@@ -3325,7 +4668,7 @@
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
+ I2C_ITMasterSeqCplt(hi2c);
}
else
{
@@ -3335,7 +4678,7 @@
}
}
}
- else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
@@ -3350,7 +4693,7 @@
else
{
/* Call I2C Master Sequential complete process */
- I2C_ITMasterSequentialCplt(hi2c);
+ I2C_ITMasterSeqCplt(hi2c);
}
}
}
@@ -3361,11 +4704,15 @@
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
+ else
+ {
+ /* Nothing to do */
+ }
- if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
- I2C_ITMasterCplt(hi2c, ITFlags);
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
@@ -3384,10 +4731,20 @@
*/
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t tmpITFlags = ITFlags;
+
/* Process locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, tmpITFlags);
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -3395,13 +4752,12 @@
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
- if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
- (hi2c->State == HAL_I2C_STATE_LISTEN))
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
+ I2C_ITListenCplt(hi2c, tmpITFlags);
}
- else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3411,7 +4767,7 @@
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
+ I2C_ITSlaveSeqCplt(hi2c);
}
else
{
@@ -3427,30 +4783,40 @@
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
}
}
- else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
if (hi2c->XferCount > 0U)
{
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferSize--;
hi2c->XferCount--;
}
if ((hi2c->XferCount == 0U) && \
- (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+ (tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
+ I2C_ITSlaveSeqCplt(hi2c);
}
}
- else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
- I2C_ITAddrCplt(hi2c, ITFlags);
+ I2C_ITAddrCplt(hi2c, tmpITFlags);
}
- else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
@@ -3459,26 +4825,27 @@
if (hi2c->XferCount > 0U)
{
/* Write data to TXDR */
- hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
hi2c->XferCount--;
hi2c->XferSize--;
}
else
{
- if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
{
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
- I2C_ITSlaveSequentialCplt(hi2c);
+ I2C_ITSlaveSeqCplt(hi2c);
}
}
}
-
- /* Check if STOPF is set */
- if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else
{
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
+ /* Nothing to do */
}
/* Process Unlocked */
@@ -3497,13 +4864,13 @@
*/
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0U;
- uint32_t xfermode = 0U;
+ uint16_t devaddress;
+ uint32_t xfermode;
/* Process Locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3519,7 +4886,7 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
@@ -3527,7 +4894,7 @@
if (hi2c->XferCount != 0U)
{
/* Recover Slave address */
- devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
+ devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
/* Prepare the new XferSize to transfer */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
@@ -3538,11 +4905,18 @@
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ {
+ xfermode = hi2c->XferOptions;
+ }
+ else
+ {
+ xfermode = I2C_AUTOEND_MODE;
+ }
}
/* Set the new XferSize in Nbytes register */
- I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -3559,16 +4933,55 @@
}
else
{
- /* Wrong size Status regarding TCR flag event */
+ /* Call TxCpltCallback() if no stop mode is set */
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->XferCount == 0U)
+ {
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ {
+ /* Generate a stop condition in case of no transfer option */
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call I2C Master Sequential complete process */
+ I2C_ITMasterSeqCplt(hi2c);
+ }
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TC flag event */
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
- else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3586,39 +4999,106 @@
*/
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
+ uint32_t tmpoptions = hi2c->XferOptions;
+ uint32_t treatdmanack = 0U;
+
/* Process locked */
__HAL_LOCK(hi2c);
- if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ /* Check if STOPF is set */
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Slave complete process */
+ I2C_ITSlaveCplt(hi2c, ITFlags);
+ }
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
- if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
+ if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
{
- /* Clear NACK Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ /* Split check of hdmarx, for MISRA compliance */
+ if (hi2c->hdmarx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ /* Split check of hdmatx, for MISRA compliance */
+ if (hi2c->hdmatx != NULL)
+ {
+ if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
+ {
+ if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ {
+ treatdmanack = 1U;
+ }
+ }
+ }
+
+ if (treatdmanack == 1U)
+ {
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ {
+ /* Call I2C Listen complete process */
+ I2C_ITListenCplt(hi2c, ITFlags);
+ }
+ else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+ }
+ else
+ {
+ /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, hi2c->ErrorCode);
+ }
+ }
}
else
{
- /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
- /* Clear NACK Flag */
+ /* Only Clear NACK Flag, no DMA treatment is pending */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
+ I2C_ITAddrCplt(hi2c, ITFlags);
}
- else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else
{
- /* Call I2C Slave complete process */
- I2C_ITSlaveCplt(hi2c, ITFlags);
+ /* Nothing to do */
}
/* Process Unlocked */
@@ -3632,7 +5112,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -3641,19 +5121,12 @@
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
@@ -3671,14 +5144,7 @@
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -3688,7 +5154,7 @@
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
return HAL_OK;
@@ -3699,7 +5165,7 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -3708,19 +5174,12 @@
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* If Memory address size is 8Bit */
@@ -3738,14 +5197,7 @@
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
/* Send LSB of Memory Address */
@@ -3755,7 +5207,7 @@
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
return HAL_OK;
@@ -3769,16 +5221,16 @@
*/
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
- uint8_t transferdirection = 0U;
- uint16_t slaveaddrcode = 0U;
- uint16_t ownadd1code = 0U;
- uint16_t ownadd2code = 0U;
+ uint8_t transferdirection;
+ uint16_t slaveaddrcode;
+ uint16_t ownadd1code;
+ uint16_t ownadd2code;
/* Prevent unused argument(s) compilation warning */
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
{
transferdirection = I2C_GET_DIR(hi2c);
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
@@ -3804,7 +5256,11 @@
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
else
@@ -3818,7 +5274,11 @@
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* else 7 bits addressing mode is selected */
@@ -3831,7 +5291,11 @@
__HAL_UNLOCK(hi2c);
/* Call Slave Addr callback */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#else
HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* Else clear address flag only */
@@ -3850,7 +5314,7 @@
* @param hi2c I2C handle.
* @retval None
*/
-static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
+static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
{
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -3870,7 +5334,11 @@
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
else
@@ -3886,7 +5354,11 @@
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -3895,7 +5367,7 @@
* @param hi2c I2C handle.
* @retval None
*/
-static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
+static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
{
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -3912,8 +5384,12 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
@@ -3928,8 +5404,16 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
@@ -3941,6 +5425,8 @@
*/
static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
+ uint32_t tmperror;
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@@ -3952,7 +5438,7 @@
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if ((ITFlags & I2C_FLAG_AF) != RESET)
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3967,8 +5453,11 @@
/* Disable Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ /* Store current volatile hi2c->ErrorCode, misra rule */
+ tmperror = hi2c->ErrorCode;
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
+ if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
@@ -3986,7 +5475,11 @@
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemTxCpltCallback(hi2c);
+#else
HAL_I2C_MemTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -3996,7 +5489,11 @@
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterTxCpltCallback(hi2c);
+#else
HAL_I2C_MasterTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
@@ -4011,7 +5508,12 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MemRxCpltCallback(hi2c);
+#else
HAL_I2C_MemRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4020,9 +5522,18 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->MasterRxCpltCallback(hi2c);
+#else
HAL_I2C_MasterRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
@@ -4033,12 +5544,12 @@
*/
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
+ uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
+ uint32_t tmpITFlags = ITFlags;
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
-
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
@@ -4052,10 +5563,42 @@
I2C_Flush_TXDR(hi2c);
/* If a DMA is ongoing, Update handle size context */
- if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
- ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
+ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
{
- hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
+ if (hi2c->hdmatx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ }
+ }
+ else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
+ {
+ if (hi2c->hdmarx != NULL)
+ {
+ hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ }
+ }
+ else
+ {
+ /* Do nothing */
+ }
+
+ /* Store Last receive data if any */
+ if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ if ((hi2c->XferSize > 0U))
+ {
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
}
/* All data are not transferred, so set error code accordingly */
@@ -4065,22 +5608,6 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
- /* Store Last receive data if any */
- if (((ITFlags & I2C_FLAG_RXNE) != RESET))
- {
- /* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
-
- if ((hi2c->XferSize > 0U))
- {
- hi2c->XferSize--;
- hi2c->XferCount--;
-
- /* Set ErrorCode corresponding to a Non-Acknowledge */
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- }
-
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
@@ -4094,11 +5621,14 @@
if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
/* Call I2C Listen complete process */
- I2C_ITListenCplt(hi2c, ITFlags);
+ I2C_ITListenCplt(hi2c, tmpITFlags);
}
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+ I2C_ITSlaveSeqCplt(hi2c);
+
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4106,7 +5636,11 @@
__HAL_UNLOCK(hi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
@@ -4116,8 +5650,12 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Slave Rx Complete callback */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveRxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveRxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4126,8 +5664,12 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Call the Slave Tx Complete callback */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->SlaveTxCpltCallback(hi2c);
+#else
HAL_I2C_SlaveTxCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -4147,10 +5689,13 @@
hi2c->XferISR = NULL;
/* Store Last receive data if any */
- if (((ITFlags & I2C_FLAG_RXNE) != RESET))
+ if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
if ((hi2c->XferSize > 0U))
{
@@ -4172,7 +5717,11 @@
__HAL_UNLOCK(hi2c);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ListenCpltCallback(hi2c);
+#else
HAL_I2C_ListenCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
/**
@@ -4183,6 +5732,8 @@
*/
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
+ HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
/* Reset handle parameters */
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -4192,9 +5743,9 @@
hi2c->ErrorCode |= ErrorCode;
/* Disable Interrupts */
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
@@ -4225,18 +5776,21 @@
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA TX */
- if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ if (hi2c->hdmatx != NULL)
{
- /* Call Directly XferAbortCallback function in case of error */
- hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
}
}
/* Abort DMA RX transfer if any */
@@ -4244,18 +5798,21 @@
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
- /* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
- hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Abort DMA RX */
- if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ if (hi2c->hdmarx != NULL)
{
- /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
- hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ /* Set the I2C DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
}
}
else if (hi2c->State == HAL_I2C_STATE_ABORT)
@@ -4266,7 +5823,11 @@
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
@@ -4274,7 +5835,11 @@
__HAL_UNLOCK(hi2c);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -4306,7 +5871,7 @@
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -4334,10 +5899,16 @@
}
/* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
}
}
@@ -4348,12 +5919,24 @@
*/
static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tmpoptions = hi2c->XferOptions;
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
+ if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
+
+ /* Last Byte is Transmitted */
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
}
/**
@@ -4363,7 +5946,7 @@
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -4391,10 +5974,16 @@
}
/* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
-
- /* Enable TC interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
+ }
+ else
+ {
+ /* Enable TC interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
+ }
}
}
@@ -4405,12 +5994,24 @@
*/
static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tmpoptions = hi2c->XferOptions;
- /* No specific action, Master fully manage the generation of STOP condition */
- /* Mean that this generation can arrive at any time, at the end or during DMA process */
- /* So STOP condition should be manage through Interrupt treatment */
+ if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+ (tmpoptions != I2C_NO_OPTION_FRAME))
+ {
+ /* Disable DMA Request */
+ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
+
+ /* Call I2C Slave Sequential complete process */
+ I2C_ITSlaveSeqCplt(hi2c);
+ }
+ else
+ {
+ /* No specific action, Master fully manage the generation of STOP condition */
+ /* Mean that this generation can arrive at any time, at the end or during DMA process */
+ /* So STOP condition should be manage through Interrupt treatment */
+ }
}
/**
@@ -4420,7 +6021,7 @@
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -4437,10 +6038,7 @@
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
- /* Disable Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Reset AbortCpltCallback */
hi2c->hdmatx->XferAbortCallback = NULL;
@@ -4452,12 +6050,20 @@
hi2c->State = HAL_I2C_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->AbortCpltCallback(hi2c);
+#else
HAL_I2C_AbortCpltCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
+ hi2c->ErrorCallback(hi2c);
+#else
HAL_I2C_ErrorCallback(hi2c);
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
}
@@ -4478,14 +6084,15 @@
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -4513,7 +6120,7 @@
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4522,7 +6129,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
}
@@ -4548,7 +6155,7 @@
}
/* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4557,7 +6164,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -4584,24 +6191,35 @@
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ /* Check if an RXNE is pending */
+ /* Store Last receive data if any */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+ {
+ /* Return HAL_OK */
+ /* The Reading of data from RXDR will be done in caller function */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ return HAL_ERROR;
+ }
}
/* Check for the Timeout */
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4609,7 +6227,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
return HAL_OK;
@@ -4634,14 +6252,16 @@
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
+ hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+
+ return HAL_ERROR;
}
}
}
@@ -4658,7 +6278,7 @@
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -4689,27 +6309,16 @@
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
- uint32_t tmpreg = 0U;
-
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
- /* Get the CR2 register value */
- tmpreg = hi2c->Instance->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
/* update CR2 register */
- hi2c->Instance->CR2 = tmpreg;
+ MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -4717,9 +6326,9 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
@@ -4770,7 +6379,7 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ else if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
@@ -4781,8 +6390,6 @@
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
-
- return HAL_OK;
}
/**
@@ -4790,9 +6397,9 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
+static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
{
uint32_t tmpisr = 0U;
@@ -4801,7 +6408,7 @@
/* Disable TC and TXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
@@ -4813,7 +6420,7 @@
/* Disable TC and RXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
- if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
@@ -4848,8 +6455,34 @@
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_I2C_DISABLE_IT(hi2c, tmpisr);
+}
- return HAL_OK;
+/**
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
+{
+ /* if user set XferOptions to I2C_OTHER_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* set XferOptions to I2C_FIRST_FRAME */
+ if (hi2c->XferOptions == I2C_OTHER_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_FRAME;
+ }
+ /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
+ /* it request implicitly to generate a restart condition */
+ /* then generate a stop condition at the end of transfer */
+ /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
+ else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
+ {
+ hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
diff --git a/Src/stm32f0xx_hal_i2c_ex.c b/Src/stm32f0xx_hal_i2c_ex.c
index 6c24c54..f06c366 100644
--- a/Src/stm32f0xx_hal_i2c_ex.c
+++ b/Src/stm32f0xx_hal_i2c_ex.c
@@ -17,7 +17,8 @@
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
- (+) Disable or enable wakeup from Stop mode
+ (+) Disable or enable wakeup from Stop mode(s)
+ (+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
@@ -34,29 +35,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -96,6 +81,7 @@
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Wake Up Feature
+ (+) Configure Fast Mode Plus
@endverbatim
* @{
@@ -154,7 +140,7 @@
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@@ -199,7 +185,7 @@
#if defined(I2C_CR1_WUPEN)
/**
- * @brief Enable I2C wakeup from stop mode.
+ * @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
@@ -238,7 +224,7 @@
}
/**
- * @brief Disable I2C wakeup from stop mode.
+ * @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
diff --git a/Src/stm32f0xx_hal_i2s.c b/Src/stm32f0xx_hal_i2s.c
index d0fe3da..f1ee15e 100644
--- a/Src/stm32f0xx_hal_i2s.c
+++ b/Src/stm32f0xx_hal_i2s.c
@@ -3,7 +3,7 @@
* @file stm32f0xx_hal_i2s.c
* @author MCD Application Team
* @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
@@ -14,10 +14,10 @@
===============================================================================
[..]
The I2S HAL driver can be used as follow:
-
+
(#) Declare a I2S_HandleTypeDef handle structure.
(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
- (##) Enable the SPIx interface clock.
+ (##) Enable the SPIx interface clock.
(##) I2S pins configuration:
(+++) Enable the clock for the I2S GPIOs.
(+++) Configure these I2S pins as alternate function pull-up.
@@ -27,73 +27,73 @@
(+++) Enable the NVIC I2S IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
and HAL_I2S_Receive_DMA() APIs:
- (+++) Declare a DMA handle structure for the Tx/Rx Channel.
+ (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
(+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx Channel.
- (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
- DMA Tx/Rx Channel.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx Stream/Channel.
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
+ DMA Tx/Rx Stream/Channel.
(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
using HAL_I2S_Init() function.
- -@- The specific I2S interrupts (Transmission complete interrupt,
+ -@- The specific I2S interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-@- Make sure that either:
- (+@) External clock source is configured after setting correctly
- the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
+ (+@) External clock source is configured after setting correctly
+ the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
- (#) Three mode of operations are available within this driver :
+ (#) Three mode of operations are available within this driver :
*** Polling mode IO operation ***
=================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
+
*** Interrupt mode IO operation ***
===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
*** DMA mode IO operation ***
==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
*** I2S HAL driver macros list ***
- =============================================
+ ===================================
[..]
Below the list of most used macros in I2S HAL driver.
-
- (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
@@ -102,48 +102,85 @@
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
+ *** I2S HAL driver macros list ***
+ ===================================
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_I2S_RegisterCallback() allows to register following callbacks:
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+
+ [..]
+ By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
+ or HAL_I2S_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
#ifdef HAL_I2S_MODULE_ENABLED
-#if defined(STM32F031x6) || defined(STM32F038xx) || \
- defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F042x6) || defined(STM32F048xx) || \
- defined(STM32F091xC) || defined(STM32F098xx)
-
+#if defined(SPI_I2S_SUPPORT)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -162,13 +199,14 @@
* @{
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMAError(DMA_HandleTypeDef *hdma);
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout);
/**
* @}
*/
@@ -179,36 +217,36 @@
* @{
*/
-/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Sx peripheral in simplex mode:
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the I2Sx peripheral in simplex mode:
- (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
- (+) Call the function HAL_I2S_Init() to configure the selected device with
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
the selected configuration:
(++) Mode
- (++) Standard
+ (++) Standard
(++) Data Format
(++) MCLK Output
(++) Audio frequency
(++) Polarity
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx periperal.
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx peripheral.
@endverbatim
* @{
*/
/**
- * @brief Initializes the I2S according to the specified parameters
+ * @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
@@ -216,15 +254,18 @@
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
- uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U, i2sclk = 0U;
-
+ uint32_t i2sdiv;
+ uint32_t i2sodd;
+ uint32_t packetlength;
+ uint32_t tmp;
+ uint32_t i2sclk;
+
/* Check the I2S handle allocation */
- if(hi2s == NULL)
+ if (hi2s == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
@@ -233,102 +274,145 @@
assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
-
- if(hi2s->State == HAL_I2S_STATE_RESET)
+
+ if (hi2s->State == HAL_I2S_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2s->Lock = HAL_UNLOCKED;
-
+
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ /* Init the I2S Callback settings */
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (hi2s->MspInitCallback == NULL)
+ {
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hi2s->MspInitCallback(hi2s);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
-
+
hi2s->State = HAL_I2S_STATE_BUSY;
-
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
- SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
hi2s->Instance->I2SPR = 0x0002U;
-
- /* Get the I2SCFGR register value */
- tmpreg = hi2s->Instance->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
- {
- i2sodd = (uint16_t)0U;
- i2sdiv = (uint16_t)2U;
- }
+
+ /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
/* If the requested audio frequency is not the default, compute the prescaler */
- else
+ if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
{
- /* Check the frame length (For the Prescaler computing) *******************/
- if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ /* Check the frame length (For the Prescaler computing) ********************/
+ if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
{
/* Packet length is 16 bits */
- packetlength = 1U;
+ packetlength = 16U;
}
else
{
/* Packet length is 32 bits */
- packetlength = 2U;
+ packetlength = 32U;
}
- /* Get I2S source Clock frequency ****************************************/
+ /* I2S standard */
+ if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
+ {
+ /* In I2S standard packet lenght is multiplied by 2 */
+ packetlength = packetlength * 2U;
+ }
+
+ /* Get the source clock value: based on System Clock value */
i2sclk = HAL_RCC_GetSysClockFreq();
-
+
/* Compute the Real divider depending on the MCLK output state, with a floating point */
- if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
+ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
- tmp = (uint32_t)(((((i2sclk / 256U) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
+ else
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
+ }
}
else
{
/* MCLK output is disabled */
- tmp = (uint32_t)(((((i2sclk / (32U * packetlength)) *10U ) / hi2s->Init.AudioFreq)) + 5U);
+ tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
}
/* Remove the flatting point */
- tmp = tmp / 10U;
+ tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint32_t)(tmp & 1U);
+ i2sodd = (uint32_t)(tmp & (uint32_t)1U);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint32_t) (i2sodd << 8U);
+ i2sodd = (uint32_t)(i2sodd << 8U);
}
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ else
{
/* Set the default values */
i2sdiv = 2U;
i2sodd = 0U;
}
-
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+ return HAL_ERROR;
+ }
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
+
/* Write to SPIx I2SPR register the computed value */
hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-
- /* Configure the I2S with the I2S_InitStruct values */
- tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
-
- /* Write to SPIx I2SCFGR */
- hi2s->Instance->I2SCFGR = tmpreg;
-
+
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ /* And configure the I2S with the I2S_InitStruct values */
+ MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
+ (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
+ hi2s->Init.Standard | hi2s->Init.DataFormat | \
+ hi2s->Init.CPOL));
+
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
+ {
+ /* Write to SPIx I2SCFGR */
+ SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
+ }
+#endif /* SPI_I2SCFGR_ASTRTEN */
+
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State= HAL_I2S_STATE_READY;
-
+ hi2s->State = HAL_I2S_STATE_READY;
+
return HAL_OK;
}
/**
- * @brief DeInitializes the I2S peripheral
+ * @brief DeInitializes the I2S peripheral
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -336,24 +420,34 @@
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
{
/* Check the I2S handle allocation */
- if(hi2s == NULL)
+ if (hi2s == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
hi2s->State = HAL_I2S_STATE_BUSY;
-
+
/* Disable the I2S Peripheral Clock */
__HAL_I2S_DISABLE(hi2s);
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ if (hi2s->MspDeInitCallback == NULL)
+ {
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hi2s->MspDeInitCallback(hi2s);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
-
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_RESET;
+ hi2s->State = HAL_I2S_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hi2s);
@@ -367,14 +461,14 @@
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implemented in the user file
- */
+ */
}
/**
@@ -383,45 +477,237 @@
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implemented in the user file
- */
+ */
}
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User I2S Callback
+ * To be used instead of the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+ pI2S_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = pCallback;
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+
+/**
+ * @brief Unregister an I2S Callback
+ * I2S callback is redirected to the weak predefined callback
+ * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for the specified I2S.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hi2s);
+
+ if (HAL_I2S_STATE_READY == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_TX_COMPLETE_CB_ID :
+ hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_I2S_RX_COMPLETE_CB_ID :
+ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
+ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
+ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_I2S_ERROR_CB_ID :
+ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_I2S_STATE_RESET == hi2s->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_I2S_MSPINIT_CB_ID :
+ hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_I2S_MSPDEINIT_CB_ID :
+ hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hi2s);
+ return status;
+}
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
+/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
+ * @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the I2S data
+ This subsection provides a set of functions allowing to manage the I2S data
transfers.
(#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
(#) Blocking mode functions are :
(++) HAL_I2S_Transmit()
(++) HAL_I2S_Receive()
-
+
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_I2S_Transmit_IT()
(++) HAL_I2S_Receive_IT()
@@ -440,323 +726,372 @@
*/
/**
- * @brief Transmit an amount of data in blocking mode
+ * @brief Transmit an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
* @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0U))
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Set state and reset error code */
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->pTxBuffPtr = pData;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- while(hi2s->TxXferCount > 0U)
- {
- /* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
- }
-
- /* Wait until TXE flag is set, to confirm the end of the transcation */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR;
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ while (hi2s->TxXferCount > 0U)
+ {
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
+ hi2s->TxXferCount--;
+
+ /* Wait until TXE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if an underrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ {
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+ }
+
+ /* Check if Slave mode is selected */
+ if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
+ || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
+ {
+ /* Wait until Busy flag is reset */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in blocking mode
+ * @brief Receive an amount of data in blocking mode
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @param Timeout Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @param Timeout Timeout duration
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0U))
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Set state and reset error code */
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->pRxBuffPtr = pData;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Receive data */
- while(hi2s->RxXferCount > 0U)
- {
- /* Wait until RXNE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
- }
-
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Receive data */
+ while (hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
+ {
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
+ hi2s->RxXferCount--;
+
+ /* Check if an overrun occurs */
+ if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ {
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+ }
+
+ hi2s->State = HAL_I2S_STATE_READY;
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0U))
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_READY)
+
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- hi2s->pTxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
- * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0U))
- {
- return HAL_ERROR;
- }
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_READY)
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- hi2s->pRxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
+ return HAL_BUSY;
+ }
- return HAL_OK;
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Enable RXNE and ERR interrupt */
+ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Check if the I2S is already enabled */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Transmit an amount of data in non-blocking mode with DMA
+ * @brief Transmit an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Transmit data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0U))
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -764,80 +1099,90 @@
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
- hi2s->pTxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->TxXferSize = (Size << 1U);
- hi2s->TxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->TxXferSize = Size;
- hi2s->TxXferCount = Size;
- }
-
- /* Set the I2S Tx DMA Half transfert complete callback */
- hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
- /* Set the I2S Tx DMA transfert complete callback */
- hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
- /* Enable the Tx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if the I2S Tx request is already enabled */
- if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
- {
- /* Enable Tx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pTxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->TxXferSize = Size;
+ hi2s->TxXferCount = Size;
+ }
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
+
+ /* Set the I2S Tx DMA transfer complete callback */
+ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
+
+ /* Enable the Tx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
+ (uint32_t)hi2s->pTxBuffPtr,
+ (uint32_t)&hi2s->Instance->DR,
+ hi2s->TxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Tx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Enable Tx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Receive an amount of data in non-blocking mode with DMA
+ * @brief Receive an amount of data in non-blocking mode with DMA
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData a 16-bit pointer to the Receive data buffer.
- * @param Size number of data sample to be sent:
- * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
+ * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0U))
+ uint32_t tmpreg_cfgr;
+
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -845,74 +1190,79 @@
/* Process Locked */
__HAL_LOCK(hi2s);
- if(hi2s->State == HAL_I2S_STATE_READY)
+ if (hi2s->State != HAL_I2S_STATE_READY)
{
- hi2s->pRxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
- {
- hi2s->RxXferSize = (Size << 1U);
- hi2s->RxXferCount = (Size << 1U);
- }
- else
- {
- hi2s->RxXferSize = Size;
- hi2s->RxXferCount = Size;
- }
-
-
- /* Set the I2S Rx DMA Half transfert complete callback */
- hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
- /* Set the I2S Rx DMA transfert complete callback */
- hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
- /* Set the DMA error callback */
- hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
- /* Check if Master Receiver mode is selected */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
- {
- /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
- __HAL_I2S_CLEAR_OVRFLAG(hi2s);
- }
-
- /* Enable the Rx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
- {
- /* Enable I2S peripheral */
- __HAL_I2S_ENABLE(hi2s);
- }
-
- /* Check if the I2S Rx request is already enabled */
- if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
- {
- /* Enable Rx DMA Request */
- hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
- }
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
- }
- else
- {
- /* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
+
+ /* Set state and reset error code */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->pRxBuffPtr = pData;
+
+ tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
+ {
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
+ else
+ {
+ hi2s->RxXferSize = Size;
+ hi2s->RxXferCount = Size;
+ }
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
+
+ /* Set the I2S Rx DMA transfer complete callback */
+ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
+
+ /* Set the DMA error callback */
+ hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
+
+ /* Check if Master Receiver mode is selected */
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
+ {
+ /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Enable the Rx DMA Stream/Channel */
+ if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
+ hi2s->RxXferSize))
+ {
+ /* Update SPI error code */
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_ERROR;
+ }
+
+ /* Check if the I2S is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
+ __HAL_I2S_ENABLE(hi2s);
+ }
+
+ /* Check if the I2S Rx request is already enabled */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ }
+
+ __HAL_UNLOCK(hi2s);
+ return HAL_OK;
}
/**
- * @brief Pauses the audio stream playing from the Media.
+ * @brief Pauses the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -921,26 +1271,30 @@
{
/* Process Locked */
__HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Disable the I2S DMA Tx request */
- hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Disable the I2S DMA Rx request */
- hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
-
+ else
+ {
+ /* nothing to do */
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Resumes the audio stream playing from the Media.
+ * @brief Resumes the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -949,70 +1303,82 @@
{
/* Process Locked */
__HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+
+ if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Enable the I2S DMA Tx request */
- hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
- else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Enable the I2S DMA Rx request */
- hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
+ SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
-
- /* If the I2S peripheral is still not enabled, enable it */
- if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
+ else
{
- /* Enable I2S peripheral */
+ /* nothing to do */
+ }
+
+ /* If the I2S peripheral is still not enabled, enable it */
+ if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ {
+ /* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_OK;
}
/**
- * @brief Resumes the audio stream playing from the Media.
+ * @brief Stops the audio DMA Stream/Channel playing from the Media.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
+ HAL_StatusTypeDef errorcode = HAL_OK;
+ /* The Lock is not implemented on this API to allow the user application
+ to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
+ */
+
/* Disable the I2S Tx/Rx DMA requests */
- hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
- hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
-
- /* Abort the I2S DMA tx channel */
- if(hi2s->hdmatx != NULL)
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Abort the I2S DMA tx Stream/Channel */
+ if (hi2s->hdmatx != NULL)
{
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmatx);
- HAL_DMA_Abort(hi2s->hdmatx);
+ /* Disable the I2S DMA tx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
- /* Abort the I2S DMA rx channel */
- if(hi2s->hdmarx != NULL)
+
+ /* Abort the I2S DMA rx Stream/Channel */
+ if (hi2s->hdmarx != NULL)
{
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmarx);
- HAL_DMA_Abort(hi2s->hdmarx);
+ /* Disable the I2S DMA rx Stream/Channel */
+ if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
+ {
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
-
+
hi2s->State = HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_OK;
+
+ return errorcode;
}
/**
@@ -1022,87 +1388,94 @@
* @retval None
*/
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- uint32_t i2ssr = hi2s->Instance->SR;
-
+{
+ uint32_t itsource = hi2s->Instance->CR2;
+ uint32_t itflag = hi2s->Instance->SR;
+
/* I2S in mode Receiver ------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
- ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
+ (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
{
I2S_Receive_IT(hi2s);
return;
}
-
+
/* I2S in mode Tramitter -----------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
+ if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
+ {
I2S_Transmit_IT(hi2s);
return;
- }
-
- /* I2S Overrun error interrupt occured ---------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ }
+
+ /* I2S interrupt error -------------------------------------------------*/
+ if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
{
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
+ /* I2S Overrun error interrupt occurred ---------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ }
+
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ }
+
/* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
- }
-
- /* I2S Underrun error interrupt occured --------------------------------*/
- if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
-
- /* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
- HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
- * @brief Tx Transfer Half completed callbacks
+ * @brief Tx Transfer Half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Tx Transfer completed callbacks
+ * @brief Tx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Rx Transfer half completed callbacks
+ * @brief Rx Transfer half completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1113,12 +1486,12 @@
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2S_RxCpltCallback could be implemented in the user file
+ the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Rx Transfer completed callbacks
+ * @brief Rx Transfer completed callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1134,34 +1507,34 @@
}
/**
- * @brief I2S error callbacks
+ * @brief I2S error callbacks
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
+__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
- */
+ */
}
/**
* @}
*/
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State functions
+/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1201,96 +1574,123 @@
* @{
*/
/**
- * @brief DMA I2S transmit process complete callback
+ * @brief DMA I2S transmit process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
{
/* Disable Tx DMA Request */
- hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
hi2s->TxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S transmit process half complete callback
+ * @brief DMA I2S transmit process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Tx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxHalfCpltCallback(hi2s);
+#else
HAL_I2S_TxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S receive process complete callback
+ * @brief DMA I2S receive process complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ /* if DMA is configured in DMA_NORMAL Mode */
+ if (hdma->Init.Mode == DMA_NORMAL)
{
/* Disable Rx DMA Request */
- hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
- hi2s->RxXferCount = 0;
+ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0U;
hi2s->State = HAL_I2S_STATE_READY;
}
- HAL_I2S_RxCpltCallback(hi2s);
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
+ HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S receive process half complete callback
+ * @brief DMA I2S receive process half complete callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
- HAL_I2S_RxHalfCpltCallback(hi2s);
+ /* Call user Rx half complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxHalfCpltCallback(hi2s);
+#else
+ HAL_I2S_RxHalfCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief DMA I2S communication error callback
+ * @brief DMA I2S communication error callback
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+ I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+
/* Disable Rx and Tx DMA Request */
- hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
hi2s->TxXferCount = 0U;
hi2s->RxXferCount = 0U;
-
- hi2s->State= HAL_I2S_STATE_READY;
-
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
/* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ /* Call user error callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->ErrorCallback(hi2s);
+#else
HAL_I2S_ErrorCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
/**
- * @brief Transmit an amount of data in non-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
@@ -1298,90 +1698,84 @@
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
/* Transmit data */
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
+ hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
+ hi2s->pTxBuffPtr++;
hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0)
+
+ if (hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Tx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->TxCpltCallback(hi2s);
+#else
HAL_I2S_TxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
/**
-* @brief Receive an amount of data in non-blocking mode with Interrupt
-* @param hi2s I2S handle
+ * @brief Receive an amount of data in non-blocking mode with Interrupt
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
* @retval None
-*/
+ */
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
- /* Receive data */
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
+ /* Receive data */
+ (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
+ hi2s->pRxBuffPtr++;
hi2s->RxXferCount--;
-
- if(hi2s->RxXferCount == 0U)
+
+ if (hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_RxCpltCallback(hi2s);
+ hi2s->State = HAL_I2S_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
+ hi2s->RxCpltCallback(hi2s);
+#else
+ HAL_I2S_RxCpltCallback(hi2s);
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
-
/**
- * @brief This function handles I2S Communication Timeout.
+ * @brief This function handles I2S Communication Timeout.
* @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param Flag Flag checked
- * @param State Value of the flag expected
- * @param Timeout Duration of the timeout
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+ uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(State == RESET)
+ uint32_t tickstart;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until flag is set to status*/
+ while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
{
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+ if (Timeout != HAL_MAX_DELAY)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
@@ -1399,12 +1793,7 @@
/**
* @}
*/
-
-#endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
- /* defined(STM32F051x8) || defined(STM32F058xx) || */
- /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
- /* defined(STM32F042x6) || defined(STM32F048xx) || */
- /* defined(STM32F091xC) || defined(STM32F098xx) */
+#endif /* SPI_I2S_SUPPORT */
#endif /* HAL_I2S_MODULE_ENABLED */
diff --git a/Src/stm32f0xx_hal_irda.c b/Src/stm32f0xx_hal_irda.c
index 606972c..00d4c54 100644
--- a/Src/stm32f0xx_hal_irda.c
+++ b/Src/stm32f0xx_hal_irda.c
@@ -26,13 +26,13 @@
(+++) Enable the clock for the USARTx/UARTx GPIOs.
(+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input).
(++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
- and HAL_IRDA_Receive_IT() APIs):
+ and HAL_IRDA_Receive_IT() APIs):
(+++) Configure the USARTx/UARTx interrupt priority.
- (+++) Enable the NVIC USARTx/UARTx IRQ handle.
+ (+++) Enable the NVIC USARTx/UARTx IRQ handle.
(+++) The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
+
(++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
and HAL_IRDA_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
@@ -48,7 +48,7 @@
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_IRDA_MspInit() API.
-
+
-@@- The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
@@ -105,33 +105,81 @@
[..]
(@) You can refer to the IRDA HAL driver header file for more useful macros
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
+ Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : IRDA MspInit.
+ (+) MspDeInitCallback : IRDA MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
+ and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
+ or @ref HAL_IRDA_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -139,8 +187,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-
+#if defined(USART_IRDA_SUPPORT)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -157,22 +204,44 @@
/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
-#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
+#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */
+
#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \
- | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+ | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
+ * @param __PCLK__ IRDA clock source.
+ * @param __BAUD__ Baud rate set by the user.
+ * @retval Division result
+ */
+#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__))
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup IRDA_Private_Functions
* @{
*/
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@@ -185,9 +254,9 @@
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
@@ -211,7 +280,8 @@
(+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
- (++) Parity
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
(++) Power mode
(++) Prescaler setting
(++) Receiver/transmitter modes
@@ -221,18 +291,12 @@
(details for the procedures are available in reference manual).
@endverbatim
- * @{
- */
-/*
- Additional Table: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible IRDA frame formats are as listed in the following table:
+ Depending on the frame length defined either by the M bit (8-bits or 9-bits)
+ or by the M1 and M0 bits (7-bit, 8-bit or 9-bit), the possible IRDA frame
+ formats are listed in the following table.
- Table 1. IRDA frame format.
+ Table 1. IRDA frame format.
+-----------------------------------------------------------------------+
| M bit | PCE bit | IRDA frame |
|-------------------|-----------|---------------------------------------|
@@ -246,20 +310,21 @@
+-----------------------------------------------------------------------+
| M1 bit | M0 bit | PCE bit | IRDA frame |
|---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
|---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
|---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+-----------------------------------------------------------------------+
-*/
+ * @{
+ */
/**
* @brief Initialize the IRDA mode according to the specified
@@ -271,7 +336,7 @@
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == NULL)
+ if (hirda == NULL)
{
return HAL_ERROR;
}
@@ -279,13 +344,25 @@
/* Check the USART/UART associated to the IRDA handle */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
- if(hirda->gState == HAL_IRDA_STATE_RESET)
+ if (hirda->gState == HAL_IRDA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hirda->Lock = HAL_UNLOCKED;
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ IRDA_InitCallbacksToDefault(hirda);
+
+ if (hirda->MspInitCallback == NULL)
+ {
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hirda->MspInitCallback(hirda);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_IRDA_MspInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
hirda->gState = HAL_IRDA_STATE_BUSY;
@@ -324,7 +401,7 @@
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
{
/* Check the IRDA handle allocation */
- if(hirda == NULL)
+ if (hirda == NULL)
{
return HAL_ERROR;
}
@@ -335,7 +412,16 @@
hirda->gState = HAL_IRDA_STATE_BUSY;
/* DeInit the low level hardware */
+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
+ if (hirda->MspDeInitCallback == NULL)
+ {
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hirda->MspDeInitCallback(hirda);
+#else
HAL_IRDA_MspDeInit(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/* Disable the Peripheral */
__HAL_IRDA_DISABLE(hirda);
@@ -381,6 +467,245 @@
*/
}
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User IRDA Callback
+ * To be used instead of the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+ pIRDA_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (hirda->gState == HAL_IRDA_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hirda->gState == HAL_IRDA_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = pCallback;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an IRDA callback
+ * IRDA callback is redirected to the weak predefined callback
+ * @param hirda irda handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hirda);
+
+ if (HAL_IRDA_STATE_READY == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_TX_HALFCOMPLETE_CB_ID :
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_TX_COMPLETE_CB_ID :
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_HALFCOMPLETE_CB_ID :
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_IRDA_RX_COMPLETE_CB_ID :
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_IRDA_ERROR_CB_ID :
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_IRDA_ABORT_COMPLETE_CB_ID :
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_IRDA_STATE_RESET == hirda->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_IRDA_MSPINIT_CB_ID :
+ hirda->MspInitCallback = HAL_IRDA_MspInit;
+ break;
+
+ case HAL_IRDA_MSPDEINIT_CB_ID :
+ hirda->MspDeInitCallback = HAL_IRDA_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hirda);
+
+ return status;
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -390,7 +715,7 @@
*
@verbatim
===============================================================================
- ##### IO operation functions #####
+ ##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
@@ -402,7 +727,8 @@
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
- (#) There are two mode of transfer:
+ [..]
+ (#) There are two modes of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
@@ -453,51 +779,57 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
*/
/**
- * @brief Send an amount of data in blocking mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @param Timeout Specify timeout value.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
- * @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
- if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -514,27 +846,40 @@
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0U)
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ while (hirda->TxXferCount > 0U)
{
hirda->TxXferCount--;
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pData += 2;
+ hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
}
else
{
- hirda->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
}
}
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -554,38 +899,44 @@
}
/**
- * @brief Receive an amount of data in blocking mode.
+ * @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @param Timeout Specify timeout value.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Specify timeout value.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
- * @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be received from RDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
- if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -608,24 +959,36 @@
IRDA_MASK_COMPUTATION(hirda);
uhMask = hirda->Mask;
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
/* Check data remaining to be received */
- while(hirda->RxXferCount > 0U)
+ while (hirda->RxXferCount > 0U)
{
hirda->RxXferCount--;
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(hirda->Instance->RDR & uhMask);
- pData +=2;
+ *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask);
+ pdata16bits++;
}
else
{
- *pData++ = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
}
}
@@ -644,33 +1007,38 @@
}
/**
- * @brief Send an amount of data in interrupt mode.
+ * @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
- * @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
- if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -701,33 +1069,38 @@
}
/**
- * @brief Receive an amount of data in interrupt mode.
+ * @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the configuration information for the specified IRDA module.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
- * @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be received from RDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
- if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -751,7 +1124,7 @@
__HAL_UNLOCK(hirda);
/* Enable the IRDA Parity Error and Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -765,33 +1138,38 @@
}
/**
- * @brief Send an amount of data in DMA mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @param pData pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
- * @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(hirda->gState == HAL_IRDA_STATE_READY)
+ if (hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data copy into TDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
+ should be aligned on a u16 frontier, as data copy into TDR will be
handled by DMA from a u16 frontier. */
- if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -820,19 +1198,33 @@
hirda->hdmatx->XferAbortCallback = NULL;
/* Enable the IRDA transmit DMA channel */
- HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size);
+ if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
- /* Clear the TC flag in the ICR register */
- __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->gState to ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -841,33 +1233,40 @@
}
/**
- * @brief Receive an amount of data in DMA mode.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
+ * @note When the IRDA parity is enabled (PCE = 1), the received data contains
+ * the parity bit (MSB position).
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+/**
+ * @note When IRDA parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
- * @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hirda->RxState == HAL_IRDA_STATE_READY)
+ if (hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data copy from RDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
+ should be aligned on a u16 frontier, as data copy from RDR will be
handled by DMA from a u16 frontier. */
- if ((hirda->Init.WordLength == UART_WORDLENGTH_9B) && (hirda->Init.Parity == UART_PARITY_NONE))
+ if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -895,22 +1294,36 @@
hirda->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size);
+ if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ /* Restore hirda->RxState to ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -920,9 +1333,9 @@
/**
- * @brief Pause the DMA Transfer.
+ * @brief Pause the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
@@ -930,21 +1343,25 @@
/* Process Locked */
__HAL_LOCK(hirda);
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- /* Disable the IRDA DMA Tx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable the IRDA DMA Tx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+ }
}
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
- /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Disable the IRDA DMA Rx request */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ /* Disable the IRDA DMA Rx request */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ }
}
/* Process Unlocked */
@@ -954,9 +1371,9 @@
}
/**
- * @brief Resume the DMA Transfer.
+ * @brief Resume the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
@@ -964,12 +1381,12 @@
/* Process Locked */
__HAL_LOCK(hirda);
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
- if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
@@ -989,48 +1406,70 @@
}
/**
- * @brief Stop the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() /
- HAL_IRDA_TxHalfCpltCallback() / HAL_IRDA_RxHalfCpltCallback():
+ HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback:
indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
/* Stop IRDA DMA Tx request if ongoing */
- if ((hirda->gState == HAL_IRDA_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)))
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Abort the IRDA DMA Tx channel */
- if(hirda->hdmatx != NULL)
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
- HAL_DMA_Abort(hirda->hdmatx);
- }
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- IRDA_EndTxTransfer(hirda);
+ /* Abort the IRDA DMA Tx channel */
+ if (hirda->hdmatx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ IRDA_EndTxTransfer(hirda);
+ }
}
/* Stop IRDA DMA Rx request if ongoing */
- if ((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
- /* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
- HAL_DMA_Abort(hirda->hdmarx);
- }
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- IRDA_EndRxTransfer(hirda);
+ /* Abort the IRDA DMA Rx channel */
+ if (hirda->hdmarx != NULL)
+ {
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ IRDA_EndRxTransfer(hirda);
+ }
}
return HAL_OK;
@@ -1040,7 +1479,7 @@
* @brief Abort ongoing transfers (blocking mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1048,7 +1487,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1061,13 +1500,22 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
- /* Set the IRDA DMA Abort callback to Null.
+ /* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmatx);
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -1077,19 +1525,28 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
- /* Set the IRDA DMA Abort callback to Null.
+ /* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmarx);
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0U;
- hirda->RxXferCount = 0U;
+ hirda->TxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1108,7 +1565,7 @@
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1116,7 +1573,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
@@ -1128,18 +1585,27 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
- /* Set the IRDA DMA Abort callback to Null.
+ /* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmatx);
+ if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx transfer counter */
- hirda->TxXferCount = 0U;
+ hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
@@ -1151,7 +1617,7 @@
* @brief Abort ongoing Receive transfer (blocking mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1159,7 +1625,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1172,18 +1638,27 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
- /* Set the IRDA DMA Abort callback to Null.
+ /* Set the IRDA DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hirda->hdmarx);
+ if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hirda->ErrorCode = HAL_IRDA_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Rx transfer counter */
- hirda->RxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1198,7 +1673,7 @@
* @brief Abort ongoing transfers (Interrupt mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1208,11 +1683,11 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
{
uint32_t abortcplt = 1U;
-
+
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1220,11 +1695,11 @@
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
}
@@ -1234,11 +1709,11 @@
}
}
/* DMA Rx Handle is valid */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
{
hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
}
@@ -1247,21 +1722,21 @@
hirda->hdmarx->XferAbortCallback = NULL;
}
}
-
+
/* Disable the IRDA DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
- /* IRDA Tx DMA Abort callback has already been initialised :
+ /* IRDA Tx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
hirda->hdmatx->XferAbortCallback = NULL;
}
@@ -1278,20 +1753,20 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
- /* IRDA Rx DMA Abort callback has already been initialised :
+ /* IRDA Rx DMA Abort callback has already been initialised :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
hirda->hdmarx->XferAbortCallback = NULL;
- abortcplt = 1;
+ abortcplt = 1U;
}
else
{
- abortcplt = 0;
+ abortcplt = 0U;
}
}
}
@@ -1300,7 +1775,7 @@
if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
- hirda->TxXferCount = 0U;
+ hirda->TxXferCount = 0U;
hirda->RxXferCount = 0U;
/* Reset errorCode */
@@ -1314,7 +1789,13 @@
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1324,7 +1805,7 @@
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1334,7 +1815,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE and TCIE interrupts */
@@ -1346,14 +1827,14 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
/* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
- /* Set the IRDA DMA Abort callback :
+ /* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
{
/* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
@@ -1362,25 +1843,37 @@
else
{
/* Reset Tx transfer counter */
- hirda->TxXferCount = 0U;
+ hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Tx transfer counter */
- hirda->TxXferCount = 0U;
+ hirda->TxXferCount = 0U;
/* Restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1390,7 +1883,7 @@
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable IRDA Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1400,7 +1893,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1413,14 +1906,14 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
- /* Set the IRDA DMA Abort callback :
+ /* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
@@ -1429,7 +1922,7 @@
else
{
/* Reset Rx transfer counter */
- hirda->RxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1438,13 +1931,19 @@
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
/* Reset Rx transfer counter */
- hirda->RxXferCount = 0U;
+ hirda->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF);
@@ -1453,15 +1952,21 @@
hirda->RxState = HAL_IRDA_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
- * @brief Handle IRDA interrupt request.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Handle IRDA interrupt request.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1471,27 +1976,28 @@
uint32_t cr1its = READ_REG(hirda->Instance->CR1);
uint32_t cr3its;
uint32_t errorflags;
+ uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
+ if (errorflags == 0U)
{
/* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
IRDA_Receive_IT(hirda);
return;
}
- }
+ }
/* If some errors occur */
cr3its = READ_REG(hirda->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
{
/* IRDA parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF);
@@ -1499,7 +2005,7 @@
}
/* IRDA frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF);
@@ -1507,7 +2013,7 @@
}
/* IRDA noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF);
@@ -1515,8 +2021,8 @@
}
/* IRDA Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ if (((isrflags & USART_ISR_ORE) != 0U) &&
+ (((cr1its & USART_CR1_RXNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U)))
{
__HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF);
@@ -1524,19 +2030,20 @@
}
/* Call IRDA Error Call back function if need be --------------------------*/
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
{
/* IRDA in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
IRDA_Receive_IT(hirda);
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
- if (((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)))
- {
+ errorcode = hirda->ErrorCode;
+ if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & HAL_IRDA_ERROR_ORE) != 0U))
+ {
/* Blocking error : transfer is aborted
Set the IRDA state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
@@ -1548,14 +2055,14 @@
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
/* Abort the IRDA DMA Rx channel */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
- /* Set the IRDA DMA Abort callback :
+ /* Set the IRDA DMA Abort callback :
will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
{
/* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
@@ -1563,21 +2070,37 @@
}
else
{
- /* Call user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
else
{
- /* Non Blocking error : transfer could go on.
+ /* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
}
}
@@ -1586,14 +2109,14 @@
} /* End if some error occurs */
/* IRDA in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_ISR_TXE) != 0U) && ((cr1its & USART_CR1_TXEIE) != 0U))
{
IRDA_Transmit_IT(hirda);
return;
}
/* IRDA in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
{
IRDA_EndTransmit_IT(hirda);
return;
@@ -1652,7 +2175,7 @@
/**
* @brief Rx Half Transfer complete callback.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * the configuration information for the specified IRDA module.
* @retval None
*/
__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
@@ -1687,7 +2210,7 @@
* the configuration information for the specified IRDA module.
* @retval None
*/
-__weak void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -1703,7 +2226,7 @@
* the configuration information for the specified IRDA module.
* @retval None
*/
-__weak void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -1719,7 +2242,7 @@
* the configuration information for the specified IRDA module.
* @retval None
*/
-__weak void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
@@ -1733,7 +2256,7 @@
* @}
*/
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Error functions
+/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
* @brief IRDA State and Errors functions
*
@verbatim
@@ -1753,24 +2276,25 @@
*/
/**
- * @brief Return the IRDA handle state.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified IRDA module.
+ * @brief Return the IRDA handle state.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * the configuration information for the specified IRDA module.
* @retval HAL state
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
/* Return IRDA handle state */
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hirda->gState;
- temp2 = hirda->RxState;
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = (uint32_t)hirda->gState;
+ temp2 = (uint32_t)hirda->RxState;
return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
- * @brief Return the IRDA handle error code.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Return the IRDA handle error code.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval IRDA Error Code
*/
@@ -1791,17 +2315,39 @@
* @{
*/
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
- * @brief Configure the IRDA peripheral.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Initialize the callbacks to their default values.
+ * @param hirda IRDA handle.
+ * @retval none
+ */
+void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda)
+{
+ /* Init the IRDA Callback settings */
+ hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */
+ hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the IRDA peripheral.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval None
+ * @retval HAL status
*/
static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
- uint32_t tmpreg = 0x00000000U;
- IRDA_ClockSourceTypeDef clocksource = IRDA_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t tmpreg;
+ IRDA_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t pclk;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@@ -1823,43 +2369,56 @@
/*-------------------------- USART CR3 Configuration -----------------------*/
MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode);
+
/*-------------------------- USART GTPR Configuration ----------------------*/
- MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
+ MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource);
+ tmpreg = 0U;
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_HSI:
- hirda->Instance->BRR = (uint16_t)((HSI_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
- hirda->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate));
break;
case IRDA_CLOCKSOURCE_LSE:
- hirda->Instance->BRR = (uint16_t)((LSE_VALUE + (hirda->Init.BaudRate/2)) / hirda->Init.BaudRate);
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate));
break;
- case IRDA_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hirda->Instance->BRR = tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
return ret;
}
/**
- * @brief Check the IRDA Idle State.
- * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Check the IRDA Idle State.
+ * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
@@ -1867,35 +2426,26 @@
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
- Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
- */
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
- if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hirda->Instance))
+ /* Check if the Transmitter is enabled */
+ if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
- /* Check if the Transmitter is enabled */
- if((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ /* Wait until TEACK flag is set */
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
{
- /* Wait until TEACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the Receiver is enabled */
- if((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
}
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+ /* Check if the Receiver is enabled */
+ if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
/* Initialize the IRDA state*/
hirda->gState = HAL_IRDA_STATE_READY;
@@ -1912,20 +2462,21 @@
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param Flag Specifies the IRDA flag to check.
- * @param Status the new flag status (SET or RESET). The function is locked in a while loop as long as the flag remains set to Status.
+ * @param Status Flag status (SET or RESET)
* @param Tickstart Tick start value
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
+ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
@@ -1936,7 +2487,6 @@
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
return HAL_TIMEOUT;
}
}
@@ -1986,10 +2536,10 @@
*/
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
hirda->TxXferCount = 0U;
@@ -2003,7 +2553,13 @@
/* DMA Circular mode */
else
{
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
}
@@ -2016,9 +2572,15 @@
*/
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half complete callback */
+ hirda->TxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2029,10 +2591,10 @@
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
hirda->RxXferCount = 0U;
@@ -2048,7 +2610,13 @@
hirda->RxState = HAL_IRDA_STATE_READY;
}
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
/**
@@ -2059,39 +2627,55 @@
*/
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ hirda->RxHalfCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx Half complete callback */
HAL_IRDA_RxHalfCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
- * @brief DMA IRDA communication error callback.
- * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA IRDA communication error callback.
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
/* Stop IRDA DMA Tx request if ongoing */
- if ( (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) )
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- hirda->TxXferCount = 0U;
- IRDA_EndTxTransfer(hirda);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
}
/* Stop IRDA DMA Rx request if ongoing */
- if ( (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) )
+ if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
- hirda->RxXferCount = 0;
- IRDA_EndRxTransfer(hirda);
+ if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
}
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2102,11 +2686,17 @@
*/
static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->RxXferCount = 0U;
hirda->TxXferCount = 0U;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hirda->ErrorCallback(hirda);
+#else
+ /* Call legacy weak user error callback */
HAL_IRDA_ErrorCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2119,19 +2709,19 @@
*/
static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
-
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
hirda->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hirda->hdmarx != NULL)
+ if (hirda->hdmarx != NULL)
{
- if(hirda->hdmarx->XferAbortCallback != NULL)
+ if (hirda->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0U;
hirda->RxXferCount = 0U;
@@ -2147,7 +2737,13 @@
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
@@ -2161,19 +2757,19 @@
*/
static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef* )(hdma->Parent);
-
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
+
hirda->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hirda->hdmatx != NULL)
+ if (hirda->hdmatx != NULL)
{
- if(hirda->hdmatx->XferAbortCallback != NULL)
+ if (hirda->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hirda->TxXferCount = 0U;
hirda->RxXferCount = 0U;
@@ -2189,7 +2785,13 @@
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hirda->AbortCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_IRDA_AbortCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
@@ -2203,7 +2805,7 @@
*/
static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = (IRDA_HandleTypeDef*)(hdma->Parent);
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent);
hirda->TxXferCount = 0U;
@@ -2211,7 +2813,13 @@
hirda->gState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hirda->AbortTransmitCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_IRDA_AbortTransmitCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2224,7 +2832,7 @@
*/
static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
hirda->RxXferCount = 0U;
@@ -2235,7 +2843,13 @@
hirda->RxState = HAL_IRDA_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hirda->AbortReceiveCpltCallback(hirda);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_IRDA_AbortReceiveCpltCallback(hirda);
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2244,55 +2858,48 @@
* interruptions have been enabled by HAL_IRDA_Transmit_IT().
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
+static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp;
+ uint16_t *tmp;
/* Check that a Tx process is ongoing */
- if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
+ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
- if(hirda->TxXferCount == 0U)
+ if (hirda->TxXferCount == 0U)
{
/* Disable the IRDA Transmit Data Register Empty Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
/* Enable the IRDA Transmit Complete Interrupt */
SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
}
else
{
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- tmp = (uint16_t*) hirda->pTxBuffPtr;
- hirda->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
+ tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+ hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
hirda->pTxBuffPtr += 2U;
}
else
{
- hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0xFFU);
+ hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU);
+ hirda->pTxBuffPtr++;
}
hirda->TxXferCount--;
-
- return HAL_OK;
}
}
- else
- {
- return HAL_BUSY;
- }
}
/**
* @brief Wrap up transmission in non-blocking mode.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
+static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable the IRDA Transmit Complete Interrupt */
CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
@@ -2300,9 +2907,13 @@
/* Tx process is ended, restore hirda->gState to Ready */
hirda->gState = HAL_IRDA_STATE_READY;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hirda->TxCpltCallback(hirda);
+#else
+ /* Call legacy weak Tx complete callback */
HAL_IRDA_TxCpltCallback(hirda);
-
- return HAL_OK;
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */
}
/**
@@ -2311,11 +2922,11 @@
* interruptions have been enabled by HAL_IRDA_Receive_IT()
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
+static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp;
+ uint16_t *tmp;
uint16_t uhMask = hirda->Mask;
uint16_t uhdata;
@@ -2325,16 +2936,18 @@
uhdata = (uint16_t) READ_REG(hirda->Instance->RDR);
if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
{
- tmp = (uint16_t*) hirda->pRxBuffPtr ;
+ tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */
*tmp = (uint16_t)(uhdata & uhMask);
- hirda->pRxBuffPtr +=2U;
+ hirda->pRxBuffPtr += 2U;
}
else
{
- *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
+ *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ hirda->pRxBuffPtr++;
}
- if(--hirda->RxXferCount == 0U)
+ hirda->RxXferCount--;
+ if (hirda->RxXferCount == 0U)
{
/* Disable the IRDA Parity Error Interrupt and RXNE interrupt */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
@@ -2345,19 +2958,19 @@
/* Rx process is completed, restore hirda->RxState to Ready */
hirda->RxState = HAL_IRDA_STATE_READY;
+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hirda->RxCpltCallback(hirda);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_IRDA_RxCpltCallback(hirda);
-
- return HAL_OK;
+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
}
-
- return HAL_OK;
}
else
{
/* Clear RXNE interrupt flag */
__HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
}
}
@@ -2373,7 +2986,6 @@
/**
* @}
*/
-
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
+#endif /* USART_IRDA_SUPPORT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_iwdg.c b/Src/stm32f0xx_hal_iwdg.c
index 1899f1f..de98403 100644
--- a/Src/stm32f0xx_hal_iwdg.c
+++ b/Src/stm32f0xx_hal_iwdg.c
@@ -3,7 +3,7 @@
* @file stm32f0xx_hal_iwdg.c
* @author MCD Application Team
* @brief IWDG HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and Start functions
* + IO operation functions
@@ -19,12 +19,12 @@
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
- (+) Once the IWDG is started, the LSI is forced ON and both can not be
+ (+) Once the IWDG is started, the LSI is forced ON and both can not be
disabled. The counter starts counting down from the reset value (0xFFF).
- When it reaches the end of count value (0x000) a reset signal is
+ When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
- (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
@@ -34,11 +34,11 @@
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
- the IWDG counter either continues to work normally or stops, depending
+ the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
- [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~26.2s
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
@@ -48,18 +48,18 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
- (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
- clock is forced ON and IWDG counter starts downcounting.
- (++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
- IWDG_WINR.
- (++) Configure the IWDG prescaler and counter reload value. This reload
- value will be loaded in the IWDG counter each time the watchdog is
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts counting down.
+ (++) Enable write access to configuration registers:
+ IWDG_PR, IWDG_RLR and IWDG_WINR.
+ (++) Configure the IWDG prescaler and counter reload value. This reload
+ value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (++) wait for status flags to be reset"
+ (++) Wait for status flags to be reset.
(++) Depending on window parameter:
- (+++) If Window Init parameter is same as Window register value,
- nothing more is done but reload counter value in order to exit
- function withy exact time base.
+ (+++) If Window Init parameter is same as Window register value,
+ nothing more is done but reload counter value in order to exit
+ function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
@@ -79,29 +79,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -124,10 +108,10 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to LSI variation, we need to wait at
- least 6 cycles so 39 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 39U
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
+ higher prescaler (256), and according to LSI variation, we need to wait at
+ least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
* @}
*/
@@ -142,17 +126,17 @@
*/
/** @addtogroup IWDG_Exported_Functions_Group1
- * @brief Initialization and Start functions.
- *
+ * @brief Initialization and Start functions.
+ *
@verbatim
===============================================================================
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Initialize the IWDG according to the specified parameters in the
+ (+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Manage Window option.
- (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
@@ -160,8 +144,8 @@
*/
/**
- * @brief Initialize the IWDG according to the specified parameters in the
- * IWDG_InitTypeDef and start watchdog. Before exiting function,
+ * @brief Initialize the IWDG according to the specified parameters in the
+ * IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
@@ -172,7 +156,7 @@
uint32_t tickstart;
/* Check the IWDG handle allocation */
- if(hiwdg == NULL)
+ if (hiwdg == NULL)
{
return HAL_ERROR;
}
@@ -183,7 +167,7 @@
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
- /* Enable IWDG. LSI is turned on automaticaly */
+ /* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
@@ -197,21 +181,21 @@
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
- /* Wait for register to be updated */
- while(hiwdg->Instance->SR != RESET)
+ /* Wait for register to be updated */
+ while (hiwdg->Instance->SR != 0x00u)
{
- if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
- /* If window parameter is different than current value, modify window
+ /* If window parameter is different than current value, modify window
register */
- if(hiwdg->Instance->WINR != hiwdg->Init.Window)
+ if (hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
- even if window feature is disabled, Watchdog will be reloaded by writing
+ even if window feature is disabled, Watchdog will be reloaded by writing
windows register */
hiwdg->Instance->WINR = hiwdg->Init.Window;
}
@@ -231,8 +215,8 @@
/** @addtogroup IWDG_Exported_Functions_Group2
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
diff --git a/Src/stm32f0xx_hal_msp_template.c b/Src/stm32f0xx_hal_msp_template.c
index 9600b21..24f2d53 100644
--- a/Src/stm32f0xx_hal_msp_template.c
+++ b/Src/stm32f0xx_hal_msp_template.c
@@ -16,32 +16,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
diff --git a/Src/stm32f0xx_hal_pcd.c b/Src/stm32f0xx_hal_pcd.c
index a802483..b909612 100644
--- a/Src/stm32f0xx_hal_pcd.c
+++ b/Src/stm32f0xx_hal_pcd.c
@@ -3,13 +3,13 @@
* @file stm32f0xx_hal_pcd.c
* @author MCD Application Team
* @brief PCD HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,52 +19,36 @@
(#) Declare a PCD_HandleTypeDef handle structure, for example:
PCD_HandleTypeDef hpcd;
-
+
(#) Fill parameters of Init structure in HCD handle
-
- (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...)
+
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
- (##) Enable the PCD/USB Low Level interface clock using
- (+++) __HAL_RCC_USB_CLK_ENABLE);
-
+ (##) Enable the PCD/USB Low Level interface clock using
+ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
+
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
(##) Configure PCD NVIC interrupt
-
+
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
- (#)Enable HCD transmission and reception:
+ (#)Enable PCD transmission and reception:
(##) HAL_PCD_Start();
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -76,162 +60,187 @@
* @{
*/
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
-
/** @defgroup PCD PCD
* @brief PCD HAL module driver
* @{
*/
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+#ifdef HAL_PCD_MODULE_ENABLED
-/** @defgroup PCD_Private_Define PCD Private Define
+#if defined (USB)
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
-#define BTABLE_ADDRESS (0x000)
+#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
/**
* @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
/** @defgroup PCD_Private_Functions PCD Private Functions
* @{
*/
+
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
-void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
+
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
-
+
@endverbatim
* @{
*/
/**
* @brief Initializes the PCD according to the specified
- * parameters in the PCD_InitTypeDef and create the associated handle.
+ * parameters in the PCD_InitTypeDef and initialize the associated handle.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
- uint32_t i = 0U;
+{
+ uint8_t i;
- uint32_t wInterrupt_Mask = 0U;
-
/* Check the PCD handle allocation */
- if(hpcd == NULL)
+ if (hpcd == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
- if(hpcd->State == HAL_PCD_STATE_RESET)
- {
+ if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
-
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;
+ hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;
+
+ if (hpcd->MspInitCallback == NULL)
+ {
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hpcd->MspInitCallback(hpcd);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
+#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */
}
hpcd->State = HAL_PCD_STATE_BUSY;
-
- /* Init endpoints structures */
- for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
- {
- /* Init ep structure */
- hpcd->IN_ep[i].is_in = 1U;
- hpcd->IN_ep[i].num = i;
- /* Control until ep is actvated */
- hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
- hpcd->IN_ep[i].maxpacket = 0U;
- hpcd->IN_ep[i].xfer_buff = 0U;
- hpcd->IN_ep[i].xfer_len = 0U;
- }
-
- for (i = 0U; i < hpcd->Init.dev_endpoints ; i++)
- {
- hpcd->OUT_ep[i].is_in = 0U;
- hpcd->OUT_ep[i].num = i;
- /* Control until ep is activated */
- hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
- hpcd->OUT_ep[i].maxpacket = 0U;
- hpcd->OUT_ep[i].xfer_buff = 0U;
- hpcd->OUT_ep[i].xfer_len = 0U;
- }
-
- /* Init Device */
- /*CNTR_FRES = 1*/
- hpcd->Instance->CNTR = USB_CNTR_FRES;
-
- /*CNTR_FRES = 0*/
- hpcd->Instance->CNTR = 0;
-
- /*Clear pending interrupts*/
- hpcd->Instance->ISTR = 0;
-
- /*Set Btable Adress*/
- hpcd->Instance->BTABLE = BTABLE_ADDRESS;
-
- /*set wInterrupt_Mask global variable*/
- wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-
- /*Set interrupt mask*/
- hpcd->Instance->CNTR = wInterrupt_Mask;
-
- hpcd->USB_Address = 0U;
- hpcd->State= HAL_PCD_STATE_READY;
- return HAL_OK;
+ /* Disable the Interrupts */
+ __HAL_PCD_DISABLE(hpcd);
+
+ /* Init endpoints structures */
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ /* Init ep structure */
+ hpcd->IN_ep[i].is_in = 1U;
+ hpcd->IN_ep[i].num = i;
+ hpcd->IN_ep[i].tx_fifo_num = i;
+ /* Control until ep is activated */
+ hpcd->IN_ep[i].type = EP_TYPE_CTRL;
+ hpcd->IN_ep[i].maxpacket = 0U;
+ hpcd->IN_ep[i].xfer_buff = 0U;
+ hpcd->IN_ep[i].xfer_len = 0U;
+ }
+
+ for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
+ {
+ hpcd->OUT_ep[i].is_in = 0U;
+ hpcd->OUT_ep[i].num = i;
+ /* Control until ep is activated */
+ hpcd->OUT_ep[i].type = EP_TYPE_CTRL;
+ hpcd->OUT_ep[i].maxpacket = 0U;
+ hpcd->OUT_ep[i].xfer_buff = 0U;
+ hpcd->OUT_ep[i].xfer_len = 0U;
+ }
+
+ /* Init Device */
+ (void)USB_DevInit(hpcd->Instance, hpcd->Init);
+
+ hpcd->USB_Address = 0U;
+ hpcd->State = HAL_PCD_STATE_READY;
+
+ /* Activate LPM */
+ if (hpcd->Init.lpm_enable == 1U)
+ {
+ (void)HAL_PCDEx_ActivateLPM(hpcd);
+ }
+
+ return HAL_OK;
}
/**
- * @brief DeInitializes the PCD peripheral
+ * @brief DeInitializes the PCD peripheral.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
{
/* Check the PCD handle allocation */
- if(hpcd == NULL)
+ if (hpcd == NULL)
{
return HAL_ERROR;
}
hpcd->State = HAL_PCD_STATE_BUSY;
-
+
/* Stop Device */
- HAL_PCD_Stop(hpcd);
-
+ (void)HAL_PCD_Stop(hpcd);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ if (hpcd->MspDeInitCallback == NULL)
+ {
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
/* DeInit the low level hardware */
+ hpcd->MspDeInitCallback(hpcd);
+#else
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_PCD_MspDeInit(hpcd);
-
- hpcd->State = HAL_PCD_STATE_RESET;
-
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
return HAL_OK;
}
@@ -245,7 +254,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implemented in the user file
*/
}
@@ -260,40 +269,702 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_MspDeInit could be implemented in the user file
*/
}
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User USB PCD Callback
+ * To be used instead of the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = pCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = pCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = pCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = pCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = pCallback;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Unregister an USB PCD Callback
+ * USB PCD callabck is redirected to the weak predefined callback
+ * @param hpcd USB PCD handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID
+ * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID
+ * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID
+ * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
+ * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
+ * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
+ * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ /* Setup Legacy weak Callbacks */
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_SOF_CB_ID :
+ hpcd->SOFCallback = HAL_PCD_SOFCallback;
+ break;
+
+ case HAL_PCD_SETUPSTAGE_CB_ID :
+ hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;
+ break;
+
+ case HAL_PCD_RESET_CB_ID :
+ hpcd->ResetCallback = HAL_PCD_ResetCallback;
+ break;
+
+ case HAL_PCD_SUSPEND_CB_ID :
+ hpcd->SuspendCallback = HAL_PCD_SuspendCallback;
+ break;
+
+ case HAL_PCD_RESUME_CB_ID :
+ hpcd->ResumeCallback = HAL_PCD_ResumeCallback;
+ break;
+
+ case HAL_PCD_CONNECT_CB_ID :
+ hpcd->ConnectCallback = HAL_PCD_ConnectCallback;
+ break;
+
+ case HAL_PCD_DISCONNECT_CB_ID :
+ hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;
+ break;
+
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hpcd->State == HAL_PCD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_PCD_MSPINIT_CB_ID :
+ hpcd->MspInitCallback = HAL_PCD_MspInit;
+ break;
+
+ case HAL_PCD_MSPDEINIT_CB_ID :
+ hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data OUT Stage Callback
+ * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data OUT Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Data OUT Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Data IN Stage Callback
+ * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Data IN Stage Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Data IN Stage Callback
+ * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso OUT incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Iso OUT incomplete Callback
+ * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD Iso IN incomplete Callback
+ * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD Iso IN incomplete Callback
+ * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD BCD Callback
+ * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD BCD Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->BCDCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD BCD Callback
+ * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief Register USB PCD LPM Callback
+ * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @param pCallback pointer to the USB PCD LPM Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the USB PCD LPM Callback
+ * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hpcd);
+
+ if (hpcd->State == HAL_PCD_STATE_READY)
+ {
+ hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */
+ }
+ else
+ {
+ /* Update the error code */
+ hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hpcd);
+
+ return status;
+}
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
+/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the PCD data
+ This subsection provides a set of functions allowing to manage the PCD data
transfers.
@endverbatim
* @{
*/
-
+
/**
- * @brief Start the USB device.
+ * @brief Start the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
- /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
- hpcd->Instance->BCDR |= USB_BCDR_DPPU;
-
+{
+ __HAL_LOCK(hpcd);
+ (void)USB_DevConnect(hpcd->Instance);
+ __HAL_PCD_ENABLE(hpcd);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
@@ -303,22 +974,18 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
-
- /* disable all interrupts and force USB reset */
- hpcd->Instance->CNTR = USB_CNTR_FRES;
-
- /* clear interrupt status register */
- hpcd->Instance->ISTR = 0;
-
- /* switch-off device */
- hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
-
- __HAL_UNLOCK(hpcd);
+{
+ __HAL_LOCK(hpcd);
+ __HAL_PCD_DISABLE(hpcd);
+
+ (void)USB_StopDevice(hpcd->Instance);
+
+ __HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
+
/**
* @brief This function handles PCD interrupt request.
* @param hpcd PCD handle
@@ -326,261 +993,312 @@
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
- uint32_t wInterrupt_Mask = 0U;
-
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
- PCD_EP_ISR_Handler(hpcd);
+ (void)PCD_EP_ISR_Handler(hpcd);
}
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResetCallback(hpcd);
+#else
HAL_PCD_ResetCallback(hpcd);
- HAL_PCD_SetAddress(hpcd, 0U);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ (void)HAL_PCD_SetAddress(hpcd, 0U);
}
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))
{
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
}
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))
{
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
}
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
{
-
- hpcd->Instance->CNTR &= (uint16_t)(~(USB_CNTR_LPMODE));
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
+ hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
- /*set wInterrupt_Mask global variable*/
- wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-
- /*Set interrupt mask*/
- hpcd->Instance->CNTR = wInterrupt_Mask;
-
+ if (hpcd->LPM_State == LPM_L1)
+ {
+ hpcd->LPM_State = LPM_L0;
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);
+#else
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->ResumeCallback(hpcd);
+#else
HAL_PCD_ResumeCallback(hpcd);
-
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
}
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
- {
- /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
+ {
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP) == 0U)
{
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
+ /* Handle LPM Interrupt */
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_L1REQ))
{
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
- HAL_PCD_SOFCallback(hpcd);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ);
+ if (hpcd->LPM_State == LPM_L0)
+ {
+ /* Force suspend and low-power mode before going to L1 state*/
+ hpcd->Instance->CNTR |= USB_CNTR_LPMODE;
+ hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+
+ hpcd->LPM_State = LPM_L1;
+ hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2;
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);
+#else
+ HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SuspendCallback(hpcd);
+#else
+ HAL_PCD_SuspendCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
}
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))
+ {
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SOFCallback(hpcd);
+#else
+ HAL_PCD_SOFCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+ if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))
{
/* clear ESOF flag in ISTR */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
}
}
+
/**
- * @brief Data out stage callbacks
+ * @brief Data OUT stage callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Data IN stage callbacks
+ * @brief Data IN stage callback
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DataInStageCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Setup stage callback
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SetupStageCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief USB Start Of Frame callbacks
+ * @brief USB Start Of Frame callback.
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SOFCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief USB Reset callbacks
+ * @brief USB Reset callback.
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResetCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Suspend event callbacks
+ * @brief Suspend event callback.
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_SuspendCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Resume event callbacks
+ * @brief Resume event callback.
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ResumeCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Incomplete ISO OUT callbacks
+ * @brief Incomplete ISO OUT callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Incomplete ISO IN callbacks
+ * @brief Incomplete ISO IN callback.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval None
*/
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(epnum);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Connection event callbacks
+ * @brief Connection event callback.
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_ConnectCallback could be implemented in the user file
- */
+ */
}
/**
- * @brief Disconnection event callbacks
+ * @brief Disconnection event callback.
* @param hpcd PCD handle
* @retval None
*/
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
+__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCD_DisconnectCallback could be implemented in the user file
- */
+ */
}
+
/**
* @}
*/
-
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
+
+/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the PCD data
+ This subsection provides a set of functions allowing to control the PCD data
transfers.
@endverbatim
@@ -588,287 +1306,150 @@
*/
/**
- * @brief Connect the USB device
+ * @brief Connect the USB device
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{
- __HAL_LOCK(hpcd);
-
- /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
- hpcd->Instance->BCDR |= USB_BCDR_DPPU;
-
- __HAL_UNLOCK(hpcd);
+ __HAL_LOCK(hpcd);
+ (void)USB_DevConnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Disconnect the USB device
+ * @brief Disconnect the USB device.
* @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{
- __HAL_LOCK(hpcd);
-
- /* Disable DP Pull-Down bit*/
- hpcd->Instance->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
-
- __HAL_UNLOCK(hpcd);
+ __HAL_LOCK(hpcd);
+ (void)USB_DevDisconnect(hpcd->Instance);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Set the USB Device address
+ * @brief Set the USB Device address.
* @param hpcd PCD handle
* @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
- __HAL_LOCK(hpcd);
-
- if(address == 0U)
- {
- /* set device address and enable function */
- hpcd->Instance->DADDR = USB_DADDR_EF;
- }
- else /* USB Address will be applied later */
- {
- hpcd->USB_Address = address;
- }
-
- __HAL_UNLOCK(hpcd);
+ __HAL_LOCK(hpcd);
+ hpcd->USB_Address = address;
+ (void)USB_SetDevAddress(hpcd->Instance, address);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Open and configure an endpoint
+ * @brief Open and configure an endpoint.
* @param hpcd PCD handle
* @param ep_addr endpoint address
- * @param ep_mps endpoint max packert size
- * @param ep_type endpoint type
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
-
+
if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
}
- ep->num = ep_addr & 0x7FU;
-
- ep->is_in = (0x80U & ep_addr) != 0U;
+
+ ep->num = ep_addr & EP_ADDR_MSK;
ep->maxpacket = ep_mps;
ep->type = ep_type;
-
- __HAL_LOCK(hpcd);
- /* initialize Endpoint */
- switch (ep->type)
+ if (ep->is_in != 0U)
{
- case PCD_EP_TYPE_CTRL:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
- break;
- case PCD_EP_TYPE_BULK:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
- break;
- case PCD_EP_TYPE_INTR:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
- break;
- case PCD_EP_TYPE_ISOC:
- PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
- break;
- default:
- break;
- }
-
- PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
-
- if (ep->doublebuffer == 0U)
- {
- if (ep->is_in)
- {
- /*Set the endpoint Transmit buffer address */
- PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- /* Configure NAK status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK)
- }
- else
- {
- /*Set the endpoint Receive buffer address */
- PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
- /*Set the endpoint Receive buffer counter*/
- PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- /* Configure VALID status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
- }
+ /* Assign a Tx FIFO */
+ ep->tx_fifo_num = ep->num;
}
- /*Double Buffer*/
- else
+ /* Set initial data PID. */
+ if (ep_type == EP_TYPE_BULK)
{
- /*Set the endpoint as double buffered*/
- PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
- /*Set buffer address for double buffered mode*/
- PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
-
- if (ep->is_in==0U)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
-
- /* Reset value of the data toggle bits for the endpoint out*/
- PCD_TX_DTOG(hpcd->Instance, ep->num);
-
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- PCD_RX_DTOG(hpcd->Instance, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- }
- }
-
- __HAL_UNLOCK(hpcd);
+ ep->data_pid_start = 0U;
+ }
+
+ __HAL_LOCK(hpcd);
+ (void)USB_ActivateEndpoint(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+
return ret;
}
-
/**
- * @brief Deactivate an endpoint
+ * @brief Deactivate an endpoint.
* @param hpcd PCD handle
* @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
+{
PCD_EPTypeDef *ep;
-
+
if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
}
- ep->num = ep_addr & 0x7FU;
-
- ep->is_in = (0x80U & ep_addr) != 0U;
-
- __HAL_LOCK(hpcd);
+ ep->num = ep_addr & EP_ADDR_MSK;
- if (ep->doublebuffer == 0U)
- {
- if (ep->is_in)
- {
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- }
- else
- {
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- }
- }
- /*Double Buffer*/
- else
- {
- if (ep->is_in==0U)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
-
- /* Reset value of the data toggle bits for the endpoint out*/
- PCD_TX_DTOG(hpcd->Instance, ep->num);
-
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- PCD_RX_DTOG(hpcd->Instance, ep->num);
- /* Configure DISABLE status for the Endpoint*/
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
- }
- }
-
- __HAL_UNLOCK(hpcd);
+ __HAL_LOCK(hpcd);
+ (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Receive an amount of data
+ * @brief Receive an amount of data.
* @param hpcd PCD handle
* @param ep_addr endpoint address
- * @param pBuf pointer to the reception buffer
+ * @param pBuf pointer to the reception buffer
* @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
-
- PCD_EPTypeDef *ep;
-
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
-
+ PCD_EPTypeDef *ep;
+
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+
/*setup and start the Xfer */
- ep->xfer_buff = pBuf;
+ ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
- ep->num = ep_addr & 0x7FU;
-
- /* Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
- len=ep->maxpacket;
- ep->xfer_len-=len;
+ (void)USB_EP0StartXfer(hpcd->Instance, ep);
}
else
{
- len=ep->xfer_len;
- ep->xfer_len =0U;
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
}
-
- /* configure and validate Rx endpoint */
- if (ep->doublebuffer == 0)
- {
- /*Set RX buffer count*/
- PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
- }
- else
- {
- /*Set the Double buffer counter*/
- PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len)
- }
-
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
-
+
return HAL_OK;
}
@@ -878,72 +1459,40 @@
* @param ep_addr endpoint address
* @retval Data Size
*/
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
+ return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
/**
- * @brief Send an amount of data
+ * @brief Send an amount of data
* @param hpcd PCD handle
* @param ep_addr endpoint address
- * @param pBuf pointer to the transmission buffer
+ * @param pBuf pointer to the transmission buffer
* @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
PCD_EPTypeDef *ep;
- uint16_t pmabuffer = 0U;
-
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
-
+
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+
/*setup and start the Xfer */
- ep->xfer_buff = pBuf;
+ ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
- ep->num = ep_addr & 0x7FU;
-
- /*Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
- len=ep->maxpacket;
- ep->xfer_len-=len;
- }
- else
- {
- len=ep->xfer_len;
- ep->xfer_len =0U;
- }
-
- /* configure and validate Tx endpoint */
- if (ep->doublebuffer == 0U)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
- PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
+ (void)USB_EP0StartXfer(hpcd->Instance, ep);
}
else
{
- /*Write the data to the USB endpoint*/
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
- {
- /*Set the Double buffer counter for pmabuffer1*/
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
- pmabuffer = ep->pmaaddr1;
- }
- else
- {
- /*Set the Double buffer counter for pmabuffer0*/
- PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len)
- pmabuffer = ep->pmaaddr0;
- }
-
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
}
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
-
return HAL_OK;
}
@@ -956,40 +1505,35 @@
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
-
- __HAL_LOCK(hpcd);
-
+
+ if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
+
if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
+ ep->is_in = 0U;
}
-
- ep->is_stall = 1;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-
- if (ep->num == 0U)
+
+ ep->is_stall = 1U;
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+
+ (void)USB_EPSetStall(hpcd->Instance, ep);
+ if ((ep_addr & EP_ADDR_MSK) == 0U)
{
- /* This macro sets STALL status for RX & TX*/
- PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL)
+ (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
}
- else
- {
- if (ep->is_in)
- {
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
- }
- else
- {
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
- }
- }
- __HAL_UNLOCK(hpcd);
-
+ __HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -1002,34 +1546,30 @@
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
PCD_EPTypeDef *ep;
-
+
+ if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
+
if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 1U;
}
else
{
- ep = &hpcd->OUT_ep[ep_addr];
+ ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+ ep->is_in = 0U;
}
-
+
ep->is_stall = 0U;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-
- __HAL_LOCK(hpcd);
-
- if (ep->is_in)
- {
- PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
- PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
- }
- else
- {
- PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
- }
- __HAL_UNLOCK(hpcd);
-
+ ep->num = ep_addr & EP_ADDR_MSK;
+
+ __HAL_LOCK(hpcd);
+ (void)USB_EPClearStall(hpcd->Instance, ep);
+ __HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -1040,64 +1580,47 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(ep_addr);
+
return HAL_OK;
}
/**
- * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling
-* @param hpcd PCD handle
-* @retval HAL status
-*/
+ * @brief Activate remote wakeup signalling
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- if (hpcd->Init.lpm_enable ==1)
- {
- /* Apply L1 Resume */
- hpcd->Instance->CNTR |= USB_CNTR_L1RESUME;
- }
- else
- {
- /* Apply L2 Resume */
- hpcd->Instance->CNTR |= USB_CNTR_RESUME;
- }
-
- return (HAL_OK);
+ return (USB_ActivateRemoteWakeup(hpcd->Instance));
}
/**
-* @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling
-* @param hpcd PCD handle
-* @retval HAL status
-*/
+ * @brief De-activate remote wakeup signalling.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- if (hpcd->Init.lpm_enable ==1)
- {
- /* Release L1 Resume */
- hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_L1RESUME));
- }
- else
- {
- /* Release L2 Resume */
- hpcd->Instance->CNTR &= ((uint16_t)(~ USB_CNTR_RESUME)) ;
- }
-
- return (HAL_OK);
+ return (USB_DeActivateRemoteWakeup(hpcd->Instance));
}
+
/**
* @}
*/
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1105,7 +1628,7 @@
*/
/**
- * @brief Return the PCD state
+ * @brief Return the PCD handle state.
* @param hpcd PCD handle
* @retval HAL state
*/
@@ -1113,72 +1636,20 @@
{
return hpcd->State;
}
-/**
- * @}
- */
-
+
/**
* @}
*/
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
/** @addtogroup PCD_Private_Functions
* @{
*/
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx USB peripheral instance register address.
- * @param pbUsrBuf pointer to user memory area.
- * @param wPMABufAddr address into PMA.
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
- uint32_t i;
- uint16_t temp1, temp2;
- uint16_t *pdwVal;
- pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
-
- for (i = n; i != 0; i--)
- {
- temp1 = (uint16_t) * pbUsrBuf;
- pbUsrBuf++;
- temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
- *pdwVal++ = temp2;
- pbUsrBuf++;
- }
-}
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param USBx USB peripheral instance register address.
- * @param pbUsrBuf = pointer to user memory area.
- * @param wPMABufAddr address into PMA.
- * @param wNBytes no. of bytes to be copied.
- * @retval None
- */
-void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = (uint32_t)wNBytes >> 1U;
- uint32_t i;
- uint16_t *pdwVal;
- uint32_t temp;
- pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr + (uint32_t)USBx + 0x400U));
-
- for (i = n; i != 0U; i--)
- {
- temp = *pdwVal++;
- *pbUsrBuf++ = ((temp >> 0) & 0xFF);
- *pbUsrBuf++ = ((temp >> 8) & 0xFF);
- }
-
- if (wNBytes % 2)
- {
- temp = *pdwVal++;
- *pbUsrBuf++ = ((temp >> 0) & 0xFF);
- }
-}
/**
* @brief This function handles PCD Endpoint interrupt request.
@@ -1188,217 +1659,211 @@
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
- uint16_t count=0U;
- uint8_t EPindex;
- __IO uint16_t wIstr;
- __IO uint16_t wEPVal = 0U;
-
+ uint16_t count;
+ uint16_t wIstr;
+ uint16_t wEPVal;
+ uint8_t epindex;
+
/* stay in loop while pending interrupts */
- while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0U)
+ while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
{
+ wIstr = hpcd->Instance->ISTR;
/* extract highest priority endpoint number */
- EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
- if (EPindex == 0U)
+ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
+
+ if (epindex == 0U)
{
/* Decode and service control endpoint interrupt */
-
- /* DIR bit = origin of the interrupt */
+
+ /* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
{
/* DIR = 0 */
-
+
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
ep = &hpcd->IN_ep[0];
-
+
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
ep->xfer_buff += ep->xfer_count;
-
+
/* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, 0U);
+#else
HAL_PCD_DataInStageCallback(hpcd, 0U);
-
-
- if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U))
{
- hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
+ hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF);
hpcd->USB_Address = 0U;
}
-
}
else
{
/* DIR = 1 */
-
+
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
ep = &hpcd->OUT_ep[0];
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-
+
if ((wEPVal & USB_EP_SETUP) != 0U)
{
/* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- PCD_ReadPMA(hpcd->Instance, (uint8_t*)(void*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);
- /* SETUP bit kept frozen while CTR_RX = 1*/
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-
+
+ USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
+ ep->pmaadress, (uint16_t)ep->xfer_count);
+
+ /* SETUP bit kept frozen while CTR_RX = 1*/
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
/* Process SETUP Packet*/
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->SetupStageCallback(hpcd);
+#else
HAL_PCD_SetupStageCallback(hpcd);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
-
+
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
/* Get Control Data OUT Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-
- if (ep->xfer_count != 0U)
+
+ if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
{
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- ep->xfer_buff+=ep->xfer_count;
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
+ ep->pmaadress, (uint16_t)ep->xfer_count);
+
+ ep->xfer_buff += ep->xfer_count;
+
+ /* Process Control Data OUT Packet*/
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, 0U);
+#else
+ HAL_PCD_DataOutStageCallback(hpcd, 0U);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
-
- /* Process Control Data OUT Packet*/
- HAL_PCD_DataOutStageCallback(hpcd, 0U);
-
- PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
- PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
+
+ PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
}
}
}
else
{
-
/* Decode and service non control endpoints interrupt */
-
+
/* process related endpoint register */
- wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
+ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
if ((wEPVal & USB_EP_CTR_RX) != 0U)
- {
+ {
/* clear int flag */
- PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
- ep = &hpcd->OUT_ep[EPindex];
-
+ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
+ ep = &hpcd->OUT_ep[epindex];
+
/* OUT double Buffering*/
if (ep->doublebuffer == 0U)
{
- count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+ count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
}
else
{
-
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
/*read from endpoint BUF0Addr buffer*/
- count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
}
else
{
/*read from endpoint BUF1Addr buffer*/
- count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
- PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)
+ /* free EP OUT Buffer */
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
}
/*multi-packet on the NON control OUT endpoint*/
- ep->xfer_count+=count;
- ep->xfer_buff+=count;
-
+ ep->xfer_count += count;
+ ep->xfer_buff += count;
+
if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
{
/* RX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataOutStageCallback(hpcd, ep->num);
+#else
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
- HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
}
-
+
} /* if((wEPVal & EP_CTR_RX) */
-
+
if ((wEPVal & USB_EP_CTR_TX) != 0U)
{
- ep = &hpcd->IN_ep[EPindex];
-
+ ep = &hpcd->IN_ep[epindex];
+
/* clear int flag */
- PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
-
- /* IN double Buffering*/
- if (ep->doublebuffer == 0U)
- {
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- }
- }
- else
- {
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
- {
- /*read from endpoint BUF0Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
- {
- PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
- }
- }
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
- }
+ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
+
/*multi-packet on the NON control IN endpoint*/
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff+=ep->xfer_count;
-
+ ep->xfer_buff += ep->xfer_count;
+
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
{
/* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
- HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
}
- }
+ }
}
}
return HAL_OK;
}
-/**
- * @}
- */
+
/**
* @}
*/
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
-
+#endif /* defined (USB) */
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_pcd_ex.c b/Src/stm32f0xx_hal_pcd_ex.c
index b00d2f8..31978b0 100644
--- a/Src/stm32f0xx_hal_pcd_ex.c
+++ b/Src/stm32f0xx_hal_pcd_ex.c
@@ -2,37 +2,21 @@
******************************************************************************
* @file stm32f0xx_hal_pcd_ex.c
* @author MCD Application Team
- * @brief Extended PCD HAL module driver.
- * This file provides firmware functions to manage the following
+ * @brief PCD Extended HAL module driver.
+ * This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
- * + Configuration of the PMA for EP
- *
+ * + Extended features functions
+ *
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -40,10 +24,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
-#ifdef HAL_PCD_MODULE_ENABLED
-
-#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)|| defined(STM32F070x6)
-
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -53,91 +33,289 @@
* @{
*/
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+#ifdef HAL_PCD_MODULE_ENABLED
+
+#if defined (USB)
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief PCDEx control functions
- *
+ * @brief PCDEx control functions
+ *
@verbatim
===============================================================================
- ##### Extended Peripheral Control functions #####
+ ##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Update PMA configuration
+ (+) Update FIFO configuration
@endverbatim
* @{
*/
/**
- * @brief Configure PMA for EP
- * @param hpcd PCD handle
+ * @brief Configure PMA for EP
+ * @param hpcd Device instance
* @param ep_addr endpoint address
* @param ep_kind endpoint Kind
- * @arg USB_SNG_BUF: Single Buffer used
- * @arg USB_DBL_BUF: Double Buffer used
- * @param pmaadress EP address in The PMA: In case of single buffer endpoint
+ * USB_SNG_BUF: Single Buffer used
+ * USB_DBL_BUF: Double Buffer used
+ * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
* this parameter is 16-bit value providing the address
* in PMA allocated to endpoint.
* In case of double buffer endpoint this parameter
* is a 32-bit value providing the endpoint buffer 0 address
* in the LSB part of 32-bit value and endpoint buffer 1 address
* in the MSB part of 32-bit value.
- * @retval : status
+ * @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress)
-
+HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
+ uint16_t ep_addr,
+ uint16_t ep_kind,
+ uint32_t pmaadress)
{
PCD_EPTypeDef *ep;
-
+
/* initialize ep structure*/
if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
}
-
+
/* Here we check if the endpoint is single or double Buffer*/
if (ep_kind == PCD_SNG_BUF)
{
- /*Single Buffer*/
+ /* Single Buffer */
ep->doublebuffer = 0U;
- /*Configure the PMA*/
+ /* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
}
- else /*USB_DBL_BUF*/
+ else /* USB_DBL_BUF */
{
- /*Double Buffer Endpoint*/
+ /* Double Buffer Endpoint */
ep->doublebuffer = 1U;
- /*Configure the PMA*/
- ep->pmaaddr0 = pmaadress & 0xFFFFU;
- ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
+ /* Configure the PMA */
+ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
+ ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
}
-
+
return HAL_OK;
}
-/**
- * @}
- */
/**
- * @}
+ * @brief Activate BatteryCharging feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
*/
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+ USB_TypeDef *USBx = hpcd->Instance;
+ hpcd->battery_charging_active = 1U;
+
+ /* Enable BCD feature */
+ USBx->BCDR |= USB_BCDR_BCDEN;
+
+ /* Enable DCD : Data Contact Detect */
+ USBx->BCDR &= ~(USB_BCDR_PDEN);
+ USBx->BCDR &= ~(USB_BCDR_SDEN);
+ USBx->BCDR |= USB_BCDR_DCDEN;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate BatteryCharging feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+ USB_TypeDef *USBx = hpcd->Instance;
+ hpcd->battery_charging_active = 0U;
+
+ /* Disable BCD feature */
+ USBx->BCDR &= ~(USB_BCDR_BCDEN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle BatteryCharging Process.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+ USB_TypeDef *USBx = hpcd->Instance;
+ uint32_t tickstart = HAL_GetTick();
+
+ /* Wait Detect flag or a timeout is happen*/
+ while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > 1000U)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
+ }
+ }
+
+ HAL_Delay(200U);
+
+ /* Data Pin Contact ? Check Detect flag */
+ if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
+ {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ /* Primary detection: checks if connected to Standard Downstream Port
+ (without charging capability) */
+ USBx->BCDR &= ~(USB_BCDR_DCDEN);
+ HAL_Delay(50U);
+ USBx->BCDR |= (USB_BCDR_PDEN);
+ HAL_Delay(50U);
+
+ /* If Charger detect ? */
+ if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
+ {
+ /* Start secondary detection to check connection to Charging Downstream
+ Port or Dedicated Charging Port */
+ USBx->BCDR &= ~(USB_BCDR_PDEN);
+ HAL_Delay(50U);
+ USBx->BCDR |= (USB_BCDR_SDEN);
+ HAL_Delay(50U);
+
+ /* If CDP ? */
+ if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
+ {
+ /* Dedicated Downstream Port DCP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Charging Downstream Port CDP */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ }
+ else /* NO */
+ {
+ /* Standard Downstream Port */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+
+ /* Battery Charging capability discovery finished Start Enumeration */
+ (void)HAL_PCDEx_DeActivateBCD(hpcd);
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+}
+
+
+/**
+ * @brief Activate LPM feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+
+ USB_TypeDef *USBx = hpcd->Instance;
+ hpcd->lpm_active = 1U;
+ hpcd->LPM_State = LPM_L0;
+
+ USBx->LPMCSR |= USB_LPMCSR_LMPEN;
+ USBx->LPMCSR |= USB_LPMCSR_LPMACK;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivate LPM feature.
+ * @param hpcd PCD handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+ USB_TypeDef *USBx = hpcd->Instance;
+
+ hpcd->lpm_active = 0U;
+
+ USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
+ USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
+
+ return HAL_OK;
+}
+
+
+
+/**
+ * @brief Send LPM message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_LPM_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Send BatteryCharging message to user layer callback.
+ * @param hpcd PCD handle
+ * @param msg LPM message
+ * @retval HAL status
+ */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hpcd);
+ UNUSED(msg);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_PCDEx_BCD_Callback could be implemented in the user file
+ */
+}
/**
* @}
@@ -146,9 +324,15 @@
/**
* @}
*/
-
-#endif /* STM32F042x6 || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
-
+#endif /* defined (USB) */
#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_pwr.c b/Src/stm32f0xx_hal_pwr.c
index 4eef3d0..435b265 100644
--- a/Src/stm32f0xx_hal_pwr.c
+++ b/Src/stm32f0xx_hal_pwr.c
@@ -12,29 +12,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Src/stm32f0xx_hal_pwr_ex.c b/Src/stm32f0xx_hal_pwr_ex.c
index d83817d..c9b16dc 100644
--- a/Src/stm32f0xx_hal_pwr_ex.c
+++ b/Src/stm32f0xx_hal_pwr_ex.c
@@ -11,31 +11,15 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_hal_rcc.c b/Src/stm32f0xx_hal_rcc.c
index 619a481..601add0 100644
--- a/Src/stm32f0xx_hal_rcc.c
+++ b/Src/stm32f0xx_hal_rcc.c
@@ -48,32 +48,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
-*/
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -217,39 +201,86 @@
* - AHB, APB1 prescaler set to 1.
* - CSS and MCO1 OFF
* - All interrupts disabled
+ * - All interrupt and reset flags cleared
* @note This function does not modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
- * @retval None
+ * @retval HAL status
*/
-void HAL_RCC_DeInit(void)
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
{
+ uint32_t tickstart;
+
+ /* Get Start Tick*/
+ tickstart = HAL_GetTick();
+
/* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);
+ /* Wait till HSI as SYSCLK status is enabled */
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Update the SystemCoreClock global variable for HSI as system clock source */
+ SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Reset HSEON, CSSON, PLLON bits */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
/* Reset HSEBYP bit */
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+ /* Get start tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till PLLRDY is cleared */
+ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
-
+
/* Reset CFGR2 register */
CLEAR_REG(RCC->CFGR2);
-
+
/* Reset CFGR3 register */
CLEAR_REG(RCC->CFGR3);
-
+
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HSI_VALUE;
+ /* Clear all reset flags */
+ __HAL_RCC_CLEAR_RESET_FLAGS();
+
+ return HAL_OK;
}
/**
@@ -268,10 +299,17 @@
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+ uint32_t pll_config;
+ uint32_t pll_config2;
+
+ /* Check Null pointer */
+ if(RCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
- assert_param(RCC_OscInitStruct != NULL);
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
@@ -692,10 +730,26 @@
}
else
{
- return HAL_ERROR;
+ /* Check if there is a request to disable the PLL used as System clock source */
+ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Do not return HAL_ERROR if request repeats the current configuration */
+ pll_config = RCC->CFGR;
+ pll_config2 = RCC->CFGR2;
+ if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV) ||
+ (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
+ {
+ return HAL_ERROR;
+ }
+ }
}
}
-
+
return HAL_OK;
}
@@ -724,10 +778,15 @@
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
- assert_param(RCC_ClkInitStruct != NULL);
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency));
@@ -736,14 +795,14 @@
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
@@ -752,13 +811,21 @@
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
+ /* Set the highest APB divider in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
+ }
+
+ /* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
+ {
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
@@ -804,58 +871,24 @@
/* Get Start Tick */
tickstart = HAL_GetTick();
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-#if defined(RCC_CFGR_SWS_HSI48)
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
- {
- if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
-#endif /* RCC_CFGR_SWS_HSI48 */
- else
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
+ }
+
/* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
@@ -1088,23 +1121,23 @@
if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
- pllclk = (HSE_VALUE / prediv) * pllmul;
+ pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV)
else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
{
/* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
- pllclk = (HSI48_VALUE / prediv) * pllmul;
+ pllclk = (uint32_t)((uint64_t) HSI48_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */
else
{
#if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
- pllclk = (HSI_VALUE / prediv) * pllmul;
+ pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
#else
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
- pllclk = (uint32_t)((HSI_VALUE >> 1U) * pllmul);
+ pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
#endif
}
sysclockfreq = pllclk;
@@ -1280,7 +1313,7 @@
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
/* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+ *pFLatency = __HAL_FLASH_GET_LATENCY();
}
/**
diff --git a/Src/stm32f0xx_hal_rcc_ex.c b/Src/stm32f0xx_hal_rcc_ex.c
index a5699bf..873725d 100644
--- a/Src/stm32f0xx_hal_rcc_ex.c
+++ b/Src/stm32f0xx_hal_rcc_ex.c
@@ -11,32 +11,16 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
diff --git a/Src/stm32f0xx_hal_rtc.c b/Src/stm32f0xx_hal_rtc.c
index c884b7c..f2d4f6d 100644
--- a/Src/stm32f0xx_hal_rtc.c
+++ b/Src/stm32f0xx_hal_rtc.c
@@ -3,83 +3,121 @@
* @file stm32f0xx_hal_rtc.c
* @author MCD Application Team
* @brief RTC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
* + Initialization and de-initialization functions
* + RTC Time and Date functions
* + RTC Alarm functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
==============================================================================
##### How to use RTC Driver #####
===================================================================
- [..]
+ [..]
(+) Enable the RTC domain access (see description in the section above).
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
-
+
*** Time and Date configuration ***
===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
and HAL_RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
+
*** Alarm configuration ***
===========================
[..]
(+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the
+ You can also configure the RTC Alarm with interrupt mode using the
HAL_RTC_SetAlarm_IT() function.
(+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
##### RTC and low power modes #####
===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
function.
- [..] The RTC alternate functions are the RTC alarm (Alarm A),
+ [..] The RTC alternate functions are the RTC alarm (Alarm A),
RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
+ These RTC alternate functions can wake up the system from the Stop and
Standby low power modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wake-up mode), by using the RTC alarm
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wake-up mode), by using the RTC alarm
or the RTC wake-up events.
- [..] The RTC provides a programmable time base for waking up from the
+ [..] The RTC provides a programmable time base for waking up from the
Stop or Standby mode at regular intervals.
Wake-up from STOP and STANDBY modes is possible only when the RTC clock source
is LSE or LSI.
-
+
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+
+ Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) AlarmAEventCallback : RTC Alarm A Event callback.
+ (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
+ (+) Tamper1EventCallback : RTC Tamper 1 Event callback.
+ (+) Tamper2EventCallback : RTC Tamper 2 Event callback.
+ (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
+ (+) MspInitCallback : RTC MspInit callback.
+ (+) MspDeInitCallback : RTC MspDeInit callback.
+
+ By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+ all callbacks are set to the corresponding weak functions :
+ examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
+ Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
+ in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+ (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
+ or @ref HAL_RTC_Init() function.
+
+ When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
@endverbatim
+
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -106,43 +144,43 @@
/** @addtogroup RTC_Exported_Functions
* @{
*/
-
+
/** @addtogroup RTC_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This section provides functions allowing to initialize and configure the
- RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
- RTC registers Write protection, enter and exit the RTC initialization mode,
+ [..] This section provides functions allowing to initialize and configure the
+ RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
+ RTC registers Write protection, enter and exit the RTC initialization mode,
RTC registers synchronization check and reference clock detection enable.
- (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
+ (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
It is split into 2 programmable prescalers to minimize power consumption.
(++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler.
- (++) When both prescalers are used, it is recommended to configure the
+ (++) When both prescalers are used, it is recommended to configure the
asynchronous prescaler to a high value to minimize power consumption.
(#) All RTC registers are Write protected. Writing to the RTC registers
is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To configure the RTC Calendar, user application should enter
- initialization mode. In this mode, the calendar counter is stopped
- and its value can be updated. When the initialization sequence is
+ (#) To configure the RTC Calendar, user application should enter
+ initialization mode. In this mode, the calendar counter is stopped
+ and its value can be updated. When the initialization sequence is
complete, the calendar restarts counting after 4 RTCCLK cycles.
- (#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wake-up from low power modes
- the software must first clear the RSF flag. The software must then
- wait until it is set again before reading the calendar, which means
- that the calendar registers have been correctly copied into the
- RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ (#) To read the calendar through the shadow registers after Calendar
+ initialization, calendar update or after wake-up from low power modes
+ the software must first clear the RSF flag. The software must then
+ wait until it is set again before reading the calendar, which means
+ that the calendar registers have been correctly copied into the
+ RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
implements the above software sequence (RSF clear and RSF check).
-
+
@endverbatim
* @{
*/
/**
- * @brief Initialize the RTC according to the specified parameters
+ * @brief Initialize the RTC according to the specified parameters
* in the RTC_InitTypeDef structure and initialize the associated handle.
* @param hrtc RTC handle
* @retval HAL status
@@ -150,11 +188,11 @@
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
/* Check the RTC peripheral state */
- if(hrtc == NULL)
+ if (hrtc == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
@@ -163,8 +201,38 @@
assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-
- if(hrtc->State == HAL_RTC_STATE_RESET)
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if (hrtc->State == HAL_RTC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hrtc->Lock = HAL_UNLOCKED;
+
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+#if defined(RTC_WAKEUP_SUPPORT)
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+#endif /* RTC_WAKEUP_SUPPORT */
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+#if defined(RTC_TAMPER3_SUPPORT)
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
+#endif /* RTC_TAMPER3_SUPPORT */
+
+ if (hrtc->MspInitCallback == NULL)
+ {
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ }
+ /* Init the low level hardware */
+ hrtc->MspInitCallback(hrtc);
+
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+ }
+#else
+ if (hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
@@ -172,42 +240,43 @@
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
-
+
return HAL_ERROR;
- }
+ }
else
- {
+ {
/* Clear RTC_CR FMT, OSEL and POL Bits */
hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
/* Set RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
+
/* Configure the RTC PRER */
hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-
+
/* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -219,14 +288,14 @@
}
hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
- hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
-
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_READY;
-
+
return HAL_OK;
}
}
@@ -251,132 +320,343 @@
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
/* Set RTC state */
- hrtc->State = HAL_RTC_STATE_BUSY;
-
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
/* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
-
+
return HAL_ERROR;
- }
+ }
else
{
/* Reset TR, DR and CR registers */
hrtc->Instance->TR = 0x00000000U;
hrtc->Instance->DR = 0x00002101U;
-
+
#if defined (STM32F030xC) || defined (STM32F070xB) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+ defined (STM32F091xC) || defined (STM32F098xx)
/* Reset All CR bits except CR[2:0] */
hrtc->Instance->CR &= 0x00000007U;
-
+
tickstart = HAL_GetTick();
-
+
/* Wait till WUTWF flag is set and if Time out is reached exit */
- while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
+ while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
{
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
- {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
+
return HAL_TIMEOUT;
- }
+ }
}
#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) ||*/
-
+
/* Reset all RTC CR register bits */
hrtc->Instance->CR &= 0x00000000U;
#if defined (STM32F030xC) || defined (STM32F070xB) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx)
+ defined (STM32F091xC) || defined (STM32F098xx)
hrtc->Instance->WUTR = 0x0000FFFFU;
#endif /* defined (STM32F030xC) || defined (STM32F070xB) ||\
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
- defined (STM32F091xC) || defined (STM32F098xx) ||*/
+ defined (STM32F091xC) || defined (STM32F098xx) ||*/
hrtc->Instance->PRER = 0x007F00FFU;
- hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->ALRMAR = 0x00000000U;
hrtc->Instance->SHIFTR = 0x00000000U;
hrtc->Instance->CALR = 0x00000000U;
hrtc->Instance->ALRMASSR = 0x00000000U;
-
+
/* Reset ISR register and exit initialization mode */
hrtc->Instance->ISR = 0x00000000U;
-
+
/* Reset Tamper and alternate functions configuration register */
hrtc->Instance->TAFCR = 0x00000000;
-
+
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
hrtc->State = HAL_RTC_STATE_ERROR;
-
+
return HAL_ERROR;
}
- }
+ }
}
-
+
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hrtc->MspDeInitCallback(hrtc);
+
+#else
/* De-Initialize RTC MSP */
HAL_RTC_MspDeInit(hrtc);
-
- hrtc->State = HAL_RTC_STATE_RESET;
-
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+
+ hrtc->State = HAL_RTC_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(hrtc);
return HAL_OK;
}
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User RTC Callback
+ * To be used instead of the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if (HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = pCallback;
+ break;
+
+#if defined(RTC_WAKEUP_SUPPORT)
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = pCallback;
+ break;
+#endif /* RTC_WAKEUP_SUPPORT */
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = pCallback;
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = pCallback;
+ break;
+
+#if defined(RTC_TAMPER3_SUPPORT)
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ hrtc->Tamper3EventCallback = pCallback;
+ break;
+#endif /* RTC_TAMPER3_SUPPORT */
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an RTC Callback
+ * RTC callabck is redirected to the weak predefined callback
+ * @param hrtc RTC handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
+ * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
+ * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
+ * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
+ * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
+ * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hrtc);
+
+ if (HAL_RTC_STATE_READY == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ break;
+
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ break;
+#if defined(RTC_WAKEUP_SUPPORT)
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+ break;
+#endif /* RTC_WAKEUP_SUPPORT */
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ break;
+
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+ break;
+#if defined( RTC_TAMPER3_SUPPORT)
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
+ break;
+#endif /* RTC_TAMPER3_SUPPORT */
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
+
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
+}
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/**
* @brief Initialize the RTC MSP.
- * @param hrtc RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
+__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_MspInit could be implemented in the user file
- */
+ */
}
/**
* @brief DeInitialize the RTC MSP.
- * @param hrtc RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
+__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_RTC_MspDeInit could be implemented in the user file
- */
+ */
}
/**
@@ -386,11 +666,11 @@
/** @addtogroup RTC_Exported_Functions_Group2
* @brief RTC Time and Date functions
*
-@verbatim
+@verbatim
===============================================================================
##### RTC Time and Date functions #####
- ===============================================================================
-
+ ===============================================================================
+
[..] This section provides functions allowing to configure Time and Date features
@endverbatim
@@ -403,31 +683,31 @@
* @param sTime Pointer to Time structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg = 0U;
-
- /* Check the parameters */
+
+ /* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-
- /* Process Locked */
+
+ /* Process Locked */
__HAL_LOCK(hrtc);
-
+
hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
+
+ if (Format == RTC_FORMAT_BIN)
{
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
assert_param(IS_RTC_HOUR12(sTime->Hours));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
- }
+ }
else
{
sTime->TimeFormat = 0x00U;
@@ -435,20 +715,19 @@
}
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
-
+
tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
- (((uint32_t)sTime->TimeFormat) << 16U));
+ (((uint32_t)sTime->TimeFormat) << 16U));
}
else
{
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sTime->Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
- }
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
+ }
else
{
sTime->TimeFormat = 0x00U;
@@ -459,84 +738,84 @@
tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
((uint32_t)(sTime->Minutes) << 8U) | \
((uint32_t)sTime->Seconds) | \
- ((uint32_t)(sTime->TimeFormat) << 16U));
+ ((uint32_t)(sTime->TimeFormat) << 16U));
}
-
+
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
/* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_ERROR;
- }
+ }
else
{
/* Set the RTC_TR register */
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
+
/* Clear the bits to be configured */
hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
/* Configure the RTC_CR register */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-
+
/* Exit Initialization mode */
hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_ERROR;
}
}
-
+
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
}
}
/**
* @brief Get RTC current time.
* @param hrtc RTC handle
- * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
+ * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
* with input format (BIN or BCD), also SubSeconds field returning the
* RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
* factor to be used for second fraction ratio computation.
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
* value in second fraction ratio with time unit following generic formula:
* Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
* This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read
* to ensure consistency between the time and date values.
@@ -548,31 +827,31 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
-
+
/* Get subseconds structure field from the corresponding register*/
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
/* Get SecondFraction structure field from the corresponding register field*/
sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
-
+
/* Get the TR register */
- tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
-
+ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
+
/* Fill the structure fields with the read parameters */
sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
- sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8U);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
-
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
+
/* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
+ if (Format == RTC_FORMAT_BIN)
{
/* Convert the time structure parameters to Binary format */
sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
- sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
+ sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
}
-
+
return HAL_OK;
}
@@ -582,105 +861,103 @@
* @param sDate Pointer to date structure
* @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg = 0U;
-
- /* Check the parameters */
+
+ /* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
}
-
+
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-
- if(Format == RTC_FORMAT_BIN)
- {
+
+ if (Format == RTC_FORMAT_BIN)
+ {
assert_param(IS_RTC_YEAR(sDate->Year));
assert_param(IS_RTC_MONTH(sDate->Month));
- assert_param(IS_RTC_DATE(sDate->Date));
-
- datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
- ((uint32_t)sDate->WeekDay << 13U));
+ assert_param(IS_RTC_DATE(sDate->Date));
+
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+ ((uint32_t)sDate->WeekDay << 13U));
}
else
- {
+ {
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- datetmpreg = RTC_Bcd2ToByte(sDate->Month);
- assert_param(IS_RTC_MONTH(datetmpreg));
- datetmpreg = RTC_Bcd2ToByte(sDate->Date);
- assert_param(IS_RTC_DATE(datetmpreg));
-
+ assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
+ assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
+
datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
(((uint32_t)sDate->Month) << 8U) | \
((uint32_t)sDate->Date) | \
- (((uint32_t)sDate->WeekDay) << 13U));
+ (((uint32_t)sDate->WeekDay) << 13U));
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
/* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
/* Set RTC state*/
hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_ERROR;
- }
+ }
else
{
/* Set the RTC_DR register */
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-
+
/* Exit Initialization mode */
hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
{
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_ERROR;
}
}
-
+
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+
+ return HAL_OK;
}
}
@@ -690,36 +967,36 @@
* @param sDate Pointer to Date structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN : Binary data format
+ * @arg RTC_FORMAT_BIN : Binary data format
* @arg RTC_FORMAT_BCD : BCD data format
- * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
* in the higher-order calendar shadow registers to ensure consistency between the time and date values.
* Reading RTC current time locks the values in calendar shadow registers until Current date is read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
- uint32_t datetmpreg = 0;
+ uint32_t datetmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
-
+
/* Get the DR register */
- datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
+ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
- sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
/* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
- {
+ if (Format == RTC_FORMAT_BIN)
+ {
/* Convert the date structure parameters to Binary format */
sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
- sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
}
return HAL_OK;
}
@@ -731,11 +1008,11 @@
/** @addtogroup RTC_Exported_Functions_Group3
* @brief RTC Alarm functions
*
-@verbatim
+@verbatim
===============================================================================
##### RTC Alarm functions #####
- ===============================================================================
-
+ ===============================================================================
+
[..] This section provides functions allowing to configure Alarm feature
@endverbatim
@@ -747,7 +1024,7 @@
* @param sAlarm Pointer to Alarm structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
@@ -755,7 +1032,7 @@
{
uint32_t tickstart = 0U;
uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
+
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
@@ -763,19 +1040,19 @@
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
+
+ /* Process Locked */
__HAL_LOCK(hrtc);
-
+
hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
+
+ if (Format == RTC_FORMAT_BIN)
{
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
+ }
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
@@ -783,8 +1060,8 @@
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
}
@@ -792,97 +1069,94 @@
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
-
+
tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
+ ((uint32_t)sAlarm->AlarmMask));
}
else
{
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
+ }
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
-
+
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
else
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
-
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
+ ((uint32_t)sAlarm->AlarmMask));
}
-
+
/* Configure the Alarm A Sub Second registers */
subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
+
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(hrtc);
- /* In case of interrupt mode is used, the interrupt source must disabled */
+ /* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
+
tickstart = HAL_GetTick();
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_TIMEOUT;
}
}
-
+
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
/* Configure the Alarm A Sub Second register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(hrtc);
-
+
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
/* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_OK;
}
@@ -892,18 +1166,18 @@
* @param sAlarm Pointer to Alarm structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the HAL_RTC_DeactivateAlarm()).
- * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t tickstart = 0U;
uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
+
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(sAlarm->Alarm));
@@ -911,19 +1185,19 @@
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
+
+ /* Process Locked */
__HAL_LOCK(hrtc);
-
+
hrtc->State = HAL_RTC_STATE_BUSY;
-
- if(Format == RTC_FORMAT_BIN)
+
+ if (Format == RTC_FORMAT_BIN)
{
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
+ }
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
@@ -931,8 +1205,8 @@
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
}
@@ -946,34 +1220,31 @@
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
+ ((uint32_t)sAlarm->AlarmMask));
}
else
{
- if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
+ }
else
{
sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
-
+
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
else
{
- tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
}
tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
@@ -981,14 +1252,14 @@
((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
+ ((uint32_t)sAlarm->AlarmMask));
}
/* Configure the Alarm A Sub Second registers */
subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
+
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(hrtc);
@@ -996,45 +1267,45 @@
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
tickstart = HAL_GetTick();
-
+
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_TIMEOUT;
- }
+ }
}
-
+
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
/* Configure the Alarm A Sub Second register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(hrtc);
/* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
+
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
+
/* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
return HAL_OK;
}
@@ -1049,52 +1320,52 @@
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
{
uint32_t tickstart = 0U;
-
+
/* Check the parameters */
assert_param(IS_RTC_ALARM(Alarm));
-
- /* Process Locked */
+
+ /* Process Locked */
__HAL_LOCK(hrtc);
-
+
hrtc->State = HAL_RTC_STATE_BUSY;
-
+
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
__HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
+
+ /* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
+
tickstart = HAL_GetTick();
-
+
/* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_TIMEOUT;
- }
+ }
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
}
-
+
/**
* @brief Get the RTC Alarm value and masks.
* @param hrtc RTC handle
@@ -1104,23 +1375,23 @@
* @arg RTC_ALARM_A: AlarmA
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
{
uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
+
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
assert_param(IS_RTC_ALARM(Alarm));
-
+
sAlarm->Alarm = RTC_ALARM_A;
-
+
tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS);
-
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
+
/* Fill the structure with the read parameters */
sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
@@ -1130,15 +1401,15 @@
sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
- if(Format == RTC_FORMAT_BIN)
+
+ if (Format == RTC_FORMAT_BIN)
{
sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- }
-
+ }
+
return HAL_OK;
}
@@ -1147,27 +1418,31 @@
* @param hrtc RTC handle
* @retval None
*/
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
/* Get the AlarmA interrupt source enable status */
- if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
+ if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
{
/* Get the pending status of the AlarmA Interrupt */
- if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
+ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
{
/* AlarmA callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmAEventCallback(hrtc);
+#else
HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the AlarmA interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
}
}
-
+
/* Clear the EXTI's line Flag for RTC Alarm */
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
+
/* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
+ hrtc->State = HAL_RTC_STATE_READY;
}
/**
@@ -1194,27 +1469,27 @@
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
-
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
+ uint32_t tickstart = HAL_GetTick();
+
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
-
+
/* Clear the Alarm interrupt pending bit */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
+
/* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
}
/**
@@ -1222,12 +1497,12 @@
*/
/** @addtogroup RTC_Exported_Functions_Group4
- * @brief Peripheral Control functions
+ * @brief Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Wait for RTC Time and Date Synchronization
@@ -1239,9 +1514,9 @@
/**
* @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
* synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
* initialization, calendar update or after wakeup from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
@@ -1250,7 +1525,7 @@
* @param hrtc RTC handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
@@ -1260,12 +1535,12 @@
tickstart = HAL_GetTick();
/* Wait the registers to be synchronised */
- while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
+ while ((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
return HAL_TIMEOUT;
- }
+ }
}
return HAL_OK;
@@ -1276,12 +1551,12 @@
*/
/** @addtogroup RTC_Exported_Functions_Group5
- * @brief Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Get RTC state
@@ -1294,7 +1569,7 @@
* @param hrtc RTC handle
* @retval HAL state
*/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
{
/* Return RTC handle state */
return hrtc->State;
@@ -1318,29 +1593,29 @@
* @param hrtc RTC handle
* @retval HAL status
*/
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
-
+
/* Check if the Initialization mode is set */
- if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ if ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-
+
tickstart = HAL_GetTick();
-
+
/* Wait till RTC is in INIT state and if Time out is reached exit */
- while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ while ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
return HAL_TIMEOUT;
- }
+ }
}
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
@@ -1352,14 +1627,14 @@
uint8_t RTC_ByteToBcd2(uint8_t Value)
{
uint32_t bcdhigh = 0U;
-
- while(Value >= 10U)
+
+ while (Value >= 10U)
{
bcdhigh++;
Value -= 10U;
}
-
- return ((uint8_t)(bcdhigh << 4U) | Value);
+
+ return ((uint8_t)(bcdhigh << 4U) | Value);
}
/**
diff --git a/Src/stm32f0xx_hal_rtc_ex.c b/Src/stm32f0xx_hal_rtc_ex.c
index de88f3a..362ad9c 100644
--- a/Src/stm32f0xx_hal_rtc_ex.c
+++ b/Src/stm32f0xx_hal_rtc_ex.c
@@ -3,91 +3,75 @@
* @file stm32f0xx_hal_rtc_ex.c
* @author MCD Application Team
* @brief Extended RTC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extended peripheral:
* + RTC Time Stamp functions
- * + RTC Tamper functions
+ * + RTC Tamper functions
* + RTC Wake-up functions
* + Extended Control functions
- * + Extended RTC features functions
+ * + Extended RTC features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
+ [..]
(+) Enable the RTC domain access.
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
format using the HAL_RTC_Init() function.
*** RTC Wake-up configuration ***
================================
- [..]
+ [..]
(+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
+ function. You can also configure the RTC Wakeup timer with interrupt mode
using the HAL_RTCEx_SetWakeUpTimer_IT() function.
(+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
function.
- (@) Not available on F030x4/x6/x8 and F070x6
-
+ (@) Not available on F030x4/x6/x8 and F070x6
+
*** TimeStamp configuration ***
===============================
[..]
- (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
- HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
+ (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
+ HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
(+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
function.
-
+
*** Tamper configuration ***
============================
[..]
- (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt
+ (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
+ or Level according to the Tamper filter (if equal to 0 Edge else Level)
+ value, sampling frequency, precharge or discharge and Pull-UP using the
+ HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt
mode using HAL_RTCEx_SetTamper_IT() function.
-
+
*** Backup Data Registers configuration ***
===========================================
[..]
(+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
- function.
+ function.
(+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
function.
(@) Not available on F030x6/x8/xC and F070x6/xB (F0xx Value Line devices)
-
-
+
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -120,11 +104,11 @@
/** @addtogroup RTCEx_Exported_Functions_Group1
* @brief RTC TimeStamp and Tamper functions
*
-@verbatim
+@verbatim
===============================================================================
##### RTC TimeStamp and Tamper functions #####
- ===============================================================================
-
+ ===============================================================================
+
[..] This section provides functions allowing to configure TimeStamp feature
@endverbatim
@@ -138,9 +122,9 @@
* @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
@@ -163,7 +147,7 @@
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
- tmpreg|= TimeStampEdge;
+ tmpreg |= TimeStampEdge;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
@@ -189,12 +173,12 @@
* @brief Set TimeStamp with Interrupt.
* @param hrtc RTC handle
* @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
* @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
@@ -209,7 +193,7 @@
assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
- /* Process Locked */
+ /* Process Locked */
__HAL_LOCK(hrtc);
hrtc->State = HAL_RTC_STATE_BUSY;
@@ -228,7 +212,7 @@
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
/* Enable IT timestamp */
- __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
+ __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
/* RTC timestamp Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
@@ -288,14 +272,14 @@
* @param hrtc RTC handle
* @param sTimeStamp Pointer to Time structure
- * @param sTimeStampDate Pointer to Date structure
+ * @param sTimeStampDate Pointer to Date structure
* @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
{
uint32_t tmptime = 0U, tmpdate = 0U;
@@ -320,7 +304,7 @@
sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
/* Check the input parameters format */
- if(Format == RTC_FORMAT_BIN)
+ if (Format == RTC_FORMAT_BIN)
{
/* Convert the TimeStamp structure parameters to Binary format */
sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
@@ -346,7 +330,7 @@
* @param sTamper Pointer to Tamper Structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
{
uint32_t tmpreg = 0U;
@@ -364,22 +348,22 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
}
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
(uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS | \
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
(uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
hrtc->Instance->TAFCR |= tmpreg;
-
- hrtc->State = HAL_RTC_STATE_READY;
+
+ hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
@@ -395,12 +379,12 @@
* @param sTamper Pointer to RTC Tamper.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
- assert_param(IS_RTC_TAMPER(sTamper->Tamper));
+ assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
@@ -414,17 +398,17 @@
hrtc->State = HAL_RTC_STATE_BUSY;
/* Configure the tamper trigger */
- if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
}
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
+ tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
(uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
+ hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS | \
+ (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
(uint32_t)RTC_TAFCR_TAMPPUDIS);
hrtc->Instance->TAFCR |= tmpreg;
@@ -434,7 +418,7 @@
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
+
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
hrtc->State = HAL_RTC_STATE_READY;
@@ -478,29 +462,37 @@
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{
+{
/* Get the TimeStamp interrupt source enable status */
- if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
+ if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
{
/* Get the pending status of the TIMESTAMP Interrupt */
- if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
+ if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
{
- /* TIMESTAMP callback */
+ /* TIMESTAMP callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->TimeStampEventCallback(hrtc);
+#else
HAL_RTCEx_TimeStampEventCallback(hrtc);
-
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/* Clear the TIMESTAMP interrupt pending bit */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
}
}
/* Get the Tamper interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
{
- /* Get the pending status of the Tamper1 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
+ /* Get the pending status of the Tamper1 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
{
/* Tamper1 callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper1EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper1EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper1 interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
@@ -508,13 +500,17 @@
}
/* Get the Tamper interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
{
- /* Get the pending status of the Tamper2 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
+ /* Get the pending status of the Tamper2 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
{
/* Tamper2 callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper2EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper2EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper2 interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
@@ -523,13 +519,17 @@
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/* Get the Tamper interrupts source enable status */
- if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
{
- /* Get the pending status of the Tamper3 Interrupt */
- if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
+ /* Get the pending status of the Tamper3 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
{
/* Tamper3 callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->Tamper3EventCallback(hrtc);
+#else
HAL_RTCEx_Tamper3EventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Clear the Tamper3 interrupt pending bit */
__HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
@@ -545,7 +545,7 @@
}
/**
- * @brief TimeStamp callback.
+ * @brief TimeStamp callback.
* @param hrtc RTC handle
* @retval None
*/
@@ -575,7 +575,7 @@
}
/**
- * @brief Tamper 2 callback.
+ * @brief Tamper 2 callback.
* @param hrtc RTC handle
* @retval None
*/
@@ -591,7 +591,7 @@
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
/**
- * @brief Tamper 3 callback.
+ * @brief Tamper 3 callback.
* @param hrtc RTC handle
* @retval None
*/
@@ -613,12 +613,12 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
+{
uint32_t tickstart = HAL_GetTick();
- while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+ while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
{
- if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
+ if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
{
/* Clear the TIMESTAMP OverRun Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
@@ -629,9 +629,9 @@
return HAL_ERROR;
}
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -641,7 +641,7 @@
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
-
+
return HAL_OK;
}
@@ -656,11 +656,11 @@
uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -669,12 +669,12 @@
}
/* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
@@ -688,11 +688,11 @@
uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -701,7 +701,7 @@
}
/* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -717,15 +717,15 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
+{
uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -734,7 +734,7 @@
}
/* Clear the Tamper Flag */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -746,16 +746,16 @@
/**
* @}
*/
-
+
#if defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/** @addtogroup RTCEx_Exported_Functions_Group2
* @brief RTC Wake-up functions
*
-@verbatim
+@verbatim
===============================================================================
##### RTC Wake-up functions #####
- ===============================================================================
-
+ ===============================================================================
+
[..] This section provides functions allowing to configure Wake-up feature
@endverbatim
@@ -786,23 +786,24 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
}
}
}
@@ -812,9 +813,9 @@
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -837,7 +838,7 @@
/* Configure the Wakeup Timer counter */
hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
- /* Enable the Wakeup Timer */
+ /* Enable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
@@ -855,7 +856,7 @@
* @brief Set wake up timer with interrupt.
* @param hrtc RTC handle
* @param WakeUpCounter Wake up counter
- * @param WakeUpClock Wake up clock
+ * @param WakeUpClock Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -875,23 +876,24 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET){
+ if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ {
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
- {
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
}
}
}
@@ -905,9 +907,9 @@
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -936,8 +938,8 @@
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Configure the Interrupt in the RTC_CR register */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
+
/* Enable the Wakeup Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
@@ -954,7 +956,7 @@
/**
* @brief Deactivate wake up timer counter.
- * @param hrtc RTC handle
+ * @param hrtc RTC handle
* @retval HAL status
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -973,13 +975,13 @@
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
/* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1006,7 +1008,7 @@
/**
* @brief Get wake up timer counter.
- * @param hrtc RTC handle
+ * @param hrtc RTC handle
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -1023,14 +1025,18 @@
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
/* Get the WAKEUPTIMER interrupt source enable status */
- if(__HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(hrtc, RTC_IT_WUT) != RESET)
+ if (__HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(hrtc, RTC_IT_WUT) != RESET)
{
- /* Get the pending status of the WAKEUPTIMER Interrupt */
- if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
+ /* Get the pending status of the WAKEUPTIMER Interrupt */
+ if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
{
- /* WAKEUPTIMER callback */
+ /* WAKEUPTIMER callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->WakeUpTimerEventCallback(hrtc);
+#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
@@ -1038,7 +1044,7 @@
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
@@ -1069,14 +1075,14 @@
{
uint32_t tickstart = HAL_GetTick();
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
+
return HAL_TIMEOUT;
}
}
@@ -1084,7 +1090,7 @@
/* Clear the WAKEUPTIMER Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
+
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -1099,10 +1105,10 @@
/** @addtogroup RTCEx_Exported_Functions_Group3
* @brief Extended Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Write a data in a specified RTC Backup data register
@@ -1125,11 +1131,11 @@
#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/**
* @brief Write a data in a specified RTC Backup data register.
- * @param hrtc RTC handle
+ * @param hrtc RTC handle
* @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
* specify the register.
- * @param Data Data to be written in the specified RTC Backup data register.
+ * @param Data Data to be written in the specified RTC Backup data register.
* @retval None
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
@@ -1139,7 +1145,7 @@
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
- tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp = (uint32_t) & (hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
/* Write the specified register */
@@ -1148,10 +1154,10 @@
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc RTC handle
+ * @param hrtc RTC handle
* @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
- * specify the register.
+ * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
+ * specify the register.
* @retval Read value
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
@@ -1161,9 +1167,9 @@
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
- tmp = (uint32_t)&(hrtc->Instance->BKP0R);
+ tmp = (uint32_t) & (hrtc->Instance->BKP0R);
tmp += (BackupRegister * 4U);
-
+
/* Read the specified register */
return (*(__IO uint32_t *)tmp);
}
@@ -1171,7 +1177,7 @@
/**
* @brief Set the Smooth calibration parameters.
- * @param hrtc RTC handle
+ * @param hrtc RTC handle
* @param SmoothCalibPeriod Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
@@ -1183,12 +1189,12 @@
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
* @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
- * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
+ * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
* SmoothCalibMinusPulsesValue mut be equal to 0.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
{
uint32_t tickstart = 0U;
@@ -1206,14 +1212,14 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* check if a calibration is pending*/
- if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
{
tickstart = HAL_GetTick();
/* check if a calibration is pending*/
- while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
{
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1246,17 +1252,17 @@
/**
* @brief Configure the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc RTC handle
+ * @note When REFCKON is set, firmware must not write to Shift control register.
+ * @param hrtc RTC handle
* @param ShiftAdd1S Select to add or not 1 second to the time calendar.
* This parameter can be one of the following values :
- * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
+ * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
* @arg RTC_SHIFTADD1S_RESET: No effect.
* @param ShiftSubFS Select the number of Second Fractions to substitute.
* This parameter can be one any value from 0 to 0x7FFF.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
{
uint32_t tickstart = 0U;
@@ -1272,61 +1278,61 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- tickstart = HAL_GetTick();
+ tickstart = HAL_GetTick();
- /* Wait until the shift is completed*/
- while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
- {
- if((HAL_GetTick()-tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the reference clock detection is disabled */
- if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
- }
- else
+ /* Wait until the shift is completed*/
+ while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
- return HAL_ERROR;
+ return HAL_TIMEOUT;
}
+ }
+
+ /* Check if the reference clock detection is disabled */
+ if ((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+ {
+ /* Configure the Shift settings */
+ hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
+
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+ else
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1349,7 +1355,7 @@
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput)
{
/* Check the parameters */
assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
@@ -1387,7 +1393,7 @@
* @param hrtc RTC handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
{
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1416,7 +1422,7 @@
* @param hrtc RTC handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
{
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1427,7 +1433,7 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1451,7 +1457,7 @@
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
+ /* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -1465,7 +1471,7 @@
* @param hrtc RTC handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
{
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1474,9 +1480,9 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
+
/* Set Initialization mode */
- if(RTC_EnterInitMode(hrtc) != HAL_OK)
+ if (RTC_EnterInitMode(hrtc) != HAL_OK)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1516,7 +1522,7 @@
* directly from the Calendar counter.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc)
{
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1548,7 +1554,7 @@
* directly from the Calendar counter.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc)
{
/* Process Locked */
__HAL_LOCK(hrtc);
diff --git a/Src/stm32f0xx_hal_smartcard.c b/Src/stm32f0xx_hal_smartcard.c
index e111236..0d75f1a 100644
--- a/Src/stm32f0xx_hal_smartcard.c
+++ b/Src/stm32f0xx_hal_smartcard.c
@@ -22,20 +22,20 @@
(#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
(++) Enable the USARTx interface clock.
(++) USART pins configuration:
- (+++) Enable the clock for the USART GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (+++) Enable the clock for the USART GPIOs.
+ (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
(++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
and HAL_SMARTCARD_Receive_IT() APIs):
- (+++) Configure the USARTx interrupt priority.
- (+++) Enable the NVIC USART IRQ handle.
+ (+++) Configure the USARTx interrupt priority.
+ (+++) Enable the NVIC USART IRQ handle.
(++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
and HAL_SMARTCARD_Receive_DMA() APIs):
- (+++) Declare a DMA handle structure for the Tx/Rx channel.
- (+++) Enable the DMAx interface clock.
- (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
- (+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Declare a DMA handle structure for the Tx/Rx channel.
+ (+++) Enable the DMAx interface clock.
+ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+ (+++) Configure the DMA Tx/Rx channel.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@@ -45,7 +45,7 @@
in the hsmartcard handle AdvancedInit structure.
(#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
- (++) This API configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_SMARTCARD_MspInit() API.
[..]
(@) The specific SMARTCARD interrupts (Transmission complete interrupt,
@@ -99,42 +99,85 @@
[..]
(@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+ ##### Callback registration #####
+ ==================================
+
+ [..]
+ The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) MspInitCallback : SMARTCARD MspInit.
+ (+) MspDeInitCallback : SMARTCARD MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
+ and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
+ or @ref HAL_SMARTCARD_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
-
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
-#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -149,15 +192,23 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
- * @{
- */
+ * @{
+ */
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
-#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
-#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
-#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
+ USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+
+#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */
+
+#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */
/**
* @}
*/
@@ -168,10 +219,14 @@
/** @addtogroup SMARTCARD_Private_Functions
* @{
*/
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
@@ -182,9 +237,9 @@
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
@@ -196,7 +251,7 @@
*/
/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
@@ -205,17 +260,9 @@
[..]
This subsection provides a set of functions allowing to initialize the USARTx
associated to the SmartCard.
- [..]
- The Smartcard interface is designed to support asynchronous protocol Smartcards as
- defined in the ISO 7816-3 standard.
- [..]
- The USART can provide a clock to the smartcard through the SCLK output.
- In smartcard mode, SCLK is not associated to the communication but is simply derived
- from the internal peripheral input clock through a 5-bit prescaler.
- [..]
(+) These parameters can be configured:
(++) Baud Rate
- (++) Parity: should be enabled
+ (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
(++) Receiver/transmitter modes
(++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
(++) Prescaler value
@@ -237,20 +284,19 @@
(details for the procedures are available in reference manual).
@endverbatim
- * @{
- */
-/*
- Additional Table:
- Frame Length is fixed to 8 bits plus parity:
- SMARTCARD frame format is given in the following table
+ The USART frame format is given in the following table:
+
+ Table 1. USART frame format.
+---------------------------------------------------------------+
- | M1M0 bits | PCE bit | SMARTCARD frame |
+ | M1M0 bits | PCE bit | USART frame |
|-----------------------|---------------------------------------|
| 01 | 1 | | SB | 8 bit data | PB | STB | |
+---------------------------------------------------------------+
-*/
+
+ * @{
+ */
/**
* @brief Initialize the SMARTCARD mode according to the specified
@@ -262,7 +308,7 @@
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
+ if (hsmartcard == NULL)
{
return HAL_ERROR;
}
@@ -270,13 +316,25 @@
/* Check the USART associated to the SMARTCARD handle */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsmartcard->Lock = HAL_UNLOCKED;
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ SMARTCARD_InitCallbacksToDefault(hsmartcard);
+
+ if (hsmartcard->MspInitCallback == NULL)
+ {
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hsmartcard->MspInitCallback(hsmartcard);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_SMARTCARD_MspInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
}
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
@@ -299,6 +357,9 @@
return HAL_ERROR;
}
+ /* Set the SMARTCARD transmission completion indication */
+ SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
+
if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
{
SMARTCARD_AdvFeatureConfig(hsmartcard);
@@ -320,7 +381,7 @@
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check the SMARTCARD handle allocation */
- if(hsmartcard == NULL)
+ if (hsmartcard == NULL)
{
return HAL_ERROR;
}
@@ -340,7 +401,16 @@
WRITE_REG(hsmartcard->Instance->GTPR, 0x0U);
/* DeInit the low level hardware */
+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
+ if (hsmartcard->MspDeInitCallback == NULL)
+ {
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hsmartcard->MspDeInitCallback(hsmartcard);
+#else
HAL_SMARTCARD_MspDeInit(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->gState = HAL_SMARTCARD_STATE_RESET;
@@ -384,6 +454,229 @@
*/
}
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMARTCARD Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = pCallback;
+ break;
+
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an SMARTCARD callback
+ * SMARTCARD callback is redirected to the weak predefined callback
+ * @param hsmartcard smartcard handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmartcard);
+
+ if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ERROR_CB_ID :
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMARTCARD_MSPINIT_CB_ID :
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit;
+ break;
+
+ case HAL_SMARTCARD_MSPDEINIT_CB_ID :
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmartcard);
+
+ return status;
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -406,7 +699,7 @@
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
[..]
- (#) There are two modes of transfer:
+ (+) There are two modes of transfer:
(++) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
@@ -420,24 +713,25 @@
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
- (#) Blocking mode APIs are :
+ (+) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
(++) HAL_SMARTCARD_Receive()
- (#) Non Blocking mode APIs with Interrupt are :
+ (+) Non Blocking mode APIs with Interrupt are :
(++) HAL_SMARTCARD_Transmit_IT()
(++) HAL_SMARTCARD_Receive_IT()
(++) HAL_SMARTCARD_IRQHandler()
- (#) Non Blocking mode functions with DMA are :
+ (+) Non Blocking mode functions with DMA are :
(++) HAL_SMARTCARD_Transmit_DMA()
(++) HAL_SMARTCARD_Receive_DMA()
- (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SMARTCARD_TxCpltCallback()
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
+ [..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
(++) HAL_SMARTCARD_Abort()
(++) HAL_SMARTCARD_AbortTransmit()
@@ -453,14 +747,14 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -475,14 +769,16 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((ptmpdata == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -492,7 +788,7 @@
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Disable the Peripheral first to update mode for TX master */
@@ -500,9 +796,9 @@
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
+
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
@@ -510,21 +806,23 @@
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
- while(hsmartcard->TxXferCount > 0U)
+ while (hsmartcard->TxXferCount > 0U)
{
hsmartcard->TxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
+ ptmpdata++;
}
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
+ Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
{
/* Disable the Peripheral first to update modes */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
@@ -532,7 +830,7 @@
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
}
-
+
/* At end of Tx process, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -556,14 +854,16 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
+ uint8_t *ptmpdata = pData;
/* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((ptmpdata == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -574,22 +874,23 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hsmartcard->RxXferSize = Size;
hsmartcard->RxXferCount = Size;
/* Check the remain data to be received */
- while(hsmartcard->RxXferCount > 0U)
+ while (hsmartcard->RxXferCount > 0U)
{
hsmartcard->RxXferCount--;
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FFU);
+ *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+ ptmpdata++;
}
/* At end of Rx process, restore hsmartcard->RxState to Ready */
@@ -619,7 +920,7 @@
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -630,21 +931,26 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
- hsmartcard->pTxBuffPtr = pData;
- hsmartcard->TxXferSize = Size;
+ hsmartcard->pTxBuffPtr = pData;
+ hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
+ hsmartcard->TxISR = NULL;
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
+
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Configure Tx interrupt processing */
+ /* Set the Tx ISR function pointer */
+ hsmartcard->TxISR = SMARTCARD_TxISR;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
@@ -673,9 +979,9 @@
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -690,11 +996,15 @@
hsmartcard->RxXferSize = Size;
hsmartcard->RxXferCount = Size;
+ /* Configure Rx interrupt processing */
+ /* Set the Rx ISR function pointer */
+ hsmartcard->RxISR = SMARTCARD_RxISR;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmartcard);
/* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -720,7 +1030,7 @@
/* Check that a Tx process is not already ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -740,9 +1050,9 @@
/* Disable Rx, enable Tx */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+ SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
-
+
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
@@ -756,22 +1066,37 @@
hsmartcard->hdmatx->XferAbortCallback = NULL;
/* Enable the SMARTCARD transmit DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+ if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR,
+ Size) == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
- /* Clear the TC flag in the ICR register */
- CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
+ /* Enable the UART Error Interrupt: (Frame error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Error Interrupt: (Frame error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -792,9 +1117,9 @@
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -818,22 +1143,37 @@
hsmartcard->hdmarx->XferAbortCallback = NULL;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
+ if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr,
+ Size) == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
- /* Process Unlocked */
- __HAL_UNLOCK(hsmartcard);
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD associated USART CR3 register */
+ SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD associated USART CR3 register */
- SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
- return HAL_OK;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmartcard);
+
+ /* Restore hsmartcard->State to ready */
+ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -845,7 +1185,7 @@
* @brief Abort ongoing transfers (blocking mode).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -853,11 +1193,12 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Disable the SMARTCARD DMA Tx request if enabled */
@@ -866,13 +1207,22 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback to Null.
+ /* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmatx);
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -882,22 +1232,33 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback to Null.
+ /* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmarx);
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0U;
- hsmartcard->RxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -913,7 +1274,7 @@
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -921,14 +1282,14 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -940,18 +1301,27 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback to Null.
+ /* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmatx);
+ if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
@@ -966,7 +1336,7 @@
* @brief Abort ongoing Receive transfer (blocking mode).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -974,14 +1344,15 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -993,21 +1364,32 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback to Null.
+ /* Set the SMARTCARD DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(hsmartcard->hdmarx);
+ if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1019,7 +1401,7 @@
* @brief Abort ongoing transfers (Interrupt mode).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1029,23 +1411,24 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
uint32_t abortcplt = 1U;
-
+
/* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1,
+ (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
{
hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
}
@@ -1055,11 +1438,11 @@
}
}
/* DMA Rx Handle is valid */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
{
hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
}
@@ -1068,21 +1451,21 @@
hsmartcard->hdmarx->XferAbortCallback = NULL;
}
}
-
+
/* Disable the SMARTCARD DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
- /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
{
hsmartcard->hdmatx->XferAbortCallback = NULL;
}
@@ -1099,13 +1482,13 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
- /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
{
hsmartcard->hdmarx->XferAbortCallback = NULL;
abortcplt = 1U;
@@ -1121,21 +1504,33 @@
if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
- hsmartcard->TxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
hsmartcard->RxXferCount = 0U;
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
/* Reset errorCode */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1145,7 +1540,7 @@
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1155,14 +1550,14 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable TXEIE and TCIE interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -1174,14 +1569,14 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback :
+ /* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
@@ -1190,19 +1585,31 @@
else
{
/* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
/* Restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Reset Tx transfer counter */
- hsmartcard->TxXferCount = 0U;
+ hsmartcard->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ hsmartcard->TxISR = NULL;
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
@@ -1211,7 +1618,13 @@
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
@@ -1221,7 +1634,7 @@
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable SMARTCARD Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1231,14 +1644,15 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -1250,14 +1664,14 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback :
+ /* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
@@ -1266,39 +1680,61 @@
else
{
/* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
/* Reset Rx transfer counter */
- hsmartcard->RxXferCount = 0U;
+ hsmartcard->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
return HAL_OK;
}
/**
- * @brief Handle SMARTCARD interrupt requests.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Handle SMARTCARD interrupt requests.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
@@ -1306,30 +1742,33 @@
{
uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR);
uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1);
- uint32_t cr3its;
+ uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3);
uint32_t errorflags;
+ uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
- if (errorflags == RESET)
+ if (errorflags == 0U)
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- SMARTCARD_Receive_IT(hsmartcard);
- /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
return;
}
- }
+ }
/* If some errors occur */
- cr3its = READ_REG(hsmartcard->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
{
/* SMARTCARD parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
@@ -1337,7 +1776,7 @@
}
/* SMARTCARD frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
@@ -1345,7 +1784,7 @@
}
/* SMARTCARD noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
@@ -1353,8 +1792,9 @@
}
/* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE) != 0U)
+ || ((cr3its & USART_CR3_EIE) != 0U)))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
@@ -1362,7 +1802,7 @@
}
/* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
@@ -1370,12 +1810,16 @@
}
/* Call SMARTCARD Error Call back function if need be --------------------------*/
- if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
{
/* SMARTCARD in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- SMARTCARD_Receive_IT(hsmartcard);
+ if (hsmartcard->RxISR != NULL)
+ {
+ hsmartcard->RxISR(hsmartcard);
+ }
}
/* If Error is to be considered as blocking :
@@ -1383,9 +1827,10 @@
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
- if ( ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
- || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
- {
+ errorcode = hsmartcard->ErrorCode;
+ if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U))
+ {
/* Blocking error : transfer is aborted
Set the SMARTCARD state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
@@ -1397,14 +1842,14 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
/* Abort the SMARTCARD DMA Rx channel */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback :
+ /* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
@@ -1412,20 +1857,31 @@
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
/* other error type to be considered as blocking :
- Frame error in Transmission
*/
- else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+ else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+ && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U))
{
/* Blocking error : transfer is aborted
Set the SMARTCARD state ready to be able to start again the process,
@@ -1438,14 +1894,14 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Abort the SMARTCARD DMA Tx channel */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
- /* Set the SMARTCARD DMA Abort callback :
+ /* Set the SMARTCARD DMA Abort callback :
will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
{
/* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
@@ -1453,21 +1909,37 @@
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
- /* Call user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
}
else
{
- /* Non Blocking error : transfer could go on.
+ /* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
}
}
@@ -1476,30 +1948,44 @@
} /* End if some error occurs */
/* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
- if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
+ if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U))
{
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
__HAL_UNLOCK(hsmartcard);
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
/* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
- * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+ to be available during HAL_SMARTCARD_RxCpltCallback() processing */
__HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
return;
}
/* SMARTCARD in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_ISR_TXE) != 0U)
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
{
- SMARTCARD_Transmit_IT(hsmartcard);
+ if (hsmartcard->TxISR != NULL)
+ {
+ hsmartcard->TxISR(hsmartcard);
+ }
return;
}
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if((__HAL_SMARTCARD_GET_IT(hsmartcard, SMARTCARD_IT_TC) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, SMARTCARD_IT_TC) != RESET))
+ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
{
- SMARTCARD_EndTransmit_IT(hsmartcard);
- return;
+ if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET)
+ {
+ SMARTCARD_EndTransmit_IT(hsmartcard);
+ return;
+ }
}
+
}
/**
@@ -1556,7 +2042,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
-__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -1572,7 +2058,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
-__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -1588,7 +2074,7 @@
* the configuration information for the specified SMARTCARD module.
* @retval None
*/
-__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsmartcard);
@@ -1602,8 +2088,8 @@
* @}
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SMARTCARD State and Errors functions
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief SMARTCARD State and Errors functions
*
@verbatim
==============================================================================
@@ -1630,9 +2116,10 @@
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Return SMARTCARD handle state */
- uint32_t temp1= 0x00U, temp2 = 0x00U;
- temp1 = hsmartcard->gState;
- temp2 = hsmartcard->RxState;
+ uint32_t temp1;
+ uint32_t temp2;
+ temp1 = (uint32_t)hsmartcard->gState;
+ temp2 = (uint32_t)hsmartcard->RxState;
return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
}
@@ -1642,7 +2129,7 @@
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval SMARTCARD handle Error Code
-*/
+ */
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
{
return hsmartcard->ErrorCode;
@@ -1660,17 +2147,37 @@
* @{
*/
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
- * @brief Configure the SMARTCARD associated USART peripheral.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @brief Initialize the callbacks to their default values.
+ * @param hsmartcard SMARTCARD handle.
+ * @retval none
+ */
+void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+ /* Init the SMARTCARD Callback settings */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+
+}
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
+
+/**
+ * @brief Configure the SMARTCARD associated USART peripheral.
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t tmpreg = 0x00000000U;
- SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
- HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t tmpreg;
+ SMARTCARD_ClockSourceTypeDef clocksource;
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
@@ -1693,8 +2200,7 @@
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
- tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
- tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+ tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength);
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
@@ -1711,46 +2217,65 @@
* according to hsmartcard->Init.OneBitSampling
* - NACK transmission in case of parity error according
* to hsmartcard->Init.NACKEnable
- * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
- tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
- tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
- MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+ * - autoretry counter according to hsmartcard->Init.AutoRetryCount */
+
+ tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+ tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos);
+ MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
/*-------------------------- USART GTPR Configuration ----------------------*/
- tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
- MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+ tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
+ MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
/*-------------------------- USART RTOR Configuration ----------------------*/
- tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+ tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
- tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
+ tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
}
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+ MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
/*-------------------------- USART BRR Configuration -----------------------*/
SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+ tmpreg = 0U;
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
- hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
- hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetSysClockFreq() + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
- hsmartcard->Instance->BRR = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate/2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
- case SMARTCARD_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
+ {
+ hsmartcard->Instance->BRR = tmpreg;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+
+ /* Clear ISR function pointers */
+ hsmartcard->RxISR = NULL;
+ hsmartcard->TxISR = NULL;
+
return ret;
}
@@ -1758,7 +2283,7 @@
/**
* @brief Configure the SMARTCARD associated USART peripheral advanced features.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -1820,48 +2345,41 @@
/**
* @brief Check the SMARTCARD Idle State.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Initialize the SMARTCARD ErrorCode */
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
- /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
- Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
- */
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
- if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(hsmartcard->Instance))
+ /* Check if the Transmitter is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
- /* Check if the Transmitter is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ /* Wait until TEACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
{
- /* Wait until TEACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the Receiver is enabled */
- if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
}
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+ /* Check if the Receiver is enabled */
+ if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart,
+ SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
/* Initialize the SMARTCARD states */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1876,22 +2394,23 @@
/**
* @brief Handle SMARTCARD Communication Timeout.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @param Flag Specifies the SMARTCARD flag to check.
* @param Status The new Flag status (SET or RESET).
* @param Tickstart Tick start value
* @param Timeout Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag,
+ FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
@@ -1913,7 +2432,7 @@
/**
* @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -1930,7 +2449,7 @@
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * the configuration information for the specified SMARTCARD module.
* @retval None
*/
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
@@ -1952,7 +2471,7 @@
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
hsmartcard->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
@@ -1960,7 +2479,7 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
/* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
}
/**
@@ -1971,7 +2490,7 @@
*/
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
hsmartcard->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1985,7 +2504,13 @@
/* At end of Rx process, restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -1996,26 +2521,36 @@
*/
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
/* Stop SMARTCARD DMA Tx request if ongoing */
- if ( (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
- hsmartcard->TxXferCount = 0U;
- SMARTCARD_EndTxTransfer(hsmartcard);
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsmartcard->TxXferCount = 0U;
+ SMARTCARD_EndTxTransfer(hsmartcard);
+ }
}
/* Stop SMARTCARD DMA Rx request if ongoing */
- if ( (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
- hsmartcard->RxXferCount = 0U;
- SMARTCARD_EndRxTransfer(hsmartcard);
+ if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsmartcard->RxXferCount = 0U;
+ SMARTCARD_EndRxTransfer(hsmartcard);
+ }
}
hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -2026,11 +2561,17 @@
*/
static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
hsmartcard->RxXferCount = 0U;
hsmartcard->TxXferCount = 0U;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered user error callback */
+ hsmartcard->ErrorCallback(hsmartcard);
+#else
+ /* Call legacy weak user error callback */
HAL_SMARTCARD_ErrorCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -2043,19 +2584,19 @@
*/
static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
hsmartcard->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmarx != NULL)
+ if (hsmartcard->hdmarx != NULL)
{
- if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+ if (hsmartcard->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hsmartcard->TxXferCount = 0U;
hsmartcard->RxXferCount = 0U;
@@ -2064,14 +2605,21 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
@@ -2085,19 +2633,19 @@
*/
static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
-
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
+
hsmartcard->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(hsmartcard->hdmatx != NULL)
+ if (hsmartcard->hdmatx != NULL)
{
- if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+ if (hsmartcard->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
hsmartcard->TxXferCount = 0U;
hsmartcard->RxXferCount = 0U;
@@ -2106,14 +2654,21 @@
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ hsmartcard->AbortCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
@@ -2127,7 +2682,7 @@
*/
static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
hsmartcard->TxXferCount = 0U;
@@ -2137,8 +2692,13 @@
/* Restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ hsmartcard->AbortTransmitCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
@@ -2151,77 +2711,77 @@
*/
static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+ SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent);
hsmartcard->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
- __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
+ SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
- /* Call user Abort complete callback */
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ hsmartcard->AbortReceiveCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
- * @brief Send an amount of data in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
- * @retval HAL status
+ * @brief Send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT().
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
*/
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check that a Tx process is ongoing */
if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
- if(hsmartcard->TxXferCount == 0U)
+ if (hsmartcard->TxXferCount == 0U)
{
/* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
/* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-
- return HAL_OK;
+ __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
}
else
{
- hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFFU);
+ hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU);
+ hsmartcard->pTxBuffPtr++;
hsmartcard->TxXferCount--;
-
- return HAL_OK;
}
}
- else
- {
- return HAL_BUSY;
- }
}
/**
* @brief Wrap up transmission in non-blocking mode.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+ __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
/* Check if a receive process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
/* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
{
/* Disable the Peripheral first to update modes */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
@@ -2229,36 +2789,45 @@
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
}
-
+
/* Tx process is ended, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
- HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+ /* Clear TxISR function pointer */
+ hsmartcard->TxISR = NULL;
- return HAL_OK;
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx complete callback */
+ hsmartcard->TxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Tx complete callback */
+ HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
/**
- * @brief Receive an amount of data in non-blocking mode.
- * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
+ * @brief Receive an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
* interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
- * @retval HAL status
+ * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD module.
+ * @retval None
*/
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Check that a Rx process is ongoing */
if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
- *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFFU);
+ *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+ hsmartcard->pRxBuffPtr++;
- if(--hsmartcard->RxXferCount == 0U)
+ hsmartcard->RxXferCount--;
+ if (hsmartcard->RxXferCount == 0U)
{
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
/* Check if a transmit process is ongoing or not. If not disable ERR IT */
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -2269,19 +2838,22 @@
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+ /* Clear RxISR function pointer */
+ hsmartcard->RxISR = NULL;
+
+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx complete callback */
+ hsmartcard->RxCpltCallback(hsmartcard);
+#else
+ /* Call legacy weak Rx complete callback */
HAL_SMARTCARD_RxCpltCallback(hsmartcard);
-
- return HAL_OK;
+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */
}
-
- return HAL_OK;
}
else
{
/* Clear RXNE interrupt flag */
__HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
}
}
@@ -2297,7 +2869,5 @@
/**
* @}
*/
-
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_smartcard_ex.c b/Src/stm32f0xx_hal_smartcard_ex.c
index 3f764d3..fb761c5 100644
--- a/Src/stm32f0xx_hal_smartcard_ex.c
+++ b/Src/stm32f0xx_hal_smartcard_ex.c
@@ -8,7 +8,6 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
- *
@verbatim
=============================================================================
##### SMARTCARD peripheral extended features #####
@@ -19,45 +18,24 @@
(#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
auto-retry counter,...) in the hsmartcard AdvancedInit structure.
-
-
-
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
-
+#if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
-
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
@@ -73,7 +51,6 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions
* @{
@@ -97,8 +74,7 @@
* @{
*/
-/**
- * @brief Update on the fly the SMARTCARD block length in RTOR register.
+/** @brief Update on the fly the SMARTCARD block length in RTOR register.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @param BlockLength SMARTCARD block length (8-bit long at most)
@@ -106,11 +82,10 @@
*/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
{
- MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+ MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos));
}
-/**
- * @brief Update on the fly the receiver timeout value in RTOR register.
+/** @brief Update on the fly the receiver timeout value in RTOR register.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @param TimeOutValue receiver timeout value in number of baud blocks. The timeout
@@ -123,16 +98,14 @@
MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
}
-/**
- * @brief Enable the SMARTCARD receiver timeout feature.
+/** @brief Enable the SMARTCARD receiver timeout feature.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmartcard);
@@ -155,16 +128,14 @@
}
}
-/**
- * @brief Disable the SMARTCARD receiver timeout feature.
+/** @brief Disable the SMARTCARD receiver timeout feature.
* @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
{
-
- if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+ if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmartcard);
@@ -191,6 +162,31 @@
* @}
*/
+/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions
+ * @brief SMARTCARD Transmit and Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+@endverbatim
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
+ * @{
+ */
+
/**
* @}
*/
@@ -204,7 +200,5 @@
/**
* @}
*/
-
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
-
+#endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_smbus.c b/Src/stm32f0xx_hal_smbus.c
index c693b6e..72794e5 100644
--- a/Src/stm32f0xx_hal_smbus.c
+++ b/Src/stm32f0xx_hal_smbus.c
@@ -20,7 +20,7 @@
(#) Declare a SMBUS_HandleTypeDef handle structure, for example:
SMBUS_HandleTypeDef hsmbus;
- (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
+ (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
(##) Enable the SMBUSx interface clock
(##) SMBUS pins configuration
(+++) Enable the clock for the SMBUS GPIOs
@@ -33,91 +33,133 @@
Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
- (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
+ (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
(++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
+ by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
- (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
+ (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
(#) For SMBUS IO operations, only one mode of operations is available within this driver
*** Interrupt mode IO operation ***
===================================
[..]
- (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
- (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Master_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
- (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
+ (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
+ (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
+ (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
(++) The associated previous transfer callback is called at the end of abort process
- (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
- (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+ (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+ (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
(+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
- using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
- (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can
+ using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
+ (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
- (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
- (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Transmit_IT()
- (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
- (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using HAL_SMBUS_Slave_Receive_IT()
- (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
- (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() HAL_SMBUS_DisableAlert_IT()
- (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Alert Error Code using function HAL_SMBUS_GetError()
- (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
- (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMBUS_ErrorCallback()
- to check the Error Code using function HAL_SMBUS_GetError()
+ (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
+ (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
+ (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
+ (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
+ (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
+ (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
+ (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
+ (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
+ (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
+ to check the Error Code using function @ref HAL_SMBUS_GetError()
*** SMBUS HAL driver macros list ***
==================================
[..]
Below the list of most used macros in SMBUS HAL driver.
- (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
- (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
- (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
- (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
- (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
- (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+ (+) @ref __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral
+ (+) @ref __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not
+ (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag
+ (+) @ref __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt
+ (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt
+
+ *** Callback registration ***
+ =============================================
+ [..]
+ The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
+ to register an interrupt callback.
+ [..]
+ Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+ [..]
+ For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
+ [..]
+ Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
+ (+) MasterRxCpltCallback : callback for Master reception end of transfer.
+ (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
+ (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
+ (+) ListenCpltCallback : callback for end of listen mode.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
+ [..]
+ By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
+ Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
+ or @ref HAL_SMBUS_Init() function.
+ [..]
+ When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
[..]
(@) You can refer to the SMBUS HAL driver header file for more useful macros
-
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -141,7 +183,7 @@
/** @defgroup SMBUS_Private_Define SMBUS Private Constants
* @{
*/
-#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< SMBUS TIMING clear register Mask */
+#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */
#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */
#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */
#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */
@@ -161,18 +203,18 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest);
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus);
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
+static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
*/
@@ -255,8 +297,26 @@
/* Allocate lock resource and initialize it */
hsmbus->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+
+ if (hsmbus->MspInitCallback == NULL)
+ {
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hsmbus->MspInitCallback(hsmbus);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_SMBUS_MspInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
hsmbus->State = HAL_SMBUS_STATE_BUSY;
@@ -278,7 +338,7 @@
/* Configure SMBUSx: Own Address1 and ack own address1 mode */
hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- if (hsmbus->Init.OwnAddress1 != 0U)
+ if (hsmbus->Init.OwnAddress1 != 0UL)
{
if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
{
@@ -347,8 +407,18 @@
/* Disable the SMBUS Peripheral Clock */
__HAL_SMBUS_DISABLE(hsmbus);
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ if (hsmbus->MspDeInitCallback == NULL)
+ {
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ hsmbus->MspDeInitCallback(hsmbus);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_SMBUS_MspDeInit(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
@@ -447,7 +517,7 @@
*/
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
{
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -490,6 +560,299 @@
}
}
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User SMBUS Callback
+ * To be used instead of the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Unregister an SMBUS Callback
+ * SMBUS callback is redirected to the weak predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
+ * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
+ * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID :
+ hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID :
+ hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID :
+ hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
+ break;
+
+ case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID :
+ hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
+ break;
+
+ case HAL_SMBUS_LISTEN_COMPLETE_CB_ID :
+ hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
+ break;
+
+ case HAL_SMBUS_ERROR_CB_ID :
+ hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SMBUS_STATE_RESET == hsmbus->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SMBUS_MSPINIT_CB_ID :
+ hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SMBUS_MSPDEINIT_CB_ID :
+ hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief Register the Slave Address Match SMBUS Callback
+ * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param pCallback pointer to the Address Match Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = pCallback;
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+/**
+ * @brief UnRegister the Slave Address Match SMBUS Callback
+ * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hsmbus);
+
+ if (HAL_SMBUS_STATE_READY == hsmbus->State)
+ {
+ hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
+ }
+ else
+ {
+ /* Update the error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hsmbus);
+ return status;
+}
+
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -542,7 +905,7 @@
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
@@ -550,6 +913,8 @@
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
+ uint32_t tmp;
+
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -583,17 +948,21 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+
+ /* Store current volatile XferOptions, misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -602,12 +971,12 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
}
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -635,7 +1004,7 @@
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
@@ -643,6 +1012,8 @@
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
+ uint32_t tmp;
+
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -677,17 +1048,21 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+
+ /* Store current volatile XferOptions, Misra rule */
+ tmp = hsmbus->XferOptions;
+
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -696,7 +1071,7 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
}
}
@@ -722,7 +1097,7 @@
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
@@ -752,7 +1127,7 @@
/* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */
/* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
- SMBUS_TransferConfig(hsmbus, DevAddress, 1U, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP);
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -768,6 +1143,10 @@
{
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
}
+ else
+ {
+ /* Nothing to do */
+ }
return HAL_OK;
}
@@ -791,11 +1170,12 @@
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
- if ((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0UL))
{
- return HAL_ERROR;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
@@ -804,7 +1184,7 @@
/* Process Locked */
__HAL_LOCK(hsmbus);
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_TX;
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN);
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
/* Set SBC bit to manage Acknowledge at each bit */
@@ -831,18 +1211,18 @@
}
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
+ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -866,7 +1246,7 @@
}
else
{
- return HAL_ERROR;
+ return HAL_BUSY;
}
}
@@ -884,11 +1264,12 @@
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
- if ((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0UL))
{
- return HAL_ERROR;
+ hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM;
+ return HAL_ERROR;
}
/* Disable Interrupts, to prevent preemption during treatment in case of multicall */
@@ -897,7 +1278,7 @@
/* Process Locked */
__HAL_LOCK(hsmbus);
- hsmbus->State |= HAL_SMBUS_STATE_SLAVE_BUSY_RX;
+ hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN);
hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE;
/* Set SBC bit to manage Acknowledge at each bit */
@@ -920,13 +1301,13 @@
/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
{
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
else
{
- SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP);
}
/* Clear ADDR flag after prepare the transfer parameters */
@@ -946,7 +1327,7 @@
}
else
{
- return HAL_ERROR;
+ return HAL_BUSY;
}
}
@@ -1031,16 +1412,19 @@
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
- __IO uint32_t SMBUS_Trials = 0U;
+ __IO uint32_t SMBUS_Trials = 0UL;
+
+ FlagStatus tmp1;
+ FlagStatus tmp2;
if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
@@ -1063,20 +1447,30 @@
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
+
+ while ((tmp1 == RESET) && (tmp2 == RESET))
{
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* Device is ready */
hsmbus->State = HAL_SMBUS_STATE_READY;
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
}
+
+ tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF);
+ tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF);
}
/* Check if the NACKF flag has not been set */
@@ -1085,7 +1479,7 @@
/* Wait until STOPF flag is reset */
if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
@@ -1104,7 +1498,7 @@
/* Wait until STOPF flag is reset */
if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear NACK Flag */
@@ -1115,7 +1509,7 @@
}
/* Check if the maximum allowed number of trials has been reached */
- if (SMBUS_Trials++ == Trials)
+ if (SMBUS_Trials == Trials)
{
/* Generate Stop */
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
@@ -1123,21 +1517,27 @@
/* Wait until STOPF flag is reset */
if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
}
+
+ /* Increment Trials */
+ SMBUS_Trials++;
}
while (SMBUS_Trials < Trials);
hsmbus->State = HAL_SMBUS_STATE_READY;
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
+
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- return HAL_TIMEOUT;
+ return HAL_ERROR;
}
else
{
@@ -1160,49 +1560,55 @@
*/
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
{
- uint32_t tmpisrvalue = 0U;
-
/* Use a local variable to store the current ISR flags */
/* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */
- tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
+ uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR);
+ uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
- SMBUS_Slave_ISR(hsmbus);
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
}
/* Master mode selected */
else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
- SMBUS_Master_ISR(hsmbus);
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
}
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
- SMBUS_Slave_ISR(hsmbus);
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
}
/* Master mode selected */
else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
- SMBUS_Master_ISR(hsmbus);
+ (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue);
+ }
+ else
+ {
+ /* Nothing to do */
}
}
/* SMBUS in mode Listener Only --------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
- && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+ if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
- if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
- SMBUS_Slave_ISR(hsmbus);
+ (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue);
}
}
}
@@ -1392,16 +1798,17 @@
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus)
+static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
uint16_t DevAddress;
/* Process Locked */
__HAL_LOCK(hsmbus);
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
@@ -1414,9 +1821,13 @@
__HAL_UNLOCK(hsmbus);
/* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
{
/* Check and treat errors if errors occurs during STOP process */
SMBUS_ITErrorHandler(hsmbus);
@@ -1446,15 +1857,23 @@
/* REenable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
/* Store Last receive data if any */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
if ((hsmbus->XferSize > 0U))
{
@@ -1478,28 +1897,47 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
hsmbus->XferSize--;
hsmbus->XferCount--;
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
+ /* Increment Size counter */
hsmbus->XferSize--;
hsmbus->XferCount--;
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)
{
- if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
{
- DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
+ DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD);
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
@@ -1509,17 +1947,17 @@
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
}
}
}
- else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
+ else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U))
{
/* Call TxCpltCallback() if no stop mode is set */
if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
@@ -1535,7 +1973,12 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
@@ -1546,12 +1989,25 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET)
{
if (hsmbus->XferCount == 0U)
{
@@ -1578,7 +2034,12 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
@@ -1589,11 +2050,28 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->MasterRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -1604,17 +2082,18 @@
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
+ * @param StatusFlags Value of Interrupt Flags.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus)
+static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags)
{
- uint8_t TransferDirection = 0U;
- uint16_t SlaveAddrCode = 0U;
+ uint8_t TransferDirection;
+ uint16_t SlaveAddrCode;
/* Process Locked */
__HAL_LOCK(hsmbus);
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET)
{
/* Check that SMBUS transfer finished */
/* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
@@ -1650,13 +2129,17 @@
__HAL_UNLOCK(hsmbus);
/* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET)
{
- TransferDirection = SMBUS_GET_DIR(hsmbus);
- SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
+ TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus));
+ SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus));
/* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/
/* Other ADDRInterrupt will be treat in next Listen usecase */
@@ -1666,14 +2149,22 @@
__HAL_UNLOCK(hsmbus);
/* Call Slave Addr callback */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#else
HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
- else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+ else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
{
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1683,7 +2174,7 @@
/* or only the last Byte of Transfer */
/* So reset the RELOAD bit mode */
hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
- SMBUS_TransferConfig(hsmbus, 0U , 1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
else if (hsmbus->XferCount == 0U)
{
@@ -1697,13 +2188,17 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveRxCpltCallback(hsmbus);
+#else
HAL_SMBUS_SlaveRxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
else
{
/* Set Reload for next Bytes */
- SMBUS_TransferConfig(hsmbus, 0U, 1U, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
/* Ack last Byte Read */
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -1711,20 +2206,20 @@
}
else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
- if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
+ if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U))
{
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1732,8 +2227,12 @@
}
}
}
+ else
+ {
+ /* Nothing to do */
+ }
}
- else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
@@ -1742,7 +2241,11 @@
if (hsmbus->XferCount > 0U)
{
/* Write data to TXDR */
- hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
+
hsmbus->XferCount--;
hsmbus->XferSize--;
}
@@ -1758,13 +2261,21 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Tx complete callback to inform upper layer of the end of transmit process */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->SlaveTxCpltCallback(hsmbus);
+#else
HAL_SMBUS_SlaveTxCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Check if STOPF is set */
- if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET)
{
if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
@@ -1772,7 +2283,10 @@
if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
- (*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
+ *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR);
+
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
if ((hsmbus->XferSize > 0U))
{
@@ -1799,7 +2313,7 @@
/* Clear ADDR flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
- hsmbus->XferOptions = 0U;
+ hsmbus->XferOptions = 0;
hsmbus->PreviousState = hsmbus->State;
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1807,7 +2321,11 @@
__HAL_UNLOCK(hsmbus);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ListenCpltCallback(hsmbus);
+#else
HAL_SMBUS_ListenCpltCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
@@ -1823,9 +2341,9 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
- uint32_t tmpisr = 0U;
+ uint32_t tmpisr = 0UL;
if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
{
@@ -1855,8 +2373,6 @@
/* to avoid the risk of SMBUS interrupt handle execution before */
/* all interrupts requested done */
__HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
}
/**
* @brief Manage the disabling of Interrupts.
@@ -1865,11 +2381,12 @@
* @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition.
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t InterruptRequest)
+static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest)
{
- uint32_t tmpisr = 0U;
+ uint32_t tmpisr = 0UL;
+ uint32_t tmpstate = hsmbus->State;
- if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
+ if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
@@ -1877,48 +2394,48 @@
if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
{
- /* Disable TC, STOP, NACK, TXI interrupt */
+ /* Disable TC, STOP, NACK and TXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
- if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
- /* Disable STOPI, NACKI */
+ /* Disable STOP and NACK interrupt */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
{
- /* Disable TC, STOP, NACK, RXI interrupt */
+ /* Disable TC, STOP, NACK and RXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
- if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
+ && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
- /* Disable STOPI, NACKI */
+ /* Disable STOP and NACK interrupt */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
{
- /* Enable ADDR, STOP interrupt */
+ /* Disable ADDR, STOP and NACK interrupt */
tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL)
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
@@ -1929,8 +2446,6 @@
/* to avoid a breaking situation like at "t" time */
/* all disable interrupts request are not done */
__HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr);
-
- return HAL_OK;
}
/**
@@ -1938,13 +2453,15 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus)
{
uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+ uint32_t tmpstate;
+ uint32_t tmperror;
/* SMBUS Bus error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
@@ -1953,7 +2470,7 @@
}
/* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
@@ -1962,7 +2479,7 @@
}
/* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
@@ -1971,7 +2488,7 @@
}
/* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
@@ -1980,7 +2497,7 @@
}
/* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
@@ -1989,7 +2506,7 @@
}
/* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
{
hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
@@ -1997,14 +2514,20 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
+ /* Store current volatile hsmbus->State, misra rule */
+ tmperror = hsmbus->ErrorCode;
+
/* Call the Error Callback in case of Error detected */
- if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+ if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF))
{
/* Do not Reset the HAL state in case of ALERT error */
- if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
{
- if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ /* Store current volatile hsmbus->State, misra rule */
+ tmpstate = hsmbus->State;
+
+ if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
{
/* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
/* keep HAL_SMBUS_STATE_LISTEN if set */
@@ -2014,7 +2537,11 @@
}
/* Call the Error callback to inform upper layer */
+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
+ hsmbus->ErrorCallback(hsmbus);
+#else
HAL_SMBUS_ErrorCallback(hsmbus);
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
}
@@ -2027,51 +2554,32 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
/* Wait until flag is set */
- if (Status == RESET)
+ while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status)
{
- while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
+ hsmbus->PreviousState = hsmbus->State;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
+ /* Update SMBUS error code */
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT;
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_ERROR;
}
}
}
- else
- {
- while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
- {
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hsmbus->PreviousState = hsmbus->State;
- hsmbus->State = HAL_SMBUS_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hsmbus);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
return HAL_OK;
}
@@ -2095,27 +2603,16 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
- uint32_t tmpreg = 0U;
-
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
- /* Get the CR2 register value */
- tmpreg = hsmbus->Instance->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
/* update CR2 register */
- hsmbus->Instance->CR2 = tmpreg;
+ MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -2123,7 +2620,7 @@
* @param hsmbus SMBUS handle.
* @retval None
*/
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
+static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus)
{
/* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
/* it request implicitly to generate a restart condition */
@@ -2155,6 +2652,10 @@
{
hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
}
+ else
+ {
+ /* Nothing to do */
+ }
}
/**
* @}
diff --git a/Src/stm32f0xx_hal_spi.c b/Src/stm32f0xx_hal_spi.c
index 1fc6912..dbf1d1b 100644
--- a/Src/stm32f0xx_hal_spi.c
+++ b/Src/stm32f0xx_hal_spi.c
@@ -33,7 +33,7 @@
(+++) Enable the DMAx clock
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx Stream/Channel
- (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
+ (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
@@ -52,18 +52,12 @@
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
[..]
Master Receive mode restriction:
- (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
does not initiate a new transfer the following procedure has to be respected:
(##) HAL_SPI_DeInit()
(##) HAL_SPI_Init()
[..]
- The HAL drivers do not allow reaching all supported SPI frequencies in the different SPI
- modes. Refer to the source code (stm32xxxx_hal_spi.c header) to get a summary of the
- maximum SPI frequency that can be reached with a data size of 8 or 16 bits, depending on
- the APBx peripheral clock frequency (fPCLK) used by the SPI instance.
-
- [..]
Data buffer address alignment restriction:
(#) In case more than 1 byte is requested to be transferred, the HAL SPI uses 16-bit access for data buffer.
But there is no support for unaligned accesses on the Cortex-M0 processor.
@@ -72,6 +66,72 @@
(##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT()
(#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA()
and HAL_SPI_TransmitReceive_DMA().
+ [..]
+ Callback registration:
+
+ (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
+
+ Function HAL_SPI_RegisterCallback() allows to register following callbacks:
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+
+ (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
+ weak function.
+ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+
+ [..]
+ By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
+ or HAL_SPI_Init() function.
+
+ [..]
+ When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ [..]
+ Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
+ the following table resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
@endverbatim
@@ -136,29 +196,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -202,7 +246,7 @@
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart);
@@ -237,8 +281,8 @@
*/
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -319,8 +363,28 @@
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ /* Init the SPI Callback settings */
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+
+ if (hspi->MspInitCallback == NULL)
+ {
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, NVIC... */
+ hspi->MspInitCallback(hspi);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
@@ -373,7 +437,7 @@
}
#endif /* USE_SPI_CRC */
- /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo Threshold */
+ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
@@ -419,8 +483,18 @@
/* Disable the SPI Peripheral Clock */
__HAL_SPI_DISABLE(hspi);
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ if (hspi->MspDeInitCallback == NULL)
+ {
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+ hspi->MspDeInitCallback(hspi);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_SPI_MspDeInit(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_RESET;
@@ -463,13 +537,229 @@
*/
}
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+/**
+ * @brief Register a User SPI Callback
+ * To be used instead of the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be registered
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = pCallback;
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = pCallback;
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+
+/**
+ * @brief Unregister an SPI Callback
+ * SPI callback is redirected to the weak predefined callback
+ * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for the specified SPI.
+ * @param CallbackID ID of the callback to be unregistered
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ if (HAL_SPI_STATE_READY == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_TX_COMPLETE_CB_ID :
+ hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_SPI_RX_COMPLETE_CB_ID :
+ hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_COMPLETE_CB_ID :
+ hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
+ hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
+ hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
+ hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
+ break;
+
+ case HAL_SPI_ERROR_CB_ID :
+ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_SPI_ABORT_CB_ID :
+ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_SPI_STATE_RESET == hspi->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_SPI_MSPINIT_CB_ID :
+ hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_SPI_MSPDEINIT_CB_ID :
+ hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hspi);
+ return status;
+}
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -511,10 +801,11 @@
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
+ uint16_t initial_TxXferCount;
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
{
/* in this case, 16-bit access is performed on Data
So, check Data is 16-bit aligned address */
@@ -529,6 +820,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
+ initial_TxXferCount = Size;
if (hspi->State != HAL_SPI_STATE_READY)
{
@@ -580,10 +872,10 @@
/* Transmit data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
/* Transmit data in 16 Bit mode */
@@ -592,14 +884,14 @@
/* Wait until TXE flag is set to send data */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -610,18 +902,19 @@
/* Transmit data in 8 Bit mode */
else
{
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr ++;
hspi->TxXferCount--;
}
}
@@ -633,20 +926,21 @@
if (hspi->TxXferCount > 1U)
{
/* write on the data register in packing mode */
- hspi->Instance->DR = *((uint16_t *)pData);
- pData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++);
+ *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -697,13 +991,10 @@
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
{
/* in this case, 16-bit access is performed on Data
So, check Data is 16-bit aligned address */
@@ -759,15 +1050,15 @@
}
#endif /* USE_SPI_CRC */
- /* Set the Rx FiFo threshold */
+ /* Set the Rx Fifo threshold */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* set fiforxthresold according the reception data length: 16bit */
+ /* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthresold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -794,14 +1085,14 @@
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
/* read the received data */
- (* (uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
- pData += sizeof(uint8_t);
+ (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint8_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -817,14 +1108,14 @@
/* Check the RXNE flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- *((uint16_t *)pData) = hspi->Instance->DR;
- pData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
}
else
{
/* Timeout management */
- if ((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout)))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -851,12 +1142,12 @@
/* Receive last data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- *((uint16_t *)pData) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
}
/* Receive last data in 8 Bit mode */
else
{
- (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
}
/* Wait the CRC data */
@@ -870,28 +1161,25 @@
/* Read CRC to Flush DR and RXNE flag */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC */
+ READ_REG(hspi->Instance->DR);
}
else
{
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
{
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
errorcode = HAL_TIMEOUT;
goto error;
}
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
}
}
@@ -936,16 +1224,21 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout)
{
- uint32_t tmp = 0U, tmp1 = 0U;
+ uint16_t initial_TxXferCount;
+ uint16_t initial_RxXferCount;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
+ uint32_t spi_cr1;
+ uint32_t spi_cr2;
#endif /* USE_SPI_CRC */
- uint32_t tickstart = 0U;
- /* Variable used to alternate Rx and Tx during transfer */
- uint32_t txallowed = 1U;
- HAL_StatusTypeDef errorcode = HAL_OK;
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
{
/* in this case, 16-bit access is performed on Data
So, check Data is 16-bit aligned address */
@@ -962,11 +1255,18 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+ initial_TxXferCount = Size;
+ initial_RxXferCount = Size;
+#if (USE_SPI_CRC != 0U)
+ spi_cr1 = READ_REG(hspi->Instance->CR1);
+ spi_cr2 = READ_REG(hspi->Instance->CR2);
+#endif /* USE_SPI_CRC */
- if (!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
@@ -1006,14 +1306,14 @@
#endif /* USE_SPI_CRC */
/* Set the Rx Fifo threshold */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1U))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
{
- /* set fiforxthreshold according the reception data length: 16bit */
+ /* Set fiforxthreshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* set fiforxthreshold according the reception data length: 8bit */
+ /* Set fiforxthreshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -1027,19 +1327,19 @@
/* Transmit and Receive data in 16 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
/* Check TXE flag */
- if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount--;
/* Next Data is a reception (Rx). Tx not allowed */
txallowed = 0U;
@@ -1049,7 +1349,7 @@
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
@@ -1059,15 +1359,15 @@
}
/* Check RXNE flag */
- if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
+ if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -1077,34 +1377,36 @@
/* Transmit and Receive data in 8 Bit mode */
else
{
- if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
+ if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
{
if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
}
while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
- /* check TXE flag */
- if (txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
+ /* Check TXE flag */
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
{
if (hspi->TxXferCount > 1U)
{
- hspi->Instance->DR = *((uint16_t *)pTxData);
- pTxData += sizeof(uint16_t);
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
hspi->TxXferCount -= 2U;
}
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
/* Next Data is a reception (Rx). Tx not allowed */
@@ -1115,7 +1417,7 @@
if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
/* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
- if (((hspi->Instance->CR1 & SPI_CR1_MSTR) == 0U) && ((hspi->Instance->CR2 & SPI_CR2_NSSP) == SPI_CR2_NSSP))
+ if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
}
@@ -1125,28 +1427,29 @@
}
/* Wait until RXNE flag is reset */
- if ((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
{
if (hspi->RxXferCount > 1U)
{
- *((uint16_t *)pRxData) = hspi->Instance->DR;
- pRxData += sizeof(uint16_t);
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount -= 2U;
if (hspi->RxXferCount <= 1U)
{
- /* set fiforxthresold before to switch on 8 bit data size */
+ /* Set RX Fifo threshold before to switch on 8 bit data size */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
}
else
{
- (*(uint8_t *)pRxData++) = *(__IO uint8_t *)&hspi->Instance->DR;
+ (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
}
/* Next Data is a Transmission (Tx). Tx is allowed */
txallowed = 1U;
}
- if ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick() - tickstart) >= Timeout))
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -1169,15 +1472,13 @@
/* Read CRC */
if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
{
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC */
+ READ_REG(hspi->Instance->DR);
}
else
{
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
@@ -1188,9 +1489,8 @@
errorcode = HAL_TIMEOUT;
goto error;
}
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
}
}
@@ -1209,12 +1509,8 @@
/* Check the end of the transaction */
if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
{
- hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
- }
-
- if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
errorcode = HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
error :
@@ -1235,7 +1531,7 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
{
/* in this case, 16-bit access is performed on Data
So, check Data is 16-bit aligned address */
@@ -1325,7 +1621,7 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
{
/* in this case, 16-bit access is performed on Data
So, check Data is 16-bit aligned address */
@@ -1370,13 +1666,13 @@
/* Check the data size to adapt Rx threshold and the set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* Set fiforxthresold according the reception data length: 16 bit */
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_16BIT;
}
else
{
- /* Set fiforxthresold according the reception data length: 8 bit */
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
hspi->RxISR = SPI_RxISR_8BIT;
}
@@ -1435,10 +1731,11 @@
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- uint32_t tmp = 0U, tmp1 = 0U;
- HAL_StatusTypeDef errorcode = HAL_OK;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size > 1U))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (Size > 1U)))
{
/* in this case, 16-bit access is performed on Data
So, check Data is 16-bit aligned address */
@@ -1452,11 +1749,12 @@
/* Process locked */
__HAL_LOCK(hspi);
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
- if (!((tmp == HAL_SPI_STATE_READY) || \
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ if (!((tmp_state == HAL_SPI_STATE_READY) || \
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
@@ -1513,14 +1811,14 @@
#endif /* USE_SPI_CRC */
/* Check if packing mode is enabled and if there is more than 2 data to receive */
- if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2U))
+ if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
{
- /* Set fiforxthresold according the reception data length: 16 bit */
+ /* Set RX Fifo threshold according the reception data length: 16 bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* Set fiforxthresold according the reception data length: 8 bit */
+ /* Set RX Fifo threshold according the reception data length: 8 bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
@@ -1552,7 +1850,7 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
- /* check tx dma handle */
+ /* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
/* Check Direction parameter */
@@ -1631,7 +1929,16 @@
}
/* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1666,14 +1973,14 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
- /* check rx dma handle */
+ /* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
- /* check tx dma handle */
+ /* Check tx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
@@ -1735,17 +2042,17 @@
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- /* Set fiforxthresold according the reception data length: 16bit */
+ /* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
else
{
- /* Set fiforxthresold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- /* set fiforxthresold according the reception data length: 16bit */
+ /* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
if ((hspi->RxXferCount & 0x1U) == 0x0U)
@@ -1774,7 +2081,16 @@
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1808,10 +2124,11 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
- uint32_t tmp = 0U, tmp1 = 0U;
+ uint32_t tmp_mode;
+ HAL_SPI_StateTypeDef tmp_state;
HAL_StatusTypeDef errorcode = HAL_OK;
- /* check rx & tx dma handles */
+ /* Check rx & tx dma handles */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
@@ -1821,10 +2138,12 @@
/* Process locked */
__HAL_LOCK(hspi);
- tmp = hspi->State;
- tmp1 = hspi->Init.Mode;
- if (!((tmp == HAL_SPI_STATE_READY) ||
- ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
+ /* Init temporary variables */
+ tmp_state = hspi->State;
+ tmp_mode = hspi->Init.Mode;
+
+ if (!((tmp_state == HAL_SPI_STATE_READY) ||
+ ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
{
errorcode = HAL_BUSY;
goto error;
@@ -1864,7 +2183,7 @@
#endif /* USE_SPI_CRC */
#if defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F051x8) || defined (STM32F058xx)
- /* packing mode management is enabled by the DMA settings */
+ /* Packing mode management is enabled by the DMA settings */
if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
{
/* Restriction the DMA data received is not allowed in this mode */
@@ -1873,7 +2192,6 @@
}
#endif
-
/* Reset the threshold bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
@@ -1885,7 +2203,7 @@
}
else
{
- /* Set fiforxthresold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
@@ -1904,7 +2222,7 @@
if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
{
- /* Set fiforxthresold according the reception data length: 16bit */
+ /* Set RX Fifo threshold according the reception data length: 16bit */
CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
if ((hspi->RxXferCount & 0x1U) == 0x0U)
@@ -1941,7 +2259,16 @@
hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
+ hspi->RxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Enable Rx DMA Request */
SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
@@ -1954,7 +2281,16 @@
hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
+ hspi->TxXferCount))
+ {
+ /* Update SPI error code */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+
+ hspi->State = HAL_SPI_STATE_READY;
+ goto error;
+ }
/* Check if the SPI is already enabled */
if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
@@ -1986,17 +2322,21 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
- __IO uint32_t count, resetcount;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
count = resetcount;
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
@@ -2004,13 +2344,13 @@
/* Wait HAL_SPI_STATE_ABORT state */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2021,22 +2361,19 @@
/* Wait HAL_SPI_STATE_ABORT state */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
- /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ /* Disable the SPI DMA Tx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
/* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
if (hspi->hdmatx != NULL)
@@ -2068,6 +2405,11 @@
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
}
+ }
+
+ /* Disable the SPI DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
/* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
if (hspi->hdmarx != NULL)
{
@@ -2140,12 +2482,13 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
{
HAL_StatusTypeDef errorcode;
uint32_t abortcplt ;
- __IO uint32_t count, resetcount;
+ __IO uint32_t count;
+ __IO uint32_t resetcount;
/* Initialized local variable */
errorcode = HAL_OK;
@@ -2153,6 +2496,9 @@
resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
count = resetcount;
+ /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
/* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
{
@@ -2160,13 +2506,13 @@
/* Wait HAL_SPI_STATE_ABORT state */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2177,20 +2523,17 @@
/* Wait HAL_SPI_STATE_ABORT state */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ count--;
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
- /* Clear ERRIE interrupts in case of DMA Mode */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
-
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
@@ -2222,41 +2565,7 @@
}
}
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
- if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
- {
- /* Abort the SPI DMA Tx Stream/Channel */
- if (hspi->hdmatx != NULL)
- {
- /* Abort DMA Tx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
- {
- hspi->hdmatx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- /* Abort the SPI DMA Rx Stream/Channel */
- if (hspi->hdmarx != NULL)
- {
- /* Abort DMA Rx Handle linked to SPI Peripheral */
- if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
- {
- hspi->hdmarx->XferAbortCallback = NULL;
- hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
- abortcplt = 1U;
- }
- else
- {
- abortcplt = 0U;
- }
- }
- }
-
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ /* Disable the SPI DMA Tx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
{
/* Abort the SPI DMA Tx Stream/Channel */
@@ -2274,7 +2583,7 @@
}
}
}
- /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ /* Disable the SPI DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
{
/* Abort the SPI DMA Rx Stream/Channel */
@@ -2319,7 +2628,11 @@
hspi->State = HAL_SPI_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
return errorcode;
@@ -2366,13 +2679,14 @@
}
/**
- * @brief Stop the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
{
+ HAL_StatusTypeDef errorcode = HAL_OK;
/* The Lock is not implemented on this API to allow the user application
to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
@@ -2382,18 +2696,26 @@
/* Abort the SPI DMA tx Stream/Channel */
if (hspi->hdmatx != NULL)
{
- HAL_DMA_Abort(hspi->hdmatx);
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
/* Abort the SPI DMA rx Stream/Channel */
if (hspi->hdmarx != NULL)
{
- HAL_DMA_Abort(hspi->hdmarx);
+ if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ errorcode = HAL_ERROR;
+ }
}
/* Disable the SPI DMA Tx & Rx requests */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->State = HAL_SPI_STATE_READY;
- return HAL_OK;
+ return errorcode;
}
/**
@@ -2408,25 +2730,26 @@
uint32_t itflag = hspi->Instance->SR;
/* SPI in mode Receiver ----------------------------------------------------*/
- if (((itflag & SPI_FLAG_OVR) == RESET) &&
- ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
+ (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
/* SPI in mode Transmitter -------------------------------------------------*/
- if (((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
+ if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
/* SPI in Error Treatment --------------------------------------------------*/
- if (((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
+ if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
+ || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
{
/* SPI Overrun error interrupt occurred ----------------------------------*/
- if ((itflag & SPI_FLAG_OVR) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
{
if (hspi->State != HAL_SPI_STATE_BUSY_TX)
{
@@ -2441,14 +2764,14 @@
}
/* SPI Mode Fault error interrupt occurred -------------------------------*/
- if ((itflag & SPI_FLAG_MODF) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
__HAL_SPI_CLEAR_MODFFLAG(hspi);
}
/* SPI Frame error interrupt occurred ------------------------------------*/
- if ((itflag & SPI_FLAG_FRE) != RESET)
+ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
__HAL_SPI_CLEAR_FREFLAG(hspi);
@@ -2471,7 +2794,10 @@
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmarx);
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
}
/* Abort the SPI DMA Tx channel */
if (hspi->hdmatx != NULL)
@@ -2479,13 +2805,20 @@
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
- HAL_DMA_Abort_IT(hspi->hdmatx);
+ if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ }
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
return;
@@ -2493,7 +2826,7 @@
}
/**
- * @brief Tx Transfer completed callback.
+ * @brief Tx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2509,7 +2842,7 @@
}
/**
- * @brief Rx Transfer completed callback.
+ * @brief Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2525,7 +2858,7 @@
}
/**
- * @brief Tx and Rx Transfer completed callback.
+ * @brief Tx and Rx Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2541,7 +2874,7 @@
}
/**
- * @brief Tx Half Transfer completed callback.
+ * @brief Tx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2557,7 +2890,7 @@
}
/**
- * @brief Rx Half Transfer completed callback.
+ * @brief Rx Half Transfer completed callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2573,7 +2906,7 @@
}
/**
- * @brief Tx and Rx Half Transfer callback.
+ * @brief Tx and Rx Half Transfer callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2589,7 +2922,7 @@
}
/**
- * @brief SPI error callback.
+ * @brief SPI error callback.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
@@ -2679,17 +3012,17 @@
*/
/**
- * @brief DMA SPI transmit process complete callback.
+ * @brief DMA SPI transmit process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
/* DMA Normal Mode */
@@ -2718,26 +3051,33 @@
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user Tx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
- * @brief DMA SPI receive process complete callback.
+ * @brief DMA SPI receive process complete callback.
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO uint16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -2753,7 +3093,7 @@
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
/* Wait until RXNE flag */
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
@@ -2761,26 +3101,23 @@
/* Read CRC */
if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC */
+ READ_REG(hspi->Instance->DR);
}
else
{
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
{
- if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
/* Error on the CRC reception */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
}
}
@@ -2809,11 +3146,21 @@
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2824,11 +3171,9 @@
*/
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- uint32_t tickstart = 0U;
-#if (USE_SPI_CRC != 0U)
- __IO int16_t tmpreg = 0U;
-#endif /* USE_SPI_CRC */
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ uint32_t tickstart;
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -2851,9 +3196,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
}
else
{
@@ -2863,9 +3206,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
}
/* Read CRC to Flush DR and RXNE flag */
- tmpreg = hspi->Instance->DR;
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ READ_REG(hspi->Instance->DR);
}
}
#endif /* USE_SPI_CRC */
@@ -2894,11 +3235,21 @@
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
return;
}
}
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2909,9 +3260,14 @@
*/
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Tx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxHalfCpltCallback(hspi);
+#else
HAL_SPI_TxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2922,9 +3278,14 @@
*/
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user Rx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxHalfCpltCallback(hspi);
+#else
HAL_SPI_RxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2935,9 +3296,14 @@
*/
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+ /* Call user TxRx half complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxHalfCpltCallback(hspi);
+#else
HAL_SPI_TxRxHalfCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2948,14 +3314,19 @@
*/
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Stop the disable DMA transfer on SPI side */
CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2966,11 +3337,16 @@
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
hspi->RxXferCount = 0U;
hspi->TxXferCount = 0U;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -2983,7 +3359,7 @@
*/
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
hspi->hdmatx->XferAbortCallback = NULL;
@@ -3032,7 +3408,11 @@
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -3045,7 +3425,7 @@
*/
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
/* Disable SPI Peripheral */
__HAL_SPI_DISABLE(hspi);
@@ -3095,7 +3475,11 @@
hspi->State = HAL_SPI_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->AbortCpltCallback(hspi);
+#else
HAL_SPI_AbortCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
/**
@@ -3109,23 +3493,24 @@
/* Receive data in packing mode */
if (hspi->RxXferCount > 1U)
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount -= 2U;
if (hspi->RxXferCount == 1U)
{
- /* set fiforxthresold according the reception data length: 8bit */
+ /* Set RX Fifo threshold according the reception data length: 8bit */
SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
}
}
/* Receive data in 8 Bit mode */
else
{
- *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
}
- /* check end of the reception */
+ /* Check end of the reception */
if (hspi->RxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
@@ -3156,17 +3541,12 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Regsiter */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
hspi->CRCSize--;
- /* check end of the reception */
+ /* Check end of the reception */
if (hspi->CRCSize == 0U)
{
/* Disable RXNE and ERR interrupt */
@@ -3198,11 +3578,12 @@
/* Transmit data in 8 Bit mode */
else
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
}
- /* check the end of the transmission */
+ /* Check the end of the transmission */
if (hspi->TxXferCount == 0U)
{
#if (USE_SPI_CRC != 0U)
@@ -3235,7 +3616,7 @@
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
/* Receive data in 16 Bit mode */
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
@@ -3268,14 +3649,8 @@
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- /* Receive data in 16 Bit mode */
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC to flush Data Regsiter */
+ READ_REG(hspi->Instance->DR);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -3330,13 +3705,8 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Register */
+ READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
hspi->CRCSize--;
@@ -3355,7 +3725,8 @@
*/
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->pRxBuffPtr++;
hspi->RxXferCount--;
#if (USE_SPI_CRC != 0U)
@@ -3388,13 +3759,8 @@
*/
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint16_t tmpreg = 0U;
-
- /* Read data register to flush CRC */
- tmpreg = hspi->Instance->DR;
-
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 16bit CRC to flush Data Register */
+ READ_REG(hspi->Instance->DR);
/* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@@ -3411,7 +3777,7 @@
*/
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
{
- *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
@@ -3444,7 +3810,8 @@
*/
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
{
- *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr++;
hspi->TxXferCount--;
if (hspi->TxXferCount == 0U)
@@ -3487,23 +3854,23 @@
}
/**
- * @brief Handle SPI Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Flag SPI flag to check
- * @param State flag state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
+ if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -3539,32 +3906,29 @@
}
/**
- * @brief Handle SPI FIFO Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Fifo Fifo to check
- * @param State Fifo state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
uint32_t Timeout, uint32_t Tickstart)
{
- __IO uint8_t tmpreg;
-
while ((hspi->Instance->SR & Fifo) != State)
{
if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
{
- tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
- /* To avoid GCC warning */
- UNUSED(tmpreg);
+ /* Read 8bit CRC to flush Data Register */
+ READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
}
if (Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) >= Timeout))
+ if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -3665,6 +4029,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
return HAL_TIMEOUT;
}
+
return HAL_OK;
}
@@ -3676,7 +4041,7 @@
*/
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
@@ -3697,7 +4062,12 @@
hspi->State = HAL_SPI_STATE_READY;
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
@@ -3707,18 +4077,33 @@
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user TxRx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxRxCpltCallback(hspi);
+#else
HAL_SPI_TxRxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
else
{
hspi->State = HAL_SPI_STATE_READY;
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
#if (USE_SPI_CRC != 0U)
}
@@ -3749,18 +4134,33 @@
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
#endif /* USE_SPI_CRC */
if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->RxCpltCallback(hspi);
+#else
HAL_SPI_RxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
#if (USE_SPI_CRC != 0U)
}
@@ -3775,7 +4175,7 @@
*/
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -3798,11 +4198,21 @@
hspi->State = HAL_SPI_STATE_READY;
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
+ /* Call user error callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->ErrorCallback(hspi);
+#else
HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
else
{
+ /* Call user Rx complete callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
+ hspi->TxCpltCallback(hspi);
+#else
HAL_SPI_TxCpltCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
@@ -3821,19 +4231,19 @@
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
/* Check RXNEIE is disabled */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
@@ -3862,19 +4272,19 @@
count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
- CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+ /* Disable TXEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
/* Check TXEIE is disabled */
do
{
- if (count-- == 0U)
+ if (count == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{
@@ -3890,6 +4300,35 @@
hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
}
+ /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ /* Disable RXNEIE interrupt */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
+
+ /* Check RXNEIE is disabled */
+ do
+ {
+ if (count == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+ break;
+ }
+ count--;
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+
+ /* Control the BSY flag */
+ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+
+ /* Empty the FRLVL fifo */
+ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
+ {
+ hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
+ }
+ }
hspi->State = HAL_SPI_STATE_ABORT;
}
diff --git a/Src/stm32f0xx_hal_spi_ex.c b/Src/stm32f0xx_hal_spi_ex.c
index 2ae2a39..fb88495 100644
--- a/Src/stm32f0xx_hal_spi_ex.c
+++ b/Src/stm32f0xx_hal_spi_ex.c
@@ -10,29 +10,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -55,7 +39,7 @@
/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
* @{
*/
-#define SPI_FIFO_SIZE 4
+#define SPI_FIFO_SIZE 4UL
/**
* @}
*/
@@ -63,7 +47,7 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
* @{
@@ -88,7 +72,7 @@
*/
/**
- * @brief Flush the RX fifo.
+ * @brief Flush the RX fifo.
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
diff --git a/Src/stm32f0xx_hal_tim.c b/Src/stm32f0xx_hal_tim.c
index 459f362..b5377fe 100644
--- a/Src/stm32f0xx_hal_tim.c
+++ b/Src/stm32f0xx_hal_tim.c
@@ -3,51 +3,54 @@
* @file stm32f0xx_hal_tim.c
* @author MCD Application Team
* @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
- * + Time Base Initialization
- * + Time Base Start
- * + Time Base Start Interruption
- * + Time Base Start DMA
- * + Time Output Compare/PWM Initialization
- * + Time Output Compare/PWM Channel Configuration
- * + Time Output Compare/PWM Start
- * + Time Output Compare/PWM Start Interruption
- * + Time Output Compare/PWM Start DMA
- * + Time Input Capture Initialization
- * + Time Input Capture Channel Configuration
- * + Time Input Capture Start
- * + Time Input Capture Start Interruption
- * + Time Input Capture Start DMA
- * + Time One Pulse Initialization
- * + Time One Pulse Channel Configuration
- * + Time One Pulse Start
- * + Time Encoder Interface Initialization
- * + Time Encoder Interface Start
- * + Time Encoder Interface Start Interruption
- * + Time Encoder Interface Start DMA
+ * + TIM Time Base Initialization
+ * + TIM Time Base Start
+ * + TIM Time Base Start Interruption
+ * + TIM Time Base Start DMA
+ * + TIM Output Compare/PWM Initialization
+ * + TIM Output Compare/PWM Channel Configuration
+ * + TIM Output Compare/PWM Start
+ * + TIM Output Compare/PWM Start Interruption
+ * + TIM Output Compare/PWM Start DMA
+ * + TIM Input Capture Initialization
+ * + TIM Input Capture Channel Configuration
+ * + TIM Input Capture Start
+ * + TIM Input Capture Start Interruption
+ * + TIM Input Capture Start DMA
+ * + TIM One Pulse Initialization
+ * + TIM One Pulse Channel Configuration
+ * + TIM One Pulse Start
+ * + TIM Encoder Interface Initialization
+ * + TIM Encoder Interface Start
+ * + TIM Encoder Interface Start Interruption
+ * + TIM Encoder Interface Start DMA
* + Commutation Event configuration with Interruption and DMA
- * + Time OCRef clear configuration
- * + Time External Clock configuration
+ * + TIM OCRef clear configuration
+ * + TIM External Clock configuration
@verbatim
==============================================================================
##### TIMER Generic features #####
==============================================================================
[..] The Timer features include:
(#) 16-bit up, down, up/down auto-reload counter.
- (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
+ (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
counter clock frequency either by any factor between 1 and 65536.
(#) Up to 4 independent channels for:
(++) Input Capture
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
+ (#) Synchronization circuit to control the timer with external signals and to interconnect
+ several timers together.
+ (#) Supports incremental encoder for positioning purposes
##### How to use this driver #####
==============================================================================
[..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
(++) Time Base : HAL_TIM_Base_MspInit()
(++) Input Capture : HAL_TIM_IC_MspInit()
(++) Output Compare : HAL_TIM_OC_MspInit()
@@ -62,22 +65,22 @@
__HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
- (#) The external Clock can be configured, if needed (the default clock is the
+ (#) The external Clock can be configured, if needed (the default clock is the
internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
- (#) Configure the TIM in the desired functioning mode using one of the
+ (#) Configure the TIM in the desired functioning mode using one of the
Initialization function of this driver:
(++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
- (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
+ (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
Output Compare signal.
- (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
+ (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
PWM signal.
- (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
+ (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
external signal.
- (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
- in One Pulse Mode.
+ (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
+ in One Pulse Mode.
(++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
(#) Activate the TIM peripheral using one of the start functions depending from the feature used:
@@ -92,33 +95,89 @@
HAL_TIM_DMABurst_WriteStart()
HAL_TIM_DMABurst_ReadStart()
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+ @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ [..]
+ These functions allow to register/unregister following callbacks:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
+ (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
+ (+) BreakCallback : TIM Break Callback.
+
+ [..]
+By default, after the Init and when the state is HAL_TIM_STATE_RESET
+all interrupt callbacks are set to the corresponding weak functions:
+ examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+ [..]
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init / DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
+ keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
+
+ [..]
+ Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
+ Exception done MspInit / MspDeInit that can be registered / unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+ [..]
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -142,8 +201,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions TIM_Private_Functions
+/** @addtogroup TIM_Private_Functions
* @{
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@@ -151,32 +209,32 @@
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
+ uint32_t TIM_ICFilter);
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
+ uint32_t TIM_ICFilter);
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter);
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
+ uint32_t TIM_ICFilter);
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig);
-
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
-
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
- * @brief Time Base functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
+ * @brief Time Base functions
+ *
+@verbatim
==============================================================================
##### Time Base functions #####
==============================================================================
@@ -196,14 +254,18 @@
*/
/**
* @brief Initializes the TIM Time base Unit according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * parameters in the TIM_HandleTypeDef and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -214,29 +276,41 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Base_MspInitCallback == NULL)
+ {
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM Base peripheral
+ * @brief DeInitializes the TIM Base peripheral
* @param htim TIM Base handle
* @retval HAL status
*/
@@ -250,8 +324,17 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Base_MspDeInitCallback == NULL)
+ {
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Base_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -264,7 +347,7 @@
/**
* @brief Initializes the TIM Base MSP.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
@@ -272,14 +355,14 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Base MSP.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
@@ -287,7 +370,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspDeInit could be implemented in the user file
*/
}
@@ -295,22 +378,28 @@
/**
* @brief Starts the TIM Base generation.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -318,22 +407,22 @@
/**
* @brief Stops the TIM Base generation.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
/* Change the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
@@ -341,19 +430,25 @@
/**
* @brief Starts the TIM Base generation in interrupt mode.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Enable the TIM Update interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+ /* Enable the TIM Update interrupt */
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -361,9 +456,9 @@
/**
* @brief Stops the TIM Base generation in interrupt mode.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
@@ -380,23 +475,25 @@
/**
* @brief Starts the TIM Base generation in DMA mode.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to peripheral.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((pData == 0 ) && (Length > 0))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -405,20 +502,33 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
- /* Set the DMA Period elapsed callback */
+ else
+ {
+ /* nothing to do */
+ }
+
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Update DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -426,9 +536,9 @@
/**
* @brief Stops the TIM Base generation in DMA mode.
- * @param htim TIM handle
+ * @param htim TIM Base handle
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
@@ -437,6 +547,8 @@
/* Disable the TIM Update DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -451,37 +563,41 @@
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- * @brief Time Output Compare functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
+ * @brief TIM Output Compare functions
+ *
+@verbatim
==============================================================================
- ##### Time Output Compare functions #####
+ ##### TIM Output Compare functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Output Compare.
(+) De-initialize the TIM Output Compare.
- (+) Start the Time Output Compare.
- (+) Stop the Time Output Compare.
- (+) Start the Time Output Compare and enable interrupt.
- (+) Stop the Time Output Compare and disable interrupt.
- (+) Start the Time Output Compare and enable DMA transfer.
- (+) Stop the Time Output Compare and disable DMA transfer.
+ (+) Start the TIM Output Compare.
+ (+) Stop the TIM Output Compare.
+ (+) Start the TIM Output Compare and enable interrupt.
+ (+) Stop the TIM Output Compare and disable interrupt.
+ (+) Start the TIM Output Compare and enable DMA transfer.
+ (+) Stop the TIM Output Compare and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Output Compare according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
* @param htim TIM Output Compare handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -492,29 +608,41 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OC_MspInitCallback == NULL)
+ {
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OC_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM peripheral
+ * @brief DeInitializes the TIM peripheral
* @param htim TIM Output Compare handle
* @retval HAL status
*/
@@ -523,13 +651,22 @@
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OC_MspDeInitCallback == NULL)
+ {
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OC_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -542,7 +679,7 @@
/**
* @brief Initializes the TIM Output Compare MSP.
- * @param htim TIM handle
+ * @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
@@ -550,14 +687,14 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Output Compare MSP.
- * @param htim TIM handle
+ * @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
@@ -565,38 +702,44 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim TIM Output Compare handle
+ * @param htim TIM Output Compare handle
* @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -604,7 +747,7 @@
/**
* @brief Stops the TIM Output Compare signal generation.
- * @param htim TIM handle
+ * @param htim TIM Output Compare handle
* @param Channel TIM Channel to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -612,7 +755,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -621,9 +764,9 @@
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -636,7 +779,7 @@
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim TIM OC handle
+ * @param htim TIM Output Compare handle
* @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -644,9 +787,11 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -656,45 +801,49 @@
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -710,7 +859,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -722,40 +871,40 @@
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -778,19 +927,21 @@
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U ) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -799,87 +950,110 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -895,7 +1069,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -907,40 +1081,44 @@
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -958,37 +1136,41 @@
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- * @brief Time PWM functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
+ * @brief TIM PWM functions
+ *
+@verbatim
==============================================================================
- ##### Time PWM functions #####
+ ##### TIM PWM functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize and configure the TIM OPWM.
+ (+) Initialize and configure the TIM PWM.
(+) De-initialize the TIM PWM.
- (+) Start the Time PWM.
- (+) Stop the Time PWM.
- (+) Start the Time PWM and enable interrupt.
- (+) Stop the Time PWM and disable interrupt.
- (+) Start the Time PWM and enable DMA transfer.
- (+) Stop the Time PWM and disable DMA transfer.
+ (+) Start the TIM PWM.
+ (+) Stop the TIM PWM.
+ (+) Start the TIM PWM and enable interrupt.
+ (+) Stop the TIM PWM and disable interrupt.
+ (+) Start the TIM PWM and enable DMA transfer.
+ (+) Stop the TIM PWM and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM PWM Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim TIM handle
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
+ * @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -999,30 +1181,42 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->PWM_MspInitCallback == NULL)
+ {
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->PWM_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM peripheral
- * @param htim TIM handle
+ * @brief DeInitializes the TIM peripheral
+ * @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
@@ -1035,8 +1229,17 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->PWM_MspDeInitCallback == NULL)
+ {
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->PWM_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1049,7 +1252,7 @@
/**
* @brief Initializes the TIM PWM MSP.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
@@ -1057,14 +1260,14 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM PWM MSP.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
@@ -1072,7 +1275,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspDeInit could be implemented in the user file
*/
}
@@ -1087,23 +1290,29 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1111,7 +1320,7 @@
/**
* @brief Stops the PWM signal generation.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -1119,7 +1328,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -1128,9 +1337,9 @@
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1146,7 +1355,7 @@
/**
* @brief Starts the PWM signal generation in interrupt mode.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -1154,9 +1363,10 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1166,45 +1376,49 @@
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1212,7 +1426,7 @@
/**
* @brief Stops the PWM signal generation in interrupt mode.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -1220,8 +1434,8 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+ */
+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1232,40 +1446,40 @@
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1278,7 +1492,7 @@
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -1288,19 +1502,21 @@
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U ) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1309,87 +1525,109 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Capture/Compare 3 request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
}
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1397,7 +1635,7 @@
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -1405,7 +1643,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -1417,40 +1655,44 @@
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -1468,37 +1710,41 @@
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- * @brief Time Input Capture functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
+ * @brief TIM Input Capture functions
+ *
+@verbatim
==============================================================================
- ##### Time Input Capture functions #####
+ ##### TIM Input Capture functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Input Capture.
(+) De-initialize the TIM Input Capture.
- (+) Start the Time Input Capture.
- (+) Stop the Time Input Capture.
- (+) Start the Time Input Capture and enable interrupt.
- (+) Stop the Time Input Capture and disable interrupt.
- (+) Start the Time Input Capture and enable DMA transfer.
- (+) Stop the Time Input Capture and disable DMA transfer.
+ (+) Start the TIM Input Capture.
+ (+) Stop the TIM Input Capture.
+ (+) Start the TIM Input Capture and enable interrupt.
+ (+) Stop the TIM Input Capture and disable interrupt.
+ (+) Start the TIM Input Capture and enable DMA transfer.
+ (+) Stop the TIM Input Capture and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
* @param htim TIM Input Capture handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -1509,29 +1755,41 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->IC_MspInitCallback == NULL)
+ {
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->IC_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Init the base time for the input capture */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM peripheral
+ * @brief DeInitializes the TIM peripheral
* @param htim TIM Input Capture handle
* @retval HAL status
*/
@@ -1545,8 +1803,17 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->IC_MspDeInitCallback == NULL)
+ {
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->IC_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1559,7 +1826,7 @@
/**
* @brief Initializes the TIM Input Capture MSP.
- * @param htim TIM handle
+ * @param htim TIM Input Capture handle
* @retval None
*/
__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
@@ -1567,7 +1834,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_MspInit could be implemented in the user file
*/
}
@@ -1582,7 +1849,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_MspDeInit could be implemented in the user file
*/
}
@@ -1597,17 +1864,23 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1615,7 +1888,7 @@
/**
* @brief Stops the TIM Input Capture measurement.
- * @param htim TIM handle
+ * @param htim TIM Input Capture handle
* @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -1623,7 +1896,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -1649,9 +1922,11 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+ */
+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@@ -1661,38 +1936,42 @@
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1700,7 +1979,7 @@
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim TIM handle
+ * @param htim TIM Input Capture handle
* @param Channel TIM Channels to be disabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
@@ -1708,7 +1987,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -1720,32 +1999,32 @@
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Input Capture channel */
@@ -1770,20 +2049,22 @@
* @param pData The destination Buffer address.
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((pData == 0U ) && (Length > 0U))
+ if ((pData == NULL) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1792,82 +2073,102 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Enable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1883,7 +2184,7 @@
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -1896,32 +2197,36 @@
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
/* Disable the TIM Capture/Compare 4 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Disable the Input Capture channel */
@@ -1940,41 +2245,45 @@
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- * @brief Time One Pulse functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
+ * @brief TIM One Pulse functions
+ *
+@verbatim
==============================================================================
- ##### Time One Pulse functions #####
+ ##### TIM One Pulse functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM One Pulse.
(+) De-initialize the TIM One Pulse.
- (+) Start the Time One Pulse.
- (+) Stop the Time One Pulse.
- (+) Start the Time One Pulse and enable interrupt.
- (+) Stop the Time One Pulse and disable interrupt.
- (+) Start the Time One Pulse and enable DMA transfer.
- (+) Stop the Time One Pulse and disable DMA transfer.
+ (+) Start the TIM One Pulse.
+ (+) Stop the TIM One Pulse.
+ (+) Start the TIM One Pulse and enable interrupt.
+ (+) Stop the TIM One Pulse and disable interrupt.
+ (+) Start the TIM One Pulse and enable DMA transfer.
+ (+) Stop the TIM One Pulse and disable DMA transfer.
@endverbatim
* @{
*/
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
- * parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim TIM OnePulse handle
+ * parameters in the TIM_HandleTypeDef and initializes the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
+ * @param htim TIM One Pulse handle
* @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
- * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
+ * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
{
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
@@ -1986,17 +2295,29 @@
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->OnePulse_MspInitCallback == NULL)
+ {
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OnePulse_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Configure the Time base in the One Pulse Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -2008,13 +2329,13 @@
htim->Instance->CR1 |= OnePulseMode;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM One Pulse
+ * @brief DeInitializes the TIM One Pulse
* @param htim TIM One Pulse handle
* @retval HAL status
*/
@@ -2028,8 +2349,17 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->OnePulse_MspDeInitCallback == NULL)
+ {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_OnePulse_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2042,7 +2372,7 @@
/**
* @brief Initializes the TIM One Pulse MSP.
- * @param htim TIM handle
+ * @param htim TIM One Pulse handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
@@ -2050,14 +2380,14 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM One Pulse MSP.
- * @param htim TIM handle
+ * @param htim TIM One Pulse handle
* @retval None
*/
__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2065,7 +2395,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
*/
}
@@ -2078,22 +2408,25 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
- /* Enable the Capture compare and the Input Capture channels
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
- No need to enable the counter, it's enabled automatically by hardware
+ No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -2111,21 +2444,24 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
- /* Disable the Capture compare and the Input Capture channels
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
@@ -2144,16 +2480,19 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
- /* Enable the Capture compare and the Input Capture channels
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
+ /* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
- in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
- No need to enable the counter, it's enabled automatically by hardware
+ No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
/* Enable the TIM Capture/Compare 1 interrupt */
@@ -2165,7 +2504,7 @@
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
@@ -2183,31 +2522,34 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
- /* Disable the Capture compare and the Input Capture channels
+ /* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
- if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
+ if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
{
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
}
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ __HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
@@ -2217,74 +2559,93 @@
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- * @brief Time Encoder functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
+ * @brief TIM Encoder functions
+ *
+@verbatim
==============================================================================
- ##### Time Encoder functions #####
+ ##### TIM Encoder functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the TIM Encoder.
(+) De-initialize the TIM Encoder.
- (+) Start the Time Encoder.
- (+) Stop the Time Encoder.
- (+) Start the Time Encoder and enable interrupt.
- (+) Stop the Time Encoder and disable interrupt.
- (+) Start the Time Encoder and enable DMA transfer.
- (+) Stop the Time Encoder and disable DMA transfer.
+ (+) Start the TIM Encoder.
+ (+) Stop the TIM Encoder.
+ (+) Start the TIM Encoder and enable interrupt.
+ (+) Stop the TIM Encoder and disable interrupt.
+ (+) Start the TIM Encoder and enable DMA transfer.
+ (+) Stop the TIM Encoder and disable DMA transfer.
@endverbatim
* @{
*/
/**
- * @brief Initializes the TIM Encoder Interface and create the associated handle.
+ * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
+ * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+ * requires a timer reset to avoid unexpected direction
+ * due to DIR bit readonly in center aligned mode.
+ * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
+ * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
+ * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
+ * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
* @param htim TIM Encoder Interface handle
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy weak callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->Encoder_MspInitCallback == NULL)
+ {
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
- /* Reset the SMS bits */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ /* Reset the SMS and ECE bits */
+ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -2305,7 +2666,7 @@
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
+ /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
@@ -2326,15 +2687,15 @@
htim->Instance->CCER = tmpccer;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM Encoder interface
- * @param htim TIM Encoder handle
+ * @brief DeInitializes the TIM Encoder interface
+ * @param htim TIM Encoder Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
@@ -2347,8 +2708,17 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->Encoder_MspDeInitCallback == NULL)
+ {
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Encoder_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Encoder_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2361,7 +2731,7 @@
/**
* @brief Initializes the TIM Encoder Interface MSP.
- * @param htim TIM handle
+ * @param htim TIM Encoder Interface handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
@@ -2369,14 +2739,14 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim TIM handle
+ * @param htim TIM Encoder Interface handle
* @retval None
*/
__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
@@ -2384,7 +2754,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
*/
}
@@ -2398,7 +2768,7 @@
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -2408,20 +2778,22 @@
switch (Channel)
{
case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
break;
- }
+ }
+
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
break;
- }
+ }
+
default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- break;
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
}
/* Enable the Peripheral */
@@ -2440,31 +2812,33 @@
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- /* Disable the Input Capture channels 1 and 2
+ /* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
switch (Channel)
{
case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
break;
- }
+ }
+
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
break;
- }
+ }
+
default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
- break;
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
+ break;
}
}
@@ -2484,7 +2858,7 @@
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -2495,24 +2869,26 @@
switch (Channel)
{
case TIM_CHANNEL_1:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
break;
- }
+ }
+
case TIM_CHANNEL_2:
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
break;
- }
+ }
+
default :
- {
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
- break;
+ {
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
}
@@ -2532,7 +2908,7 @@
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -2540,19 +2916,19 @@
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
+ if (Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 1 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
}
- else if(Channel == TIM_CHANNEL_2)
+ else if (Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare Interrupts 2 */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
}
else
{
@@ -2586,19 +2962,20 @@
* @param pData2 The destination Buffer address for IC2.
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
+ */
+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
+ uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
+ if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -2607,20 +2984,27 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
@@ -2629,19 +3013,22 @@
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
@@ -2650,30 +3037,37 @@
/* Enable the Capture compare channel */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ break;
}
- break;
case TIM_CHANNEL_ALL:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
- /* Enable the Peripheral */
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ /* Enable the Peripheral */
__HAL_TIM_ENABLE(htim);
/* Enable the Capture compare channel */
@@ -2684,11 +3078,11 @@
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the TIM Input Capture DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
default:
- break;
+ break;
}
/* Return function status */
return HAL_OK;
@@ -2703,7 +3097,7 @@
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
@@ -2711,19 +3105,21 @@
/* Disable the Input Capture channels 1 and 2
(in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
- if(Channel == TIM_CHANNEL_1)
+ if (Channel == TIM_CHANNEL_1)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 1 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
}
- else if(Channel == TIM_CHANNEL_2)
+ else if (Channel == TIM_CHANNEL_2)
{
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
/* Disable the capture compare DMA Request 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
}
else
{
@@ -2733,6 +3129,8 @@
/* Disable the capture compare DMA Request 1 and 2 */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
}
/* Disable the Peripheral */
@@ -2748,10 +3146,10 @@
/**
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- * @brief IRQ handler management
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
+ * @brief TIM IRQ handler management
+ *
+@verbatim
==============================================================================
##### IRQ handler management #####
==============================================================================
@@ -2769,126 +3167,178 @@
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
/* Capture compare 1 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
}
/* Capture compare 2 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 3 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* Capture compare 4 event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
}
/* TIM Update event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
- if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
{
- if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
+ if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
- HAL_TIMEx_CommutationCallback(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
@@ -2897,10 +3347,10 @@
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
+ * @brief TIM Peripheral Control functions
+ *
+@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
@@ -2921,22 +3371,24 @@
* parameters in the TIM_OC_InitTypeDef.
* @param htim TIM Output Compare handle
* @param sConfig TIM Output Compare configuration structure
- * @param Channel TIM Channels to be enabled
+ * @param Channel TIM Channels to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
- /* Check input state */
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -2945,39 +3397,48 @@
{
case TIM_CHANNEL_1:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
case TIM_CHANNEL_4:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- /* Configure the TIM Channel 4 in Output Compare */
- TIM_OC4_SetConfig(htim->Instance, sConfig);
+
+ /* Configure the TIM Channel 4 in Output Compare */
+ TIM_OC4_SetConfig(htim->Instance, sConfig);
+ break;
}
- break;
default:
- break;
+ break;
}
+
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
@@ -2990,15 +3451,15 @@
* parameters in the TIM_IC_InitTypeDef.
* @param htim TIM IC handle
* @param sConfig TIM Input Capture configuration structure
- * @param Channel TIM Channels to be enabled
+ * @param Channel TIM Channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -3007,6 +3468,7 @@
assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
+ /* Process Locked */
__HAL_LOCK(htim);
htim->State = HAL_TIM_STATE_BUSY;
@@ -3015,9 +3477,9 @@
{
/* TI1 Configuration */
TIM_TI1_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC1PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
@@ -3047,9 +3509,9 @@
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
TIM_TI3_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC3PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
@@ -3063,9 +3525,9 @@
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
TIM_TI4_SetConfig(htim->Instance,
- sConfig->ICPolarity,
- sConfig->ICSelection,
- sConfig->ICFilter);
+ sConfig->ICPolarity,
+ sConfig->ICSelection,
+ sConfig->ICFilter);
/* Reset the IC4PSC Bits */
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
@@ -3084,9 +3546,9 @@
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim TIM handle
+ * @param htim TIM PWM handle
* @param sConfig TIM PWM configuration structure
- * @param Channel TIM Channels to be enabled
+ * @param Channel TIM Channels to be configured
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3094,23 +3556,28 @@
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
+ TIM_OC_InitTypeDef *sConfig,
+ uint32_t Channel)
{
- __HAL_LOCK(htim);
-
/* Check the parameters */
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
+ /* Process Locked */
+ __HAL_LOCK(htim);
+
htim->State = HAL_TIM_STATE_BUSY;
switch (Channel)
{
case TIM_CHANNEL_1:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
@@ -3120,12 +3587,14 @@
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ break;
}
- break;
case TIM_CHANNEL_2:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
@@ -3135,41 +3604,45 @@
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ break;
}
- break;
case TIM_CHANNEL_3:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
+
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- /* Configure the Output Fast mode */
+ /* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ break;
}
- break;
case TIM_CHANNEL_4:
{
+ /* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
+
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- /* Configure the Output Fast mode */
+ /* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ break;
}
- break;
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -3184,17 +3657,22 @@
* parameters in the TIM_OnePulse_InitTypeDef.
* @param htim TIM One Pulse handle
* @param sConfig TIM One Pulse configuration structure
- * @param OutputChannel TIM Channels to be enabled
+ * @param OutputChannel TIM output channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel TIM Channels to be enabled
+ * @param InputChannel TIM input Channel to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
+ uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
@@ -3202,90 +3680,92 @@
assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
- if(OutputChannel != InputChannel)
+ if (OutputChannel != InputChannel)
{
- __HAL_LOCK(htim);
+ /* Process Locked */
+ __HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
- /* Extract the Ouput compare configuration from sConfig structure */
- temp1.OCMode = sConfig->OCMode;
- temp1.Pulse = sConfig->Pulse;
- temp1.OCPolarity = sConfig->OCPolarity;
- temp1.OCNPolarity = sConfig->OCNPolarity;
- temp1.OCIdleState = sConfig->OCIdleState;
- temp1.OCNIdleState = sConfig->OCNIdleState;
+ /* Extract the Output compare configuration from sConfig structure */
+ temp1.OCMode = sConfig->OCMode;
+ temp1.Pulse = sConfig->Pulse;
+ temp1.OCPolarity = sConfig->OCPolarity;
+ temp1.OCNPolarity = sConfig->OCNPolarity;
+ temp1.OCIdleState = sConfig->OCIdleState;
+ temp1.OCNIdleState = sConfig->OCNIdleState;
switch (OutputChannel)
- {
- case TIM_CHANNEL_1:
{
+ case TIM_CHANNEL_1:
+ {
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- TIM_OC1_SetConfig(htim->Instance, &temp1);
- }
- break;
- case TIM_CHANNEL_2:
- {
+ TIM_OC1_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- TIM_OC2_SetConfig(htim->Instance, &temp1);
+ TIM_OC2_SetConfig(htim->Instance, &temp1);
+ break;
+ }
+ default:
+ break;
}
- break;
- default:
- break;
- }
- switch (InputChannel)
- {
- case TIM_CHANNEL_1:
+
+ switch (InputChannel)
{
- assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+ case TIM_CHANNEL_1:
+ {
+ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
- TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
- /* Reset the IC1PSC Bits */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+ /* Reset the IC1PSC Bits */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
- /* Select the Trigger source */
+ /* Select the Trigger source */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI1FP1;
+ htim->Instance->SMCR |= TIM_TS_TI1FP1;
- /* Select the Slave Mode */
+ /* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
- }
- break;
- case TIM_CHANNEL_2:
- {
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+ case TIM_CHANNEL_2:
+ {
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
- sConfig->ICSelection, sConfig->ICFilter);
+ TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+ sConfig->ICSelection, sConfig->ICFilter);
- /* Reset the IC2PSC Bits */
+ /* Reset the IC2PSC Bits */
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
- /* Select the Trigger source */
+ /* Select the Trigger source */
htim->Instance->SMCR &= ~TIM_SMCR_TS;
- htim->Instance->SMCR |= TIM_TS_TI2FP2;
+ htim->Instance->SMCR |= TIM_TS_TI2FP2;
- /* Select the Slave Mode */
+ /* Select the Slave Mode */
htim->Instance->SMCR &= ~TIM_SMCR_SMS;
- htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+ break;
+ }
+
+ default:
+ break;
}
- break;
- default:
- break;
+ htim->State = HAL_TIM_STATE_READY;
+
+ __HAL_UNLOCK(htim);
+
+ return HAL_OK;
}
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
else
{
return HAL_ERROR;
@@ -3293,11 +3773,11 @@
}
/**
- * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
+ * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
* @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
* This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
* @arg TIM_DMABASE_SMCR
* @arg TIM_DMABASE_DIER
@@ -3306,16 +3786,15 @@
* @arg TIM_DMABASE_CCMR1
* @arg TIM_DMABASE_CCMR2
* @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
* @arg TIM_DMABASE_ARR
* @arg TIM_DMABASE_RCR
* @arg TIM_DMABASE_CCR1
* @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3328,12 +3807,14 @@
* @param BurstBuffer The Buffer address.
* @param BurstLength DMA Burst length. This parameter can be one value
* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
-return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
+ return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
}
/**
@@ -3359,7 +3840,6 @@
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3376,8 +3856,9 @@
* between 1 and 0xFFFF.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -3386,13 +3867,13 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((BurstBuffer == 0U ) && (BurstLength > 0U))
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3401,215 +3882,214 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
- switch(BurstRequestSrc)
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ /* Set the DMA compare callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_COM:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA commutation callbacks */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA trigger callbacks */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
default:
- break;
+ break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
- /* Enable the TIM DMA Request */
- __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Enable the TIM DMA Request */
+ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the TIM DMA Burst mode
+ * @brief Stops the TIM DMA Burst mode
* @param htim TIM handle
* @param BurstRequestSrc TIM DMA Request sources to disable
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
/* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
}
- break;
case TIM_DMA_CC1:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_DMA_CC2:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_DMA_CC3:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_DMA_CC4:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
case TIM_DMA_COM:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
}
- break;
default:
- break;
+ break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
- * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
* @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
- * This parameter can be one of the following values:
- * @arg TIM_DMABASE_CR1
- * @arg TIM_DMABASE_CR2
- * @arg TIM_DMABASE_SMCR
- * @arg TIM_DMABASE_DIER
- * @arg TIM_DMABASE_SR
- * @arg TIM_DMABASE_EGR
- * @arg TIM_DMABASE_CCMR1
- * @arg TIM_DMABASE_CCMR2
- * @arg TIM_DMABASE_CCER
- * @arg TIM_DMABASE_CNT
- * @arg TIM_DMABASE_PSC
- * @arg TIM_DMABASE_ARR
- * @arg TIM_DMABASE_RCR
- * @arg TIM_DMABASE_CCR1
- * @arg TIM_DMABASE_CCR2
- * @arg TIM_DMABASE_CCR3
- * @arg TIM_DMABASE_CCR4
- * @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc TIM DMA Request sources
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer The Buffer address.
- * @param BurstLength DMA Burst length. This parameter can be one value
- * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
-{
-return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
-}
-
-/**
- * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
- * @param htim TIM handle
- * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
* This parameter can be one of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
@@ -3629,7 +4109,51 @@
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
- * @arg TIM_DMABASE_DCR
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @note This function should be used only when BurstLength is equal to DMA data transfer length.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -3646,8 +4170,9 @@
* between 1 and 0xFFFF.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -3656,13 +4181,13 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if((BurstBuffer == 0U ) && (BurstLength > 0U))
+ if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3671,98 +4196,137 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
- switch(BurstRequestSrc)
+ else
+ {
+ /* nothing to do */
+ }
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA Period elapsed callbacks */
htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
+ htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC1:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC2:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC3:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_CC4:
{
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ /* Set the DMA capture callbacks */
+ htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_COM:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA commutation callbacks */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA trigger callbacks */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
+ htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ break;
}
- break;
default:
- break;
+ break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = BurstBaseAddress | BurstLength;
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
@@ -3774,63 +4338,67 @@
}
/**
- * @brief Stop the DMA burst reading
+ * @brief Stop the DMA burst reading
* @param htim TIM handle
* @param BurstRequestSrc TIM DMA Request sources to disable.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
/* Abort the DMA transfer (at least disable the DMA channel) */
- switch(BurstRequestSrc)
+ switch (BurstRequestSrc)
{
case TIM_DMA_UPDATE:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ break;
}
- break;
case TIM_DMA_CC1:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_DMA_CC2:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_DMA_CC3:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
case TIM_DMA_CC4:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ break;
}
- break;
case TIM_DMA_COM:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ break;
}
- break;
case TIM_DMA_TRIGGER:
{
- HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ break;
}
- break;
default:
- break;
+ break;
}
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ if (HAL_OK == status)
+ {
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+ }
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -3843,11 +4411,13 @@
* @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
* @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
* @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EVENTSOURCE_COM: Timer COM event source
+ * @arg TIM_EVENTSOURCE_COM: Timer COM event source
* @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
* @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
+ * @note Basic timers can only generate an update event.
+ * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
+ * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances
+ * supporting a break input.
* @retval HAL status
*/
@@ -3887,17 +4457,14 @@
* @arg TIM_CHANNEL_3: TIM Channel 3
* @arg TIM_CHANNEL_4: TIM Channel 4
* @retval HAL status
- */
-__weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+ TIM_ClearInputConfigTypeDef *sClearInputConfig,
+ uint32_t Channel)
{
- uint32_t tmpsmcr = 0;
-
/* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
/* Process Locked */
__HAL_LOCK(htim);
@@ -3908,98 +4475,106 @@
{
case TIM_CLEARINPUTSOURCE_NONE:
{
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
+ /* Clear the OCREF clear selection bit and the the ETR Bits */
+ CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
+ break;
+ }
+ case TIM_CLEARINPUTSOURCE_OCREFCLR:
+ {
/* Clear the OCREF clear selection bit */
- tmpsmcr &= ~TIM_SMCR_OCCS;
-
- /* Clear the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set TIMx_SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
+ CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+ }
break;
case TIM_CLEARINPUTSOURCE_ETR:
{
+ /* Check the parameters */
+ assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
+ assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
+ assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
+
+ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+ if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
+
TIM_ETR_SetConfig(htim->Instance,
sClearInputConfig->ClearInputPrescaler,
sClearInputConfig->ClearInputPolarity,
sClearInputConfig->ClearInputFilter);
/* Set the OCREF clear selection bit */
- htim->Instance->SMCR |= TIM_SMCR_OCCS;
+ SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+ break;
}
- break;
+
default:
- break;
+ break;
}
switch (Channel)
{
case TIM_CHANNEL_1:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
- }
+ /* Enable the OCREF clear feature for Channel 1 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+ }
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 1 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
}
break;
+ }
case TIM_CHANNEL_2:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
- }
+ /* Enable the OCREF clear feature for Channel 2 */
+ SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
}
- break;
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 2 */
+ CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+ }
+ break;
+ }
case TIM_CHANNEL_3:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
- }
+ /* Enable the OCREF clear feature for Channel 3 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
}
- break;
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 3 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+ }
+ break;
+ }
case TIM_CHANNEL_4:
+ {
+ if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
{
- assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
- }
+ /* Enable the OCREF clear feature for Channel 4 */
+ SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
}
- break;
+ else
+ {
+ /* Disable the OCREF clear feature for Channel 4 */
+ CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+ }
+ break;
+ }
default:
- break;
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -4015,10 +4590,10 @@
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
- */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+ */
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
@@ -4036,15 +4611,13 @@
switch (sClockSourceConfig->ClockSource)
{
- case TIM_CLOCKSOURCE_INTERNAL:
+ case TIM_CLOCKSOURCE_INTERNAL:
{
assert_param(IS_TIM_INSTANCE(htim->Instance));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+ break;
}
- break;
- case TIM_CLOCKSOURCE_ETRMODE1:
+ case TIM_CLOCKSOURCE_ETRMODE1:
{
/* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
@@ -4053,24 +4626,22 @@
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
+
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
- /* Reset the SMS and TS Bits */
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+
/* Select the External clock mode1 and the ETRF trigger */
+ tmpsmcr = htim->Instance->SMCR;
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
+ break;
}
- break;
- case TIM_CLOCKSOURCE_ETRMODE2:
+ case TIM_CLOCKSOURCE_ETRMODE2:
{
/* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
@@ -4079,7 +4650,7 @@
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
+
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
sClockSourceConfig->ClockPrescaler,
@@ -4087,10 +4658,10 @@
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
+ break;
}
- break;
- case TIM_CLOCKSOURCE_TI1:
+ case TIM_CLOCKSOURCE_TI1:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
@@ -4098,19 +4669,20 @@
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
+
TIM_TI1_ConfigInputStage(htim->Instance,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
+ break;
}
- break;
- case TIM_CLOCKSOURCE_TI2:
+
+ case TIM_CLOCKSOURCE_TI2:
{
/* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
- /* Check TI2 input conditioning related parameters */
+ /* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
@@ -4118,9 +4690,10 @@
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
+ break;
}
- break;
- case TIM_CLOCKSOURCE_TI1ED:
+
+ case TIM_CLOCKSOURCE_TI1ED:
{
/* Check whether or not the timer instance supports external clock mode 1 */
assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
@@ -4133,43 +4706,23 @@
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
+ break;
}
- break;
- case TIM_CLOCKSOURCE_ITR0:
+
+ case TIM_CLOCKSOURCE_ITR0:
+ case TIM_CLOCKSOURCE_ITR1:
+ case TIM_CLOCKSOURCE_ITR2:
+ case TIM_CLOCKSOURCE_ITR3:
{
- /* Check whether or not the timer instance supports external clock mode 1 */
+ /* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
}
- break;
- case TIM_CLOCKSOURCE_ITR1:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
- }
- break;
- case TIM_CLOCKSOURCE_ITR2:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
- }
- break;
- case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports external clock mode 1 */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
- TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
- }
- break;
-
- default:
- break;
+ default:
+ break;
}
htim->State = HAL_TIM_STATE_READY;
@@ -4192,7 +4745,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
@@ -4204,7 +4757,7 @@
/* Reset the TI1 selection */
tmpcr2 &= ~TIM_CR2_TI1S;
- /* Set the the TI1 selection */
+ /* Set the TI1 selection */
tmpcr2 |= TI1_Selection;
/* Write to TIMxCR2 */
@@ -4218,11 +4771,11 @@
* @param htim TIM handle.
* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -4233,7 +4786,12 @@
htim->State = HAL_TIM_STATE_BUSY;
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
/* Disable Trigger Interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
@@ -4246,21 +4804,21 @@
__HAL_UNLOCK(htim);
return HAL_OK;
- }
+}
/**
* @brief Configures the TIM in Slave mode in interrupt mode
* @param htim TIM handle.
* @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
- * timer input or external trigger input) and the ) and the Slave
- * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
+ * timer input or external trigger input) and the Slave mode
+ * (Disable, Reset, Gated, Trigger, External clock mode 1).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
- {
- /* Check the parameters */
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
+{
+ /* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
@@ -4269,7 +4827,12 @@
htim->State = HAL_TIM_STATE_BUSY;
- TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
+ if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
+ {
+ htim->State = HAL_TIM_STATE_READY;
+ __HAL_UNLOCK(htim);
+ return HAL_ERROR;
+ }
/* Enable Trigger Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
@@ -4289,21 +4852,19 @@
* @param htim TIM handle.
* @param Channel TIM Channels to be enabled
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
- * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
- * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
- * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval Captured value
*/
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
uint32_t tmpreg = 0U;
- __HAL_LOCK(htim);
-
switch (Channel)
{
- case TIM_CHANNEL_1:
+ case TIM_CHANNEL_1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -4313,7 +4874,7 @@
break;
}
- case TIM_CHANNEL_2:
+ case TIM_CHANNEL_2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -4324,7 +4885,7 @@
break;
}
- case TIM_CHANNEL_3:
+ case TIM_CHANNEL_3:
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
@@ -4335,7 +4896,7 @@
break;
}
- case TIM_CHANNEL_4:
+ case TIM_CHANNEL_4:
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
@@ -4346,11 +4907,10 @@
break;
}
- default:
- break;
+ default:
+ break;
}
- __HAL_UNLOCK(htim);
return tmpreg;
}
@@ -4359,26 +4919,26 @@
*/
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- * @brief TIM Callbacks functions
- *
-@verbatim
+ * @brief TIM Callbacks functions
+ *
+@verbatim
==============================================================================
##### TIM Callbacks functions #####
==============================================================================
[..]
This section provides TIM callback functions:
- (+) Timer Period elapsed callback
- (+) Timer Output Compare callback
- (+) Timer Input capture callback
- (+) Timer Trigger callback
- (+) Timer Error callback
+ (+) TIM Period elapsed callback
+ (+) TIM Output Compare callback
+ (+) TIM Input capture callback
+ (+) TIM Trigger callback
+ (+) TIM Error callback
@endverbatim
* @{
*/
/**
- * @brief Period elapsed callback in non blocking mode
+ * @brief Period elapsed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -4387,13 +4947,28 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
*/
-
}
+
/**
- * @brief Output Compare callback in non blocking mode
+ * @brief Period elapsed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
@@ -4402,12 +4977,13 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
+
/**
- * @brief Input Capture callback in non blocking mode
+ * @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
@@ -4416,13 +4992,28 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
/**
- * @brief PWM Pulse finished callback in non blocking mode
+ * @brief Input Capture half complete callback in non-blocking mode
+ * @param htim TIM IC handle
+ * @retval None
+ */
+__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -4431,13 +5022,28 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
/**
- * @brief Hall Trigger detection callback in non blocking mode
+ * @brief PWM Pulse finished half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -4446,13 +5052,28 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
/**
- * @brief Timer error callback in non blocking mode
+ * @brief Hall Trigger detection half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Timer error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -4461,24 +5082,507 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_ErrorCallback could be implemented in the user file
*/
}
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
+ pTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a TIM callback
+ * TIM callback is redirected to the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if (htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ break;
+
+ case HAL_TIM_TRIGGER_HALF_CB_ID :
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ break;
+
+ case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_HALF_CB_ID :
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
+ * @brief TIM Peripheral State functions
+ *
+@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -4486,7 +5590,7 @@
*/
/**
- * @brief Return the TIM Base state
+ * @brief Return the TIM Base handle state.
* @param htim TIM Base handle
* @retval HAL state
*/
@@ -4496,8 +5600,8 @@
}
/**
- * @brief Return the TIM OC state
- * @param htim TIM Ouput Compare handle
+ * @brief Return the TIM OC handle state.
+ * @param htim TIM Output Compare handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
@@ -4506,7 +5610,7 @@
}
/**
- * @brief Return the TIM PWM state
+ * @brief Return the TIM PWM handle state.
* @param htim TIM handle
* @retval HAL state
*/
@@ -4516,7 +5620,7 @@
}
/**
- * @brief Return the TIM Input Capture state
+ * @brief Return the TIM Input Capture handle state.
* @param htim TIM IC handle
* @retval HAL state
*/
@@ -4526,7 +5630,7 @@
}
/**
- * @brief Return the TIM One Pulse Mode state
+ * @brief Return the TIM One Pulse Mode handle state.
* @param htim TIM OPM handle
* @retval HAL state
*/
@@ -4536,8 +5640,8 @@
}
/**
- * @brief Return the TIM Encoder Mode state
- * @param htim TIM Encoder handle
+ * @brief Return the TIM Encoder Mode handle state.
+ * @param htim TIM Encoder Interface handle
* @retval HAL state
*/
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
@@ -4553,22 +5657,26 @@
* @}
*/
-/** @addtogroup TIM_Private_Functions TIM_Private_Functions
+/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
/**
- * @brief TIM DMA error callback
+ * @brief TIM DMA error callback
* @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMAError(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
@@ -4578,9 +5686,9 @@
*/
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
@@ -4598,11 +5706,61 @@
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
+ else
+ {
+ /* nothing to do */
+ }
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
+
+/**
+ * @brief TIM DMA Delay Pulse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
/**
* @brief TIM DMA Capture complete callback.
* @param hdma pointer to DMA handle.
@@ -4610,9 +5768,9 @@
*/
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
@@ -4630,8 +5788,57 @@
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
+ else
+ {
+ /* nothing to do */
+ }
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+}
+
+/**
+ * @brief TIM DMA Capture half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+ if (hdma == htim->hdma[TIM_DMA_ID_CC1])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ }
+ else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
+ {
+ htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ }
+ else
+ {
+ /* nothing to do */
+ }
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureHalfCpltCallback(htim);
+#else
+ HAL_TIM_IC_CaptureHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
@@ -4643,11 +5850,33 @@
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Period Elapse half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedHalfCpltCallback(htim);
+#else
+ HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
@@ -4657,22 +5886,44 @@
*/
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Trigger half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerHalfCpltCallback(htim);
+#else
+ HAL_TIM_TriggerHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
* @brief Time Base configuration
- * @param TIMx TIM periheral
+ * @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- uint32_t tmpcr1 = 0U;
+ uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
/* Set TIM Time Base Unit parameters ---------------------------------------*/
@@ -4683,7 +5934,7 @@
tmpcr1 |= Structure->CounterMode;
}
- if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
@@ -4699,7 +5950,7 @@
TIMx->ARR = (uint32_t)Structure->Period ;
/* Set the Prescaler value */
- TIMx->PSC = (uint32_t)Structure->Prescaler;
+ TIMx->PSC = Structure->Prescaler;
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
{
@@ -4707,24 +5958,24 @@
TIMx->RCR = Structure->RepetitionCounter;
}
- /* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
}
/**
- * @brief Time Ouput Compare 1 configuration
+ * @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
- /* Disable the Channel 1: Reset the CC1E Bit */
+ /* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
/* Get the TIMx CCER register value */
@@ -4746,7 +5997,7 @@
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
@@ -4759,7 +6010,7 @@
tmpccer &= ~TIM_CCER_CC1NE;
}
- if(IS_TIM_BREAK_INSTANCE(TIMx))
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
@@ -4773,6 +6024,7 @@
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
}
+
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
@@ -4787,16 +6039,16 @@
}
/**
- * @brief Time Ouput Compare 2 configuration
- * @param TIMx to select the TIM peripheral
+ * @brief Timer Output Compare 2 configuration
+ * @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -4821,7 +6073,7 @@
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
@@ -4834,7 +6086,7 @@
}
- if(IS_TIM_BREAK_INSTANCE(TIMx))
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
@@ -4863,16 +6115,16 @@
}
/**
- * @brief Time Ouput Compare 3 configuration
- * @param TIMx to select the TIM peripheral
+ * @brief Timer Output Compare 3 configuration
+ * @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -4896,7 +6148,7 @@
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
- if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
+ if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
@@ -4908,7 +6160,7 @@
tmpccer &= ~TIM_CCER_CC3NE;
}
- if(IS_TIM_BREAK_INSTANCE(TIMx))
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
{
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
@@ -4937,16 +6189,16 @@
}
/**
- * @brief Time Ouput Compare 4 configuration
- * @param TIMx to select the TIM peripheral
+ * @brief Timer Output Compare 4 configuration
+ * @param TIMx to select the TIM peripheral
* @param OC_Config The ouput configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmrx;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -4971,12 +6223,14 @@
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
- if(IS_TIM_BREAK_INSTANCE(TIMx))
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
{
+ /* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
- /* Reset the Output Compare IDLE State */
+ /* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
+
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
}
@@ -4994,12 +6248,18 @@
TIMx->CCER = tmpccer;
}
-static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
- TIM_SlaveConfigTypeDef * sSlaveConfig)
+/**
+ * @brief Slave Timer configuration function
+ * @param htim TIM handle
+ * @param sSlaveConfig Slave timer configuration
+ * @retval None
+ */
+static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
+ TIM_SlaveConfigTypeDef *sSlaveConfig)
{
- uint32_t tmpsmcr = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
@@ -5020,7 +6280,7 @@
/* Configure the trigger prescaler, filter, and polarity */
switch (sSlaveConfig->InputTrigger)
{
- case TIM_TS_ETRF:
+ case TIM_TS_ETRF:
{
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
@@ -5032,15 +6292,20 @@
sSlaveConfig->TriggerPrescaler,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_TI1F_ED:
+ case TIM_TS_TI1F_ED:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
+ if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ {
+ return HAL_ERROR;
+ }
+
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = htim->Instance->CCER;
htim->Instance->CCER &= ~TIM_CCER_CC1E;
@@ -5053,11 +6318,10 @@
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;
htim->Instance->CCER = tmpccer;
-
+ break;
}
- break;
- case TIM_TS_TI1FP1:
+ case TIM_TS_TI1FP1:
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
@@ -5068,10 +6332,10 @@
TIM_TI1_ConfigInputStage(htim->Instance,
sSlaveConfig->TriggerPolarity,
sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_TI2FP2:
+ case TIM_TS_TI2FP2:
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -5080,69 +6344,52 @@
/* Configure TI2 Filter and Polarity */
TIM_TI2_ConfigInputStage(htim->Instance,
- sSlaveConfig->TriggerPolarity,
- sSlaveConfig->TriggerFilter);
+ sSlaveConfig->TriggerPolarity,
+ sSlaveConfig->TriggerFilter);
+ break;
}
- break;
- case TIM_TS_ITR0:
+ case TIM_TS_ITR0:
+ case TIM_TS_ITR1:
+ case TIM_TS_ITR2:
+ case TIM_TS_ITR3:
{
/* Check the parameter */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
}
- break;
- case TIM_TS_ITR1:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR2:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- }
- break;
-
- default:
- break;
+ default:
+ break;
}
+ return HAL_OK;
}
/**
* @brief Configure the TI1 as Input.
- * @param TIMx to select the TIM peripheral.
+ * @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_TRC : TIM Input 1 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
- * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
+ * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
* protected against un-initialized filter and polarity values.
*/
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -5150,7 +6397,7 @@
tmpccer = TIMx->CCER;
/* Select the Input */
- if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
+ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
{
tmpccmr1 &= ~TIM_CCMR1_CC1S;
tmpccmr1 |= TIM_ICSelection;
@@ -5175,7 +6422,7 @@
/**
* @brief Configure the Polarity and Filter for TI1.
- * @param TIMx to select the TIM peripheral.
+ * @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
@@ -5187,8 +6434,8 @@
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
@@ -5210,29 +6457,29 @@
/**
* @brief Configure the TI2 as Input.
- * @param TIMx to select the TIM peripheral
+ * @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSELECTION_TRC : TIM Input 2 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
- * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
+ * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5258,7 +6505,7 @@
/**
* @brief Configure the Polarity and Filter for TI2.
- * @param TIMx to select the TIM peripheral.
+ * @param TIMx to select the TIM peripheral.
* @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
@@ -5270,8 +6517,8 @@
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5293,29 +6540,29 @@
/**
* @brief Configure the TI3 as Input.
- * @param TIMx to select the TIM peripheral
+ * @param TIMx to select the TIM peripheral
* @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_TRC : TIM Input 3 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -5346,24 +6593,24 @@
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
- * @arg TIM_ICSELECTION_DIRECTTI : TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSELECTION_INDIRECTTI : TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSELECTION_TRC : TIM Input 4 is selected to be connected to TRC.
+ * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
+ * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
+ * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
- * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
- * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
+ * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
+ * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
* protected against un-initialized filter and polarity values.
* @retval None
*/
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
- uint32_t TIM_ICFilter)
+ uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -5389,53 +6636,53 @@
/**
* @brief Selects the Input Trigger source
- * @param TIMx to select the TIM peripheral
+ * @param TIMx to select the TIM peripheral
* @param InputTriggerSource The Input Trigger source.
* This parameter can be one of the following values:
- * @arg TIM_TS_ITR0 : Internal Trigger 0
- * @arg TIM_TS_ITR1 : Internal Trigger 1
- * @arg TIM_TS_ITR2 : Internal Trigger 2
- * @arg TIM_TS_ITR3 : Internal Trigger 3
- * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
- * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
- * @arg TIM_TS_ETRF : External Trigger input
+ * @arg TIM_TS_ITR0: Internal Trigger 0
+ * @arg TIM_TS_ITR1: Internal Trigger 1
+ * @arg TIM_TS_ITR2: Internal Trigger 2
+ * @arg TIM_TS_ITR3: Internal Trigger 3
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+ * @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
+static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpsmcr;
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= ~TIM_SMCR_TS;
- /* Set the Input Trigger source and the slave mode*/
- tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = TIMx->SMCR;
+ /* Reset the TS Bits */
+ tmpsmcr &= ~TIM_SMCR_TS;
+ /* Set the Input Trigger source and the slave mode*/
+ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ /* Write to TIMx SMCR */
+ TIMx->SMCR = tmpsmcr;
}
/**
* @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx to select the TIM peripheral
+ * @param TIMx to select the TIM peripheral
* @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
* This parameter can be one of the following values:
- * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
- * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
- * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
- * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
+ * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
+ * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
+ * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
+ * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
* @param TIM_ExtTRGPolarity The external Trigger Polarity.
* This parameter can be one of the following values:
- * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
- * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
+ * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
+ * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
* @param ExtTRGFilter External Trigger Filter.
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
-void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
@@ -5451,34 +6698,59 @@
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx to select the TIM peripheral
+ * @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1 : TIM Channel 1
- * @arg TIM_CHANNEL_2 : TIM Channel 2
- * @arg TIM_CHANNEL_3 : TIM Channel 3
- * @arg TIM_CHANNEL_4 : TIM Channel 4
+ * @arg TIM_CHANNEL_1: TIM Channel 1
+ * @arg TIM_CHANNEL_2: TIM Channel 2
+ * @arg TIM_CHANNEL_3: TIM Channel 3
+ * @arg TIM_CHANNEL_4: TIM Channel 4
* @param ChannelState specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
+ * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
- uint32_t tmp = 0U;
+ uint32_t tmp;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
- tmp = TIM_CCER_CC1E << Channel;
+ tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy weak callbacks.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+ /* Reset the TIM callback to the legacy weak callbacks */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
+ htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
+ htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
+ htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
+ htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
+ htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
+ htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
diff --git a/Src/stm32f0xx_hal_tim_ex.c b/Src/stm32f0xx_hal_tim_ex.c
index 9bf2c75..02eafb1 100644
--- a/Src/stm32f0xx_hal_tim_ex.c
+++ b/Src/stm32f0xx_hal_tim_ex.c
@@ -3,12 +3,13 @@
* @file stm32f0xx_hal_tim_ex.c
* @author MCD Application Team
* @brief TIM HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
* + Time Hall Sensor Interface Initialization
* + Time Hall Sensor Interface Start
- * + Time Complementary signal bread and dead time configuration
+ * + Time Complementary signal break and dead time configuration
* + Time Master and Slave synchronization configuration
+ * + Time OCRef clear configuration
* + Timer remapping capabilities configuration
@verbatim
==============================================================================
@@ -20,21 +21,18 @@
(++) Output Compare
(++) PWM generation (Edge and Center-aligned Mode)
(++) One-pulse mode output
- (#) Synchronization circuit to control the timer with external signals and to
+ (#) Synchronization circuit to control the timer with external signals and to
interconnect several timers together.
(#) Break input to put the timer output signals in reset state or in a known state.
- (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
+ (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
positioning purposes
##### How to use this driver #####
==============================================================================
[..]
- (#) Initialize the TIM low level resources by implementing the following functions
- depending from feature used :
- (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
- (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
- (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
- (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
+ (#) Initialize the TIM low level resources by implementing the following functions
+ depending on the selected feature:
+ (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
(#) Initialize the TIM low level resources :
(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
@@ -43,56 +41,39 @@
__HAL_RCC_GPIOx_CLK_ENABLE();
(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
- (#) The external Clock can be configured, if needed (the default clock is the
+ (#) The external Clock can be configured, if needed (the default clock is the
internal clock from the APBx), using the following function:
- HAL_TIM_ConfigClockSource, the clock configuration should be done before
+ HAL_TIM_ConfigClockSource, the clock configuration should be done before
any start function.
- (#) Configure the TIM in the desired functioning mode using one of the
+ (#) Configure the TIM in the desired functioning mode using one of the
initialization function of this driver:
- (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
- Timer Hall Sensor Interface and the commutation event with the corresponding
- Interrupt and DMA request if needed (Note that One Timer is used to interface
- with the Hall sensor Interface and another Timer should be used to use
- the commutation event).
+ (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the
+ Timer Hall Sensor Interface and the commutation event with the corresponding
+ Interrupt and DMA request if needed (Note that One Timer is used to interface
+ with the Hall sensor Interface and another Timer should be used to use
+ the commutation event).
(#) Activate the TIM peripheral using one of the start functions:
- (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
+ (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
-
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
-*/
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
@@ -113,25 +94,17 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
- * @{
- */
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
-/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
- * @brief Timer Hall Sensor functions
- *
-@verbatim
+/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
+ * @brief Timer Hall Sensor functions
+ *
+@verbatim
==============================================================================
##### Timer Hall Sensor functions #####
==============================================================================
@@ -150,40 +123,53 @@
* @{
*/
/**
- * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim TIM Encoder Interface handle
+ * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle.
+ * @param htim TIM Hall Sensor Interface handle
* @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
{
TIM_OC_InitTypeDef OC_Config;
/* Check the TIM handle allocation */
- if(htim == NULL)
+ if (htim == NULL)
{
return HAL_ERROR;
}
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
- assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
- if(htim->State == HAL_TIM_STATE_RESET)
+ if (htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if (htim->HallSensor_MspInitCallback == NULL)
+ {
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->HallSensor_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
- htim->State= HAL_TIM_STATE_BUSY;
+ htim->State = HAL_TIM_STATE_BUSY;
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -224,14 +210,14 @@
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
/* Initialize the TIM state*/
- htim->State= HAL_TIM_STATE_READY;
+ htim->State = HAL_TIM_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the TIM Hall Sensor interface
- * @param htim TIM Hall Sensor handle
+ * @brief DeInitializes the TIM Hall Sensor interface
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
@@ -244,8 +230,17 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if (htim->HallSensor_MspDeInitCallback == NULL)
+ {
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->HallSensor_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIMEx_HallSensor_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -258,7 +253,7 @@
/**
* @brief Initializes the TIM Hall Sensor MSP.
- * @param htim TIM handle
+ * @param htim TIM Hall Sensor Interface handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
@@ -266,14 +261,14 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim TIM handle
+ * @param htim TIM Hall Sensor Interface handle
* @retval None
*/
__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
@@ -281,27 +276,33 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
*/
}
/**
* @brief Starts the TIM Hall Sensor Interface.
- * @param htim TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -309,13 +310,13 @@
/**
* @brief Stops the TIM Hall sensor Interface.
- * @param htim TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channels 1, 2 and 3
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
@@ -330,13 +331,15 @@
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Enable the capture compare Interrupts 1 event */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -345,8 +348,12 @@
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -354,13 +361,13 @@
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim TIM handle
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
@@ -378,23 +385,25 @@
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM Hall Sensor handle
+ * @param htim TIM Hall Sensor Interface handle
* @param pData The destination Buffer address.
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
{
- /* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
+ uint32_t tmpsmcr;
- if((htim->State == HAL_TIM_STATE_BUSY))
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
+
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U ) && (Length > 0U))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -403,23 +412,34 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- /* Set the DMA Input Capture 1 Callback */
+ /* Set the DMA Input Capture 1 Callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel for Capture 1*/
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the capture compare 1 Interrupt */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -427,13 +447,13 @@
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim TIM handle
+ * @param htim TIM Hall Sensor Interface handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
{
/* Check the parameters */
- assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
/* Disable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
@@ -443,6 +463,7 @@
/* Disable the capture compare Interrupts 1 event */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -454,10 +475,10 @@
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
- * @brief Timer Complementary Output Compare functions
- *
-@verbatim
+/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ * @brief Timer Complementary Output Compare functions
+ *
+@verbatim
==============================================================================
##### Timer Complementary Output Compare functions #####
==============================================================================
@@ -477,28 +498,33 @@
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim TIM Output Compare handle
+ * @param htim TIM Output Compare handle
* @param Channel TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -513,7 +539,6 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -521,11 +546,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- /* Disable the Capture compare channel N */
+ /* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -535,7 +560,7 @@
}
/**
- * @brief Starts the TIM Output Compare signal generation in interrupt mode
+ * @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
* @param htim TIM OC handle
* @param Channel TIM Channel to be enabled
@@ -543,11 +568,12 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -557,52 +583,50 @@
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Output Compare interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Output Compare interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the TIM Break interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
- /* Enable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ /* Enable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the TIM Output Compare signal generation in interrupt mode
+ * @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
* @param htim TIM Output Compare handle
* @param Channel TIM Channel to be disabled
@@ -610,13 +634,11 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0U;
-
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -626,46 +648,39 @@
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
- /* Disable the Capture compare channel N */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ /* Disable the Capture compare channel N */
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -675,7 +690,7 @@
}
/**
- * @brief Starts the TIM Output Compare signal generation in DMA mode
+ * @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
* @param htim TIM Output Compare handle
* @param Channel TIM Channel to be enabled
@@ -683,23 +698,24 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U ) && (Length > 0U))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -708,91 +724,93 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
+
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
-{
- /* Set the DMA Period elapsed callback */
+ {
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Output Compare DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Output Compare DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the TIM Output Compare signal generation in DMA mode
+ * @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
* @param htim TIM Output Compare handle
* @param Channel TIM Channel to be disabled
@@ -800,7 +818,6 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -814,38 +831,34 @@
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Output Compare DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Output Compare interrupt */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the Capture compare channel N */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -862,10 +875,10 @@
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
- * @brief Timer Complementary PWM functions
- *
-@verbatim
+/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ * @brief Timer Complementary PWM functions
+ *
+@verbatim
==============================================================================
##### Timer Complementary PWM functions #####
==============================================================================
@@ -900,22 +913,27 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -929,7 +947,6 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -940,7 +957,7 @@
/* Disable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -951,7 +968,7 @@
}
/**
- * @brief Starts the PWM signal generation in interrupt mode on the
+ * @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
* @param htim TIM handle
* @param Channel TIM Channel to be disabled
@@ -959,11 +976,12 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -973,32 +991,25 @@
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Enable the TIM Capture/Compare 4 interrupt */
- __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the TIM Break interrupt */
@@ -1007,18 +1018,22 @@
/* Enable the complementary PWM output */
TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the PWM signal generation in interrupt mode on the
+ * @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
* @param htim TIM handle
* @param Channel TIM Channel to be disabled
@@ -1026,12 +1041,11 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0U;
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1042,32 +1056,25 @@
{
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 3 interrupt */
- __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the complementary PWM output */
@@ -1075,12 +1082,12 @@
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
+ if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
@@ -1091,7 +1098,7 @@
}
/**
- * @brief Starts the TIM PWM signal generation in DMA mode on the
+ * @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
* @param htim TIM handle
* @param Channel TIM Channel to be enabled
@@ -1099,23 +1106,24 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param pData The source Buffer address.
* @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
- else if((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
- if(((uint32_t)pData == 0U ) && (Length > 0U))
+ if (((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1124,84 +1132,85 @@
htim->State = HAL_TIM_STATE_BUSY;
}
}
+ else
+ {
+ /* nothing to do */
+ }
switch (Channel)
{
case TIM_CHANNEL_1:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
- /* Set the DMA Period elapsed callback */
+ /* Set the DMA compare callbacks */
htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
+ htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Enable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Set the DMA Period elapsed callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
- /* Set the DMA error callback */
- htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
- /* Enable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Enable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
- __HAL_TIM_MOE_ENABLE(htim);
+ /* Enable the Main Output */
+ __HAL_TIM_MOE_ENABLE(htim);
- /* Enable the Peripheral */
- __HAL_TIM_ENABLE(htim);
+ /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
/* Return function status */
return HAL_OK;
@@ -1216,7 +1225,6 @@
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1230,39 +1238,35 @@
{
/* Disable the TIM Capture/Compare 1 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ break;
}
- break;
case TIM_CHANNEL_2:
{
/* Disable the TIM Capture/Compare 2 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ break;
}
- break;
case TIM_CHANNEL_3:
{
/* Disable the TIM Capture/Compare 3 DMA request */
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ break;
}
- break;
-
- case TIM_CHANNEL_4:
- {
- /* Disable the TIM Capture/Compare 4 DMA request */
- __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
- }
- break;
default:
- break;
+ break;
}
/* Disable the complementary PWM output */
- TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -1278,10 +1282,10 @@
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
- * @brief Timer Complementary One Pulse functions
- *
-@verbatim
+/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ * @brief Timer Complementary One Pulse functions
+ *
+@verbatim
==============================================================================
##### Timer Complementary One Pulse functions #####
==============================================================================
@@ -1297,7 +1301,7 @@
*/
/**
- * @brief Starts the TIM One Pulse signal generation on the complemetary
+ * @brief Starts the TIM One Pulse signal generation on the complementary
* output.
* @param htim TIM One Pulse handle
* @param OutputChannel TIM Channel to be enabled
@@ -1307,14 +1311,14 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
- {
+{
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
@@ -1322,7 +1326,7 @@
}
/**
- * @brief Stops the TIM One Pulse signal generation on the complementary
+ * @brief Stops the TIM One Pulse signal generation on the complementary
* output.
* @param htim TIM One Pulse handle
* @param OutputChannel TIM Channel to be disabled
@@ -1338,10 +1342,10 @@
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Disable the complementary One Pulse output */
- TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
+ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
- __HAL_TIM_MOE_DISABLE(htim);
+ /* Disable the Main Output */
+ __HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -1374,12 +1378,12 @@
/* Enable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
- /* Enable the Main Ouput */
+ /* Enable the Main Output */
__HAL_TIM_MOE_ENABLE(htim);
/* Return function status */
return HAL_OK;
- }
+}
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
@@ -1405,11 +1409,11 @@
/* Disable the complementary One Pulse output */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
- /* Disable the Main Ouput */
+ /* Disable the Main Output */
__HAL_TIM_MOE_DISABLE(htim);
/* Disable the Peripheral */
- __HAL_TIM_DISABLE(htim);
+ __HAL_TIM_DISABLE(htim);
/* Return function status */
return HAL_OK;
@@ -1418,16 +1422,19 @@
/**
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
+
+/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure the commutation event in case of use of the Hall sensor interface.
+ (+) Configure Output channels for OC and PWM mode.
+
(+) Configure Complementary channels, break features and dead time.
(+) Configure Master synchronization.
(+) Configure timer remapping capabilities.
@@ -1435,13 +1442,14 @@
@endverbatim
* @{
*/
+
/**
* @brief Configure the TIM commutation event sequence.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @param htim TIM handle
* @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
@@ -1450,14 +1458,15 @@
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
+ * @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1479,6 +1488,12 @@
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -1486,11 +1501,11 @@
/**
* @brief Configure the TIM commutation event sequence with interrupt.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @param htim TIM handle
* @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
@@ -1499,14 +1514,15 @@
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
+ * @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1528,7 +1544,10 @@
htim->Instance->CR2 &= ~TIM_CR2_CCUS;
htim->Instance->CR2 |= CommutationSource;
- /* Enable the Commutation Interrupt Request */
+ /* Disable Commutation DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+ /* Enable the Commutation Interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
__HAL_UNLOCK(htim);
@@ -1538,13 +1557,13 @@
/**
* @brief Configure the TIM commutation event sequence with DMA.
- * @note: this function is mandatory to use the commutation event in order to
+ * @note This function is mandatory to use the commutation event in order to
* update the configuration at each commutation detection on the TRGI input of the Timer,
* the typical use of this feature is with the use of another Timer(interface Timer)
- * configured in Hall sensor interface, this interface Timer will generate the
- * commutation at its TRGO output (connected to Timer used in this function) each time
+ * configured in Hall sensor interface, this interface Timer will generate the
+ * commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
+ * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
* @param htim TIM handle
* @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
* This parameter can be one of the following values:
@@ -1552,14 +1571,15 @@
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_NONE: No trigger is needed
+ * @arg TIM_TS_NONE: No trigger is needed
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
+ uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@@ -1584,9 +1604,13 @@
/* Enable the Commutation DMA Request */
/* Set the DMA Commutation Callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
+ htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
/* Set the DMA error callback */
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
+ /* Disable Commutation Interrupt */
+ __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
/* Enable the Commutation DMA Request */
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
@@ -1599,31 +1623,53 @@
* @brief Configures the TIM in master mode.
* @param htim TIM handle.
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
- * contains the selected trigger output (TRGO) and the Master/Slave
+ * contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
+ TIM_MasterConfigTypeDef *sMasterConfig)
{
+ uint32_t tmpcr2;
+ uint32_t tmpsmcr;
+
/* Check the parameters */
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
+ /* Check input state */
__HAL_LOCK(htim);
+ /* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = htim->Instance->CR2;
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = htim->Instance->SMCR;
+
/* Reset the MMS Bits */
- htim->Instance->CR2 &= ~TIM_CR2_MMS;
+ tmpcr2 &= ~TIM_CR2_MMS;
/* Select the TRGO source */
- htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
+ tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- /* Reset the MSM Bit */
- htim->Instance->SMCR &= ~TIM_SMCR_MSM;
- /* Set or Reset the MSM Bit */
- htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
+ /* Update TIMx CR2 */
+ htim->Instance->CR2 = tmpcr2;
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ /* Reset the MSM Bit */
+ tmpsmcr &= ~TIM_SMCR_MSM;
+ /* Set master mode */
+ tmpsmcr |= sMasterConfig->MasterSlaveMode;
+
+ /* Update TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ }
+
+ /* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
@@ -1632,18 +1678,22 @@
}
/**
- * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
+ * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+ * and the AOE(automatic output enable).
* @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
- */
+ */
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
- uint32_t tmpbdtr = 0;
-
+ /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+ uint32_t tmpbdtr = 0U;
+
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
@@ -1654,14 +1704,12 @@
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
- /* Process Locked */
+ /* Check input state */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
+
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
@@ -1670,12 +1718,10 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
-
+
+
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
-
- htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
@@ -1683,14 +1729,15 @@
}
/**
- * @brief Configures the TIM14 Remapping input capabilities.
+ * @brief Configures the TIMx Remapping input capabilities.
* @param htim TIM handle.
* @param Remap specifies the TIM remapping source.
- * This parameter can be one of the following values:
- * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
- * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
- * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
- * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
+ * For TIM14, the parameter can have the following values:
+ * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
+ * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
+ * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
+ * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
+ *
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
@@ -1698,13 +1745,10 @@
__HAL_LOCK(htim);
/* Check parameters */
- assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
- assert_param(IS_TIM_REMAP(Remap));
+ assert_param(IS_TIM_REMAP(htim->Instance, Remap));
/* Set the Timer remapping configuration */
- htim->Instance->OR = Remap;
-
- htim->State = HAL_TIM_STATE_READY;
+ WRITE_REG(htim->Instance->OR, Remap);
__HAL_UNLOCK(htim);
@@ -1715,170 +1759,15 @@
* @}
*/
-/** @addtogroup TIM_Exported_Functions_Group8
- * @{
- */
-#if defined(STM32F051x8) || defined(STM32F058xx) || \
- defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
- defined(STM32F091xC) || defined (STM32F098xx)
-/**
- * @brief Configures the OCRef clear feature
- * @param htim TIM handle
- * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
- * contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1
- * @arg TIM_CHANNEL_2: TIM Channel 2
- * @arg TIM_CHANNEL_3: TIM Channel 3
- * @arg TIM_CHANNEL_4: TIM Channel 4
- * @arg TIM_Channel_5: TIM Channel 5
- * @retval None
- */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
- TIM_ClearInputConfigTypeDef *sClearInputConfig,
- uint32_t Channel)
-{
- uint32_t tmpsmcr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
- assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-
- /* Check input state */
- __HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
-
- switch (sClearInputConfig->ClearInputSource)
- {
- case TIM_CLEARINPUTSOURCE_NONE:
- {
- /* Get the TIMx SMCR register value */
- tmpsmcr = htim->Instance->SMCR;
-
- /* Clear the OCREF clear selection bit */
- tmpsmcr &= ~TIM_SMCR_OCCS;
-
- /* Clear the ETR Bits */
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-
- /* Set TIMx_SMCR */
- htim->Instance->SMCR = tmpsmcr;
- }
- break;
-
- case TIM_CLEARINPUTSOURCE_OCREFCLR:
- {
- /* Clear the OCREF clear selection bit */
- htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
- }
- break;
-
- case TIM_CLEARINPUTSOURCE_ETR:
- {
- /* Check the parameters */
- assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
- assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
- assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
- TIM_ETR_SetConfig(htim->Instance,
- sClearInputConfig->ClearInputPrescaler,
- sClearInputConfig->ClearInputPolarity,
- sClearInputConfig->ClearInputFilter);
-
- /* Set the OCREF clear selection bit */
- htim->Instance->SMCR |= TIM_SMCR_OCCS;
- }
- break;
- default:
- break;
- }
-
- switch (Channel)
- {
- case TIM_CHANNEL_1:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 1 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
- }
- }
- break;
- case TIM_CHANNEL_2:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 2 */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
- }
- }
- break;
- case TIM_CHANNEL_3:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 3 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
- }
- }
- break;
- case TIM_CHANNEL_4:
- {
- if(sClearInputConfig->ClearInputState != RESET)
- {
- /* Enable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
- }
- else
- {
- /* Disable the Ocref clear feature for Channel 4 */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
- }
- }
- break;
- default:
- break;
- }
-
- htim->State = HAL_TIM_STATE_READY;
-
- __HAL_UNLOCK(htim);
-
- return HAL_OK;
-}
-#endif /* STM32F051x8 || STM32F058xx || */
- /* STM32F071xB || STM32F072xB || STM32F078xx || */
- /* STM32F091xC || STM32F098xx */
-/**
- * @}
- */
-
-/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
- * @brief Extension Callbacks functions
- *
-@verbatim
+/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
+ * @brief Extended Callbacks functions
+ *
+@verbatim
==============================================================================
- ##### Extension Callbacks functions #####
+ ##### Extended Callbacks functions #####
==============================================================================
[..]
- This section provides Extension TIM callback functions:
+ This section provides Extended TIM callback functions:
(+) Timer Commutation callback
(+) Timer Break callback
@@ -1887,22 +1776,36 @@
*/
/**
- * @brief Hall commutation changed callback in non blocking mode
+ * @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
-__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
+__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_TIMEx_CommutationCallback could be implemented in the user file
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutCallback could be implemented in the user file
+ */
+}
+/**
+ * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @param htim TIM handle
+ * @retval None
+ */
+__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(htim);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file
*/
}
/**
- * @brief Hall Break detection callback in non blocking mode
+ * @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -1911,38 +1814,23 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(htim);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
-
-/**
- * @brief TIM DMA Commutation callback.
- * @param hdma pointer to DMA handle.
- * @retval None
- */
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
-{
- TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- htim->State= HAL_TIM_STATE_READY;
-
- HAL_TIMEx_CommutationCallback(htim);
-}
-
/**
* @}
*/
-/** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
- * @brief Extension Peripheral State functions
- *
-@verbatim
+/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
+ * @brief Extended Peripheral State functions
+ *
+@verbatim
==============================================================================
- ##### Extension Peripheral State functions #####
+ ##### Extended Peripheral State functions #####
==============================================================================
[..]
- This subsection permit to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1950,7 +1838,7 @@
*/
/**
- * @brief Return the TIM Hall Sensor interface state
+ * @brief Return the TIM Hall Sensor interface handle state.
* @param htim TIM Hall Sensor handle
* @retval HAL state
*/
@@ -1967,13 +1855,53 @@
* @}
*/
-/** @addtogroup TIMEx_Private_Functions
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
/**
+ * @brief TIM DMA Commutation callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
+ HAL_TIMEx_CommutCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+/**
+ * @brief TIM DMA Commutation half complete callback.
+ * @param hdma pointer to DMA handle.
+ * @retval None
+ */
+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+ /* Change the htim state */
+ htim->State = HAL_TIM_STATE_READY;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationHalfCpltCallback(htim);
+#else
+ HAL_TIMEx_CommutHalfCpltCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+}
+
+
+/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx to select the TIM peripheral
+ * @param TIMx to select the TIM peripheral
* @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1
@@ -1983,19 +1911,18 @@
* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
* @retval None
*/
-static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
+static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)
{
- uint32_t tmp = 0U;
+ uint32_t tmp;
- tmp = TIM_CCER_CC1NE << Channel;
+ tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
}
-
/**
* @}
*/
diff --git a/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c b/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c
index 9dcafea..2306669 100644
--- a/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32f0xx_hal_timebase_rtc_alarm_template.c
@@ -31,29 +31,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c
index 4702733..1ca9117 100644
--- a/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32f0xx_hal_timebase_rtc_wakeup_template.c
@@ -32,29 +32,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Src/stm32f0xx_hal_timebase_tim_template.c b/Src/stm32f0xx_hal_timebase_tim_template.c
index bd0156c..8a062d2 100644
--- a/Src/stm32f0xx_hal_timebase_tim_template.c
+++ b/Src/stm32f0xx_hal_timebase_tim_template.c
@@ -11,29 +11,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Src/stm32f0xx_hal_tsc.c b/Src/stm32f0xx_hal_tsc.c
index eaf1697..d86046f 100644
--- a/Src/stm32f0xx_hal_tsc.c
+++ b/Src/stm32f0xx_hal_tsc.c
@@ -2,43 +2,44 @@
******************************************************************************
* @file stm32f0xx_hal_tsc.c
* @author MCD Application Team
- * @brief This file provides firmware functions to manage the following
+ * @brief This file provides firmware functions to manage the following
* functionalities of the Touch Sensing Controller (TSC) peripheral:
- * + Initialization and DeInitialization
+ * + Initialization and De-initialization
* + Channel IOs, Shield IOs and Sampling IOs configuration
* + Start and Stop an acquisition
* + Read acquisition result
* + Interrupts and flags management
- *
+ *
@verbatim
================================================================================
##### TSC specific features #####
================================================================================
[..]
- (+) Proven and robust surface charge transfer acquisition principle
+ (#) Proven and robust surface charge transfer acquisition principle
- (+) Supports up to 3 capacitive sensing channels per group
+ (#) Supports up to 3 capacitive sensing channels per group
- (+) Capacitive sensing channels can be acquired in parallel offering a very good
- response time
+ (#) Capacitive sensing channels can be acquired in parallel offering a very good
+ response time
- (+) Spread spectrum feature to improve system robustness in noisy environments
+ (#) Spread spectrum feature to improve system robustness in noisy environments
- (+) Full hardware management of the charge transfer acquisition sequence
+ (#) Full hardware management of the charge transfer acquisition sequence
- (+) Programmable charge transfer frequency
+ (#) Programmable charge transfer frequency
- (+) Programmable sampling capacitor I/O pin
+ (#) Programmable sampling capacitor I/O pin
- (+) Programmable channel I/O pin
+ (#) Programmable channel I/O pin
- (+) Programmable max count value to avoid long acquisition when a channel is faulty
+ (#) Programmable max count value to avoid long acquisition when a channel is faulty
- (+) Dedicated end of acquisition and max count error flags with interrupt capability
+ (#) Dedicated end of acquisition and max count error flags with interrupt capability
- (+) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
- components
- (+) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
+ (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
+ components
+
+ (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation
##### How to use this driver #####
================================================================================
@@ -50,14 +51,16 @@
(++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode,
and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode
using HAL_GPIO_Init() function.
- (++) Configure the alternate function on all the TSC pins using HAL_xxxx() function.
(#) Interrupts configuration
- (++) Configure the NVIC (if the interrupt model is used) using HAL_xxx() function.
+ (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority()
+ and HAL_NVIC_EnableIRQ() and function.
(#) TSC configuration
(++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function.
+ [..] TSC peripheral alternate functions are mapped on AF9.
+
*** Acquisition sequence ***
===================================
[..]
@@ -72,34 +75,73 @@
HAL_TSC_GetState() function or using WFI instruction for example.
(+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function.
(+) Read the acquisition value using HAL_TSC_GroupGetValue() function.
-
+
+ *** Callback registration ***
+ =============================================
+
+ [..]
+ The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+ Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback.
+
+ [..]
+ Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks:
+ (+) ConvCpltCallback : callback for conversion complete process.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default
+ weak function.
+ @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ [..]
+ This function allows to reset following callbacks:
+ (+) ConvCpltCallback : callback for conversion complete process.
+ (+) ErrorCallback : callback for error detection.
+ (+) MspInitCallback : callback for Msp Init.
+ (+) MspDeInitCallback : callback for Msp DeInit.
+
+ [..]
+ By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET
+ all callbacks are set to the corresponding weak functions:
+ examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback().
+ Exception done for MspInit and MspDeInit functions that are
+ reset to the legacy weak functions in the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() only when
+ these callbacks are null (not registered beforehand).
+ If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+ [..]
+ Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only.
+ Exception done MspInit/MspDeInit functions that can be registered/unregistered
+ in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ Then, the user first registers the MspInit/MspDeInit user callbacks
+ using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit()
+ or @ref HAL_TSC_Init() function.
+
+ [..]
+ When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
+ ******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -107,37 +149,35 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_hal.h"
-#ifdef HAL_TSC_MODULE_ENABLED
-
-#if defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || \
- defined(STM32F042x6) || defined(STM32F072xB) || \
- defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx)
-
+#if defined(TSC)
/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/
/** @defgroup TSC TSC
- * @brief TSC HAL module driver
+ * @brief HAL TSC module driver
* @{
*/
+#ifdef HAL_TSC_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static uint32_t TSC_extract_groups(uint32_t iomask);
-/* Exported functions ---------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
/** @defgroup TSC_Exported_Functions TSC Exported Functions
* @{
- */
+ */
-/** @defgroup TSC_Exported_Functions_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
@@ -149,12 +189,12 @@
*/
/**
- * @brief Initializes the TSC peripheral according to the specified parameters
- * in the TSC_InitTypeDef structure.
+ * @brief Initialize the TSC peripheral according to the specified parameters
+ * in the TSC_InitTypeDef structure and initialize the associated handle.
* @param htsc TSC handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc)
+HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
{
/* Check TSC handle allocation */
if (htsc == NULL)
@@ -175,29 +215,46 @@
assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode));
assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt));
+ assert_param(IS_TSC_GROUP(htsc->Init.ChannelIOs));
+ assert_param(IS_TSC_GROUP(htsc->Init.ShieldIOs));
+ assert_param(IS_TSC_GROUP(htsc->Init.SamplingIOs));
- if(htsc->State == HAL_TSC_STATE_RESET)
+ if (htsc->State == HAL_TSC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
htsc->Lock = HAL_UNLOCKED;
- }
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ /* Init the TSC Callback settings */
+ htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */
+ htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */
+
+ if (htsc->MspInitCallback == NULL)
+ {
+ htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */
+ }
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ htsc->MspInitCallback(htsc);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+ HAL_TSC_MspInit(htsc);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+ }
/* Initialize the TSC state */
htsc->State = HAL_TSC_STATE_BUSY;
- /* Init the low level hardware : GPIO, CLOCK, CORTEX */
- HAL_TSC_MspInit(htsc);
-
- /*--------------------------------------------------------------------------*/
+ /*--------------------------------------------------------------------------*/
/* Set TSC parameters */
/* Enable TSC */
htsc->Instance->CR = TSC_CR_TSCE;
-
+
/* Set all functions */
htsc->Instance->CR |= (htsc->Init.CTPulseHighLength |
htsc->Init.CTPulseLowLength |
- (uint32_t)(htsc->Init.SpreadSpectrumDeviation << 17U) |
+ (htsc->Init.SpreadSpectrumDeviation << TSC_CR_SSD_Pos) |
htsc->Init.SpreadSpectrumPrescaler |
htsc->Init.PulseGeneratorPrescaler |
htsc->Init.MaxCountValue |
@@ -209,40 +266,40 @@
{
htsc->Instance->CR |= TSC_CR_SSE;
}
-
+
/* Disable Schmitt trigger hysteresis on all used TSC IOs */
- htsc->Instance->IOHCR = (uint32_t)(~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
+ htsc->Instance->IOHCR = (~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs));
/* Set channel and shield IOs */
htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs);
-
+
/* Set sampling IOs */
htsc->Instance->IOSCR = htsc->Init.SamplingIOs;
-
+
/* Set the groups to be acquired */
htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs);
-
- /* Clear interrupts */
- htsc->Instance->IER &= (uint32_t)(~(TSC_IT_EOA | TSC_IT_MCE));
-
+
+ /* Disable interrupts */
+ htsc->Instance->IER &= (~(TSC_IT_EOA | TSC_IT_MCE));
+
/* Clear flags */
htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE);
/*--------------------------------------------------------------------------*/
-
+
/* Initialize the TSC state */
htsc->State = HAL_TSC_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Deinitializes the TSC peripheral registers to their default reset values.
- * @param htsc TSC handle
+ * @brief Deinitialize the TSC peripheral registers to their default reset values.
+ * @param htsc TSC handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc)
+HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc)
{
/* Check TSC handle allocation */
if (htsc == NULL)
@@ -252,13 +309,23 @@
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
+
/* Change TSC state */
htsc->State = HAL_TSC_STATE_BUSY;
-
+
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ if (htsc->MspDeInitCallback == NULL)
+ {
+ htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */
+ }
+
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ htsc->MspDeInitCallback(htsc);
+#else
/* DeInit the low level hardware */
HAL_TSC_MspDeInit(htsc);
-
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+
/* Change TSC state */
htsc->State = HAL_TSC_STATE_RESET;
@@ -270,53 +337,234 @@
}
/**
- * @brief Initializes the TSC MSP.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
+ * @brief Initialize the TSC MSP.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
* @retval None
*/
-__weak void HAL_TSC_MspInit(TSC_HandleTypeDef* htsc)
+__weak void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TSC_MspInit could be implemented in the user file.
- */
+ */
}
/**
- * @brief DeInitializes the TSC MSP.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
+ * @brief DeInitialize the TSC MSP.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
* @retval None
*/
-__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef* htsc)
+__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htsc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TSC_MspDeInit could be implemented in the user file.
- */
+ */
}
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TSC Callback
+ * To be used instead of the weak predefined callback
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
+ * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (HAL_TSC_STATE_READY == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_CONV_COMPLETE_CB_ID :
+ htsc->ConvCpltCallback = pCallback;
+ break;
+
+ case HAL_TSC_ERROR_CB_ID :
+ htsc->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_TSC_STATE_RESET == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = pCallback;
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htsc);
+ return status;
+}
+
+/**
+ * @brief Unregister an TSC Callback
+ * TSC callback is redirected to the weak predefined callback
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID
+ * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID
+ * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID
+ * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ if (HAL_TSC_STATE_READY == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_CONV_COMPLETE_CB_ID :
+ htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */
+ break;
+
+ case HAL_TSC_ERROR_CB_ID :
+ htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_TSC_STATE_RESET == htsc->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TSC_MSPINIT_CB_ID :
+ htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */
+ break;
+
+ case HAL_TSC_MSPDEINIT_CB_ID :
+ htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */
+ break;
+
+ default :
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htsc);
+ return status;
+}
+
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+
/**
* @}
*/
-/** @defgroup TSC_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
+/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Input and Output operation functions
*
-@verbatim
+@verbatim
===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+ ##### IO Operation functions #####
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Start acquisition in polling mode.
(+) Start acquisition in interrupt mode.
(+) Stop conversion in polling mode.
(+) Stop conversion in interrupt mode.
+ (+) Poll for acquisition completed.
(+) Get group acquisition status.
(+) Get group acquisition value.
@endverbatim
@@ -324,19 +572,19 @@
*/
/**
- * @brief Starts the acquisition.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Start the acquisition.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef* htsc)
+HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
+
/* Process locked */
__HAL_LOCK(htsc);
-
+
/* Change TSC state */
htsc->State = HAL_TSC_STATE_BUSY;
@@ -355,24 +603,24 @@
{
__HAL_TSC_SET_IODEF_INFLOAT(htsc);
}
-
+
/* Launch the acquisition */
__HAL_TSC_START_ACQ(htsc);
-
+
/* Process unlocked */
__HAL_UNLOCK(htsc);
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Enables the interrupt and starts the acquisition
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Start the acquisition in interrupt mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef* htsc)
+HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
@@ -380,10 +628,10 @@
/* Process locked */
__HAL_LOCK(htsc);
-
+
/* Change TSC state */
htsc->State = HAL_TSC_STATE_BUSY;
-
+
/* Enable end of acquisition interrupt */
__HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA);
@@ -399,7 +647,7 @@
/* Clear flags */
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
+
/* Set touch sensing IOs not acquired to the specified IODefaultMode */
if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW)
{
@@ -409,131 +657,159 @@
{
__HAL_TSC_SET_IODEF_INFLOAT(htsc);
}
-
+
/* Launch the acquisition */
__HAL_TSC_START_ACQ(htsc);
/* Process unlocked */
__HAL_UNLOCK(htsc);
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the acquisition previously launched in polling mode
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Stop the acquisition previously launched in polling mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef* htsc)
+HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
/* Process locked */
__HAL_LOCK(htsc);
-
+
/* Stop the acquisition */
__HAL_TSC_STOP_ACQ(htsc);
/* Set touch sensing IOs in low power mode (output push-pull) */
__HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-
+
/* Clear flags */
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
+
/* Change TSC state */
htsc->State = HAL_TSC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(htsc);
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Stops the acquisition previously launched in interrupt mode
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Stop the acquisition previously launched in interrupt mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef* htsc)
+HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
/* Process locked */
__HAL_LOCK(htsc);
-
+
/* Stop the acquisition */
__HAL_TSC_STOP_ACQ(htsc);
-
+
/* Set touch sensing IOs in low power mode (output push-pull) */
__HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
-
+
/* Disable interrupts */
__HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE));
/* Clear flags */
__HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE));
-
+
/* Change TSC state */
htsc->State = HAL_TSC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(htsc);
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Gets the acquisition status for a group
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Start acquisition and wait until completion.
+ * @note There is no need of a timeout parameter as the max count error is already
+ * managed by the TSC peripheral.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval HAL state
+ */
+HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Process locked */
+ __HAL_LOCK(htsc);
+
+ /* Check end of acquisition */
+ while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
+ {
+ /* The timeout (max count error) is managed by the TSC peripheral itself. */
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(htsc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the acquisition status for a group.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @param gx_index Index of the group
* @retval Group status
*/
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef* htsc, uint32_t gx_index)
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_GROUP_INDEX(gx_index));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
- /* Return the group status */
- return(__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
+ /* Return the group status */
+ return (__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index));
}
/**
- * @brief Gets the acquisition measure for a group
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Get the acquisition measure for a group.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @param gx_index Index of the group
* @retval Acquisition measure
*/
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef* htsc, uint32_t gx_index)
-{
+uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index)
+{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
- assert_param(IS_GROUP_INDEX(gx_index));
+ assert_param(IS_TSC_GROUP_INDEX(gx_index));
- /* Return the group acquisition counter */
+ /* Return the group acquisition counter */
return htsc->Instance->IOGXCR[gx_index];
}
/**
* @}
*/
-
+
/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
+ * @brief Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Configure TSC IOs
(+) Discharge TSC IOs
@@ -542,17 +818,20 @@
*/
/**
- * @brief Configures TSC IOs
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Configure TSC IOs.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
- * @param config pointer to the configuration structure.
+ * @param config Pointer to the configuration structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef* htsc, TSC_IOConfigTypeDef* config)
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
+ assert_param(IS_TSC_GROUP(config->ChannelIOs));
+ assert_param(IS_TSC_GROUP(config->ShieldIOs));
+ assert_param(IS_TSC_GROUP(config->SamplingIOs));
+
/* Process locked */
__HAL_LOCK(htsc);
@@ -560,39 +839,39 @@
__HAL_TSC_STOP_ACQ(htsc);
/* Disable Schmitt trigger hysteresis on all used TSC IOs */
- htsc->Instance->IOHCR = (uint32_t)(~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
+ htsc->Instance->IOHCR = (~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs));
/* Set channel and shield IOs */
htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs);
-
+
/* Set sampling IOs */
htsc->Instance->IOSCR = config->SamplingIOs;
-
+
/* Set groups to be acquired */
htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs);
-
+
/* Process unlocked */
__HAL_UNLOCK(htsc);
-
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Discharge TSC IOs
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Discharge TSC IOs.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
- * @param choice enable or disable
+ * @param choice This parameter can be set to ENABLE or DISABLE.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef* htsc, uint32_t choice)
-{
+HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice)
+{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
/* Process locked */
__HAL_LOCK(htsc);
-
+
if (choice == ENABLE)
{
__HAL_TSC_SET_IODEF_OUTPPLOW(htsc);
@@ -604,8 +883,8 @@
/* Process unlocked */
__HAL_UNLOCK(htsc);
-
- /* Return the group acquisition counter */
+
+ /* Return the group acquisition counter */
return HAL_OK;
}
@@ -613,34 +892,32 @@
* @}
*/
-/** @defgroup TSC_Exported_Functions_Group4 State functions
- * @brief State functions
+/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
*
-@verbatim
+@verbatim
===============================================================================
- ##### State functions #####
- ===============================================================================
+ ##### State and Errors functions #####
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Get TSC state.
- (+) Poll for acquisition completed.
- (+) Handles TSC interrupt request.
-
+
@endverbatim
* @{
*/
/**
- * @brief Return the TSC state
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Return the TSC handle state.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval HAL state
*/
-HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef* htsc)
+HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
+
if (htsc->State == HAL_TSC_STATE_BUSY)
{
/* Check end of acquisition flag */
@@ -659,92 +936,71 @@
}
}
}
-
+
/* Return TSC state */
return htsc->State;
}
/**
- * @brief Start acquisition and wait until completion
- * @note There is no need of a timeout parameter as the max count error is already
- * managed by the TSC peripheral.
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval HAL state
- */
-HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Process locked */
- __HAL_LOCK(htsc);
-
- /* Check end of acquisition */
- while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY)
- {
- /* The timeout (max count error) is managed by the TSC peripheral itself. */
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(htsc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Handles TSC interrupt request
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
- * the configuration information for the specified TSC.
- * @retval None
- */
-void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc)
-{
- /* Check the parameters */
- assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
-
- /* Check if the end of acquisition occured */
- if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
- {
- /* Clear EOA flag */
- __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
- }
-
- /* Check if max count error occured */
- if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
- {
- /* Clear MCE flag */
- __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_ERROR;
- /* Conversion completed callback */
- HAL_TSC_ErrorCallback(htsc);
- }
- else
- {
- /* Change TSC state */
- htsc->State = HAL_TSC_STATE_READY;
- /* Conversion completed callback */
- HAL_TSC_ConvCpltCallback(htsc);
- }
-}
-
-/**
* @}
*/
-/** @defgroup TSC_Exported_Functions_Group5 Callback functions
- * @brief Callback functions
- * @{
+/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
*/
-
+
/**
- * @brief Acquisition completed callback in non blocking mode
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Handle TSC interrupt request.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval None
*/
-__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef* htsc)
+void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc)
+{
+ /* Check the parameters */
+ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
+
+ /* Check if the end of acquisition occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET)
+ {
+ /* Clear EOA flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA);
+ }
+
+ /* Check if max count error occurred */
+ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET)
+ {
+ /* Clear MCE flag */
+ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE);
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_ERROR;
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ htsc->ErrorCallback(htsc);
+#else
+ /* Conversion completed callback */
+ HAL_TSC_ErrorCallback(htsc);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Change TSC state */
+ htsc->State = HAL_TSC_STATE_READY;
+#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
+ htsc->ConvCpltCallback(htsc);
+#else
+ /* Conversion completed callback */
+ HAL_TSC_ConvCpltCallback(htsc);
+#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
+ }
+}
+
+/**
+ * @brief Acquisition completed callback in non-blocking mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
+ * the configuration information for the specified TSC.
+ * @retval None
+ */
+__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htsc);
@@ -755,12 +1011,12 @@
}
/**
- * @brief Error callback in non blocking mode
- * @param htsc pointer to a TSC_HandleTypeDef structure that contains
+ * @brief Error callback in non-blocking mode.
+ * @param htsc Pointer to a TSC_HandleTypeDef structure that contains
* the configuration information for the specified TSC.
* @retval None
*/
-__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc)
+__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(htsc);
@@ -778,28 +1034,29 @@
* @}
*/
+/* Private functions ---------------------------------------------------------*/
/** @defgroup TSC_Private_Functions TSC Private Functions
- * @{
- */
-
+ * @{
+ */
+
/**
- * @brief Utility function used to set the acquired groups mask
+ * @brief Utility function used to set the acquired groups mask.
* @param iomask Channels IOs mask
* @retval Acquired groups mask
*/
static uint32_t TSC_extract_groups(uint32_t iomask)
{
- uint32_t groups = 0U;
+ uint32_t groups = 0UL;
uint32_t idx;
-
- for (idx = 0U; idx < TSC_NB_OF_GROUPS; idx++)
+
+ for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++)
{
- if ((iomask & (0x0FU << (idx * 4U))) != RESET)
+ if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL )
{
- groups |= (1U << idx);
+ groups |= (1UL << idx);
}
}
-
+
return groups;
}
@@ -807,18 +1064,15 @@
* @}
*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(STM32F051x8) || defined(STM32F071xB) || defined(STM32F091xC) || */
- /* defined(STM32F042x6) || defined(STM32F072xB) || */
- /* defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F078xx) || defined(STM32F098xx) */
-
#endif /* HAL_TSC_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TSC */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_uart.c b/Src/stm32f0xx_hal_uart.c
index 564e2a6..b0f7b21 100644
--- a/Src/stm32f0xx_hal_uart.c
+++ b/Src/stm32f0xx_hal_uart.c
@@ -3,12 +3,12 @@
* @file stm32f0xx_hal_uart.c
* @author MCD Application Team
* @brief UART HAL module driver.
- * This file provides firmware functions to manage the following
- * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
+ * This file provides firmware functions to manage the following
+ * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
- * + Peripheral State and Errors functions
+ *
*
@verbatim
===============================================================================
@@ -29,8 +29,9 @@
(+++) Enable the NVIC USART IRQ handle.
(++) UART interrupts handling:
-@@- The specific UART interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) are managed using the macros
- __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit and receive processes.
+ RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+ are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+ inside the transmit and receive processes.
(++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
and HAL_UART_Receive_DMA() APIs):
(+++) Declare a DMA handle structure for the Tx/Rx channel.
@@ -52,103 +53,102 @@
(#) For the UART Half duplex mode, initialize the UART registers by calling
the HAL_HalfDuplex_Init() API.
+ (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+ by calling the HAL_LIN_Init() API.
+
(#) For the UART Multiprocessor mode, initialize the UART registers
by calling the HAL_MultiProcessor_Init() API.
(#) For the UART RS485 Driver Enabled mode, initialize the UART registers
by calling the HAL_RS485Ex_Init() API.
- [..]
- (@) These APIs(HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_MultiProcessor_Init(),
+ [..]
+ (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
calling the customized HAL_UART_MspInit() API.
- [..]
- [..] Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
+ ##### Callback registration #####
+ ==================================
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
- (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_UART_RxCpltCallback
- (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_UART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_UART_DMAPause()
- (+) Resume the DMA Transfer using HAL_UART_DMAResume()
- (+) Stop the DMA Transfer using HAL_UART_DMAStop()
-
- *** UART HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in UART HAL driver.
-
- (+) __HAL_UART_ENABLE: Enable the UART peripheral
- (+) __HAL_UART_DISABLE: Disable the UART peripheral
- (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
- (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
- (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
- (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
-
- [..]
- (@) You can refer to the UART HAL driver header file for more useful macros
-
+ [..]
+ The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ [..]
+ Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
+ Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ [..]
+ Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+ (+) AbortReceiveCpltCallback : Abort Receive Complete Callback.
+ (+) WakeupCallback : Wakeup Callback.
+ (+) RxFifoFullCallback : Rx Fifo Full Callback.
+ (+) TxFifoEmptyCallback : Tx Fifo Empty Callback.
+ (+) MspInitCallback : UART MspInit.
+ (+) MspDeInitCallback : UART MspDeInit.
+
+ [..]
+ By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
+ and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+ [..]
+ Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
+ or @ref HAL_UART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -172,8 +172,15 @@
/** @defgroup UART_Private_Constants UART Private Constants
* @{
*/
-#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
- USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+
+#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
+#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */
+
/**
* @}
*/
@@ -187,18 +194,20 @@
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAError(DMA_HandleTypeDef *hdma);
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
/**
* @}
*/
@@ -223,7 +232,8 @@
(++) Baud Rate
(++) Word Length
(++) Stop Bit
- (++) Parity
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Method
@@ -237,51 +247,37 @@
(++) MSB first on communication line
(++) auto Baud rate detection
[..]
- The HAL_UART_Init(), HAL_HalfDuplex_Init() and HAL_MultiProcessor_Init()
- API follow respectively the UART asynchronous, UART Half duplex and multiprocessor mode
- configuration procedures (details for the procedures are available in reference manual).
+ The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+ follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+ and UART multiprocessor mode configuration procedures (details for the procedures
+ are available in reference manual).
@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
* @{
*/
-/*
- Additional Table: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible UART frame formats are as listed in the following table:
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |-------------------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
-*/
-
/**
* @brief Initialize the UART mode according to the specified
* parameters in the UART_InitTypeDef and initialize the associated handle.
@@ -291,12 +287,12 @@
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
- if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+ if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
{
/* Check the parameters */
assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
@@ -307,18 +303,29 @@
assert_param(IS_UART_INSTANCE(huart->Instance));
}
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@@ -334,27 +341,26 @@
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
- - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
+ - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register.*/
#if defined (USART_CR2_LINEN)
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
#else
CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
-#endif
+#endif /* USART_CR2_LINEN */
#if defined (USART_CR3_SCEN)
#if defined (USART_CR3_IREN)
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
#else
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-#endif
+#endif /* USART_CR3_IREN */
#else
#if defined (USART_CR3_IREN)
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
#else
CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-#endif
-#endif
+#endif /* USART_CR3_IREN*/
+#endif /* USART_CR3_SCEN */
- /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -370,7 +376,7 @@
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
@@ -378,18 +384,29 @@
/* Check UART instance */
assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@@ -405,28 +422,27 @@
/* In half-duplex mode, the following bits must be kept cleared:
- LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
- - SCEN (if Smartcard is supported), and IREN (if IrDA is supported) bits in the USART_CR3 register. */
+ - SCEN (if Smartcard is supported) and IREN (if IrDA is supported) bits in the USART_CR3 register.*/
#if defined (USART_CR2_LINEN)
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
#else
CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
-#endif
+#endif /* USART_CR2_LINEN */
#if defined (USART_CR3_SCEN)
#if defined (USART_CR3_IREN)
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
#else
CLEAR_BIT(huart->Instance->CR3, USART_CR3_SCEN);
-#endif
+#endif /* USART_CR3_IREN */
#else
#if defined (USART_CR3_IREN)
CLEAR_BIT(huart->Instance->CR3, USART_CR3_IREN);
-#endif
-#endif
+#endif /* USART_CR3_IREN */
+#endif /* USART_CR3_SCEN */
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
- /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -434,12 +450,115 @@
}
+#if defined(USART_CR2_LINEN)
+/**
+ * @brief Initialize the LIN mode according to the specified
+ * parameters in the UART_InitTypeDef and creates the associated handle.
+ * @param huart UART handle.
+ * @param BreakDetectLength Specifies the LIN break detection length.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+ * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the LIN UART instance */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+ /* Check the Break detection length parameter */
+ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+ /* LIN mode limited to 16-bit oversampling only */
+ if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ return HAL_ERROR;
+ }
+ /* LIN mode limited to 8-bit data length */
+ if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
+ /* Init the low level hardware : GPIO, CLOCK */
+ HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the UART Communication parameters */
+ if (UART_SetConfig(huart) == HAL_ERROR)
+ {
+ return HAL_ERROR;
+ }
+
+ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ {
+ UART_AdvFeatureConfig(huart);
+ }
+
+ /* In LIN mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN(if Smartcard is supported) and IREN(if IrDA is supported) bits in the USART_CR3 register.*/
+ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+#if defined (USART_CR3_SCEN)
+#if defined (USART_CR3_IREN)
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+#else
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+#endif /* USART_CR3_IREN */
+#else
+#if defined (USART_CR3_IREN)
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+#else
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+#endif /* USART_CR3_IREN*/
+#endif /* USART_CR3_SCEN */
+
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+ SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+ /* Set the USART LIN Break detection length. */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+#endif /* USART_CR2_LINEN */
+
+
/**
* @brief Initialize the multiprocessor mode according to the specified
* parameters in the UART_InitTypeDef and initialize the associated handle.
- * @param huart UART handle.
- * @param Address UART node address (4-, 6-, 7- or 8-bit long).
- * @param WakeUpMethod specifies the UART wakeup method.
+ * @param huart UART handle.
+ * @param Address UART node address (4-, 6-, 7- or 8-bit long).
+ * @param WakeUpMethod Specifies the UART wakeup method.
* This parameter can be one of the following values:
* @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
* @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
@@ -455,7 +574,7 @@
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
@@ -463,18 +582,29 @@
/* Check the wake up method parameter */
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
/* Set the UART Communication parameters */
@@ -495,20 +625,20 @@
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
#else
CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
-#endif
+#endif /* USART_CR2_LINEN */
#if defined (USART_CR3_SCEN)
#if defined (USART_CR3_IREN)
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
#else
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-#endif
+#endif /* USART_CR3_IREN */
#else
#if defined (USART_CR3_IREN)
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
#else
CLEAR_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-#endif
-#endif
+#endif /* USART_CR3_IREN */
+#endif /* USART_CR3_SCEN */
if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
{
@@ -519,7 +649,6 @@
/* Set the wake up method by setting the WAKE bit in the CR1 register */
MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
- /* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
@@ -535,7 +664,7 @@
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
{
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
@@ -545,21 +674,28 @@
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
huart->Instance->CR1 = 0x0U;
huart->Instance->CR2 = 0x0U;
huart->Instance->CR3 = 0x0U;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ if (huart->MspDeInitCallback == NULL)
+ {
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ huart->MspDeInitCallback(huart);
+#else
/* DeInit the low level hardware */
HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->gState = HAL_UART_STATE_RESET;
- huart->RxState = HAL_UART_STATE_RESET;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
- /* Process Unlock */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -595,6 +731,246 @@
*/
}
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User UART Callback
+ * To be used instead of the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+ pUART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = pCallback;
+ break;
+
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = pCallback;
+ break;
+
+
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (huart->gState == HAL_UART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param huart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+ * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+ * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+ * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+ * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+ * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ __HAL_LOCK(huart);
+
+ if (HAL_UART_STATE_READY == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_UART_TX_COMPLETE_CB_ID :
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_UART_RX_COMPLETE_CB_ID :
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_UART_ERROR_CB_ID :
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_UART_ABORT_COMPLETE_CB_ID :
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ break;
+
+ case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ break;
+
+#if defined(USART_CR1_UESM)
+ case HAL_UART_WAKEUP_CB_ID :
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+ break;
+
+#endif /* USART_CR1_UESM */
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_UART_STATE_RESET == huart->gState)
+ {
+ switch (CallbackID)
+ {
+ case HAL_UART_MSPINIT_CB_ID :
+ huart->MspInitCallback = HAL_UART_MspInit;
+ break;
+
+ case HAL_UART_MSPDEINIT_CB_ID :
+ huart->MspDeInitCallback = HAL_UART_MspDeInit;
+ break;
+
+ default :
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -610,10 +986,10 @@
and Half duplex data transfers.
(#) There are two mode of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
+ (+) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
+ (+) Non-Blocking mode: The communication is performed using Interrupts
or DMA, These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
@@ -623,51 +999,51 @@
The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
(#) Blocking mode API's are :
- (++) HAL_UART_Transmit()
- (++) HAL_UART_Receive()
+ (+) HAL_UART_Transmit()
+ (+) HAL_UART_Receive()
(#) Non-Blocking mode API's with Interrupt are :
- (++) HAL_UART_Transmit_IT()
- (++) HAL_UART_Receive_IT()
- (++) HAL_UART_IRQHandler()
+ (+) HAL_UART_Transmit_IT()
+ (+) HAL_UART_Receive_IT()
+ (+) HAL_UART_IRQHandler()
(#) Non-Blocking mode API's with DMA are :
- (++) HAL_UART_Transmit_DMA()
- (++) HAL_UART_Receive_DMA()
- (++) HAL_UART_DMAPause()
- (++) HAL_UART_DMAResume()
- (++) HAL_UART_DMAStop()
+ (+) HAL_UART_Transmit_DMA()
+ (+) HAL_UART_Receive_DMA()
+ (+) HAL_UART_DMAPause()
+ (+) HAL_UART_DMAResume()
+ (+) HAL_UART_DMAStop()
(#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
- (++) HAL_UART_TxHalfCpltCallback()
- (++) HAL_UART_TxCpltCallback()
- (++) HAL_UART_RxHalfCpltCallback()
- (++) HAL_UART_RxCpltCallback()
- (++) HAL_UART_ErrorCallback()
+ (+) HAL_UART_TxHalfCpltCallback()
+ (+) HAL_UART_TxCpltCallback()
+ (+) HAL_UART_RxHalfCpltCallback()
+ (+) HAL_UART_RxCpltCallback()
+ (+) HAL_UART_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_UART_Abort()
- (++) HAL_UART_AbortTransmit()
- (++) HAL_UART_AbortReceive()
- (++) HAL_UART_Abort_IT()
- (++) HAL_UART_AbortTransmit_IT()
- (++) HAL_UART_AbortReceive_IT()
+ (+) HAL_UART_Abort()
+ (+) HAL_UART_AbortTransmit()
+ (+) HAL_UART_AbortReceive()
+ (+) HAL_UART_Abort_IT()
+ (+) HAL_UART_AbortTransmit_IT()
+ (+) HAL_UART_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_UART_AbortCpltCallback()
- (++) HAL_UART_AbortTransmitCpltCallback()
- (++) HAL_UART_AbortReceiveCpltCallback()
+ (+) HAL_UART_AbortCpltCallback()
+ (+) HAL_UART_AbortTransmitCpltCallback()
+ (+) HAL_UART_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+ (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+ If user wants to abort it, Abort services should be called by user.
+ (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-@- In the Half duplex communication, it is forbidden to run the transmit
and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
@@ -678,41 +1054,44 @@
/**
* @brief Send an amount of data in blocking mode.
- * @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
- uint32_t tickstart = 0U;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@@ -721,27 +1100,41 @@
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- huart->TxXferSize = Size;
+ huart->TxXferSize = Size;
huart->TxXferCount = Size;
- while(huart->TxXferCount > 0)
+
+ /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- huart->TxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ while (huart->TxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pData += 2;
+ huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ pdata16bits++;
}
else
{
- huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
+ huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ pdata8bits++;
}
+ huart->TxXferCount--;
}
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -749,7 +1142,6 @@
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -762,42 +1154,45 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
- * @param Timeout Timeout duration.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp;
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0;
+ uint32_t tickstart;
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be received from RDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
@@ -806,37 +1201,48 @@
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- huart->RxXferSize = Size;
+ huart->RxXferSize = Size;
huart->RxXferCount = Size;
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
uhMask = huart->Mask;
- /* as long as data have to be received */
- while(huart->RxXferCount > 0U)
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- huart->RxXferCount--;
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ if (pdata8bits == NULL)
{
- tmp = (uint16_t*) pData ;
- *tmp = (uint16_t)(huart->Instance->RDR & uhMask);
- pData +=2U;
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
}
else
{
- *pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
}
+ huart->RxXferCount--;
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -849,50 +1255,62 @@
/**
* @brief Send an amount of data in interrupt mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
}
- /* Process Locked */
__HAL_LOCK(huart);
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
huart->TxXferCount = Size;
+ huart->TxISR = NULL;
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
- /* Process Unlocked */
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->TxISR = UART_TxISR_16BIT;
+ }
+ else
+ {
+ huart->TxISR = UART_TxISR_8BIT;
+ }
+
__HAL_UNLOCK(huart);
- /* Enable the UART Transmit Data Register Empty Interrupt */
+ /* Enable the Transmit Data Register Empty interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
@@ -905,42 +1323,45 @@
/**
* @brief Receive an amount of data in interrupt mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be received from RDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
}
- /* Process Locked */
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
huart->RxXferCount = Size;
+ huart->RxISR = NULL;
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
@@ -948,13 +1369,22 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Enable the UART Parity Error and Data Register not empty Interrupts */
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
return HAL_OK;
@@ -967,69 +1397,83 @@
/**
* @brief Send an amount of data in DMA mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Tx process is not already ongoing */
- if(huart->gState == HAL_UART_STATE_READY)
+ if (huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data copy into TDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy into TDR will be
handled by DMA from a u16 frontier. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
}
- /* Process Locked */
__HAL_LOCK(huart);
- huart->pTxBuffPtr = pData;
- huart->TxXferSize = Size;
+ huart->pTxBuffPtr = pData;
+ huart->TxXferSize = Size;
huart->TxXferCount = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
- /* Set the UART DMA transfer complete callback */
- huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+ if (huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
- /* Set the DMA error callback */
- huart->hdmatx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA error callback */
+ huart->hdmatx->XferErrorCallback = UART_DMAError;
- /* Set the DMA abort callback */
- huart->hdmatx->XferAbortCallback = NULL;
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
- /* Enable the UART transmit DMA channel */
- HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size);
+ /* Enable the UART transmit DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
- /* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the UART CR3 register */
+ in the UART CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
return HAL_OK;
@@ -1042,37 +1486,41 @@
/**
* @brief Receive an amount of data in DMA mode.
- * @param huart UART handle.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
/* Check that a Rx process is not already ongoing */
- if(huart->RxState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pData buffer provided as input paramter
- should be aligned on a u16 frontier, as data copy from RDR will be
+ /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy from RDR will be
handled by DMA from a u16 frontier. */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
- if((((uint32_t)pData)&1U) != 0U)
+ if ((((uint32_t)pData) & 1U) != 0U)
{
return HAL_ERROR;
}
}
- /* Process Locked */
__HAL_LOCK(huart);
huart->pRxBuffPtr = pData;
@@ -1081,22 +1529,34 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size);
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
- /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
__HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
@@ -1106,7 +1566,7 @@
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
+ in the UART CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
return HAL_OK;
@@ -1124,17 +1584,19 @@
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
- /* Process Locked */
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
__HAL_LOCK(huart);
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
{
/* Disable the UART DMA Tx request */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
@@ -1144,7 +1606,6 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -1157,15 +1618,14 @@
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
- if(huart->gState == HAL_UART_STATE_BUSY_TX)
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
/* Clear the Overrun flag before resuming the Rx transfer */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
@@ -1178,7 +1638,6 @@
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -1193,36 +1652,57 @@
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
- HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
- interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
the stream and the corresponding call back is executed. */
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
/* Stop UART DMA Tx request if ongoing */
- if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- HAL_DMA_Abort(huart->hdmatx);
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
UART_EndTxTransfer(huart);
}
/* Stop UART DMA Rx request if ongoing */
- if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
{
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- HAL_DMA_Abort(huart->hdmarx);
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
UART_EndRxTransfer(huart);
@@ -1234,7 +1714,7 @@
/**
* @brief Abort ongoing transfers (blocking mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable UART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1242,7 +1722,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1255,13 +1735,22 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- /* Set the UART DMA Abort callback to Null.
+ /* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmatx);
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -1271,28 +1760,40 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- /* Set the UART DMA Abort callback to Null.
+ /* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmarx);
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
- huart->RxXferCount = 0U;
+ huart->TxXferCount = 0U;
+ huart->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
- /* Reset Handle ErrorCode to No Error */
huart->ErrorCode = HAL_UART_ERROR_NONE;
return HAL_OK;
@@ -1301,7 +1802,7 @@
/**
* @brief Abort ongoing Transmit transfer (blocking mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable UART Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1309,7 +1810,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
{
/* Disable TXEIE and TCIE interrupts */
@@ -1321,18 +1822,28 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- /* Set the UART DMA Abort callback to Null.
+ /* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmatx);
+ if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
@@ -1343,7 +1854,7 @@
/**
* @brief Abort ongoing Receive transfer (blocking mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable UART Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1351,7 +1862,7 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1364,22 +1875,34 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- /* Set the UART DMA Abort callback to Null.
+ /* Set the UART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(huart->hdmarx);
+ if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
+ huart->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
@@ -1389,7 +1912,7 @@
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable UART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1399,23 +1922,23 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
{
uint32_t abortcplt = 1U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+
+ /* Disable interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
}
@@ -1425,11 +1948,11 @@
}
}
/* DMA Rx Handle is valid */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
}
@@ -1438,21 +1961,21 @@
huart->hdmarx->XferAbortCallback = NULL;
}
}
-
+
/* Disable the UART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- /* UART Tx DMA Abort callback has already been initialised :
+ /* UART Tx DMA Abort callback has already been initialised :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
{
huart->hdmatx->XferAbortCallback = NULL;
}
@@ -1469,13 +1992,13 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- /* UART Rx DMA Abort callback has already been initialised :
+ /* UART Rx DMA Abort callback has already been initialised :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
huart->hdmarx->XferAbortCallback = NULL;
abortcplt = 1U;
@@ -1491,21 +2014,35 @@
if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
- huart->TxXferCount = 0U;
+ huart->TxXferCount = 0U;
huart->RxXferCount = 0U;
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
/* Reset errorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1514,7 +2051,7 @@
/**
* @brief Abort ongoing Transmit transfer (Interrupt mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable UART Interrupts (Tx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1524,10 +2061,10 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
{
- /* Disable TXEIE and TCIE interrupts */
+ /* Disable interrupts */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
/* Disable the UART DMA Tx request if enabled */
@@ -1536,14 +2073,14 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- /* Set the UART DMA Abort callback :
+ /* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
{
/* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
huart->hdmatx->XferAbortCallback(huart->hdmatx);
@@ -1552,25 +2089,44 @@
else
{
/* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
else
{
/* Reset Tx transfer counter */
- huart->TxXferCount = 0U;
+ huart->TxXferCount = 0U;
+
+ /* Clear TxISR function pointers */
+ huart->TxISR = NULL;
+
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1579,7 +2135,7 @@
/**
* @brief Abort ongoing Receive transfer (Interrupt mode).
* @param huart UART handle.
- * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable UART Interrupts (Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1589,7 +2145,7 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
@@ -1602,14 +2158,14 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- /* Set the UART DMA Abort callback :
+ /* Set the UART DMA Abort callback :
will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
@@ -1618,22 +2174,37 @@
else
{
/* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
else
{
/* Reset Rx transfer counter */
- huart->RxXferCount = 0U;
+ huart->RxXferCount = 0U;
+
+ /* Clear RxISR function pointer */
+ huart->pRxBuffPtr = NULL;
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
@@ -1642,7 +2213,13 @@
huart->RxState = HAL_UART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1657,74 +2234,96 @@
{
uint32_t isrflags = READ_REG(huart->Instance->ISR);
uint32_t cr1its = READ_REG(huart->Instance->CR1);
- uint32_t cr3its;
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+
uint32_t errorflags;
+ uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ if (errorflags == 0U)
{
/* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- UART_Receive_IT(huart);
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
return;
}
- }
+ }
/* If some errors occur */
- cr3its = READ_REG(huart->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
{
/* UART parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
huart->ErrorCode |= HAL_UART_ERROR_PE;
}
/* UART frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
huart->ErrorCode |= HAL_UART_ERROR_FE;
}
/* UART noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
huart->ErrorCode |= HAL_UART_ERROR_NE;
}
-
+
/* UART Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ ((cr3its & USART_CR3_EIE) != 0U)))
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
huart->ErrorCode |= HAL_UART_ERROR_ORE;
}
- /* Call UART Error Call back function if need be --------------------------*/
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+ if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
{
- /* UART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver --------------------------------------------------*/
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- UART_Receive_IT(huart);
+ if (huart->RxISR != NULL)
+ {
+ huart->RxISR(huart);
+ }
}
- /* If Overrun error occurs, or if any error occurs in DMA mode reception,
- consider error as blocking */
- if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
- {
+ /* If Error is to be considered as blocking :
+ - Receiver Timeout error in Reception
+ - Overrun error in Reception
+ - any error occurs in DMA mode reception
+ */
+ errorcode = huart->ErrorCode;
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ {
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
@@ -1736,14 +2335,14 @@
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- /* Set the UART DMA Abort callback :
+ /* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
@@ -1752,49 +2351,79 @@
else
{
/* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
}
else
{
- /* Non Blocking error : transfer could go on.
+ /* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
}
}
return;
} /* End if some error occurs */
+#if defined(USART_CR1_UESM)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
- if(((isrflags & USART_ISR_WUF) != RESET) && ((cr3its & USART_CR3_WUFIE) != RESET))
+ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
{
- __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF);
- /* Set the UART state ready to be able to start again the process */
- huart->gState = HAL_UART_STATE_READY;
- huart->RxState = HAL_UART_STATE_READY;
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+ /* UART Rx state is not reset as a reception process might be ongoing.
+ If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Wakeup Callback */
+ huart->WakeupCallback(huart);
+#else
+ /* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+#endif /* USART_CR1_UESM */
/* UART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_ISR_TXE) != 0U)
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
{
- UART_Transmit_IT(huart);
+ if (huart->TxISR != NULL)
+ {
+ huart->TxISR(huart);
+ }
return;
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
{
UART_EndTransmit_IT(huart);
return;
@@ -1833,8 +2462,8 @@
}
/**
- * @brief Rx Transfer completed callback.
- * @param huart UART handle.
+ * @brief Rx Transfer completed callback.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
@@ -1863,8 +2492,8 @@
}
/**
- * @brief UART error callback.
- * @param huart UART handle.
+ * @brief UART error callback.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
@@ -1882,7 +2511,7 @@
* @param huart UART handle.
* @retval None
*/
-__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1897,7 +2526,7 @@
* @param huart UART handle.
* @retval None
*/
-__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1912,7 +2541,7 @@
* @param huart UART handle.
* @retval None
*/
-__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
@@ -1935,24 +2564,106 @@
===============================================================================
[..]
This subsection provides a set of functions allowing to control the UART.
+ (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+ (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+ (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
(+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
(+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
(+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+ (+) UART_SetConfig() API configures the UART peripheral
+ (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+ (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
(+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
(+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+ (+) HAL_LIN_SendBreak() API transmits the break characters
@endverbatim
* @{
*/
/**
- * @brief Enable UART in mute mode (does not mean UART enters mute mode;
- * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
- * @param huart UART handle.
+ * @brief Update on the fly the receiver timeout value in RTOR register.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout
+ * value must be less or equal to 0x0FFFFFFFF.
+ * @retval None
+ */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+ assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+ MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+}
+
+/**
+ * @brief Enable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Set the USART RTOEN bit */
+ SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the UART receiver timeout feature.
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
+ * the configuration information for the specified UART module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Clear the USART RTOEN bit */
+ CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable UART in mute mode (does not mean UART enters mute mode;
+ * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+ * @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
@@ -1973,12 +2684,11 @@
*/
HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
- /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+ /* Disable USART mute mode by clearing the MME bit in the CR1 register */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
huart->gState = HAL_UART_STATE_READY;
@@ -2004,18 +2714,17 @@
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
SET_BIT(huart->Instance->CR1, USART_CR1_TE);
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -2028,29 +2737,56 @@
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
{
- /* Process Locked */
__HAL_LOCK(huart);
huart->gState = HAL_UART_STATE_BUSY;
/* Clear TE and RE bits */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
SET_BIT(huart->Instance->CR1, USART_CR1_RE);
huart->gState = HAL_UART_STATE_READY;
- /* Process Unlocked */
+
__HAL_UNLOCK(huart);
return HAL_OK;
}
+
+#if defined(USART_CR2_LINEN)
+/**
+ * @brief Transmit break characters.
+ * @param huart UART handle.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+ /* Check the parameters */
+ assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+ __HAL_LOCK(huart);
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Send break characters */
+ __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+ huart->gState = HAL_UART_STATE_READY;
+
+ __HAL_UNLOCK(huart);
+
+ return HAL_OK;
+}
+#endif /* USART_CR2_LINEN */
+
/**
* @}
*/
/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief UART Peripheral State functions
- *
+ * @brief UART Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -2065,14 +2801,15 @@
*/
/**
- * @brief Return the UART handle state.
+ * @brief Return the UART handle state.
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART.
* @retval HAL state
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
- uint32_t temp1= 0x00U, temp2 = 0x00U;
+ uint32_t temp1;
+ uint32_t temp2;
temp1 = huart->gState;
temp2 = huart->RxState;
@@ -2102,108 +2839,159 @@
*/
/**
+ * @brief Initialize the callbacks to their default values.
+ * @param huart UART handle.
+ * @retval none
+ */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+ /* Init the UART Callback settings */
+ huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */
+ huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+#if defined(USART_CR1_UESM)
+ huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
+#endif /* USART_CR1_UESM */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
- uint32_t tmpreg = 0x00000000U;
- UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
+ uint32_t tmpreg;
+ uint16_t brrtemp;
+ UART_ClockSourceTypeDef clocksource;
+ uint32_t usartdiv = 0x00000000U;
HAL_StatusTypeDef ret = HAL_OK;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+ assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+
assert_param(IS_UART_PARITY(huart->Init.Parity));
assert_param(IS_UART_MODE(huart->Init.Mode));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
- assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
/*-------------------------- USART CR1 Configuration -----------------------*/
/* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
- * the UART Word Length, Parity, Mode and oversampling:
- * set the M bits according to huart->Init.WordLength value
- * set PCE and PS bits according to huart->Init.Parity value
- * set TE and RE bits according to huart->Init.Mode value
- * set OVER8 bit according to huart->Init.OverSampling value */
+ * the UART Word Length, Parity, Mode and oversampling:
+ * set the M bits according to huart->Init.WordLength value
+ * set PCE and PS bits according to huart->Init.Parity value
+ * set TE and RE bits according to huart->Init.Mode value
+ * set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
+ MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
- * to huart->Init.StopBits value */
+ * to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure
- * - UART HardWare Flow Control: set CTSE and RTSE bits according
- * to huart->Init.HwFlowCtl value
- * - one-bit sampling method versus three samples' majority rule according
- * to huart->Init.OneBitSampling */
- tmpreg = (uint32_t)huart->Init.HwFlowCtl | huart->Init.OneBitSampling ;
- MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg);
+ * - UART HardWare Flow Control: set CTSE and RTSE bits according
+ * to huart->Init.HwFlowCtl value
+ * - one-bit sampling method versus three samples' majority rule according
+ * to huart->Init.OneBitSampling (not applicable to LPUART) */
+ tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+ tmpreg |= huart->Init.OneBitSampling;
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
-
- /* Check UART Over Sampling to set Baud Rate Register */
+
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
{
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- huart->Instance->BRR = brrtemp;
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
}
else
{
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_HSI:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_SYSCLK:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
break;
case UART_CLOCKSOURCE_LSE:
- huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
+
+ /* USARTDIV must be greater than or equal to 0d16 */
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ huart->Instance->BRR = usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
}
- return ret;
+ /* Clear ISR function pointers */
+ huart->RxISR = NULL;
+ huart->TxISR = NULL;
+
+ return ret;
}
/**
@@ -2217,55 +3005,55 @@
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
}
/* if required, configure RX pin active level inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
}
/* if required, configure data inversion */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
}
/* if required, configure RX/TX pins swap */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
}
/* if required, configure RX overrun detection disabling */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
}
/* if required, configure DMA disabling on reception error */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
}
/* if required, configure auto Baud rate detection scheme */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
/* set auto Baudrate detection parameters if detection is enabled */
- if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
@@ -2273,7 +3061,7 @@
}
/* if required, configure MSB first on communication line */
- if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
@@ -2287,51 +3075,40 @@
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
- uint32_t tickstart = 0U;
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+ uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
- Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
- */
- if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance))
+ /* Check if the Transmitter is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
- /* Check if the Transmitter is enabled */
- if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ /* Wait until TEACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
- /* Wait until TEACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the Receiver is enabled */
- if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
}
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+
+ /* Check if the Receiver is enabled */
+ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
/* Initialize the UART State */
- huart->gState = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
@@ -2339,34 +3116,57 @@
/**
* @brief Handle UART Communication Timeout.
- * @param huart UART handle.
- * @param Flag Specifies the UART flag to check
- * @param Status Flag status (SET or RESET)
- * @param Tickstart Tick start value
- * @param Timeout Timeout duration
+ * @param huart UART handle.
+ * @param Flag Specifies the UART flag to check
+ * @param Status Flag status (SET or RESET)
+ * @param Tickstart Tick start value
+ * @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- huart->gState = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
- /* Process Unlocked */
__HAL_UNLOCK(huart);
+
return HAL_TIMEOUT;
}
+
+ if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ {
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ {
+ /* Clear Receiver Timeout flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
return HAL_OK;
@@ -2401,6 +3201,9 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+
+ /* Reset RxIsr function pointer */
+ huart->RxISR = NULL;
}
@@ -2411,12 +3214,12 @@
*/
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
-
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
- huart->TxXferCount = 0;
+ huart->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the UART CR3 register */
@@ -2428,9 +3231,14 @@
/* DMA Circular mode */
else
{
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
-
}
/**
@@ -2440,9 +3248,15 @@
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx Half complete callback*/
+ huart->TxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Tx Half complete callback*/
HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2452,10 +3266,10 @@
*/
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if (hdma->Init.Mode != DMA_CIRCULAR)
{
huart->RxXferCount = 0U;
@@ -2471,7 +3285,13 @@
huart->RxState = HAL_UART_STATE_READY;
}
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2481,9 +3301,15 @@
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2493,26 +3319,36 @@
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+ const HAL_UART_StateTypeDef gstate = huart->gState;
+ const HAL_UART_StateTypeDef rxstate = huart->RxState;
/* Stop UART DMA Tx request if ongoing */
- if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+ (gstate == HAL_UART_STATE_BUSY_TX))
{
huart->TxXferCount = 0U;
UART_EndTxTransfer(huart);
}
/* Stop UART DMA Rx request if ongoing */
- if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
- &&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
+ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+ (rxstate == HAL_UART_STATE_BUSY_RX))
{
huart->RxXferCount = 0U;
UART_EndRxTransfer(huart);
}
huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2523,11 +3359,17 @@
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
huart->RxXferCount = 0U;
huart->TxXferCount = 0U;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2540,19 +3382,19 @@
*/
static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
-
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
huart->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(huart->hdmarx != NULL)
+ if (huart->hdmarx != NULL)
{
- if(huart->hdmarx->XferAbortCallback != NULL)
+ if (huart->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
huart->TxXferCount = 0U;
huart->RxXferCount = 0U;
@@ -2563,12 +3405,19 @@
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
@@ -2582,19 +3431,19 @@
*/
static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef* )(hdma->Parent);
-
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
huart->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(huart->hdmatx != NULL)
+ if (huart->hdmatx != NULL)
{
- if(huart->hdmatx->XferAbortCallback != NULL)
+ if (huart->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
huart->TxXferCount = 0U;
huart->RxXferCount = 0U;
@@ -2605,12 +3454,21 @@
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort complete callback */
+ huart->AbortCpltCallback(huart);
+#else
+ /* Call legacy weak Abort complete callback */
HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
@@ -2624,15 +3482,22 @@
*/
static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
huart->TxXferCount = 0U;
+
/* Restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Transmit Complete Callback */
+ huart->AbortTransmitCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Transmit Complete Callback */
HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
@@ -2645,74 +3510,98 @@
*/
static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
{
- UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
huart->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+ /* Discard the received data */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Receive Complete Callback */
+ huart->AbortReceiveCpltCallback(huart);
+#else
+ /* Call legacy weak Abort Receive Complete Callback */
HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
- * @brief Send an amount of data in interrupt mode.
+ * @brief TX interrrupt handler for 7 or 8 bits data word length .
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
- * @param huart UART handle.
- * @retval HAL status
+ * @param huart UART handle.
+ * @retval None
*/
-HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
{
- uint16_t* tmp;
-
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
- if(huart->TxXferCount == 0U)
+ if (huart->TxXferCount == 0U)
{
/* Disable the UART Transmit Data Register Empty Interrupt */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
/* Enable the UART Transmit Complete Interrupt */
SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
- return HAL_OK;
}
else
{
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pTxBuffPtr;
- huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- huart->pTxBuffPtr += 2U;
- }
- else
- {
- huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
+ huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+ huart->pTxBuffPtr++;
huart->TxXferCount--;
-
- return HAL_OK;
}
}
- else
- {
- return HAL_BUSY;
- }
}
/**
+ * @brief TX interrrupt handler for 9 bits data word length.
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Transmit_IT().
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+
+ /* Check that a Tx process is ongoing */
+ if (huart->gState == HAL_UART_STATE_BUSY_TX)
+ {
+ if (huart->TxXferCount == 0U)
+ {
+ /* Disable the UART Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ }
+ else
+ {
+ tmp = (uint16_t *) huart->pTxBuffPtr;
+ huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+ huart->pTxBuffPtr += 2U;
+ huart->TxXferCount--;
+ }
+ }
+}
+
+
+/**
* @brief Wrap up transmission in non-blocking mode.
* @param huart pointer to a UART_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
- * @retval HAL status
+ * the configuration information for the specified UART module.
+ * @retval None
*/
-HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
@@ -2720,40 +3609,89 @@
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
- HAL_UART_TxCpltCallback(huart);
+ /* Cleat TxISR function pointer */
+ huart->TxISR = NULL;
- return HAL_OK;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Tx complete callback*/
+ huart->TxCpltCallback(huart);
+#else
+ /*Call legacy weak Tx complete callback*/
+ HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
/**
- * @brief Receive an amount of data in interrupt mode.
- * @note Function is called under interruption only, once
- * interruptions have been enabled by HAL_UART_Receive_IT()
- * @param huart UART handle.
- * @retval HAL status
+ * @brief RX interrrupt handler for 7 or 8 bits data word length .
+ * @param huart UART handle.
+ * @retval None
*/
-HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
- uint16_t* tmp;
- uint16_t uhMask = huart->Mask;
+ uint16_t uhMask = huart->Mask;
uint16_t uhdata;
/* Check that a Rx process is ongoing */
- if(huart->RxState == HAL_UART_STATE_BUSY_RX)
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- tmp = (uint16_t*) huart->pRxBuffPtr ;
- *tmp = (uint16_t)(uhdata & uhMask);
- huart->pRxBuffPtr +=2U;
- }
- else
- {
- *huart->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)uhMask);
- }
+ *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+ huart->pRxBuffPtr++;
+ huart->RxXferCount--;
- if(--huart->RxXferCount == 0U)
+ if (huart->RxXferCount == 0U)
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ }
+ else
+ {
+ /* Clear RXNE interrupt flag */
+ __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+ }
+}
+
+/**
+ * @brief RX interrrupt handler for 9 bits data word length .
+ * @note Function is called under interruption only, once
+ * interruptions have been enabled by HAL_UART_Receive_IT()
+ * @param huart UART handle.
+ * @retval None
+ */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+ uint16_t *tmp;
+ uint16_t uhMask = huart->Mask;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+ {
+ uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+ tmp = (uint16_t *) huart->pRxBuffPtr ;
+ *tmp = (uint16_t)(uhdata & uhMask);
+ huart->pRxBuffPtr += 2U;
+ huart->RxXferCount--;
+
+ if (huart->RxXferCount == 0U)
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
@@ -2764,22 +3702,26 @@
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
-
- return HAL_OK;
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
-
- return HAL_OK;
}
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
-
- return HAL_BUSY;
}
}
+
/**
* @}
*/
diff --git a/Src/stm32f0xx_hal_uart_ex.c b/Src/stm32f0xx_hal_uart_ex.c
index d9fcb1f..b8fbf04 100644
--- a/Src/stm32f0xx_hal_uart_ex.c
+++ b/Src/stm32f0xx_hal_uart_ex.c
@@ -19,34 +19,17 @@
(#) For the UART RS485 Driver Enable mode, initialize the UART registers
by calling the HAL_RS485Ex_Init() API.
-
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -67,41 +50,42 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+#if defined(USART_CR1_UESM)
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-
+#endif /* USART_CR1_UESM */
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
+/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions
* @{
*/
-/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Extended Initialization and Configuration Functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
- ==============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous mode.
(+) For the asynchronous mode the parameters below can be configured:
(++) Baud Rate
- (++) Word Length (Fixed to 8-bits only for LIN mode)
+ (++) Word Length
(++) Stop Bit
- (++) Parity
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
(++) Hardware flow control
(++) Receiver/transmitter modes
(++) Over Sampling Method
@@ -115,76 +99,61 @@
(++) MSB first on communication line
(++) auto Baud rate detection
[..]
- The HAL_LIN_Init() and HAL_RS485Ex_Init() APIs follows respectively the LIN and
- the UART RS485 mode configuration procedures (details for the procedures are
- available in reference manual).
+ The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+ procedures (details for the procedures are available in reference manual).
@endverbatim
+
+ Depending on the frame length defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit), the possible UART formats are listed in the
+ following table.
+
+ Table 1. UART frame format.
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | UART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
* @{
*/
-/*
- Additional Table: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible UART frame formats are as listed in the following table:
-
- Table 1. UART frame format.
- +-----------------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |-------------------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | UART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
-*/
-
/**
* @brief Initialize the RS485 Driver enable feature according to the specified
* parameters in the UART_InitTypeDef and creates the associated handle.
- * @param huart UART handle.
- * @param Polarity select the driver enable polarity.
- * This parameter can be one of the following values:
+ * @param huart UART handle.
+ * @param Polarity Select the driver enable polarity.
+ * This parameter can be one of the following values:
* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
- * @param AssertionTime Driver Enable assertion time:
- * 5-bit value defining the time between the activation of the DE (Driver Enable)
- * signal and the beginning of the start bit. It is expressed in sample time
- * units (1/8 or 1/16 bit time, depending on the oversampling rate)
- * @param DeassertionTime Driver Enable deassertion time:
- * 5-bit value defining the time between the end of the last stop bit, in a
- * transmitted message, and the de-activation of the DE (Driver Enable) signal.
- * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
- * oversampling rate).
+ * @param AssertionTime Driver Enable assertion time:
+ * 5-bit value defining the time between the activation of the DE (Driver Enable)
+ * signal and the beginning of the start bit. It is expressed in sample time
+ * units (1/8 or 1/16 bit time, depending on the oversampling rate)
+ * @param DeassertionTime Driver Enable deassertion time:
+ * 5-bit value defining the time between the end of the last stop bit, in a
+ * transmitted message, and the de-activation of the DE (Driver Enable) signal.
+ * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+ * oversampling rate).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+ uint32_t DeassertionTime)
{
- uint32_t temp = 0x0U;
+ uint32_t temp;
/* Check the UART handle allocation */
- if(huart == NULL)
+ if (huart == NULL)
{
return HAL_ERROR;
}
@@ -200,91 +169,25 @@
/* Check the Driver Enable deassertion time */
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
- if(huart->gState == HAL_UART_STATE_RESET)
+ if (huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ UART_InitCallbacksToDefault(huart);
+
+ if (huart->MspInitCallback == NULL)
+ {
+ huart->MspInitCallback = HAL_UART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ huart->MspInitCallback(huart);
+#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_UART_MspInit(huart);
- }
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the UART Communication parameters */
- if (UART_SetConfig(huart) == HAL_ERROR)
- {
- return HAL_ERROR;
- }
-
- if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- {
- UART_AdvFeatureConfig(huart);
- }
-
- /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
-
- /* Set the Driver Enable polarity */
- MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
-
- /* Set the Driver Enable assertion and deassertion times */
- temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
- MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
-/**
- * @brief Initialize the LIN mode according to the specified
- * parameters in the UART_InitTypeDef and creates the associated handle .
- * @param huart UART handle.
- * @param BreakDetectLength specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
- * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the LIN UART instance */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
- /* Check the Break detection length parameter */
- assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
- /* LIN mode limited to 16-bit oversampling only */
- if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
- {
- return HAL_ERROR;
- }
- /* LIN mode limited to 8-bit data length */
- if(huart->Init.WordLength != UART_WORDLENGTH_8B)
- {
- return HAL_ERROR;
- }
-
- if(huart->gState == HAL_UART_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK */
- HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
@@ -303,17 +206,16 @@
UART_AdvFeatureConfig(huart);
}
- /* In LIN mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+ /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+ /* Set the Driver Enable polarity */
+ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
- /* Set the USART LIN Break detection length. */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+ /* Set the Driver Enable assertion and deassertion times */
+ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
@@ -321,33 +223,33 @@
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
/**
* @}
*/
-/** @defgroup UARTEx_Exported_Functions_Group2 Extended IO operation function
- * @brief Extended UART Interrupt handling function
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+ * @brief Extended functions
*
@verbatim
===============================================================================
- ##### IO operation function #####
+ ##### IO operation functions #####
===============================================================================
- [..]
- This subsection provides function to handle Wake up interrupt call-back.
-
- (#) Callback provided in No_Blocking mode:
- (++) HAL_UARTEx_WakeupCallback()
+ This subsection provides a set of Wakeup and FIFO mode related callback functions.
+#if defined(USART_CR1_UESM)
+ (#) Wakeup from Stop mode Callback:
+ (+) HAL_UARTEx_WakeupCallback()
+
+#endif
@endverbatim
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+#if defined(USART_CR1_UESM)
/**
- * @brief UART wakeup from Stop mode callback.
- * @param huart UART handle.
+ * @brief UART wakeup from Stop mode callback.
+ * @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
@@ -359,50 +261,90 @@
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
-#endif /*!defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)*/
+
+#endif /* USART_CR1_UESM */
/**
* @}
*/
-
-/** @defgroup UARTEx_Exported_Functions_Group3 Extended Peripheral Control functions
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
- [..]
- This subsection provides extended functions allowing to control the UART.
- (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API sets Wakeup from Stop mode interrupt flag selection
- (+) HAL_UARTEx_EnableStopMode() API allows the UART to wake up the MCU from Stop mode as
- long as UART clock is HSI or LSE
- (+) HAL_UARTEx_DisableStopMode() API disables the above feature
+ [..] This section provides the following functions:
(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
detection length to more than 4 bits for multiprocessor address mark wake up.
- (+) HAL_LIN_SendBreak() API transmits the break characters
-
+#if defined(USART_CR1_UESM)
+ (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+ trigger: address match, Start Bit detection or RXNE bit status.
+ (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+ (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+#endif
@endverbatim
* @{
*/
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
+/**
+ * @brief By default in multiprocessor mode, when the wake up method is set
+ * to address mark, the UART handles only 4-bit long addresses detection;
+ * this API allows to enable longer addresses detection (6-, 7- or 8-bit
+ * long).
+ * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+ * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+ * @param huart UART handle.
+ * @param AddressLength This parameter can be one of the following values:
+ * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+ * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+ /* Check the UART handle allocation */
+ if (huart == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the address length parameter */
+ assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+ huart->gState = HAL_UART_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_UART_DISABLE(huart);
+
+ /* Set the address length */
+ MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+
+ /* TEACK and/or REACK to check before moving huart->gState to Ready */
+ return (UART_CheckIdleState(huart));
+}
+
+#if defined(USART_CR1_UESM)
/**
* @brief Set Wakeup from Stop mode interrupt flag selection.
- * @param huart UART handle.
- * @param WakeUpSelection address match, Start Bit detection or RXNE bit status.
- * This parameter can be one of the following values:
- * @arg @ref UART_WAKEUP_ON_ADDRESS
- * @arg @ref UART_WAKEUP_ON_STARTBIT
- * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+ * @note It is the application responsibility to enable the interrupt used as
+ * usart_wkup interrupt source before entering low-power mode.
+ * @param huart UART handle.
+ * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+ * This parameter can be one of the following values:
+ * @arg @ref UART_WAKEUP_ON_ADDRESS
+ * @arg @ref UART_WAKEUP_ON_STARTBIT
+ * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* check the wake-up from stop mode UART instance */
assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
@@ -432,7 +374,7 @@
tickstart = HAL_GetTick();
/* Wait until REACK flag is set */
- if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
{
status = HAL_TIMEOUT;
}
@@ -448,28 +390,20 @@
return status;
}
-
/**
* @brief Enable UART Stop Mode.
- * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+ * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
{
- /* Check parameter */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
-
/* Process Locked */
__HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
/* Set UESM bit */
SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
- huart->gState = HAL_UART_STATE_READY;
-
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -483,94 +417,19 @@
*/
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
{
- /* Check parameter */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
-
/* Process Locked */
__HAL_LOCK(huart);
- huart->gState = HAL_UART_STATE_BUSY;
-
/* Clear UESM bit */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
- huart->gState = HAL_UART_STATE_READY;
-
/* Process Unlocked */
__HAL_UNLOCK(huart);
return HAL_OK;
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-/**
- * @brief By default in multiprocessor mode, when the wake up method is set
- * to address mark, the UART handles only 4-bit long addresses detection;
- * this API allows to enable longer addresses detection (6-, 7- or 8-bit
- * long).
- * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
- * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
- * @param huart UART handle.
- * @param AddressLength this parameter can be one of the following values:
- * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
- * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
-{
- /* Check the UART handle allocation */
- if(huart == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the address length parameter */
- assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- /* Set the address length */
- MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
-
- /* TEACK and/or REACK to check before moving huart->gState to Ready */
- return (UART_CheckIdleState(huart));
-}
-
-
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
-/**
- * @brief Transmit break characters.
- * @param huart UART handle.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
- /* Check the parameters */
- assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
- /* Process Locked */
- __HAL_LOCK(huart);
-
- huart->gState = HAL_UART_STATE_BUSY;
-
- /* Send break characters */
- huart->Instance->RQR |= UART_SENDBREAK_REQUEST;
-
- huart->gState = HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_OK;
-}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
-
+#endif /* USART_CR1_UESM */
/**
* @}
*/
@@ -582,18 +441,16 @@
/** @addtogroup UARTEx_Private_Functions
* @{
*/
+#if defined(USART_CR1_UESM)
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/**
* @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
- * @param huart UART handle.
+ * @param huart UART handle.
* @param WakeUpSelection UART wake up from stop mode parameters.
* @retval None
*/
static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
{
- /* Check parmeters */
- assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
/* Set the USART address length */
@@ -602,7 +459,7 @@
/* Set the USART address node */
MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+#endif /* USART_CR1_UESM */
/**
* @}
diff --git a/Src/stm32f0xx_hal_usart.c b/Src/stm32f0xx_hal_usart.c
index ad262a9..4ef04b0 100644
--- a/Src/stm32f0xx_hal_usart.c
+++ b/Src/stm32f0xx_hal_usart.c
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter
+ * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
* Peripheral (USART).
* + Initialization and de-initialization functions
* + IO operation functions
@@ -41,102 +41,92 @@
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
- flow control and Mode (Receiver/Transmitter) in the husart handle Init structure.
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
+ (Receiver/Transmitter) in the husart handle Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
by calling the customized HAL_USART_MspInit(&husart) API.
- (#) Three operation modes are available within this driver :
+ [..]
+ (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
+ HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
+ HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
+ ##### Callback registration #####
+ ==================================
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_USART_ErrorCallback
+ [..]
+ The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
- *** DMA mode IO operation ***
- ==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_USART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_USART_DMAPause()
- (+) Resume the DMA Transfer using HAL_USART_DMAResume()
- (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+ [..]
+ Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
+ Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
- *** USART HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in USART HAL driver.
+ [..]
+ Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function.
+ @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+ This function allows to reset following callbacks:
+ (+) TxHalfCpltCallback : Tx Half Complete Callback.
+ (+) TxCpltCallback : Tx Complete Callback.
+ (+) RxHalfCpltCallback : Rx Half Complete Callback.
+ (+) RxCpltCallback : Rx Complete Callback.
+ (+) TxRxCpltCallback : Tx Rx Complete Callback.
+ (+) ErrorCallback : Error Callback.
+ (+) AbortCpltCallback : Abort Complete Callback.
+ (+) MspInitCallback : USART MspInit.
+ (+) MspDeInitCallback : USART MspDeInit.
- (+) __HAL_USART_ENABLE: Enable the USART peripheral
- (+) __HAL_USART_DISABLE: Disable the USART peripheral
- (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
- (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
- (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
- (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
+ [..]
+ By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+ all callbacks are set to the corresponding weak (surcharged) functions:
+ examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+ Exception done for MspInit and MspDeInit functions that are respectively
+ reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
+ and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
- [..]
- (@) You can refer to the USART HAL driver header file for more useful macros
- [..]
- (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
- HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
- HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
+ [..]
+ Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
+ or @ref HAL_USART_Init() function.
+
+ [..]
+ When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak (surcharged) callbacks are used.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -160,12 +150,15 @@
/** @defgroup USART_Private_Constants USART Private Constants
* @{
*/
-#define USART_DUMMY_DATA ((uint16_t) 0xFFFFU) /*!< USART transmitted dummy data */
-#define USART_TEACK_REACK_TIMEOUT ( 1000U) /*!< USART TX or RX enable acknowledge time-out value */
+#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */
+#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */
#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \
USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */
+
+#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */
+#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */
/**
* @}
*/
@@ -176,6 +169,9 @@
/** @addtogroup USART_Private_Functions
* @{
*/
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
static void USART_EndTransfer(USART_HandleTypeDef *husart);
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -185,13 +181,17 @@
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout);
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart);
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart);
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart);
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart);
+
+
/**
* @}
*/
@@ -216,7 +216,8 @@
(++) Baud Rate
(++) Word Length
(++) Stop Bit
- (++) Parity
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
(++) USART polarity
(++) USART phase
(++) USART LastBit
@@ -227,46 +228,42 @@
procedure (details for the procedure are available in reference manual).
@endverbatim
+
+ Depending on the frame length either defined by the M1 and M0 bits (7-bit,
+ 8-bit or 9-bit) or by the M bit (8-bits or 9-bits), the possible USART formats
+ are listed in the following table.
+
+ Table 1. USART frame format.
+ +-----------------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 0 | | SB | 8-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7-bit data | PB | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9-bit data | STB | |
+ |-------------------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8-bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+ +-----------------------------------------------------------------------+
+ | M1 bit | M0 bit | PCE bit | USART frame |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 0 | | SB | 7 bit data | STB | |
+ |---------|---------|-----------|---------------------------------------|
+ | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
+ +-----------------------------------------------------------------------+
+
* @{
*/
-/*
- Additional Table: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- According to device capability (support or not of 7-bit word length),
- frame length is either defined by the M bit (8-bits or 9-bits)
- or by the M1 and M0 bits (7-bit, 8-bit or 9-bit).
- Possible USART frame formats are as listed in the following table:
-
- Table 1. USART frame format.
- +-----------------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |-------------------|-----------|---------------------------------------|
- | 0 | 0 | | SB | 8-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7-bit data | PB | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9-bit data | STB | |
- |-------------------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8-bit data | PB | STB | |
- +-----------------------------------------------------------------------+
- | M1 bit | M0 bit | PCE bit | USART frame |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 0 | | SB | 7 bit data | STB | |
- |---------|---------|-----------|---------------------------------------|
- | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | |
- +-----------------------------------------------------------------------+
-
-*/
-
/**
* @brief Initialize the USART mode according to the specified
* parameters in the USART_InitTypeDef and initialize the associated handle.
@@ -276,7 +273,7 @@
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
- if(husart == NULL)
+ if (husart == NULL)
{
return HAL_ERROR;
}
@@ -284,13 +281,25 @@
/* Check the parameters */
assert_param(IS_USART_INSTANCE(husart->Instance));
- if(husart->State == HAL_USART_STATE_RESET)
+ if (husart->State == HAL_USART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
husart->Lock = HAL_UNLOCKED;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ USART_InitCallbacksToDefault(husart);
+
+ if (husart->MspInitCallback == NULL)
+ {
+ husart->MspInitCallback = HAL_USART_MspInit;
+ }
+
+ /* Init the low level hardware */
+ husart->MspInitCallback(husart);
+#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_USART_MspInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
husart->State = HAL_USART_STATE_BUSY;
@@ -306,23 +315,24 @@
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit (if LIN is supported) in the USART_CR2 register
- - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
-#if defined (USART_CR2_LINEN)
+ - SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register.
+ */
+#if defined (USART_CR2_LINEN)
husart->Instance->CR2 &= ~USART_CR2_LINEN;
-#endif
-#if defined (USART_CR3_SCEN)
-#if defined (USART_CR3_IREN)
+#endif /* USART_CR2_LINEN */
+#if defined (USART_CR3_SCEN)
+#if defined (USART_CR3_IREN)
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
#else
husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL);
-#endif
+#endif /* USART_CR3_IREN */
#else
-#if defined (USART_CR3_IREN)
+#if defined (USART_CR3_IREN)
husart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN);
#else
husart->Instance->CR3 &= ~(USART_CR3_HDSEL);
-#endif
-#endif
+#endif /* USART_CR3_IREN */
+#endif /* USART_CR3_SCEN */
/* Enable the Peripheral */
__HAL_USART_ENABLE(husart);
@@ -332,14 +342,14 @@
}
/**
- * @brief DeInitialize the USART peripheral.
+ * @brief DeInitialize the USART peripheral.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
{
/* Check the USART handle allocation */
- if(husart == NULL)
+ if (husart == NULL)
{
return HAL_ERROR;
}
@@ -353,8 +363,17 @@
husart->Instance->CR2 = 0x0U;
husart->Instance->CR3 = 0x0U;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ if (husart->MspDeInitCallback == NULL)
+ {
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ husart->MspDeInitCallback(husart);
+#else
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_RESET;
@@ -395,12 +414,244 @@
*/
}
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User USART Callback
+ * To be used instead of the weak predefined callback
+ * @param husart usart handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval HAL status
++ */
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+ pUSART_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (husart->State == HAL_USART_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = pCallback;
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = pCallback;
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = pCallback;
+ break;
+
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (husart->State == HAL_USART_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = pCallback;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+
+/**
+ * @brief Unregister an UART Callback
+ * UART callaback is redirected to the weak predefined callback
+ * @param husart uart handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+ * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+ * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+ * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID
+ * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+ * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(husart);
+
+ if (HAL_USART_STATE_READY == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_TX_HALFCOMPLETE_CB_ID :
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ break;
+
+ case HAL_USART_TX_COMPLETE_CB_ID :
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ break;
+
+ case HAL_USART_RX_HALFCOMPLETE_CB_ID :
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ break;
+
+ case HAL_USART_RX_COMPLETE_CB_ID :
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ break;
+
+ case HAL_USART_TX_RX_COMPLETE_CB_ID :
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ break;
+
+ case HAL_USART_ERROR_CB_ID :
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
+
+ case HAL_USART_ABORT_COMPLETE_CB_ID :
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ break;
+
+
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if (HAL_USART_STATE_RESET == husart->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_USART_MSPINIT_CB_ID :
+ husart->MspInitCallback = HAL_USART_MspInit;
+ break;
+
+ case HAL_USART_MSPDEINIT_CB_ID :
+ husart->MspDeInitCallback = HAL_USART_MspDeInit;
+ break;
+
+ default :
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Update the error code */
+ husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK;
+
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(husart);
+
+ return status;
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
+
/**
* @}
*/
/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
+ * @brief USART Transmit and Receive functions
*
@verbatim
===============================================================================
@@ -412,39 +663,41 @@
[..] The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
- (#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
- will be executed respectively at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+ [..]
- (#) Blocking mode APIs are :
- (++) HAL_USART_Transmit()in simplex mode
+ (#) There are two modes of transfer:
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
+ or DMA, These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected
+
+ (#) Blocking mode API's are :
+ (++) HAL_USART_Transmit() in simplex mode
(++) HAL_USART_Receive() in full duplex receive only
(++) HAL_USART_TransmitReceive() in full duplex mode
- (#) No-Blocking mode APIs with Interrupt are :
- (++) HAL_USART_Transmit_IT()in simplex mode
+ (#) Non-Blocking mode API's with Interrupt are :
+ (++) HAL_USART_Transmit_IT() in simplex mode
(++) HAL_USART_Receive_IT() in full duplex receive only
- (++) HAL_USART_TransmitReceive_IT()in full duplex mode
+ (++) HAL_USART_TransmitReceive_IT() in full duplex mode
(++) HAL_USART_IRQHandler()
- (#) No-Blocking mode APIs with DMA are :
- (++) HAL_USART_Transmit_DMA()in simplex mode
+ (#) No-Blocking mode API's with DMA are :
+ (++) HAL_USART_Transmit_DMA() in simplex mode
(++) HAL_USART_Receive_DMA() in full duplex receive only
(++) HAL_USART_TransmitReceive_DMA() in full duplex mode
(++) HAL_USART_DMAPause()
(++) HAL_USART_DMAResume()
(++) HAL_USART_DMAStop()
- (#) A set of Transfer Complete Callbacks are provided in Non-Blocking mode:
+ (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
(++) HAL_USART_TxCpltCallback()
(++) HAL_USART_RxCpltCallback()
(++) HAL_USART_TxHalfCpltCallback()
@@ -461,7 +714,7 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
@@ -476,34 +729,38 @@
/**
* @brief Simplex send an amount of data in blocking mode.
- * @param husart USART handle.
- * @param pTxData Pointer to data buffer.
- * @param Size Amount of data to be sent.
- * @param Timeout Timeout duration.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+ * @param husart USART handle.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0U;
- uint32_t tickstart = 0U;
+ uint8_t *ptxdata8bits;
+ uint16_t *ptxdata16bits;
+ uint32_t tickstart;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR will be
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if((((uint32_t)pTxData)&1U) != 0U)
+ if ((((uint32_t)pTxData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -521,31 +778,54 @@
husart->TxXferSize = Size;
husart->TxXferCount = Size;
- /* Check the remaining data to be sent */
- while(husart->TxXferCount > 0)
+ /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- husart->TxXferCount--;
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ ptxdata8bits = NULL;
+ ptxdata16bits = (uint16_t *) pTxData;
+ }
+ else
+ {
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ }
+
+ /* Check the remaining data to be sent */
+ while (husart->TxXferCount > 0U)
+ {
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if (ptxdata8bits == NULL)
{
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- pTxData += 2U;
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU);
+ ptxdata16bits++;
}
else
{
- husart->Instance->TDR = (*pTxData++ & (uint8_t)0xFFU);
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU);
+ ptxdata8bits++;
}
+
+ husart->TxXferCount--;
}
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
+ /* Clear Transmission Complete Flag */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+#if defined(USART_RQR_TXFRQ)
+ __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST);
+#endif /* USART_RQR_TXFRQ */
+
/* At end of Tx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
@@ -562,36 +842,40 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart USART handle.
- * @param pRxData Pointer to data buffer.
- * @param Size Amount of data to be received.
- * @param Timeout Timeout duration.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * @param husart USART handle.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0U;
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0U))
+ if ((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be received from RDR will be
+ /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if((((uint32_t)pRxData)&1U) != 0U)
+ if ((((uint32_t)pRxData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -613,39 +897,55 @@
USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
- /* as long as data have to be received */
- while(husart->RxXferCount > 0U)
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- husart->RxXferCount--;
+ prxdata8bits = NULL;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ prxdata16bits = NULL;
+ }
- /* Wait until TC flag is set to send dummy byte in order to generate the
- * clock for the slave to send data.
- * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
- * can be written for all the cases. */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ /* as long as data have to be received */
+ while (husart->RxXferCount > 0U)
+ {
{
- return HAL_TIMEOUT;
+ /* Wait until TXE flag is set to send dummy byte in order to generate the
+ * clock for the slave to send data.
+ * Whatever the frame length (7, 8 or 9-bit long), the same dummy value
+ * can be written for all the cases. */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF);
}
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FFU);
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ if (prxdata8bits == NULL)
{
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2;
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
}
else
{
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
}
+
+ husart->RxXferCount--;
+
}
+
/* At end of Rx process, restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
@@ -661,37 +961,45 @@
}
/**
- * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
- * @param Timeout Timeout duration.
+ * @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
* (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0U;
+ uint8_t *prxdata8bits;
+ uint16_t *prxdata16bits;
+ uint8_t *ptxdata8bits;
+ uint16_t *ptxdata16bits;
uint16_t uhMask;
- uint32_t tickstart = 0U;
+ uint16_t rxdatacount;
+ uint32_t tickstart;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
+ /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
+ if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
{
return HAL_ERROR;
}
@@ -715,44 +1023,91 @@
USART_MASK_COMPUTATION(husart);
uhMask = husart->Mask;
- /* Check the remain data to be sent */
- while(husart->TxXferCount > 0U)
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
+ prxdata8bits = NULL;
+ ptxdata8bits = NULL;
+ ptxdata16bits = (uint16_t *) pTxData;
+ prxdata16bits = (uint16_t *) pRxData;
+ }
+ else
+ {
+ prxdata8bits = pRxData;
+ ptxdata8bits = pTxData;
+ ptxdata16bits = NULL;
+ prxdata16bits = NULL;
+ }
+
+ if (husart->TxXferCount == 0x01U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
+ }
+
husart->TxXferCount--;
- husart->RxXferCount--;
+ }
- /* Wait until TC flag is set to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ /* Check the remain data to be sent */
+ /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ rxdatacount = husart->RxXferCount;
+ while ((husart->TxXferCount > 0U) || (rxdatacount > 0U))
+ {
+ if (husart->TxXferCount > 0U)
{
- return HAL_TIMEOUT;
- }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pTxData;
- husart->Instance->TDR = (*tmp & uhMask);
- pTxData += 2U;
- }
- else
- {
- husart->Instance->TDR = (*pTxData++ & (uint8_t)uhMask);
+ /* Wait until TXE flag is set to send data */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
+ if (ptxdata8bits == NULL)
+ {
+ husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask);
+ ptxdata16bits++;
+ }
+ else
+ {
+ husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU));
+ ptxdata8bits++;
+ }
+
+ husart->TxXferCount--;
}
- /* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ if (husart->RxXferCount > 0U)
{
- return HAL_TIMEOUT;
- }
+ /* Wait for RXNE Flag */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
+ return HAL_TIMEOUT;
+ }
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) pRxData ;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- pRxData +=2U;
+ if (prxdata8bits == NULL)
+ {
+ *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask);
+ prxdata16bits++;
+ }
+ else
+ {
+ *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU));
+ prxdata8bits++;
+ }
+
+ husart->RxXferCount--;
}
- else
- {
- *pRxData++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
+ rxdatacount = husart->RxXferCount;
}
/* At end of TxRx process, restore husart->State to Ready */
@@ -771,30 +1126,33 @@
/**
* @brief Send an amount of data in interrupt mode.
- * @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR will be
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if((((uint32_t)pTxData)&1U) != 0U)
+ if ((((uint32_t)pTxData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -803,12 +1161,13 @@
/* Process Locked */
__HAL_LOCK(husart);
- husart->pTxBuffPtr = pTxData;
- husart->TxXferSize = Size;
+ husart->pTxBuffPtr = pTxData;
+ husart->TxXferSize = Size;
husart->TxXferCount = Size;
+ husart->TxISR = NULL;
husart->ErrorCode = HAL_USART_ERROR_NONE;
- husart->State = HAL_USART_STATE_BUSY_TX;
+ husart->State = HAL_USART_STATE_BUSY_TX;
/* The USART Error Interrupts: (Frame error, noise error, overrun error)
are not managed by the USART Transmit Process to avoid the overrun interrupt
@@ -816,11 +1175,23 @@
to benefit for the frame error and noise interrupts the usart mode should be
configured only for transmit "USART_MODE_TX" */
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ {
+ /* Set the Tx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ }
- /* Enable the USART Transmit Data Register Empty Interrupt */
- __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
+ }
return HAL_OK;
}
@@ -831,32 +1202,36 @@
}
/**
- * @brief Receive an amount of data in interrupt mode.
+ * @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0U))
+ if ((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
- should be aligned on a u16 frontier, as data to be received from RDR will be
+ /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data to be received from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if((((uint32_t)pRxData)&1U) != 0U)
+ if ((((uint32_t)pRxData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -865,32 +1240,43 @@
/* Process Locked */
__HAL_LOCK(husart);
- husart->pRxBuffPtr = pRxData;
- husart->RxXferSize = Size;
+ husart->pRxBuffPtr = pRxData;
+ husart->RxXferSize = Size;
husart->RxXferCount = Size;
+ husart->RxISR = NULL;
USART_MASK_COMPUTATION(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- /* Enable the USART Parity Error and Data Register not empty Interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
-
/* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Send dummy byte in order to generate the clock for the Slave to send the next data */
- if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x01FFU);
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->RxISR = USART_RxISR_8BIT;
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error and Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
- else
+
{
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
+ /* Send dummy data in order to generate the clock for the Slave to send the next data.
+ */
+ {
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
}
return HAL_OK;
@@ -902,33 +1288,37 @@
}
/**
- * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
* (as sent/received data will be handled using u16 pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
- should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
+ /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
+ should be aligned on a u16 frontier, as data to be filled into TDR/retrieved from RDR will be
handled through a u16 cast. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
+ if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
{
return HAL_ERROR;
}
@@ -950,17 +1340,30 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ {
+ if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
+ {
+ husart->TxISR = USART_TxISR_16BIT;
+ husart->RxISR = USART_RxISR_16BIT;
+ }
+ else
+ {
+ husart->TxISR = USART_TxISR_8BIT;
+ husart->RxISR = USART_RxISR_8BIT;
+ }
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Process Locked */
+ __HAL_UNLOCK(husart);
- /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Enable the USART Transmit Data Register Empty Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+ /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+
+ /* Enable the USART Transmit Data Register Empty Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
+ }
return HAL_OK;
}
@@ -971,33 +1374,37 @@
}
/**
- * @brief Send an amount of data in DMA mode.
- * @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits)
* (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
- uint32_t *tmp=0U;
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pTxData buffer provided as input paramter
- should be aligned on a u16 frontier, as data copy into TDR will be
+ /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy into TDR will be
handled by DMA from a u16 frontier. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if((((uint32_t)pTxData)&1U) != 0U)
+ if ((((uint32_t)pTxData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -1013,30 +1420,49 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
- /* Set the USART DMA transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+ if (husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
- /* Set the DMA error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ /* Enable the USART transmit DMA channel */
+ tmp = (uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
- /* Clear the TC flag in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+ if (status == HAL_OK)
+ {
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- return HAL_OK;
+ return HAL_OK;
+ }
+ else
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1045,35 +1471,41 @@
}
/**
- * @brief Receive an amount of data in DMA mode.
- * @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @brief Receive an amount of data in DMA mode.
+ * @note When the USART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pRxData.
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @param husart USART handle.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
- uint32_t *tmp;
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t *tmp = (uint32_t *)&pRxData;
/* Check that a Rx process is not already ongoing */
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0U))
+ if ((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pRxData buffer provided as input paramter
- should be aligned on a u16 frontier, as data copy from RDR will be
+ /* In case of 9bits/No Parity transfer, pRxData buffer provided as input parameter
+ should be aligned on a u16 frontier, as data copy from RDR will be
handled by DMA from a u16 frontier. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if((((uint32_t)pRxData)&1U) != 0U)
+ if ((((uint32_t)pRxData) & 1U) != 0U)
{
return HAL_ERROR;
}
@@ -1090,46 +1522,78 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+ if (husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+ /* Enable the USART receive DMA channel */
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
+ }
- /* Enable the USART transmit DMA channel: the transmit channel is used in order
- to generate in the non-blocking mode the clock to the slave device,
- this mode isn't a simplex receive mode but a full-duplex receive mode */
- /* Set the USART DMA Tx Complete and Error callback to Null */
- husart->hdmatx->XferErrorCallback = NULL;
- husart->hdmatx->XferHalfCpltCallback = NULL;
- husart->hdmatx->XferCpltCallback = NULL;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ {
+ /* Enable the USART transmit DMA channel: the transmit channel is used in order
+ to generate in the non-blocking mode the clock to the slave device,
+ this mode isn't a simplex receive mode but a full-duplex receive mode */
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Set the USART DMA Tx Complete and Error callback to Null */
+ if (husart->hdmatx != NULL)
+ {
+ husart->hdmatx->XferErrorCallback = NULL;
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
+ }
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- return HAL_OK;
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ return HAL_OK;
+ }
+ else
+ {
+ if (husart->hdmarx != NULL)
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* No need to check on error code */
+ UNUSED(status);
+
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1138,34 +1602,40 @@
}
/**
- * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be received/sent.
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffers containing data to be sent/received, should be aligned on a half word frontier (16 bits)
* (as sent/received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pTxData and pRxData.
+ * @param husart USART handle.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+ uint16_t Size)
{
+ HAL_StatusTypeDef status;
uint32_t *tmp;
- if(husart->State == HAL_USART_STATE_READY)
+ if (husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input paramter
- should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be
+ /* In case of 9bits/No Parity transfer, pTxData and pRxData buffers provided as input parameter
+ should be aligned on a u16 frontier, as data copy to/from TDR/RDR will be
handled by DMA from a u16 frontier. */
if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
{
- if(((((uint32_t)pTxData)&1U) != 0U) || ((((uint32_t)pRxData)&1U) != 0U))
+ if (((((uint32_t)pTxData) & 1U) != 0U) || ((((uint32_t)pRxData) & 1U) != 0U))
{
return HAL_ERROR;
}
@@ -1182,53 +1652,87 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX_RX;
- /* Set the USART DMA Rx transfer complete callback */
- husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
+ if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL))
+ {
+ /* Set the USART DMA Rx transfer complete callback */
+ husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
- /* Set the USART DMA Tx transfer complete callback */
- husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
+ /* Set the USART DMA Tx transfer complete callback */
+ husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
- /* Set the USART DMA Half transfer complete callback */
- husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
+ /* Set the USART DMA Half transfer complete callback */
+ husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
- /* Set the USART DMA Tx transfer error callback */
- husart->hdmatx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Tx transfer error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
- /* Set the USART DMA Rx transfer error callback */
- husart->hdmarx->XferErrorCallback = USART_DMAError;
+ /* Set the USART DMA Rx transfer error callback */
+ husart->hdmarx->XferErrorCallback = USART_DMAError;
- /* Enable the USART receive DMA channel */
- tmp = (uint32_t*)&pRxData;
- HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t*)tmp, Size);
+ /* Enable the USART receive DMA channel */
+ tmp = (uint32_t *)&pRxData;
+ status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
- /* Enable the USART transmit DMA channel */
- tmp = (uint32_t*)&pTxData;
- HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ /* Enable the USART transmit DMA channel */
+ if (status == HAL_OK)
+ {
+ tmp = (uint32_t *)&pTxData;
+ status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ if (status == HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- /* Enable the USART Parity Error Interrupt */
- SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Clear the TC flag in the ICR register */
- __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
+ /* Clear the TC flag in the ICR register */
+ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- return HAL_OK;
+ return HAL_OK;
+ }
+ else
+ {
+ if (husart->hdmarx != NULL)
+ {
+ status = HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* No need to check on error code */
+ UNUSED(status);
+
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Restore husart->State to ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ return HAL_ERROR;
+ }
}
else
{
@@ -1237,23 +1741,25 @@
}
/**
- * @brief Pause the DMA Transfer.
+ * @brief Pause the DMA Transfer.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
{
+ const HAL_USART_StateTypeDef state = husart->State;
+
/* Process Locked */
__HAL_LOCK(husart);
- if( (husart->State == HAL_USART_STATE_BUSY_TX) &&
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)))
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) &&
+ (state == HAL_USART_STATE_BUSY_TX))
{
/* Disable the USART DMA Tx request */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
- else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
- (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
@@ -1270,6 +1776,10 @@
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
}
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1278,22 +1788,24 @@
}
/**
- * @brief Resume the DMA Transfer.
+ * @brief Resume the DMA Transfer.
* @param husart USART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
{
+ const HAL_USART_StateTypeDef state = husart->State;
+
/* Process Locked */
__HAL_LOCK(husart);
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (state == HAL_USART_STATE_BUSY_TX)
{
/* Enable the USART DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
- else if( (husart->State == HAL_USART_STATE_BUSY_RX) ||
- (husart->State == HAL_USART_STATE_BUSY_TX_RX) )
+ else if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
@@ -1308,6 +1820,10 @@
/* Enable the USART DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
}
+ else
+ {
+ /* Nothing to do */
+ }
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1316,7 +1832,7 @@
}
/**
- * @brief Stop the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param husart USART handle.
* @retval HAL status
*/
@@ -1324,25 +1840,42 @@
{
/* The Lock is not implemented on this API to allow the user application
to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() /
- HAL_USART_TxHalfCpltCallback() / HAL_USART_RxHalfCpltCallback ():
- indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete interrupt is
- generated if the DMA transfer interruption occurs at the middle or at the end of the stream
- and the corresponding call back is executed.
- */
+ HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback:
+ indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+ interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+ the stream and the corresponding call back is executed. */
/* Disable the USART Tx/Rx DMA requests */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA tx channel */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
- HAL_DMA_Abort(husart->hdmatx);
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
/* Abort the USART DMA rx channel */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
- HAL_DMA_Abort(husart->hdmarx);
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
USART_EndTransfer(husart);
@@ -1354,7 +1887,7 @@
/**
* @brief Abort ongoing transfers (blocking mode).
* @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable USART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1362,10 +1895,9 @@
* - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
{
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1375,13 +1907,22 @@
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
- /* Set the USART DMA Abort callback to Null.
+ /* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
husart->hdmatx->XferAbortCallback = NULL;
- HAL_DMA_Abort(husart->hdmatx);
+ if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
@@ -1391,23 +1932,36 @@
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
- /* Set the USART DMA Abort callback to Null.
+ /* Set the USART DMA Abort callback to Null.
No call back execution at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = NULL;
- HAL_DMA_Abort(husart->hdmarx);
+ if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK)
+ {
+ if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+ {
+ /* Set error code to DMA */
+ husart->ErrorCode = HAL_USART_ERROR_DMA;
+
+ return HAL_TIMEOUT;
+ }
+ }
}
}
/* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0U;
- husart->RxXferCount = 0U;
+ husart->TxXferCount = 0U;
+ husart->RxXferCount = 0U;
/* Clear the Error flags in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
@@ -1420,7 +1974,7 @@
/**
* @brief Abort ongoing transfers (Interrupt mode).
* @param husart USART handle.
- * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
* This procedure performs following operations :
* - Disable USART Interrupts (Tx and Rx)
* - Disable the DMA transfer in the peripheral register (if enabled)
@@ -1430,23 +1984,22 @@
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
{
uint32_t abortcplt = 1U;
-
- /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
}
@@ -1456,11 +2009,11 @@
}
}
/* DMA Rx Handle is valid */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
/* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
Otherwise, set it to NULL */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
}
@@ -1469,21 +2022,21 @@
husart->hdmarx->XferAbortCallback = NULL;
}
}
-
+
/* Disable the USART DMA Tx request if enabled */
- if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
- /* USART Tx DMA Abort callback has already been initialised :
+ /* USART Tx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
{
husart->hdmatx->XferAbortCallback = NULL;
}
@@ -1500,13 +2053,13 @@
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
- /* USART Rx DMA Abort callback has already been initialised :
+ /* USART Rx DMA Abort callback has already been initialised :
will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
husart->hdmarx->XferAbortCallback = NULL;
abortcplt = 1U;
@@ -1522,7 +2075,7 @@
if (abortcplt == 1U)
{
/* Reset Tx and Rx transfer counters */
- husart->TxXferCount = 0U;
+ husart->TxXferCount = 0U;
husart->RxXferCount = 0U;
/* Reset errorCode */
@@ -1531,11 +2084,21 @@
/* Clear the Error flags in the ICR register */
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
+
+ /* Discard the received data */
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
+
/* Restore husart->State to Ready */
husart->State = HAL_USART_STATE_READY;
/* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
return HAL_OK;
@@ -1550,36 +2113,34 @@
{
uint32_t isrflags = READ_REG(husart->Instance->ISR);
uint32_t cr1its = READ_REG(husart->Instance->CR1);
- uint32_t cr3its;
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);
+
uint32_t errorflags;
+ uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
- if (errorflags == RESET)
+ if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->RxISR != NULL)
{
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
+ husart->RxISR(husart);
}
return;
}
}
/* If some errors occur */
- cr3its = READ_REG(husart->Instance->CR3);
- if( (errorflags != RESET)
- && ( ((cr3its & USART_CR3_EIE) != RESET)
- || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)) )
+ if ((errorflags != 0U)
+ && (((cr3its & USART_CR3_EIE) != 0U)
+ || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U)))
{
/* USART parity error interrupt occurred -------------------------------------*/
- if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF);
@@ -1587,7 +2148,7 @@
}
/* USART frame error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF);
@@ -1595,7 +2156,7 @@
}
/* USART noise error interrupt occurred --------------------------------------*/
- if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF);
@@ -1603,35 +2164,35 @@
}
/* USART Over-Run interrupt occurred -----------------------------------------*/
- if(((isrflags & USART_ISR_ORE) != RESET) &&
- (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+ if (((isrflags & USART_ISR_ORE) != 0U)
+ && (((cr1its & USART_CR1_RXNEIE) != 0U) ||
+ ((cr3its & USART_CR3_EIE) != 0U)))
{
__HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF);
husart->ErrorCode |= HAL_USART_ERROR_ORE;
}
+
/* Call USART Error Call back function if need be --------------------------*/
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ if (husart->ErrorCode != HAL_USART_ERROR_NONE)
{
/* USART in mode Receiver ---------------------------------------------------*/
- if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ if (((isrflags & USART_ISR_RXNE) != 0U)
+ && ((cr1its & USART_CR1_RXNEIE) != 0U))
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->RxISR != NULL)
{
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
+ husart->RxISR(husart);
}
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
- if (((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) ||
- (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)))
- {
+ errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE;
+ if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) ||
+ (errorcode != 0U))
+ {
/* Blocking error : transfer is aborted
Set the USART state ready to be able to start again the process,
Disable Interrupts, and disable DMA requests, if ongoing */
@@ -1643,25 +2204,25 @@
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
/* Abort the USART DMA Tx channel */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
/* Set the USART Tx DMA Abort callback to NULL : no callback
executed at end of DMA abort procedure */
husart->hdmatx->XferAbortCallback = NULL;
-
+
/* Abort DMA TX */
- HAL_DMA_Abort_IT(husart->hdmatx);
+ (void)HAL_DMA_Abort_IT(husart->hdmatx);
}
/* Abort the USART DMA Rx channel */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
- /* Set the USART Rx DMA Abort callback :
+ /* Set the USART Rx DMA Abort callback :
will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
{
/* Call Directly husart->hdmarx->XferAbortCallback function in case of error */
husart->hdmarx->XferAbortCallback(husart->hdmarx);
@@ -1670,20 +2231,38 @@
else
{
/* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
else
{
/* Call user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
else
{
- /* Non Blocking error : transfer could go on.
+ /* Non Blocking error : transfer could go on.
Error is notified to user through user error callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
husart->ErrorCode = HAL_USART_ERROR_NONE;
}
}
@@ -1693,21 +2272,18 @@
/* USART in mode Transmitter ------------------------------------------------*/
- if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+ if (((isrflags & USART_ISR_TXE) != 0U)
+ && ((cr1its & USART_CR1_TXEIE) != 0U))
{
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->TxISR != NULL)
{
- USART_Transmit_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
+ husart->TxISR(husart);
}
return;
}
/* USART in mode Transmitter (transmission end) -----------------------------*/
- if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+ if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
{
USART_EndTransmit_IT(husart);
return;
@@ -1716,8 +2292,8 @@
}
/**
- * @brief Tx Transfer completed callback.
- * @param husart USART handle.
+ * @brief Tx Transfer completed callback.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
@@ -1732,7 +2308,7 @@
/**
* @brief Tx Half Transfer completed callback.
- * @param husart USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1747,7 +2323,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param husart USART handle.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
@@ -1761,8 +2337,8 @@
}
/**
- * @brief Rx Half Transfer completed callback.
- * @param husart USART handle.
+ * @brief Rx Half Transfer completed callback.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1776,8 +2352,8 @@
}
/**
- * @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart USART handle.
+ * @brief Tx/Rx Transfers completed callback for the non-blocking process.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1791,8 +2367,8 @@
}
/**
- * @brief USART error callback.
- * @param husart USART handle.
+ * @brief USART error callback.
+ * @param husart USART handle.
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
@@ -1810,7 +2386,7 @@
* @param husart USART handle.
* @retval None
*/
-__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
@@ -1824,9 +2400,9 @@
* @}
*/
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief USART Peripheral State and Error functions
- *
+/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions
+ * @brief USART Peripheral State and Error functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -1842,9 +2418,9 @@
/**
- * @brief Return the USART handle state.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
+ * @brief Return the USART handle state.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
* @retval USART handle state
*/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
@@ -1853,9 +2429,9 @@
}
/**
- * @brief Return the USART error code.
- * @param husart pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART.
+ * @brief Return the USART error code.
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART.
* @retval USART handle Error Code
*/
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
@@ -1872,17 +2448,28 @@
*/
/** @defgroup USART_Private_Functions USART Private Functions
- * @brief USART Private functions
- *
-@verbatim
- [..]
- This subsection provides a set of functions allowing to control the USART.
- (+) USART_SetConfig() API is used to set the USART communication parameters.
- (+) USART_CheckIdleState() APi ensures that TEACK and/or REACK bits are set after initialization
-
-@endverbatim
* @{
*/
+
+/**
+ * @brief Initialize the callbacks to their default values.
+ * @param husart USART handle.
+ * @retval none
+ */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart)
+{
+ /* Init the USART Callback settings */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+}
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
/**
* @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion).
* @param husart USART handle.
@@ -1890,9 +2477,8 @@
*/
static void USART_EndTransfer(USART_HandleTypeDef *husart)
{
- /* Disable TXEIE and TCIE interrupts */
- /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | USART_CR1_PEIE));
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
/* At end of process, restore husart->State to Ready */
@@ -1900,20 +2486,20 @@
}
/**
- * @brief DMA USART transmit process complete callback.
+ * @brief DMA USART transmit process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
husart->TxXferCount = 0U;
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the USART CR3 register */
@@ -1926,36 +2512,48 @@
/* DMA Circular mode */
else
{
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
}
}
/**
- * @brief DMA USART transmit process half complete callback.
+ * @brief DMA USART transmit process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Half Complete Callback */
+ husart->TxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Half Complete Callback */
HAL_USART_TxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
- * @brief DMA USART receive process complete callback.
+ * @brief DMA USART receive process complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
husart->RxXferCount = 0U;
@@ -1970,62 +2568,97 @@
clock to the slave device */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
}
/* DMA circular mode */
else
{
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if (husart->State == HAL_USART_STATE_BUSY_RX)
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
- }
-
+ }
}
/**
- * @brief DMA USART receive process half complete callback.
+ * @brief DMA USART receive process half complete callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Half Complete Callback */
+ husart->RxHalfCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Half Complete Callback */
HAL_USART_RxHalfCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
- * @brief DMA USART communication error callback.
+ * @brief DMA USART communication error callback.
* @param hdma DMA handle.
* @retval None
*/
static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
USART_EndTransfer(husart);
husart->ErrorCode |= HAL_USART_ERROR_DMA;
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
@@ -2036,11 +2669,17 @@
*/
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef*)(hdma->Parent);
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
husart->RxXferCount = 0U;
husart->TxXferCount = 0U;
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Error Callback */
+ husart->ErrorCallback(husart);
+#else
+ /* Call legacy weak Error Callback */
HAL_USART_ErrorCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
/**
@@ -2053,19 +2692,19 @@
*/
static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
-
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
husart->hdmatx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(husart->hdmarx != NULL)
+ if (husart->hdmarx != NULL)
{
- if(husart->hdmarx->XferAbortCallback != NULL)
+ if (husart->hdmarx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
husart->TxXferCount = 0U;
husart->RxXferCount = 0U;
@@ -2077,10 +2716,17 @@
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF);
/* Restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+
}
@@ -2094,19 +2740,19 @@
*/
static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
{
- USART_HandleTypeDef* husart = (USART_HandleTypeDef* )(hdma->Parent);
-
+ USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent);
+
husart->hdmarx->XferAbortCallback = NULL;
/* Check if an Abort process is still ongoing */
- if(husart->hdmatx != NULL)
+ if (husart->hdmatx != NULL)
{
- if(husart->hdmatx->XferAbortCallback != NULL)
+ if (husart->hdmatx->XferAbortCallback != NULL)
{
return;
}
}
-
+
/* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
husart->TxXferCount = 0U;
husart->RxXferCount = 0U;
@@ -2121,7 +2767,13 @@
husart->State = HAL_USART_STATE_READY;
/* Call user Abort complete callback */
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Abort Complete Callback */
+ husart->AbortCpltCallback(husart);
+#else
+ /* Call legacy weak Abort Complete Callback */
HAL_USART_AbortCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
}
@@ -2134,21 +2786,18 @@
* @param Timeout timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status,
+ uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is set */
- while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
+ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
-
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -2160,7 +2809,6 @@
return HAL_OK;
}
-
/**
* @brief Configure the USART peripheral.
* @param husart USART handle.
@@ -2168,11 +2816,12 @@
*/
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
{
- uint32_t tmpreg = 0x0U;
- USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED;
+ uint32_t tmpreg;
+ USART_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
- uint16_t brrtemp = 0x0000U;
- uint16_t usartdiv = 0x0000U;
+ uint16_t brrtemp;
+ uint32_t usartdiv = 0x00000000;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@@ -2184,14 +2833,13 @@
assert_param(IS_USART_PARITY(husart->Init.Parity));
assert_param(IS_USART_MODE(husart->Init.Mode));
-
/*-------------------------- USART CR1 Configuration -----------------------*/
- /* Clear M, PCE, PS, TE and RE bits and configure
- * the USART Word Length, Parity and Mode:
- * set the M bits according to husart->Init.WordLength value
- * set PCE and PS bits according to husart->Init.Parity value
- * set TE and RE bits according to husart->Init.Mode value
- * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
+ /* Clear M, PCE, PS, TE and RE bits and configure
+ * the USART Word Length, Parity and Mode:
+ * set the M bits according to husart->Init.WordLength value
+ * set PCE and PS bits according to husart->Init.Parity value
+ * set TE and RE bits according to husart->Init.Mode value
+ * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */
tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8;
MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
@@ -2199,42 +2847,56 @@
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
- * set LBCL bit according to husart->Init.CLKLastBit value
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
* set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
+ tmpreg |= (uint32_t)husart->Init.CLKLastBit;
tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase);
- tmpreg |= ((uint32_t)husart->Init.CLKLastBit | (uint32_t)husart->Init.StopBits);
+ tmpreg |= (uint32_t)husart->Init.StopBits;
MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg);
- /*-------------------------- USART CR3 Configuration -----------------------*/
- /* no CR3 register configuration */
/*-------------------------- USART BRR Configuration -----------------------*/
- /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
+ /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */
USART_GETCLOCKSOURCE(husart, clocksource);
+
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetPCLK1Freq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(((2*HSI_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(((2*HAL_RCC_GetSysClockFreq()) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate));
break;
case USART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(((2*LSE_VALUE) + (husart->Init.BaudRate/2)) / husart->Init.BaudRate);
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate));
break;
- case USART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
}
-
- brrtemp = usartdiv & 0xFFF0U;
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- husart->Instance->BRR = brrtemp;
+
+ /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */
+ if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ husart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
+
+
+ /* Clear ISR function pointers */
+ husart->RxISR = NULL;
+ husart->TxISR = NULL;
return ret;
}
@@ -2246,48 +2908,37 @@
*/
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
{
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
- uint32_t tickstart = 0U;
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+ uint32_t tickstart;
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
-#if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
/* Init tickstart for timeout managment*/
tickstart = HAL_GetTick();
- /* TEACK and REACK bits in ISR are checked only when available (not available on all F0 devices).
- Bits are defined for some specific devices, and are available only for UART instances supporting WakeUp from Stop Mode feature.
- */
- if (IS_UART_WAKEUP_FROMSTOP_INSTANCE(husart->Instance))
+ /* Check if the Transmitter is enabled */
+ if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
{
- /* Check if the Transmitter is enabled */
- if((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ /* Wait until TEACK flag is set */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
{
- /* Wait until TEACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if the Receiver is enabled */
- if((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- {
- /* Wait until REACK flag is set */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
- {
- /* Timeout occurred */
- return HAL_TIMEOUT;
- }
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
}
}
-#endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
+ /* Check if the Receiver is enabled */
+ if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ {
+ /* Wait until REACK flag is set */
+ if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK)
+ {
+ /* Timeout occurred */
+ return HAL_TIMEOUT;
+ }
+ }
/* Initialize the USART state*/
- husart->State= HAL_USART_STATE_READY;
+ husart->State = HAL_USART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -2295,54 +2946,72 @@
return HAL_OK;
}
-
/**
* @brief Simplex send an amount of data in non-blocking mode.
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Transmit_IT().
* @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when data word length is less than 9 bits long.
* @param husart USART handle.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
+static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0U;
+ const HAL_USART_StateTypeDef state = husart->State;
/* Check that a Tx process is ongoing */
- if(husart->State == HAL_USART_STATE_BUSY_TX)
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
-
- if(husart->TxXferCount == 0U)
+ if (husart->TxXferCount == 0U)
{
/* Disable the USART Transmit data register empty interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
/* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-
- return HAL_OK;
}
else
{
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFFU);
- }
-
+ husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF);
+ husart->pTxBuffPtr++;
husart->TxXferCount--;
-
- return HAL_OK;
}
}
- else
+}
+
+/**
+ * @brief Simplex send an amount of data in non-blocking mode.
+ * @note Function called under interruption only, once
+ * interruptions have been enabled by HAL_USART_Transmit_IT().
+ * @note The USART errors are not managed to avoid the overrun error.
+ * @note ISR function executed when data word length is 9 bits long.
+ * @param husart USART handle.
+ * @retval None
+ */
+static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
+{
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t *tmp;
+
+ if ((state == HAL_USART_STATE_BUSY_TX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
- return HAL_BUSY;
+ if (husart->TxXferCount == 0U)
+ {
+ /* Disable the USART Transmit data register empty interrupt */
+ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+
+ /* Enable the USART Transmit Complete Interrupt */
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
+ }
+ else
+ {
+ tmp = (uint16_t *) husart->pTxBuffPtr;
+ husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
+ husart->pTxBuffPtr += 2U;
+ husart->TxXferCount--;
+ }
}
}
@@ -2351,9 +3020,9 @@
* @brief Wraps up transmission in non-blocking mode.
* @param husart Pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
+static void USART_EndTransmit_IT(USART_HandleTypeDef *husart)
{
/* Disable the USART Transmit Complete Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TC);
@@ -2361,12 +3030,43 @@
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
- /* Tx process is ended, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
+ /* Clear TxISR function pointer */
+ husart->TxISR = NULL;
- HAL_USART_TxCpltCallback(husart);
+ if (husart->State == HAL_USART_STATE_BUSY_TX)
+ {
+ /* Clear overrun flag and discard the received data */
+ __HAL_USART_CLEAR_OREFLAG(husart);
+ __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST);
- return HAL_OK;
+ /* Tx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Complete Callback */
+ husart->TxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Complete Callback */
+ HAL_USART_TxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if (husart->RxXferCount == 0U)
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
@@ -2374,32 +3074,24 @@
* @brief Simplex receive an amount of data in non-blocking mode.
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when data word length is less than 9 bits long.
* @param husart USART handle
- * @retval HAL status
+ * @retval None
*/
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
+static void USART_RxISR_8BIT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0U;
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
uint16_t uhMask = husart->Mask;
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
+ *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
+ husart->pRxBuffPtr++;
+ husart->RxXferCount--;
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
-
- /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
- husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FFU);
-
- if(--husart->RxXferCount == 0U)
+ if (husart->RxXferCount == 0U)
{
/* Disable the USART Parity Error Interrupt and RXNE interrupt*/
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
@@ -2407,81 +3099,81 @@
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Rx process is completed, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
- HAL_USART_RxCpltCallback(husart);
+ /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ txdatacount = husart->TxXferCount;
- return HAL_OK;
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
+ else if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
}
/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @brief Simplex receive an amount of data in non-blocking mode.
* @note Function called under interruption only, once
- * interruptions have been enabled by HAL_USART_TransmitReceive_IT().
- * @param husart USART handle.
- * @retval HAL status
+ * interruptions have been enabled by HAL_USART_Receive_IT().
+ * @note ISR function executed when data word length is 9 bits long.
+ * @param husart USART handle
+ * @retval None
*/
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
+static void USART_RxISR_16BIT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0U;
+ const HAL_USART_StateTypeDef state = husart->State;
+ uint16_t txdatacount;
+ uint16_t *tmp;
uint16_t uhMask = husart->Mask;
- if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
+ if ((state == HAL_USART_STATE_BUSY_RX) ||
+ (state == HAL_USART_STATE_BUSY_TX_RX))
{
+ tmp = (uint16_t *) husart->pRxBuffPtr;
+ *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
+ husart->pRxBuffPtr += 2U;
+ husart->RxXferCount--;
- if(husart->TxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pTxBuffPtr;
- husart->Instance->TDR = (uint16_t)(*tmp & uhMask);
- husart->pTxBuffPtr += 2U;
- }
- else
- {
- husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)uhMask);
- }
- husart->TxXferCount--;
-
- /* Check the latest data transmitted */
- if(husart->TxXferCount == 0U)
- {
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- }
- }
- }
-
- if(husart->RxXferCount != 0x00U)
- {
- if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
- {
- if((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
- {
- tmp = (uint16_t*) husart->pRxBuffPtr;
- *tmp = (uint16_t)(husart->Instance->RDR & uhMask);
- husart->pRxBuffPtr += 2U;
- }
- else
- {
- *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask);
- }
- husart->RxXferCount--;
- }
- }
-
- /* Check the latest data received */
- if(husart->RxXferCount == 0U)
+ if (husart->RxXferCount == 0U)
{
/* Disable the USART Parity Error Interrupt and RXNE interrupt*/
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
@@ -2489,22 +3181,58 @@
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Rx process is completed, restore husart->State to Ready */
- husart->State = HAL_USART_STATE_READY;
+ /* Clear RxISR function pointer */
+ husart->RxISR = NULL;
- HAL_USART_TxRxCpltCallback(husart);
+ /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */
+ txdatacount = husart->TxXferCount;
- return HAL_OK;
+ if (state == HAL_USART_STATE_BUSY_RX)
+ {
+
+ /* Rx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Rx Complete Callback */
+ husart->RxCpltCallback(husart);
+#else
+ /* Call legacy weak Rx Complete Callback */
+ HAL_USART_RxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) &&
+ (txdatacount == 0U))
+ {
+ /* TxRx process is completed, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
+ /* Call registered Tx Rx Complete Callback */
+ husart->TxRxCpltCallback(husart);
+#else
+ /* Call legacy weak Tx Rx Complete Callback */
+ HAL_USART_TxRxCpltCallback(husart);
+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
+ else if (state == HAL_USART_STATE_BUSY_RX)
+ {
+ /* Send dummy byte in order to generate the clock for the Slave to Send the next data */
+ husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
}
+
/**
* @}
*/
diff --git a/Src/stm32f0xx_hal_usart_ex.c b/Src/stm32f0xx_hal_usart_ex.c
new file mode 100644
index 0000000..9ff0886
--- /dev/null
+++ b/Src/stm32f0xx_hal_usart_ex.c
@@ -0,0 +1,138 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_hal_usart_ex.c
+ * @author MCD Application Team
+ * @brief Extended USART HAL module driver.
+ * This file provides firmware functions to manage the following extended
+ * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
+ * + Peripheral Control functions
+ *
+ *
+ @verbatim
+ ==============================================================================
+ ##### USART peripheral extended features #####
+ ==============================================================================
+
+ (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+ -@- When USART operates in FIFO mode, FIFO mode must be enabled prior
+ starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+ configured prior starting RX/TX transfers.
+
+ (#) Slave mode enabling/disabling and NSS pin configuration.
+
+ -@- When USART operates in Slave mode, Slave mode must be enabled prior
+ starting RX/TX transfers.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup USARTEx USARTEx
+ * @brief USART Extended HAL module driver
+ * @{
+ */
+
+#ifdef HAL_USART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions
+ * @{
+ */
+
+/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions
+ * @brief Extended USART Transmit/Receive functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ This subsection provides a set of FIFO mode related callback functions.
+
+ (#) TX/RX Fifos Callbacks:
+ (+) HAL_USARTEx_RxFifoFullCallback()
+ (+) HAL_USARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..] This section provides the following functions:
+ (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode
+ (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode
+ (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS)
+ (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode
+ (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode
+ (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+ (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+
+@endverbatim
+ * @{
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup USARTEx_Private_Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* HAL_USART_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_hal_wwdg.c b/Src/stm32f0xx_hal_wwdg.c
index ae48b99..762eee7 100644
--- a/Src/stm32f0xx_hal_wwdg.c
+++ b/Src/stm32f0xx_hal_wwdg.c
@@ -3,120 +3,117 @@
* @file stm32f0xx_hal_wwdg.c
* @author MCD Application Team
* @brief WWDG HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
- * + Initialization and Configuration function
+ * + Initialization and Configuration functions
* + IO operation functions
@verbatim
==============================================================================
- ##### WWDG specific features #####
+ ##### WWDG Specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
time period, unless the program refreshes the counter (T[6;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
+ value rolls down from 0x40 to 0x3F).
(+) An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
-
(+) Once enabled the WWDG cannot be disabled except by a system reset.
-
- (+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
- occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
-
- (+) The WWDG downcounter input clock is derived from the APB clock divided
+ (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
+ reset occurs.
+ (+) The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
-
- (+) WWDG downcounter clock (Hz) = PCLK / (4096 * Prescaler)
-
- (+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
- where T[5;0] are the lowest 6 bits of downcounter.
-
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz)
+ where T[5;0] are the lowest 6 bits of Counter.
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
- (++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
+ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (+) Typical values:
+ (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
+ max timeout before reset: approximately 73.14µs
+ (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 8:
+ max timeout before reset: approximately 599.18ms
- (+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms
-
- (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
- operations or data logging must be performed before the actual reset is
- generated. When the downcounter reaches the value 0x40, an EWI interrupt
- is generated and the corresponding interrupt service routine (ISR) can
- be used to trigger specific actions (such as communications or data
- logging), before resetting the device.
- In some applications, the EWI interrupt can be used to manage a software
- system check and/or system recovery/graceful degradation, without
- generating a WWDG reset. In this case, the corresponding interrupt
- service routine (ISR) should reload the WWDG counter to avoid the WWDG
- reset, then trigger the required actions.
- Note:When the EWI interrupt cannot be served, e.g. due to a system lock
- in a higher priority task, the WWDG reset will eventually be generated.
-
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
- the WWDG counter either continues to work normally or stops, depending
- on DBG_WWDG_STOP configuration bit in DBG module, accessible through
- __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
-
+ ==============================================================================
##### How to use this driver #####
==============================================================================
+
+ *** Common driver usage ***
+ ===========================
+
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
-
- (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
- Interrupt mode using using HAL_WWDG_Init() function.
- This enables WWDG peripheral and the downcounter starts downcounting
- from given counter value.
- Init function can be called again to modify all watchdog parameters,
- however if EWI mode has been set once, it can't be clear until next
- reset.
-
- (+) The application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset using
+ (+) Set the WWDG prescaler, refresh window and counter value
+ using HAL_WWDG_Init() function.
+ (+) Start the WWDG using HAL_WWDG_Start() function.
+ When the WWDG is enabled the counter value should be configured to
+ a value greater than 0x40 to prevent generating an immediate reset.
+ (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
+ generated when the counter reaches 0x40, and then start the WWDG using
+ HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
+ add his own code by customization of callback HAL_WWDG_WakeupCallback.
+ Once enabled, EWI interrupt cannot be disabled except by a system reset.
+ (+) Then the application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the window value already programmed.
+ the counter is lower than the refresh window value already programmed.
- (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
- the counter reaches 0x40. User can add his own code in weak function
- HAL_WWDG_EarlyWakeupCallback().
+ *** Callback registration ***
+ =============================
- *** WWDG HAL driver macros list ***
- ==================================
- [..]
- Below the list of most used macros in WWDG HAL driver.
+ [..]
+ The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
+ the user to configure dynamically the driver callbacks. Use Functions
+ @ref HAL_WWDG_RegisterCallback() to register a user callback.
- (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
+ (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following
+ callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
+
+ (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to
+ the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback()
+ takes as parameters the HAL peripheral handle and the Callback ID.
+ This function allows to reset following callbacks:
+ (++) EwiCallback : callback for Early WakeUp Interrupt.
+ (++) MspInitCallback : WWDG MspInit.
+
+ [..]
+ When calling @ref HAL_WWDG_Init function, callbacks are reset to the
+ corresponding legacy weak (surcharged) functions:
+ @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
+ not been registered before.
+
+ [..]
+ When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
+
+ *** WWDG HAL driver macros list ***
+ ===================================
+ [..]
+ Below the list of most used macros in WWDG HAL driver.
+ (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
+ (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -146,13 +143,13 @@
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
(+) Initialize and start the WWDG according to the specified parameters
in the WWDG_InitTypeDef of associated handle.
@@ -172,7 +169,7 @@
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
- if(hwwdg == NULL)
+ if (hwwdg == NULL)
{
return HAL_ERROR;
}
@@ -184,8 +181,24 @@
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Reset Callback pointers */
+ if (hwwdg->EwiCallback == NULL)
+ {
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ }
+
+ if (hwwdg->MspInitCallback == NULL)
+ {
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ }
+
+ /* Init the low level hardware */
+ hwwdg->MspInitCallback(hwwdg);
+#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
+#endif
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@@ -217,17 +230,93 @@
*/
}
+
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User WWDG Callback
+ * To be used instead of the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @param pCallback pointer to the Callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ status = HAL_ERROR;
+ }
+ else
+ {
+ switch (CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = pCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+
+ return status;
+}
+
+
+/**
+ * @brief Unregister a WWDG Callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * @param hwwdg WWDG handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID
+ * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ switch (CallbackID)
+ {
+ case HAL_WWDG_EWI_CB_ID:
+ hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
+ break;
+
+ case HAL_WWDG_MSPINIT_CB_ID:
+ hwwdg->MspInitCallback = HAL_WWDG_MspInit;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+
+ return status;
+}
+#endif
+
/**
* @}
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..]
This section provides functions allowing to:
(+) Refresh the WWDG.
@@ -256,7 +345,7 @@
* @brief Handle WWDG interrupt request.
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
* or data logging must be performed before the actual reset is generated.
- * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+ * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
* EWIMode set to WWDG_EWI_ENABLE.
* When the downcounter reaches the value 0x40, and EWI interrupt is
* generated and the corresponding Interrupt Service Routine (ISR) can
@@ -269,16 +358,21 @@
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
/* Check if Early Wakeup Interrupt is enable */
- if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
+ if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
/* Check if WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Clear the WWDG Early Wakeup flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
- /* Early Wakeup callback */
+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
+ /* Early Wakeup registered callback */
+ hwwdg->EwiCallback(hwwdg);
+#else
+ /* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
+#endif
}
}
}
@@ -290,7 +384,7 @@
* the configuration information for the specified WWDG module.
* @retval None
*/
-__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
diff --git a/Src/stm32f0xx_ll_adc.c b/Src/stm32f0xx_ll_adc.c
index 7db18a6..ec02d40 100644
--- a/Src/stm32f0xx_ll_adc.c
+++ b/Src/stm32f0xx_ll_adc.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
@@ -415,7 +400,12 @@
| ADC_InitStruct->DataAlignment
| ADC_InitStruct->LowPowerMode
);
-
+
+ MODIFY_REG(ADCx->CFGR2,
+ ADC_CFGR2_CKMODE
+ ,
+ ADC_InitStruct->Clock
+ );
}
else
{
diff --git a/Src/stm32f0xx_ll_comp.c b/Src/stm32f0xx_ll_comp.c
index 0a4f6f9..f26acd0 100644
--- a/Src/stm32f0xx_ll_comp.c
+++ b/Src/stm32f0xx_ll_comp.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_ll_crc.c b/Src/stm32f0xx_ll_crc.c
index c634603..d343963 100644
--- a/Src/stm32f0xx_ll_crc.c
+++ b/Src/stm32f0xx_ll_crc.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -36,6 +20,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_ll_crc.h"
+#include "stm32f0xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
@@ -84,13 +69,13 @@
if (CRCx == CRC)
{
-#if defined(CRC_PROG_POLYNOMIAL_SUPPORT)
+#if defined(CRC_POL_POL)
/* Set programmable polynomial size in CR register to reset value (32 bits)*/
LL_CRC_SetPolynomialSize(CRCx, LL_CRC_POLYLENGTH_32B);
/* Set programmable polynomial in POL register to reset value */
LL_CRC_SetPolynomialCoef(CRCx, LL_CRC_DEFAULT_CRC32_POLY);
-#endif
+#endif /* CRC_POL_POL */
/* Set INIT register to reset value */
LL_CRC_SetInitialData(CRCx, LL_CRC_DEFAULT_CRC_INITVALUE);
diff --git a/Src/stm32f0xx_ll_crs.c b/Src/stm32f0xx_ll_crs.c
index 845f94e..4dccd15 100644
--- a/Src/stm32f0xx_ll_crs.c
+++ b/Src/stm32f0xx_ll_crs.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_ll_dac.c b/Src/stm32f0xx_ll_dac.c
index b4596d1..a3232fe 100644
--- a/Src/stm32f0xx_ll_dac.c
+++ b/Src/stm32f0xx_ll_dac.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
diff --git a/Src/stm32f0xx_ll_dma.c b/Src/stm32f0xx_ll_dma.c
index ac2a89c..4da47bd 100644
--- a/Src/stm32f0xx_ll_dma.c
+++ b/Src/stm32f0xx_ll_dma.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_ll_exti.c b/Src/stm32f0xx_ll_exti.c
index d9e4253..ef4d16d 100644
--- a/Src/stm32f0xx_ll_exti.c
+++ b/Src/stm32f0xx_ll_exti.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_ll_gpio.c b/Src/stm32f0xx_ll_gpio.c
index 3fae50c..1d51e77 100644
--- a/Src/stm32f0xx_ll_gpio.c
+++ b/Src/stm32f0xx_ll_gpio.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
@@ -52,6 +37,22 @@
/** @addtogroup GPIO_LL
* @{
*/
+/** MISRA C:2012 deviation rule has been granted for following rules:
+ * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
+ * range of the shift operator in following API :
+ * LL_GPIO_Init
+ * LL_GPIO_DeInit
+ * LL_GPIO_SetPinMode
+ * LL_GPIO_GetPinMode
+ * LL_GPIO_SetPinSpeed
+ * LL_GPIO_GetPinSpeed
+ * LL_GPIO_SetPinPull
+ * LL_GPIO_GetPinPull
+ * LL_GPIO_GetAFPin_0_7
+ * LL_GPIO_SetAFPin_0_7
+ * LL_GPIO_SetAFPin_8_15
+ * LL_GPIO_GetAFPin_8_15
+ */
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -60,7 +61,7 @@
/** @addtogroup GPIO_LL_Private_Macros
* @{
*/
-#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
@@ -171,8 +172,8 @@
*/
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
- uint32_t pinpos = 0x00000000U;
- uint32_t currentpin = 0x00000000U;
+ uint32_t pinpos;
+ uint32_t currentpin;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@@ -182,15 +183,15 @@
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
- /* pinpos = 0; useless as already done in default initialization */
+ pinpos = 0;
/* Configure the port pins */
- while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
{
/* Get current io position */
- currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
- if (currentpin)
+ if (currentpin != 0x00u)
{
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
diff --git a/Src/stm32f0xx_ll_i2c.c b/Src/stm32f0xx_ll_i2c.c
index 5d88640..d9167a7 100644
--- a/Src/stm32f0xx_ll_i2c.c
+++ b/Src/stm32f0xx_ll_i2c.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -100,7 +84,7 @@
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
@@ -142,7 +126,7 @@
* - SUCCESS: I2C registers are initialized
* - ERROR: Not applicable
*/
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
diff --git a/Src/stm32f0xx_ll_pwr.c b/Src/stm32f0xx_ll_pwr.c
index b4bf665..0f841ae 100644
--- a/Src/stm32f0xx_ll_pwr.c
+++ b/Src/stm32f0xx_ll_pwr.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f0xx_ll_rcc.c b/Src/stm32f0xx_ll_rcc.c
index 6a244fd..94c157e 100644
--- a/Src/stm32f0xx_ll_rcc.c
+++ b/Src/stm32f0xx_ll_rcc.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
@@ -126,24 +111,42 @@
*/
ErrorStatus LL_RCC_DeInit(void)
{
- uint32_t vl_mask = 0U;
+ __IO uint32_t vl_mask;
/* Set HSION bit */
LL_RCC_HSI_Enable();
+ /* Wait for HSI READY bit */
+ while(LL_RCC_HSI_IsReady() != 1U)
+ {}
+
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10U);
/* Reset SW, HPRE, PPRE and MCOSEL bits */
vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL));
+
+ /* Write new value in CFGR register */
LL_RCC_WriteReg(CFGR, vl_mask);
+ /* Wait till system clock source is ready */
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
+ {}
+
+ /* Read CR register */
+ vl_mask = LL_RCC_ReadReg(CR);
+
/* Reset HSEON, CSSON, PLLON bits */
- vl_mask = 0xFFFFFFFFU;
CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
+
+ /* Write new value in CR register */
LL_RCC_WriteReg(CR, vl_mask);
+ /* Wait for PLL READY bit to be reset */
+ while(LL_RCC_PLL_IsReady() != 0U)
+ {}
+
/* Reset HSEBYP bit */
LL_RCC_HSE_DisableBypass();
@@ -171,14 +174,21 @@
/* Clear pending flags */
#if defined(RCC_HSI48_SUPPORT)
- vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC);
+ vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\
+ LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC);
#else
- vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC);
+ vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC |\
+ LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC);
#endif /* RCC_HSI48_SUPPORT */
- SET_BIT(RCC->CIR, vl_mask);
+
+ /* Write new value in CIR register */
+ LL_RCC_WriteReg(CIR, vl_mask);
/* Disable all interrupts */
LL_RCC_WriteReg(CIR, 0x00000000U);
+
+ /* Clear reset flags */
+ LL_RCC_ClearResetFlags();
return SUCCESS;
}
diff --git a/Src/stm32f0xx_ll_rtc.c b/Src/stm32f0xx_ll_rtc.c
index 6c1ba8e..8b7c8a8 100644
--- a/Src/stm32f0xx_ll_rtc.c
+++ b/Src/stm32f0xx_ll_rtc.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
@@ -170,14 +155,14 @@
#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
/* Reset All CR bits except CR[2:0] */
#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
#else
LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+ LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
diff --git a/Src/stm32f0xx_ll_spi.c b/Src/stm32f0xx_ll_spi.c
index 3005490..5a96635 100644
--- a/Src/stm32f0xx_ll_spi.c
+++ b/Src/stm32f0xx_ll_spi.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -76,52 +60,52 @@
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
* @{
*/
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
- || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
- || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
- || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
- || ((__VALUE__) == LL_SPI_MSB_FIRST))
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
- || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
@@ -185,7 +169,7 @@
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
@@ -314,36 +298,36 @@
* @{
*/
-#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
- || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
- || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
- || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
- && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
- || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
- || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
/**
* @}
*/
@@ -374,7 +358,7 @@
/**
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -383,10 +367,12 @@
*/
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
{
- uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U;
+ uint32_t i2sdiv = 2U;
+ uint32_t i2sodd = 0U;
+ uint32_t packetlength = 1U;
+ uint32_t tmp;
LL_RCC_ClocksTypeDef rcc_clocks;
- uint32_t sourceclock = 0U;
+ uint32_t sourceclock;
ErrorStatus status = ERROR;
/* Check the I2S parameters */
@@ -445,25 +431,25 @@
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
{
/* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
else
{
/* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
/* Remove the floating point */
tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+ i2sodd = (tmp & (uint16_t)0x0001U);
/* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+ i2sdiv = ((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t)(i2sodd << 8U);
+ i2sodd = (i2sodd << 8U);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
@@ -504,7 +490,7 @@
* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
* @param SPIx SPI Instance
- * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
* @param PrescalerParity This parameter can be one of the following values:
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
diff --git a/Src/stm32f0xx_ll_tim.c b/Src/stm32f0xx_ll_tim.c
index fa745e1..7012f8f 100644
--- a/Src/stm32f0xx_ll_tim.c
+++ b/Src/stm32f0xx_ll_tim.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -42,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F0xx_LL_Driver
* @{
@@ -62,89 +46,89 @@
* @{
*/
#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
- || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
- || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
- || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
- || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
/**
* @}
*/
@@ -281,11 +265,11 @@
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
{
/* Set the default configuration */
- TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000;
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
+ TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
}
/**
@@ -298,7 +282,7 @@
*/
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
{
- uint32_t tmpcr1 = 0U;
+ uint32_t tmpcr1;
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(TIMx));
@@ -480,8 +464,8 @@
*/
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
/* Check the parameters */
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
@@ -571,10 +555,10 @@
*/
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
{
- uint32_t tmpcr2 = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpsmcr = 0U;
+ uint32_t tmpcr2;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
@@ -653,7 +637,7 @@
TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
- TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
@@ -664,10 +648,10 @@
* @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
* depending on the LOCK configuration, it can be necessary to configure all of
* them during the first write access to the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Break and Dead Time is initialized
* - ERROR: not applicable
@@ -712,7 +696,7 @@
*/
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
- * @brief Private functions
+ * @brief Private functions
* @{
*/
/**
@@ -725,9 +709,9 @@
*/
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
@@ -804,9 +788,9 @@
*/
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
@@ -883,9 +867,9 @@
*/
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
@@ -962,9 +946,9 @@
*/
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr2;
+ uint32_t tmpccer;
+ uint32_t tmpcr2;
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
diff --git a/Src/stm32f0xx_ll_usart.c b/Src/stm32f0xx_ll_usart.c
index d671b29..cf6fc7c 100644
--- a/Src/stm32f0xx_ll_usart.c
+++ b/Src/stm32f0xx_ll_usart.c
@@ -6,29 +6,13 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
@@ -38,17 +22,17 @@
#include "stm32f0xx_ll_usart.h"
#include "stm32f0xx_ll_rcc.h"
#include "stm32f0xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F0xx_LL_Driver
* @{
*/
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART4) || defined (USART5) || defined (USART6) || defined (USART7) || defined (USART8)
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) || defined (USART6) || defined (USART7) || defined (USART8)
/** @addtogroup USART_LL
* @{
@@ -57,15 +41,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
@@ -82,52 +57,52 @@
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
- || ((__VALUE__) == LL_USART_DIRECTION_RX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX) \
- || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
- || ((__VALUE__) == LL_USART_PARITY_EVEN) \
- || ((__VALUE__) == LL_USART_PARITY_ODD))
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
#if defined(USART_7BITS_SUPPORT)
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
- || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+ || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#else
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
-#endif
+#endif /* USART_7BITS_SUPPORT */
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
- || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
- || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
- || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
- || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
- || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#if defined(USART_SMARTCARD_SUPPORT)
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
#else
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \
- || ((__VALUE__) == LL_USART_STOPBITS_2))
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
#endif
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
- || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/**
* @}
@@ -248,7 +223,7 @@
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@@ -261,9 +236,9 @@
{
ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
-#if defined(STM32F030x8) || defined(STM32F030xC) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
+#if defined(USART2)||defined(USART3)||defined(USART4)
LL_RCC_ClocksTypeDef RCC_Clocks;
-#endif
+#endif /* USART2 ||USART3 || USART4 */
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
@@ -315,7 +290,7 @@
#if defined(USART2)
else if (USARTx == USART2)
{
-#if defined (RCC_CFGR3_USART2SW)
+#if defined(RCC_CFGR3_USART2SW)
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
#else
/* USART2 clock is PCLK */
@@ -327,7 +302,7 @@
#if defined(USART3)
else if (USARTx == USART3)
{
-#if defined (RCC_CFGR3_USART3SW)
+#if defined(RCC_CFGR3_USART3SW)
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
#else
/* USART3 clock is PCLK */
@@ -339,7 +314,7 @@
#if defined(USART4)
else if (USARTx == USART4)
{
- /* USART4 clock is PCLK */
+ /* USART4 clock is PCLK1 */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
}
@@ -347,7 +322,7 @@
#if defined(USART5)
else if (USARTx == USART5)
{
- /* USART5 clock is PCLK */
+ /* USART5 clock is PCLK1 */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
}
@@ -397,7 +372,7 @@
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
- /* Check BRR is greater than or equal to 16d */
+ /* Check BRR is lower than or equal to 0xFFFF */
assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
}
@@ -409,7 +384,7 @@
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
- * whose fields will be set to default values.
+ * whose fields will be set to default values.
* @retval None
*/
@@ -429,7 +404,7 @@
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
@@ -493,7 +468,7 @@
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
- * whose fields will be set to default values.
+ * whose fields will be set to default values.
* @retval None
*/
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
@@ -517,7 +492,7 @@
* @}
*/
-#endif /* USART1 || USART2|| USART3 || USART4 || USART5 || USART6 || USART7 || USART8 */
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 || USART7 || USART8 */
/**
* @}
diff --git a/Src/stm32f0xx_ll_usb.c b/Src/stm32f0xx_ll_usb.c
new file mode 100644
index 0000000..ede74f0
--- /dev/null
+++ b/Src/stm32f0xx_ll_usb.c
@@ -0,0 +1,878 @@
+/**
+ ******************************************************************************
+ * @file stm32f0xx_ll_usb.c
+ * @author MCD Application Team
+ * @brief USB Low Layer HAL module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the USB Peripheral Controller:
+ * + Initialization/de-initialization functions
+ * + I/O operation functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f0xx_hal.h"
+
+/** @addtogroup STM32F0xx_LL_USB_DRIVER
+ * @{
+ */
+
+#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
+#if defined (USB)
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/**
+ * @brief Initializes the USB Core
+ * @param USBx: USB Instance
+ * @param cfg : pointer to a USB_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(cfg);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EnableGlobalInt
+ * Enables the controller's Global Int in the AHB Config reg
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
+{
+ uint16_t winterruptmask;
+
+ /* Set winterruptmask variable */
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
+ USB_CNTR_SUSPM | USB_CNTR_ERRM |
+ USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+ /* Set interrupt mask */
+ USBx->CNTR |= winterruptmask;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DisableGlobalInt
+ * Disable the controller's Global Int in the AHB Config reg
+ * @param USBx : Selected device
+ * @retval HAL status
+*/
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
+{
+ uint16_t winterruptmask;
+
+ /* Set winterruptmask variable */
+ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
+ USB_CNTR_SUSPM | USB_CNTR_ERRM |
+ USB_CNTR_SOFM | USB_CNTR_ESOFM |
+ USB_CNTR_RESETM | USB_CNTR_L1REQM;
+
+ /* Clear interrupt mask */
+ USBx->CNTR &= ~winterruptmask;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetCurrentMode : Set functional mode
+ * @param USBx : Selected device
+ * @param mode : current core mode
+ * This parameter can be one of the these values:
+ * @arg USB_DEVICE_MODE: Peripheral mode mode
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(mode);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevInit : Initializes the USB controller registers
+ * for device mode
+ * @param USBx : Selected device
+ * @param cfg : pointer to a USB_CfgTypeDef structure that contains
+ * the configuration information for the specified USBx peripheral.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(cfg);
+
+ /* Init Device */
+ /*CNTR_FRES = 1*/
+ USBx->CNTR = USB_CNTR_FRES;
+
+ /*CNTR_FRES = 0*/
+ USBx->CNTR = 0;
+
+ /*Clear pending interrupts*/
+ USBx->ISTR = 0;
+
+ /*Set Btable Address*/
+ USBx->BTABLE = BTABLE_ADDRESS;
+
+ /* Enable USB Device Interrupt mask */
+ (void)USB_EnableGlobalInt(USBx);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetDevSpeed :Initializes the device speed
+ * depending on the PHY type and the enumeration speed of the device.
+ * @param USBx Selected device
+ * @param speed device speed
+ * @retval Hal status
+ */
+HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(speed);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushTxFifo : Flush a Tx FIFO
+ * @param USBx : Selected device
+ * @param num : FIFO number
+ * This parameter can be a value from 1 to 15
+ 15 means Flush all Tx FIFOs
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(num);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_FlushRxFifo : Flush Rx FIFO
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Activate and configure an endpoint
+ * @param USBx : Selected device
+ * @param ep: pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+ HAL_StatusTypeDef ret = HAL_OK;
+ uint16_t wEpRegVal;
+
+ wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK;
+
+ /* initialize Endpoint */
+ switch (ep->type)
+ {
+ case EP_TYPE_CTRL:
+ wEpRegVal |= USB_EP_CONTROL;
+ break;
+
+ case EP_TYPE_BULK:
+ wEpRegVal |= USB_EP_BULK;
+ break;
+
+ case EP_TYPE_INTR:
+ wEpRegVal |= USB_EP_INTERRUPT;
+ break;
+
+ case EP_TYPE_ISOC:
+ wEpRegVal |= USB_EP_ISOCHRONOUS;
+ break;
+
+ default:
+ ret = HAL_ERROR;
+ break;
+ }
+
+ PCD_SET_ENDPOINT(USBx, ep->num, wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX);
+
+ PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num);
+
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in != 0U)
+ {
+ /*Set the endpoint Transmit buffer address */
+ PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ }
+ else
+ {
+ /*Set the endpoint Receive buffer address */
+ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
+ /*Set the endpoint Receive buffer counter*/
+ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ /* Configure VALID status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ /* Set the endpoint as double buffered */
+ PCD_SET_EP_DBUF(USBx, ep->num);
+ /* Set buffer address for double buffered mode */
+ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
+
+ if (ep->is_in == 0U)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT */
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out */
+ PCD_TX_DTOG(USBx, ep->num);
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT */
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ PCD_RX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ else
+ {
+ /* Configure TX Endpoint to disabled state */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * @brief De-activate and de-initialize an endpoint
+ * @param USBx : Selected device
+ * @param ep: pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in != 0U)
+ {
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+ /*Double Buffer*/
+ else
+ {
+ if (ep->is_in == 0U)
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ /* Reset value of the data toggle bits for the endpoint out*/
+ PCD_TX_DTOG(USBx, ep->num);
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ }
+ else
+ {
+ /* Clear the data toggle bits for the endpoint IN/OUT*/
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+ PCD_RX_DTOG(USBx, ep->num);
+ /* Configure DISABLE status for the Endpoint*/
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPStartXfer : setup and starts a transfer over an EP
+ * @param USBx : Selected device
+ * @param ep: pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+ uint16_t pmabuffer;
+ uint32_t len;
+
+ /* IN endpoint */
+ if (ep->is_in == 1U)
+ {
+ /*Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len -= len;
+ }
+ else
+ {
+ len = ep->xfer_len;
+ ep->xfer_len = 0U;
+ }
+
+ /* configure and validate Tx endpoint */
+ if (ep->doublebuffer == 0U)
+ {
+ USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
+ PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ }
+ else
+ {
+ /* Write the data to the USB endpoint */
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+ }
+ else
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+ }
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
+ }
+
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
+ }
+ else /* OUT endpoint */
+ {
+ /* Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len -= len;
+ }
+ else
+ {
+ len = ep->xfer_len;
+ ep->xfer_len = 0U;
+ }
+
+ /* configure and validate Rx endpoint */
+ if (ep->doublebuffer == 0U)
+ {
+ /*Set RX buffer count*/
+ PCD_SET_EP_RX_CNT(USBx, ep->num, len);
+ }
+ else
+ {
+ /*Set the Double buffer counter*/
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+ }
+
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
+ * with the EP/channel
+ * @param USBx : Selected device
+ * @param src : pointer to source buffer
+ * @param ch_ep_num : endpoint or host channel number
+ * @param len : Number of bytes to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(src);
+ UNUSED(ch_ep_num);
+ UNUSED(len);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
+ * with the EP/channel
+ * @param USBx : Selected device
+ * @param dest : destination pointer
+ * @param len : Number of bytes to read
+ * @retval pointer to destination buffer
+ */
+void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(dest);
+ UNUSED(len);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return ((void *)NULL);
+}
+
+/**
+ * @brief USB_EPSetStall : set a stall condition over an EP
+ * @param USBx : Selected device
+ * @param ep: pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+ if (ep->is_in != 0U)
+ {
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL);
+ }
+ else
+ {
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_EPClearStall : Clear a stall condition over an EP
+ * @param USBx : Selected device
+ * @param ep: pointer to endpoint structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
+{
+ if (ep->doublebuffer == 0U)
+ {
+ if (ep->is_in != 0U)
+ {
+ PCD_CLEAR_TX_DTOG(USBx, ep->num);
+
+ if (ep->type != EP_TYPE_ISOC)
+ {
+ /* Configure NAK status for the Endpoint */
+ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK);
+ }
+ }
+ else
+ {
+ PCD_CLEAR_RX_DTOG(USBx, ep->num);
+
+ /* Configure VALID status for the Endpoint*/
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_StopDevice : Stop the usb device mode
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
+{
+ /* disable all interrupts and force USB reset */
+ USBx->CNTR = USB_CNTR_FRES;
+
+ /* clear interrupt status register */
+ USBx->ISTR = 0;
+
+ /* switch-off device */
+ USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_SetDevAddress : Stop the usb device mode
+ * @param USBx : Selected device
+ * @param address : new device address to be assigned
+ * This parameter can be a value from 0 to 255
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
+{
+ if (address == 0U)
+ {
+ /* set device address and enable function */
+ USBx->DADDR = USB_DADDR_EF;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
+{
+ /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
+ USBx->BCDR |= USB_BCDR_DPPU;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
+{
+ /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */
+ USBx->BCDR &= (uint16_t)(~(USB_BCDR_DPPU));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ReadInterrupts: return the global USB interrupt status
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
+{
+ uint32_t tmpreg;
+
+ tmpreg = USBx->ISTR;
+ return tmpreg;
+}
+
+/**
+ * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return (0);
+}
+
+/**
+ * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
+ * @param USBx : Selected device
+ * @retval HAL status
+ */
+uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return (0);
+}
+
+/**
+ * @brief Returns Device OUT EP Interrupt register
+ * @param USBx : Selected device
+ * @param epnum : endpoint number
+ * This parameter can be a value from 0 to 15
+ * @retval Device OUT EP Interrupt register
+ */
+uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(epnum);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return (0);
+}
+
+/**
+ * @brief Returns Device IN EP Interrupt register
+ * @param USBx : Selected device
+ * @param epnum : endpoint number
+ * This parameter can be a value from 0 to 15
+ * @retval Device IN EP Interrupt register
+ */
+uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(epnum);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return (0);
+}
+
+/**
+ * @brief USB_ClearInterrupts: clear a USB interrupt
+ * @param USBx Selected device
+ * @param interrupt interrupt flag
+ * @retval None
+ */
+void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(interrupt);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+}
+
+/**
+ * @brief Prepare the EP0 to start the first control setup
+ * @param USBx Selected device
+ * @param psetup pointer to setup packet
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(psetup);
+ /* NOTE : - This function is not required by USB Device FS peripheral, it is used
+ only by USB OTG FS peripheral.
+ - This function is added to ensure compatibility across platforms.
+ */
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
+{
+ USBx->CNTR |= USB_CNTR_RESUME;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
+ * @param USBx Selected device
+ * @retval HAL status
+ */
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
+{
+ USBx->CNTR &= ~(USB_CNTR_RESUME);
+ return HAL_OK;
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx USB peripheral instance register address.
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
+ uint32_t BaseAddr = (uint32_t)USBx;
+ uint32_t i, temp1, temp2;
+ __IO uint16_t *pdwVal;
+ uint8_t *pBuf = pbUsrBuf;
+
+ pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+
+ for (i = n; i != 0U; i--)
+ {
+ temp1 = *pBuf;
+ pBuf++;
+ temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
+ *pdwVal = (uint16_t)temp2;
+ pdwVal++;
+
+#if PMA_ACCESS > 1U
+ pdwVal++;
+#endif
+
+ pBuf++;
+ }
+}
+
+/**
+ * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @param USBx: USB peripheral instance register address.
+ * @param pbUsrBuf pointer to user memory area.
+ * @param wPMABufAddr address into PMA.
+ * @param wNBytes: no. of bytes to be copied.
+ * @retval None
+ */
+void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
+{
+ uint32_t n = (uint32_t)wNBytes >> 1;
+ uint32_t BaseAddr = (uint32_t)USBx;
+ uint32_t i, temp;
+ __IO uint16_t *pdwVal;
+ uint8_t *pBuf = pbUsrBuf;
+
+ pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+
+ for (i = n; i != 0U; i--)
+ {
+ temp = *(__IO uint16_t *)pdwVal;
+ pdwVal++;
+ *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ pBuf++;
+ *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
+ pBuf++;
+
+#if PMA_ACCESS > 1U
+ pdwVal++;
+#endif
+ }
+
+ if ((wNBytes % 2U) != 0U)
+ {
+ temp = *pdwVal;
+ *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined (USB) */
+#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f0xx_ll_utils.c b/Src/stm32f0xx_ll_utils.c
index 836204a..b256db3 100644
--- a/Src/stm32f0xx_ll_utils.c
+++ b/Src/stm32f0xx_ll_utils.c
@@ -6,32 +6,17 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.</center></h2>
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f0xx_ll_rcc.h"
#include "stm32f0xx_ll_utils.h"
