)]}'
{
  "commit": "0a8d78002ed874c0216565afde4ec8e99363d2af",
  "tree": "549bbfd18f933c7ef07223d5aa24d95f971f3f0f",
  "parents": [
    "e4a8c37fa438503f86c8156f54518077f34cfe9a"
  ],
  "author": {
    "name": "Ali Labbene",
    "email": "ali.labbene@st.com",
    "time": "Tue Feb 08 14:47:16 2022 +0100"
  },
  "committer": {
    "name": "Ali Labbene",
    "email": "ali.labbene@st.com",
    "time": "Tue Feb 08 14:47:16 2022 +0100"
  },
  "message": "[HAL][LL][USART] Handling of UART concurrent register access in case of race condition between Tx and Rx transfers\n",
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