tree 210c96268f68ef7ca0e6a35cb3f1fb840a9b0c44
parent 384da3096eba930f844931f4219082429896d60a
author Ali Labbene <ali.labbene@st.com> 1644327970 +0100
committer Ali Labbene <ali.labbene@st.com> 1644327970 +0100

[HAL][UART] Handling of UART concurrent register access in case of race condition between Tx and Rx transfers