)]}'
{
  "commit": "341c841112ab3e155c2b9c0944db86c5997786e5",
  "tree": "467e3ba29c09abc1afe419a72beac7632b9cd1cc",
  "parents": [
    "0a7d9c8ff94e2fd0b817ab938aa8d89c5b03f407"
  ],
  "author": {
    "name": "Ali Labbene",
    "email": "ali.labbene@st.com",
    "time": "Fri May 13 17:02:22 2022 +0100"
  },
  "committer": {
    "name": "Ali Labbene",
    "email": "ali.labbene@st.com",
    "time": "Fri May 13 17:02:22 2022 +0100"
  },
  "message": "[HAL][UART] Handle UART concurrent register access in case of race condition between Tx and Rx transfers\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1791d74d50c5d84450d6e3f84e039731f47a5e33",
      "old_mode": 33188,
      "old_path": "Inc/stm32f2xx_hal_uart.h",
      "new_id": "1aecf56fd2e4047e4b1a0440faa4c99dd928cdf6",
      "new_mode": 33188,
      "new_path": "Inc/stm32f2xx_hal_uart.h"
    },
    {
      "type": "modify",
      "old_id": "dd50e02b3b53984651a544d9e065685dd72922ea",
      "old_mode": 33188,
      "old_path": "Src/stm32f2xx_hal_uart.c",
      "new_id": "846ed7be2f213eb9da41b67128849d0d39532991",
      "new_mode": 33188,
      "new_path": "Src/stm32f2xx_hal_uart.c"
    }
  ]
}
