)]}'
{
  "commit": "aa1483f3c86ffdbd80c27d1f1672eec9d8f90a9d",
  "tree": "862081f99b0b613476e6f40279c78a779a81d2fc",
  "parents": [
    "1e662ebe9ac45893bfe9a05c16168d5002f4d988"
  ],
  "author": {
    "name": "Ali Labbene",
    "email": "ali.labbene@st.com",
    "time": "Tue Feb 08 15:00:44 2022 +0100"
  },
  "committer": {
    "name": "Ali Labbene",
    "email": "ali.labbene@st.com",
    "time": "Tue Feb 08 15:00:44 2022 +0100"
  },
  "message": "[HAL][LL][USART] Handling of USART concurrent register access in case of race condition between Tx and Rx transfers\n",
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