Release v1.5.7
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index ed22448..f321b33 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2019 STMicroelectronics.
+ * Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -37,14 +37,16 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
+#if defined(STM32U5)
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
+#endif /* STM32U5 || STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -104,6 +106,16 @@
#if defined(STM32H7)
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
/**
* @}
*/
@@ -131,7 +143,8 @@
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
+ input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -205,6 +218,11 @@
#endif
#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
/**
* @}
*/
@@ -213,10 +231,25 @@
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
/**
* @}
*/
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
+ inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
+ inter STM32 series compatibility */
+#endif
/**
* @}
*/
@@ -246,12 +279,25 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+ defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -316,7 +362,8 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+ defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@@ -393,6 +440,10 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -472,7 +523,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@@ -497,6 +548,9 @@
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
/**
@@ -541,6 +595,106 @@
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
/**
* @}
*/
@@ -608,14 +762,16 @@
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+ STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+ defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@@ -636,6 +792,42 @@
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@@ -816,7 +1008,8 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+ defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -873,9 +1066,19 @@
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
#endif /* STM32U5 */
/**
* @}
@@ -944,7 +1147,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1028,8 +1231,8 @@
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1040,15 +1243,42 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H5)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA */
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
-#endif /* STM32H7 */
+#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 */
/**
* @}
@@ -1215,6 +1445,10 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
+#if defined(STM32U5)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
/**
* @}
*/
@@ -1324,30 +1558,40 @@
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
+ the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
+ MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
+ or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
+ of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
+ transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
+ frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
+ de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
+ activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
+ (or time-stamp) */
#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
+ status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@@ -1518,7 +1762,8 @@
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
- )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+ HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1527,8 +1772,10 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
+ HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+ defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@@ -1562,16 +1809,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
- )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+ defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+ STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1645,10 +1897,111 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
/**
* @}
*/
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32WBA)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA */
+
+/**
+ * @}
+ */
+
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1674,7 +2027,8 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@@ -1931,7 +2285,8 @@
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+ defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@@ -2103,8 +2458,10 @@
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
/**
* @}
*/
@@ -2263,7 +2620,9 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -2272,8 +2631,12 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+ HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+ } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+ HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+ } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -2309,8 +2672,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+ HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -2814,6 +3177,11 @@
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
+#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3278,7 +3646,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3391,8 +3760,8 @@
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
-#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3403,7 +3772,112 @@
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
-#endif
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3420,7 +3894,9 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3473,6 +3949,11 @@
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3484,7 +3965,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3844,3 +4325,5 @@
#endif
#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index d0c3b72..ff69bd7 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -51,3 +51,6 @@
#endif
#endif /* __STM32_ASSERT_H */
+
+
+
diff --git a/Inc/stm32f3xx_hal.h b/Inc/stm32f3xx_hal.h
index c6692e2..eaa2c3c 100644
--- a/Inc/stm32f3xx_hal.h
+++ b/Inc/stm32f3xx_hal.h
@@ -15,7 +15,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_H
@@ -940,3 +940,5 @@
#endif
#endif /* __STM32F3xx_HAL_H */
+
+
diff --git a/Inc/stm32f3xx_hal_adc.h b/Inc/stm32f3xx_hal_adc.h
index 1957820..e151e3b 100644
--- a/Inc/stm32f3xx_hal_adc.h
+++ b/Inc/stm32f3xx_hal_adc.h
@@ -267,3 +267,4 @@
#endif
#endif /*__STM32F3xx_ADC_H */
+
diff --git a/Inc/stm32f3xx_hal_adc_ex.h b/Inc/stm32f3xx_hal_adc_ex.h
index 0525c74..3a0e62d 100644
--- a/Inc/stm32f3xx_hal_adc_ex.h
+++ b/Inc/stm32f3xx_hal_adc_ex.h
@@ -57,7 +57,7 @@
* - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group.
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
- * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
+ * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
@@ -690,7 +690,7 @@
#if defined(STM32F302xE)
/* ADC external triggers specific to device STM302xE: mask to differentiate */
/* standard triggers from specific timer 20U, needed for reallocation of */
-/* triggers common to ADC1&2 and to avoind mixing with standard */
+/* triggers common to ADC1&2 and to avoid mixing with standard */
/* triggers without remap. */
#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
@@ -3961,3 +3961,5 @@
#endif
#endif /*__STM32F3xx_ADC_H */
+
+
diff --git a/Inc/stm32f3xx_hal_cec.h b/Inc/stm32f3xx_hal_cec.h
index 4aee685..15ea72d 100644
--- a/Inc/stm32f3xx_hal_cec.h
+++ b/Inc/stm32f3xx_hal_cec.h
@@ -48,70 +48,80 @@
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
- It can be one of @ref CEC_Signal_Free_Time
+ It can be one of CEC_Signal_Free_Time
and belongs to the set {0,...,7} where
0x0 is the default configuration
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
- it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
- or CEC_EXTENDED_TOLERANCE */
+ it can be a value of CEC_Tolerance :
+ it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
- uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+ uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
+ Error stops the reception.
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
CEC_RX_STOP_ON_BRE: reception is stopped. */
- uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
+ Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
- uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+ uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
+ Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
- uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+ uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
+ Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
- It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+ It supersedes BREGEN and LBPEGEN bits for a broadcast message error
+ handling. It can take two values:
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
- a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
- and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+ a) BRE detection: error-bit generation on the CEC line if
+ BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
- no error-bit generation in case neither a) nor b) are satisfied. Additionally,
- there is no error-bit generation in case of Short Bit Period Error detection in
- a broadcast message while LSTN bit is set. */
+ no error-bit generation in case neither a) nor b) are satisfied.
+ Additionally, there is no error-bit generation in case of Short Bit
+ Period Error detection in a broadcast message while LSTN bit is set. */
- uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+ uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
- CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
+ CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end
+ of message transmission/reception. */
- uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+ uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
+ It can take two values:
- CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
- own address (OAR). Messages addressed to different destination are ignored.
+ CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
+ to its own address (OAR). Messages addressed to different destination
+ are ignored.
Broadcast messages are always received.
- CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
- address (OAR) with positive acknowledge. Messages addressed to different destination
- are received, but without interfering with the CEC bus: no acknowledge sent. */
+ CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
+ own address (OAR) with positive acknowledge. Messages addressed to
+ different destination are received, but without interfering with the
+ CEC bus: no acknowledge sent. */
- uint16_t OwnAddress; /*!< Own addresses configuration
- This parameter can be a value of @ref CEC_OWN_ADDRESS */
+ uint16_t OwnAddress; /*!< Own addresses configuration
+ This parameter can be a value of CEC_OWN_ADDRESS */
- uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
} CEC_InitTypeDef;
/**
* @brief HAL CEC State definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState
+ (see CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -159,37 +169,37 @@
typedef struct
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
- CEC_TypeDef *Instance; /*!< CEC registers base address */
+ CEC_TypeDef *Instance; /*!< CEC registers base address */
- CEC_InitTypeDef Init; /*!< CEC communication parameters */
+ CEC_InitTypeDef Init; /*!< CEC communication parameters */
- const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
- uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
+ uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
- uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
+ uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+ This parameter can be a value of HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+ This parameter can be a value of HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
- in case error is reported */
+ in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
- *hcec); /*!< CEC Tx Transfer completed callback */
+ *hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
- uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
- void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
+ uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
+ void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
- void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
- void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
+ void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
+ void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
} CEC_HandleTypeDef;
@@ -202,7 +212,7 @@
{
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
- HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
+ HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
} HAL_CEC_CallbackIDTypeDef;
@@ -212,7 +222,8 @@
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
- uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
+ uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed
+ callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
@@ -358,16 +369,16 @@
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
-#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
-#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
-#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
-#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
-#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
-#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
-#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
-#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
-#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
-#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
@@ -421,8 +432,8 @@
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
-#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
- CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+ CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
@@ -430,7 +441,7 @@
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
-#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
@@ -438,7 +449,7 @@
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
-#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
@@ -622,7 +633,8 @@
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \
+ (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
@@ -731,8 +743,9 @@
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
-#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
- ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
+ (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+ ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
diff --git a/Inc/stm32f3xx_hal_comp.h b/Inc/stm32f3xx_hal_comp.h
index d709181..a3a4a87 100644
--- a/Inc/stm32f3xx_hal_comp.h
+++ b/Inc/stm32f3xx_hal_comp.h
@@ -331,3 +331,4 @@
#endif
#endif /* STM32F3xx_HAL_COMP_H */
+
diff --git a/Inc/stm32f3xx_hal_comp_ex.h b/Inc/stm32f3xx_hal_comp_ex.h
index 05ecead..dbbd9b8 100644
--- a/Inc/stm32f3xx_hal_comp_ex.h
+++ b/Inc/stm32f3xx_hal_comp_ex.h
@@ -138,7 +138,7 @@
PA0 for COMP7) connected to comparator non inverting input */
#define COMP_NONINVERTINGINPUT_IO2 COMP_CSR_COMPxNONINSEL /*!< IO2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC output connected to comparator COMP1 non inverting input */
/**
* @}
*/
@@ -148,7 +148,7 @@
*/
#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA7 for COMP2, PB0 for COMP4, PB11 for COMP6)
connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC ouput connected to comparator COMP2 non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP2_CSR_COMP2INPDAC /*!< DAC output connected to comparator COMP2 non inverting input */
/**
* @}
*/
@@ -158,7 +158,7 @@
*/
#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA3 for COMP2)
connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP_CSR_COMP1SW1 /*!< DAC output connected to comparator COMP1 non inverting input */
/**
* @}
*/
@@ -169,7 +169,7 @@
#define COMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< IO1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
PA0 for COMP7) connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC ouput connected to comparator COMP1 non inverting input */
+#define COMP_NONINVERTINGINPUT_DAC1SWITCHCLOSED COMP1_CSR_COMP1SW1 /*!< DAC output connected to comparator COMP1 non inverting input */
/**
* @}
*/
@@ -2784,3 +2784,5 @@
#endif
#endif /* __STM32F3xx_HAL_COMP_EX_H */
+
+
diff --git a/Inc/stm32f3xx_hal_conf_template.h b/Inc/stm32f3xx_hal_conf_template.h
index 69c4421..2358932 100644
--- a/Inc/stm32f3xx_hal_conf_template.h
+++ b/Inc/stm32f3xx_hal_conf_template.h
@@ -14,7 +14,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
@@ -351,3 +351,6 @@
#endif
#endif /* __STM32F3xx_HAL_CONF_H */
+
+
+
diff --git a/Inc/stm32f3xx_hal_cortex.h b/Inc/stm32f3xx_hal_cortex.h
index d7de89f..1350620 100644
--- a/Inc/stm32f3xx_hal_cortex.h
+++ b/Inc/stm32f3xx_hal_cortex.h
@@ -9,12 +9,12 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CORTEX_H
@@ -420,3 +420,5 @@
#endif
#endif /* __STM32F3xx_HAL_CORTEX_H */
+
+
diff --git a/Inc/stm32f3xx_hal_dac.h b/Inc/stm32f3xx_hal_dac.h
index 87dd122..566d240 100644
--- a/Inc/stm32f3xx_hal_dac.h
+++ b/Inc/stm32f3xx_hal_dac.h
@@ -64,12 +64,12 @@
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer
- For a given DAC channel, is this paramater applies then DAC_OutputSwitch
+ For a given DAC channel, is this parameter applies then DAC_OutputSwitch
does not apply */
uint32_t DAC_OutputSwitch; /*!< Specifies whether the DAC channel output switch is enabled or disabled.
This parameter can be a value of @ref DAC_OutputSwitch
- For a given DAC channel, is this paramater applies then DAC_OutputBuffer
+ For a given DAC channel, is this parameter applies then DAC_OutputBuffer
does not apply */
}DAC_ChannelConfTypeDef;
@@ -209,7 +209,7 @@
*/
#endif /* DAC_CR_OUTEN1 */
-/** @defgroup DAC_data_alignement DAC data alignement
+/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R (0x00000000U)
@@ -490,3 +490,4 @@
#endif
#endif /* STM32F3xx_HAL_DAC_H */
+
diff --git a/Inc/stm32f3xx_hal_dac_ex.h b/Inc/stm32f3xx_hal_dac_ex.h
index d35ef75..b2fc723 100644
--- a/Inc/stm32f3xx_hal_dac_ex.h
+++ b/Inc/stm32f3xx_hal_dac_ex.h
@@ -338,3 +338,4 @@
#endif
#endif /* STM32F3xx_HAL_HAL_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_def.h b/Inc/stm32f3xx_hal_def.h
index d3d6df5..df8418b 100644
--- a/Inc/stm32f3xx_hal_def.h
+++ b/Inc/stm32f3xx_hal_def.h
@@ -54,7 +54,9 @@
/* Exported macro ------------------------------------------------------------*/
+#if !defined(UNUSED)
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU
@@ -172,3 +174,5 @@
#endif
#endif /* ___STM32F3xx_HAL_DEF */
+
+
diff --git a/Inc/stm32f3xx_hal_dma.h b/Inc/stm32f3xx_hal_dma.h
index fb09add..afd10eb 100644
--- a/Inc/stm32f3xx_hal_dma.h
+++ b/Inc/stm32f3xx_hal_dma.h
@@ -9,12 +9,12 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DMA_H
@@ -449,3 +449,4 @@
#endif
#endif /* __STM32F3xx_HAL_DMA_H */
+
diff --git a/Inc/stm32f3xx_hal_dma_ex.h b/Inc/stm32f3xx_hal_dma_ex.h
index 5b77465..691d12b 100644
--- a/Inc/stm32f3xx_hal_dma_ex.h
+++ b/Inc/stm32f3xx_hal_dma_ex.h
@@ -9,12 +9,12 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DMA_EX_H
@@ -269,3 +269,4 @@
/* STM32F373xC || STM32F378xx */
#endif /* __STM32F3xx_HAL_DMA_H */
+
diff --git a/Inc/stm32f3xx_hal_exti.h b/Inc/stm32f3xx_hal_exti.h
index 36facea..2e25ca3 100644
--- a/Inc/stm32f3xx_hal_exti.h
+++ b/Inc/stm32f3xx_hal_exti.h
@@ -399,3 +399,4 @@
#endif
#endif /* STM32F3xx_HAL_EXTI_H */
+
diff --git a/Inc/stm32f3xx_hal_flash.h b/Inc/stm32f3xx_hal_flash.h
index 6a17185..08be962 100644
--- a/Inc/stm32f3xx_hal_flash.h
+++ b/Inc/stm32f3xx_hal_flash.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -375,3 +374,5 @@
#endif
#endif /* __STM32F3xx_HAL_FLASH_H */
+
+
diff --git a/Inc/stm32f3xx_hal_flash_ex.h b/Inc/stm32f3xx_hal_flash_ex.h
index 901a8a0..7e6b302 100644
--- a/Inc/stm32f3xx_hal_flash_ex.h
+++ b/Inc/stm32f3xx_hal_flash_ex.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -469,3 +468,5 @@
#endif
#endif /* __STM32F3xx_HAL_FLASH_EX_H */
+
+
diff --git a/Inc/stm32f3xx_hal_gpio.h b/Inc/stm32f3xx_hal_gpio.h
index b1fcd02..29b5504 100644
--- a/Inc/stm32f3xx_hal_gpio.h
+++ b/Inc/stm32f3xx_hal_gpio.h
@@ -319,3 +319,5 @@
#endif
#endif /* __STM32F3xx_HAL_GPIO_H */
+
+
diff --git a/Inc/stm32f3xx_hal_gpio_ex.h b/Inc/stm32f3xx_hal_gpio_ex.h
index 1421e1e..8dd57aa 100644
--- a/Inc/stm32f3xx_hal_gpio_ex.h
+++ b/Inc/stm32f3xx_hal_gpio_ex.h
@@ -1517,3 +1517,4 @@
#endif
#endif /* __STM32F3xx_HAL_GPIO_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_hrtim.h b/Inc/stm32f3xx_hal_hrtim.h
index 2658e71..cfbc903 100644
--- a/Inc/stm32f3xx_hal_hrtim.h
+++ b/Inc/stm32f3xx_hal_hrtim.h
@@ -1352,10 +1352,10 @@
* @brief Constants defining the source and event to be sent on the
* synchronization outputs
*/
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
/**
* @}
*/
diff --git a/Inc/stm32f3xx_hal_i2c.h b/Inc/stm32f3xx_hal_i2c.h
index e4e2a95..814cb37 100644
--- a/Inc/stm32f3xx_hal_i2c.h
+++ b/Inc/stm32f3xx_hal_i2c.h
@@ -207,6 +207,7 @@
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@@ -217,6 +218,10 @@
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
+ __IO uint32_t Devaddress; /*!< I2C Target device address */
+
+ __IO uint32_t Memaddress; /*!< I2C Target memory address */
+
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
@@ -705,9 +710,9 @@
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
/**
* @}
@@ -800,8 +805,8 @@
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
- (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
- (~I2C_CR2_RD_WRN)))
+ (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+ (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
diff --git a/Inc/stm32f3xx_hal_i2s.h b/Inc/stm32f3xx_hal_i2s.h
index ace4aa9..a057535 100644
--- a/Inc/stm32f3xx_hal_i2s.h
+++ b/Inc/stm32f3xx_hal_i2s.h
@@ -584,3 +584,4 @@
#endif
#endif /* STM32F3xx_HAL_I2S_H */
+
diff --git a/Inc/stm32f3xx_hal_i2s_ex.h b/Inc/stm32f3xx_hal_i2s_ex.h
index cd14070..f43572a 100644
--- a/Inc/stm32f3xx_hal_i2s_ex.h
+++ b/Inc/stm32f3xx_hal_i2s_ex.h
@@ -180,3 +180,4 @@
#endif /* STM32F3xx_HAL_I2S_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_irda.h b/Inc/stm32f3xx_hal_irda.h
index ca76a38..6d5c375 100644
--- a/Inc/stm32f3xx_hal_irda.h
+++ b/Inc/stm32f3xx_hal_irda.h
@@ -850,3 +850,4 @@
#endif
#endif /* STM32F3xx_HAL_IRDA_H */
+
diff --git a/Inc/stm32f3xx_hal_irda_ex.h b/Inc/stm32f3xx_hal_irda_ex.h
index 3d4821f..decf6a5 100644
--- a/Inc/stm32f3xx_hal_irda_ex.h
+++ b/Inc/stm32f3xx_hal_irda_ex.h
@@ -49,10 +49,12 @@
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
-#elif defined(USART_CR1_M)
+#else
+#if defined(USART_CR1_M)
#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long frame */
-#endif
+#endif /* USART_CR1_M1 */
+#endif /* USART_CR1_M1 && USART_CR1_M0 */
/**
* @}
*/
@@ -74,13 +76,14 @@
* @param __CLOCKSOURCE__ output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) \
+ || defined(STM32F303xC) || defined(STM32F358xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
@@ -96,12 +99,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -117,12 +120,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -138,12 +141,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -159,12 +162,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -180,20 +183,21 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) \
+ || defined(STM32F302x8) || defined(STM32F318xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -209,7 +213,7 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -229,8 +233,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
@@ -246,12 +250,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -267,12 +271,12 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
@@ -288,7 +292,7 @@
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
@@ -343,33 +347,35 @@
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
-#elif defined(USART_CR1_M)
+#else
+#if defined(USART_CR1_M)
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
- if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x01FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- } \
- else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
- { \
- if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
- { \
+ } \
+ } \
+ else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
+ { \
+ if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
+ { \
(__HANDLE__)->Mask = 0x00FFU ; \
- } \
- else \
- { \
+ } \
+ else \
+ { \
(__HANDLE__)->Mask = 0x007FU ; \
- } \
- } \
-} while(0U)
-#endif
+ } \
+ } \
+ } while(0U)
+#endif /* USART_CR1_M */
+#endif /* USART_CR1_M && USART_CR1_M0 */
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.
@@ -379,10 +385,12 @@
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#elif defined(USART_CR1_M)
+#else
+#if defined(USART_CR1_M)
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
-#endif
+#endif /* USART_CR1_M */
+#endif /* USART_CR1_M && USART_CR1_M0 */
/**
* @}
*/
@@ -402,3 +410,4 @@
#endif
#endif /* STM32F3xx_HAL_IRDA_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_nand.h b/Inc/stm32f3xx_hal_nand.h
index 4160e2a..19d809b 100644
--- a/Inc/stm32f3xx_hal_nand.h
+++ b/Inc/stm32f3xx_hal_nand.h
@@ -24,10 +24,10 @@
extern "C" {
#endif
-#if defined(FMC_BANK3)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
+#if defined(FMC_BANK3)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
@@ -107,7 +107,7 @@
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
- Please check the Read Mode sequnece in the NAND device datasheet */
+ Please check the Read Mode sequence in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
@@ -127,7 +127,7 @@
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
- NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
+ NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
@@ -215,27 +215,27 @@
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
@@ -265,8 +265,8 @@
* @{
*/
/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
/**
* @}
*/
diff --git a/Inc/stm32f3xx_hal_nor.h b/Inc/stm32f3xx_hal_nor.h
index 5722807..7ae9d56 100644
--- a/Inc/stm32f3xx_hal_nor.h
+++ b/Inc/stm32f3xx_hal_nor.h
@@ -24,10 +24,10 @@
extern "C" {
#endif
-#if defined(FMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
+#if defined(FMC_BANK1)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
@@ -184,7 +184,7 @@
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout);
/**
* @}
*/
@@ -234,8 +234,8 @@
*/
/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
diff --git a/Inc/stm32f3xx_hal_opamp.h b/Inc/stm32f3xx_hal_opamp.h
index 02f6619..1c0ded0 100644
--- a/Inc/stm32f3xx_hal_opamp.h
+++ b/Inc/stm32f3xx_hal_opamp.h
@@ -521,3 +521,4 @@
#endif
#endif /* STM32F3xx_HAL_OPAMP_H */
+
diff --git a/Inc/stm32f3xx_hal_opamp_ex.h b/Inc/stm32f3xx_hal_opamp_ex.h
index 7384a78..f3b55b4 100644
--- a/Inc/stm32f3xx_hal_opamp_ex.h
+++ b/Inc/stm32f3xx_hal_opamp_ex.h
@@ -87,3 +87,4 @@
#endif
#endif /* STM32F3xx_HAL_OPAMP_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_pcd.h b/Inc/stm32f3xx_hal_pcd.h
index f037fc7..3a7a105 100644
--- a/Inc/stm32f3xx_hal_pcd.h
+++ b/Inc/stm32f3xx_hal_pcd.h
@@ -101,8 +101,8 @@
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
+ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
@@ -182,20 +182,20 @@
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
+#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
- & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
+ &= (uint16_t)(~(__INTERRUPT__)))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
- &= (uint16_t)(~(__INTERRUPT__)))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
+#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
+#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
@@ -261,12 +261,10 @@
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
@@ -326,24 +324,16 @@
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint16_t ep_mps, uint8_t ep_type);
-
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
@@ -427,14 +417,12 @@
#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\
- (&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
+#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \
+ (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -443,8 +431,9 @@
* @param wType Endpoint Type.
* @retval None
*/
-#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
- & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
+#define PCD_SET_EPTYPE(USBx, bEpNum, wType) \
+ (PCD_SET_ENDPOINT((USBx), (bEpNum), \
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
@@ -462,7 +451,7 @@
* @param bEpNum, bDir
* @retval None
*/
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
+#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
@@ -734,11 +723,13 @@
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
- + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) \
+ ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
+ ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
- + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) \
+ ((uint16_t *)((((uint32_t)(USBx)->BTABLE + \
+ ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/**
@@ -791,7 +782,7 @@
{ \
(wNBlocks)--; \
} \
- *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
+ *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
@@ -801,24 +792,29 @@
{ \
(wNBlocks)++; \
} \
- *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
+ *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
- if ((wCount) == 0U) \
+ \
+ *(pdwReg) &= 0x3FFU; \
+ \
+ if ((wCount) > 62U) \
{ \
- *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
- *(pdwReg) |= USB_CNTRX_BLSIZE; \
- } \
- else if((wCount) <= 62U) \
- { \
- PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
- PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+ if ((wCount) == 0U) \
+ { \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } \
+ else \
+ { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
+ } \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
diff --git a/Inc/stm32f3xx_hal_pcd_ex.h b/Inc/stm32f3xx_hal_pcd_ex.h
index 1b449fd..4a14977 100644
--- a/Inc/stm32f3xx_hal_pcd_ex.h
+++ b/Inc/stm32f3xx_hal_pcd_ex.h
@@ -22,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
@@ -75,7 +75,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32F3xx_HAL_PCD_EX_H */
diff --git a/Inc/stm32f3xx_hal_rcc.h b/Inc/stm32f3xx_hal_rcc.h
index 422137d..f083587 100644
--- a/Inc/stm32f3xx_hal_rcc.h
+++ b/Inc/stm32f3xx_hal_rcc.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -1734,3 +1733,5 @@
#endif
#endif /* __STM32F3xx_HAL_RCC_H */
+
+
diff --git a/Inc/stm32f3xx_hal_rcc_ex.h b/Inc/stm32f3xx_hal_rcc_ex.h
index 21bae0b..ca56527 100644
--- a/Inc/stm32f3xx_hal_rcc_ex.h
+++ b/Inc/stm32f3xx_hal_rcc_ex.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -3821,3 +3820,5 @@
#endif
#endif /* __STM32F3xx_HAL_RCC_EX_H */
+
+
diff --git a/Inc/stm32f3xx_hal_rtc.h b/Inc/stm32f3xx_hal_rtc.h
index 7d25304..7591894 100644
--- a/Inc/stm32f3xx_hal_rtc.h
+++ b/Inc/stm32f3xx_hal_rtc.h
@@ -17,25 +17,27 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_RTC_H
-#define __STM32F3xx_HAL_RTC_H
+#ifndef STM32F3xx_HAL_RTC_H
+#define STM32F3xx_HAL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
+
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
-/** @defgroup RTC RTC
+/** @addtogroup RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
@@ -50,7 +52,6 @@
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-
} HAL_RTCStateTypeDef;
/**
@@ -65,10 +66,10 @@
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
- This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+ This parameter can be a value of @ref RTC_Output_selection_Definitions */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
@@ -83,7 +84,7 @@
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
@@ -95,12 +96,12 @@
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
- uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
- corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ corresponding to Synchronous prescaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
@@ -162,38 +163,38 @@
typedef struct __RTC_HandleTypeDef
#else
typedef struct
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
{
- RTC_TypeDef *Instance; /*!< Register base address */
+ RTC_TypeDef *Instance; /*!< Register base address */
- RTC_InitTypeDef Init; /*!< RTC required parameters */
+ RTC_InitTypeDef Init; /*!< RTC required parameters */
- HAL_LockTypeDef Lock; /*!< RTC locking object */
+ HAL_LockTypeDef Lock; /*!< RTC locking object */
- __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
+ __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */
+ void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
- void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */
+ void (* AlarmBEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
- void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
+ void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */
- void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */
+ void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
- void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */
+ void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
- void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */
+ void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
#if defined(RTC_TAMPER3_SUPPORT)
- void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */
+ void (* Tamper3EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
#endif /* RTC_TAMPER3_SUPPORT */
- void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */
+ void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
- void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */
+ void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
} RTC_HandleTypeDef;
@@ -203,23 +204,23 @@
*/
typedef enum
{
- HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
- HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */
- HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
- HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */
- HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
- HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
+ HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
+ HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
+ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */
+ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */
+ HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
+ HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
#if defined(RTC_TAMPER3_SUPPORT)
- HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06u, /*!< RTC Tamper 3 Callback ID */
+ HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
#endif /* RTC_TAMPER3_SUPPORT */
- HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
- HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
-}HAL_RTC_CallbackIDTypeDef;
+ HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
+ HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
+} HAL_RTC_CallbackIDTypeDef;
/**
* @brief HAL RTC Callback pointer definition
*/
-typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
+typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
@@ -227,6 +228,7 @@
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
@@ -240,6 +242,17 @@
* @}
*/
+/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
+ * @{
+ */
+#define RTC_OUTPUT_DISABLE 0x00000000U
+#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
+#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
+#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
+/**
+ * @}
+ */
+
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
@@ -262,43 +275,42 @@
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x01)
/**
* @}
*/
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
-#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
+#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
/**
* @}
*/
-/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET 0x00000000U
-#define RTC_STOREOPERATION_SET RTC_CR_BCK
+#define RTC_STOREOPERATION_SET RTC_CR_BKP
/**
* @}
*/
-/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
-#define RTC_FORMAT_BIN 0x000000000U
-#define RTC_FORMAT_BCD 0x000000001U
+#define RTC_FORMAT_BIN 0x00000000U
+#define RTC_FORMAT_BCD 0x00000001U
/**
* @}
*/
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
* @{
*/
-/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
@@ -329,7 +341,7 @@
* @}
*/
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
@@ -338,7 +350,7 @@
* @}
*/
-/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE 0x00000000U
@@ -346,8 +358,7 @@
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_NONE | \
- RTC_ALARMMASK_DATEWEEKDAY | \
+#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \
RTC_ALARMMASK_HOURS | \
RTC_ALARMMASK_MINUTES | \
RTC_ALARMMASK_SECONDS)
@@ -365,41 +376,40 @@
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
-* @{
-*/
-#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are ignored in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are ignored in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] are ignored in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are ignored in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] are ignored in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] are ignored in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] are ignored in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are ignored in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] are ignored in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] are ignored in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] are ignored in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] are ignored in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] are ignored in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
- to activate alarm. */
+ * @{
+ */
+/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
+/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
+/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
+/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
+/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
+/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
+/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:0] are compared and must match to activate alarm. */
+#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
/**
* @}
*/
@@ -407,16 +417,10 @@
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
-#define RTC_IT_TS RTC_CR_TSIE
-#define RTC_IT_WUT RTC_CR_WUTIE
-#define RTC_IT_ALRB RTC_CR_ALRBIE
-#define RTC_IT_ALRA RTC_CR_ALRAIE
-#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/
-#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/
-#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/
-#endif /* RTC_TAMPER3_SUPPORT */
+#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
+#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
+#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */
+#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
/**
* @}
*/
@@ -424,24 +428,24 @@
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
-#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
+#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */
#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
+#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Tamper 3 event flag */
#endif /* RTC_TAMPER3_SUPPORT */
-#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
-#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
-#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
-#define RTC_FLAG_TSF RTC_ISR_TSF
-#define RTC_FLAG_WUTF RTC_ISR_WUTF
-#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
-#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
-#define RTC_FLAG_INITF RTC_ISR_INITF
-#define RTC_FLAG_RSF RTC_ISR_RSF
-#define RTC_FLAG_INITS RTC_ISR_INITS
-#define RTC_FLAG_SHPF RTC_ISR_SHPF
-#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
-#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
-#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
+#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */
+#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */
+#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */
+#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */
+#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */
+#define RTC_FLAG_ALRBF RTC_ISR_ALRBF /*!< Alarm B event flag */
+#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */
+#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */
+#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */
+#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */
+#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */
+#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */
+#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF /*!< ALRMBR register write allowance flag */
+#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */
/**
* @}
*/
@@ -451,20 +455,21 @@
*/
/* Exported macros -----------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
-/** @brief Reset RTC handle state
- * @param __HANDLE__ RTC handle.
+/** @brief Reset RTC handle state
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
- (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL;\
- (__HANDLE__)->MspDeInitCallback = NULL;\
- }while(0u)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_RTC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
@@ -474,21 +479,26 @@
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xCAU; \
- (__HANDLE__)->Instance->WPR = 0x53U; \
- } while(0U)
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \
+ (__HANDLE__)->Instance->WPR = 0xCAU; \
+ (__HANDLE__)->Instance->WPR = 0x53U; \
+ } while(0U)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xFFU; \
- } while(0U)
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \
+ (__HANDLE__)->Instance->WPR = 0xFFU; \
+ } while(0U)
+
+/**
+ * @brief Check whether the RTC Calendar is initialized.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
/**
* @brief Enable the RTC ALARMA peripheral.
@@ -533,9 +543,9 @@
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
@@ -549,7 +559,31 @@
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
+
+/**
+ * @brief Get the selected RTC Alarm's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag to check.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF: Alarm A interrupt flag
+ * @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag
+ * @arg RTC_FLAG_ALRBF: Alarm B interrupt flag
+ * @arg RTC_FLAG_ALRBWF: Alarm B 'write allowed' flag
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
+
+/**
+ * @brief Clear the RTC Alarm's pending flags.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm flag to be cleared.
+ * This parameter can be:
+ * @arg RTC_FLAG_ALRAF
+ * @arg RTC_FLAG_ALRBF
+ * @retval None
+ */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
@@ -560,106 +594,88 @@
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC Alarm's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to check.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @arg RTC_FLAG_ALRAWF
- * @arg RTC_FLAG_ALRBWF
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Alarm's pending flags.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @retval None
- */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
- * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @brief Enable interrupt on the RTC Alarm associated EXTI line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable interrupt on the RTC Alarm associated Exti line.
+ * @brief Disable interrupt on the RTC Alarm associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable event on the RTC Alarm associated Exti line.
+ * @brief Enable event on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable event on the RTC Alarm associated Exti line.
+ * @brief Disable event on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Clear the RTC Alarm associated Exti line flag.
+ * @brief Clear the RTC Alarm associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @brief Generate a Software interrupt on RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
@@ -671,14 +687,14 @@
#include "stm32f3xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
+
+/** @addtogroup RTC_Exported_Functions
* @{
*/
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup RTC_Exported_Functions_Group1
* @{
*/
-
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
@@ -694,27 +710,19 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+/** @addtogroup RTC_Exported_Functions_Group2
* @{
*/
-
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-
-/* RTC Daylight Saving Time functions *****************************************/
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+/** @addtogroup RTC_Exported_Functions_Group3
* @{
*/
/* RTC Alarm functions ********************************************************/
@@ -729,16 +737,23 @@
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+/** @addtogroup RTC_Exported_Functions_Group4
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
+
+/* RTC Daylight Saving Time functions *****************************************/
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+/** @addtogroup RTC_Exported_Functions_Group5
* @{
*/
/* Peripheral State functions *************************************************/
@@ -754,30 +769,39 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
-#define RTC_TR_RESERVED_MASK 0x007F7F7FU
-#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
+#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \
+ RTC_TR_MNT | RTC_TR_MNU | \
+ RTC_TR_ST | RTC_TR_SU | \
+ RTC_TR_PM))
+#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \
+ RTC_DR_MT | RTC_DR_MU | \
+ RTC_DR_DT | RTC_DR_DU | \
+ RTC_DR_WDU))
+#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT))
#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
-#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
- RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
- RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
- RTC_FLAG_INITF | RTC_FLAG_RSF | \
- RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
+#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
+ RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | \
+ RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \
+ RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
+ RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
-#define RTC_TIMEOUT_VALUE 1000
+#define RTC_TIMEOUT_VALUE 1000U
-#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19 /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
-/* Private macros -----------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
@@ -785,19 +809,25 @@
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
* @{
*/
-
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
+ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
+ ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
+
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
+
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
@@ -814,9 +844,7 @@
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
-
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
-
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
@@ -840,27 +868,27 @@
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U)
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
/**
* @}
@@ -870,13 +898,15 @@
* @}
*/
-/* Private functions -------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
-uint8_t RTC_ByteToBcd2(uint8_t Value);
-uint8_t RTC_Bcd2ToByte(uint8_t Value);
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t number);
+uint8_t RTC_Bcd2ToByte(uint8_t number);
/**
* @}
*/
@@ -893,4 +923,4 @@
}
#endif
-#endif /* __STM32F3xx_HAL_RTC_H */
+#endif /* STM32F3xx_HAL_RTC_H */
diff --git a/Inc/stm32f3xx_hal_rtc_ex.h b/Inc/stm32f3xx_hal_rtc_ex.h
index f956c86..f7a1834 100644
--- a/Inc/stm32f3xx_hal_rtc_ex.h
+++ b/Inc/stm32f3xx_hal_rtc_ex.h
@@ -17,27 +17,28 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_HAL_RTC_EX_H
-#define __STM32F3xx_HAL_RTC_EX_H
+#ifndef STM32F3xx_HAL_RTC_EX_H
+#define STM32F3xx_HAL_RTC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
+
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
-/** @defgroup RTCEx RTCEx
+/** @addtogroup RTCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTC Extended Exported Types
+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
* @{
*/
@@ -47,10 +48,10 @@
typedef struct
{
uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Definitions */
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
@@ -62,7 +63,7 @@
This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
- This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
@@ -72,72 +73,57 @@
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTC Extended Exported Constants
+
+/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
*/
-/** @defgroup RTCEx_Output_selection_Definitions RTC Extended Output Selection Definition
+/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definitions
* @{
*/
-#define RTC_OUTPUT_DISABLE 0x00000000U
-#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
-#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
-#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition
- * @{
- */
-#if RTC_BKP_NUMBER > 0U
-#define RTC_BKP_DR0 0x00000000U
-#define RTC_BKP_DR1 0x00000001U
-#define RTC_BKP_DR2 0x00000002U
-#define RTC_BKP_DR3 0x00000003U
-#define RTC_BKP_DR4 0x00000004U
-#endif /* RTC_BKP_NUMBER > 0U */
-
+#define RTC_BKP_DR0 0x00000000U
+#define RTC_BKP_DR1 0x00000001U
+#define RTC_BKP_DR2 0x00000002U
+#define RTC_BKP_DR3 0x00000003U
+#define RTC_BKP_DR4 0x00000004U
#if RTC_BKP_NUMBER > 5U
-#define RTC_BKP_DR5 0x00000005U
-#define RTC_BKP_DR6 0x00000006U
-#define RTC_BKP_DR7 0x00000007U
-#define RTC_BKP_DR8 0x00000008U
-#define RTC_BKP_DR9 0x00000009U
-#define RTC_BKP_DR10 0x0000000AU
-#define RTC_BKP_DR11 0x0000000BU
-#define RTC_BKP_DR12 0x0000000CU
-#define RTC_BKP_DR13 0x0000000DU
-#define RTC_BKP_DR14 0x0000000EU
-#define RTC_BKP_DR15 0x0000000FU
-#endif /* RTC_BKP_NUMBER > 5U */
-
+#define RTC_BKP_DR5 0x00000005U
+#define RTC_BKP_DR6 0x00000006U
+#define RTC_BKP_DR7 0x00000007U
+#define RTC_BKP_DR8 0x00000008U
+#define RTC_BKP_DR9 0x00000009U
+#define RTC_BKP_DR10 0x0000000AU
+#define RTC_BKP_DR11 0x0000000BU
+#define RTC_BKP_DR12 0x0000000CU
+#define RTC_BKP_DR13 0x0000000DU
+#define RTC_BKP_DR14 0x0000000EU
+#define RTC_BKP_DR15 0x0000000FU
#if RTC_BKP_NUMBER > 16U
-#define RTC_BKP_DR16 0x00000010U
-#define RTC_BKP_DR17 0x00000011U
-#define RTC_BKP_DR18 0x00000012U
-#define RTC_BKP_DR19 0x00000013U
-#endif /* RTC_BKP_NUMBER > 16U */
-
+#define RTC_BKP_DR16 0x00000010U
+#define RTC_BKP_DR17 0x00000011U
+#define RTC_BKP_DR18 0x00000012U
+#define RTC_BKP_DR19 0x00000013U
#if RTC_BKP_NUMBER > 20U
-#define RTC_BKP_DR20 0x00000014U
-#define RTC_BKP_DR21 0x00000015U
-#define RTC_BKP_DR22 0x00000016U
-#define RTC_BKP_DR23 0x00000017U
-#define RTC_BKP_DR24 0x00000018U
-#define RTC_BKP_DR25 0x00000019U
-#define RTC_BKP_DR26 0x0000001AU
-#define RTC_BKP_DR27 0x0000001BU
-#define RTC_BKP_DR28 0x0000001CU
-#define RTC_BKP_DR29 0x0000001DU
-#define RTC_BKP_DR30 0x0000001EU
-#define RTC_BKP_DR31 0x0000001FU
+#define RTC_BKP_DR20 0x00000014U
+#define RTC_BKP_DR21 0x00000015U
+#define RTC_BKP_DR22 0x00000016U
+#define RTC_BKP_DR23 0x00000017U
+#define RTC_BKP_DR24 0x00000018U
+#define RTC_BKP_DR25 0x00000019U
+#define RTC_BKP_DR26 0x0000001AU
+#define RTC_BKP_DR27 0x0000001BU
+#define RTC_BKP_DR28 0x0000001CU
+#define RTC_BKP_DR29 0x0000001DU
+#define RTC_BKP_DR30 0x0000001EU
+#define RTC_BKP_DR31 0x0000001FU
#endif /* RTC_BKP_NUMBER > 20U */
+#endif /* RTC_BKP_NUMBER > 16U */
+#endif /* RTC_BKP_NUMBER > 5U */
/**
* @}
*/
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition
+/** @defgroup RTCEx_Timestamp_Edges_Definitions RTCEx Timestamp Edges Definitions
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
@@ -146,15 +132,15 @@
* @}
*/
-/** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection
+/** @defgroup RTCEx_Timestamp_Pin_Selection RTC Timestamp Pin Selection
* @{
*/
-#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
+#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Extended Tamper Pins Definition
+/** @defgroup RTCEx_Tamper_Pin_Definitions RTCEx Tamper Pins Definitions
* @{
*/
#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
@@ -166,137 +152,151 @@
* @}
*/
+/** @defgroup RTCEx_Tamper_Pin_Selection RTC tamper Pins Selection
+ * @{
+ */
+#define RTC_TAMPERPIN_DEFAULT 0x00000000U
+/**
+ * @}
+ */
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition
+/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
+ * @{
+ */
+#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /*!< Enable global Tamper Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
-#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
+#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definition
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
* @{
*/
#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
-#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8
- consecutive samples at the active level. */
+#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_MASK RTC_TAFCR_TAMPFLT /*!< Masking all bits except those of
+ field TAMPFLT */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definition
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
* @{
*/
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768U */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384U */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAFCR_TAMPFREQ /*!< Masking all bits except those of
+ field TAMPFREQ */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definition
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
* @{
*/
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (RTC_TAFCR_TAMPPRCH_0 | RTC_TAFCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAFCR_TAMPPRCH /*!< Masking all bits except those of
+ field TAMPPRCH */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Extended Tamper TimeStampOnTamperDetection Definition
+/** @defgroup RTCEx_Tamper_Pull_Up_Definitions RTCEx Tamper Pull Up Definitions
* @{
*/
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_DISABLE RTC_TAFCR_TAMPPUDIS /*!< Tamper pins are not pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_MASK RTC_TAFCR_TAMPPUDIS /*!< Masking all bits except bit TAMPPUDIS */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAFCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAFCR_TAMPTS /*!< Masking all bits except bit TAMPTS */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definition
- * @{
- */
-#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< Tamper pins are not pre-charged before sampling */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definition
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (RTC_CR_WUCKSEL_2)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definition
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 32s, otherwise 2^20 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 16s, otherwise 2^19 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 8s, otherwise 2^18 RTCCLK pulses */
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definition
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth Calib Plus Pulses Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0] */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0]
- with Y = 512U, 256U, 128 when X = 32U, 16U, 8U */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
/**
* @}
*/
-/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definition
- * @{
- */
-#define RTC_CALIBOUTPUT_512HZ 0x00000000U
-#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definition
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions
* @{
*/
#define RTC_SHIFTADD1S_RESET 0x00000000U
@@ -305,19 +305,31 @@
* @}
*/
+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions
+ * @{
+ */
+#define RTC_CALIBOUTPUT_512HZ 0x00000000U
+#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
/**
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTC Extended Exported Macros
+/**
+ * @}
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
* @{
*/
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC Extended WakeUp Timer
+/* ---------------------------------WAKEUPTIMER-------------------------------*/
+
+/** @defgroup RTCEx_WakeUp_Timer RTCEx WakeUp Timer
* @{
*/
+
/**
* @brief Enable the RTC WakeUp Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
@@ -326,179 +338,186 @@
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
- * @brief Disable the RTC WakeUp Timer peripheral.
+ * @brief Disable the RTC Wakeup Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
/**
- * @brief Enable the RTC WakeUpTimer interrupt.
+ * @brief Enable the RTC Wakeup Timer interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC WakeUpTimer interrupt.
+ * @brief Disable the RTC Wakeup Timer interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @brief Check whether the specified RTC Wakeup Timer interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt to check.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
- * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @brief Check whether the specified RTC Wakeup timer interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+ * @param __INTERRUPT__ specifies the RTC Wakeup timer interrupt sources to check.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @brief Get the selected RTC Wakeup Timer's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
+ * @param __FLAG__ specifies the RTC Wakeup Timer flag to check.
* This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
+ * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt flag
+ * @arg RTC_FLAG_WUTWF: Wakeup Timer 'write allowed' flag
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
- * @brief Clear the RTC Wake Up timer's pending flags.
+ * @brief Clear the RTC Wakeup timer's pending flags.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
+ * @param __FLAG__ specifies the RTC Wakeup Timer Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt Flag
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-/* WAKE-UP TIMER EXTI */
-/* ------------------ */
/**
- * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable event on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable event on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable event on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable event on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Wakeup Timer associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Clear the RTC WakeUp Timer associated Exti line flag.
+ * @brief Clear the RTC Wakeup Timer associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.
+ * @brief Generate a Software interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
+
/**
* @}
*/
/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Extended Timestamp
+
+/** @defgroup RTCEx_Timestamp RTCEx Timestamp
* @{
*/
+
/**
- * @brief Enable the RTC TimeStamp peripheral.
+ * @brief Enable the RTC Timestamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
/**
- * @brief Disable the RTC TimeStamp peripheral.
+ * @brief Disable the RTC Timestamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
- * @brief Enable the RTC TimeStamp interrupt.
+ * @brief Enable the RTC Timestamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -506,9 +525,9 @@
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC TimeStamp interrupt.
+ * @brief Disable the RTC Timestamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -516,42 +535,43 @@
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @brief Check whether the specified RTC Timestamp interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
- * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @brief Check whether the specified RTC Timestamp interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC TimeStamp's flag status.
+ * @brief Get the selected RTC Timestamp's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
+ * @param __FLAG__ specifies the RTC Timestamp flag to check.
* This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
+ * @arg RTC_FLAG_TSF: Timestamp interrupt flag
+ * @arg RTC_FLAG_TSOVF: Timestamp overflow flag
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
- * @brief Clear the RTC Time Stamp's pending flags.
+ * @brief Clear the RTC Timestamp's pending flags.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag to clear.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
+ * @param __FLAG__ specifies the RTC Timestamp flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF: Timestamp interrupt flag
+ * @arg RTC_FLAG_TSOVF: Timestamp overflow flag
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -561,7 +581,8 @@
*/
/* ---------------------------------TAMPER------------------------------------*/
-/** @defgroup RTCEx_Tamper RTC Extended Tamper
+
+/** @defgroup RTCEx_Tamper RTCEx Tamper
* @{
*/
@@ -614,7 +635,7 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
* This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: Tamper interrupt
+ * @arg RTC_IT_TAMP: Tamper global interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
@@ -624,7 +645,7 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP: Tamper interrupt
+ * @arg RTC_IT_TAMP: Tamper global interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
@@ -634,138 +655,139 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
- * @arg RTC_IT_TAMP1: Tamper1 interrupt
- * @arg RTC_IT_TAMP2: Tamper2 interrupt
- * @arg RTC_IT_TAMP3: Tamper3 interrupt (*)
- * @note (*) RTC_IT_TAMP3 not present on all the devices
+ * @arg RTC_IT_TAMP1: Tamper 1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper 2 interrupt
+ * @arg RTC_IT_TAMP3: Tamper 3 interrupt
+ * @note RTC_IT_TAMP3 is not applicable to all devices.
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be:
- * @arg RTC_IT_TAMP: Tamper interrupt
+ * @arg RTC_IT_TAMP: Tamper global interrupt
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @arg RTC_FLAG_TAMP3F (*)
- * @note (*) RTC_FLAG_TAMP3F not present on all the devices
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
+ * @brief Get the selected RTC Tamper's flag status.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper flag to be checked.
+ * This parameter can be:
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag
+ * @note RTC_FLAG_TAMP3F is not applicable to all devices.
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
* @brief Clear the RTC Tamper's pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
- * @arg RTC_FLAG_TAMP3F (*)
- * @note (*) RTC_FLAG_TAMP3F not present on all the devices
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
+ * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag
+ * @note RTC_FLAG_TAMP3F is not applicable to all devices.
* @retval None
*/
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-
+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @}
*/
/* --------------------------TAMPER/TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Extended Tamper Timestamp EXTI
+/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI
* @{
*/
-/* TAMPER TIMESTAMP EXTI */
-/* --------------------- */
/**
- * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated EXTI line.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Tamper and Timestamp associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @brief Clear the RTC Tamper and Timestamp associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated EXTI line
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
@@ -773,8 +795,9 @@
* @}
*/
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Extended Calibration
+/* ------------------------------CALIBRATION----------------------------------*/
+
+/** @defgroup RTCEx_Calibration RTCEx Calibration
* @{
*/
@@ -811,10 +834,10 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
* This parameter can be:
- * @arg RTC_FLAG_SHPF
+ * @arg RTC_FLAG_SHPF: Shift pending flag
* @retval None
*/
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
* @}
*/
@@ -824,17 +847,17 @@
*/
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+/** @addtogroup RTCEx_Exported_Functions_Group1
+ * @{
+ */
+/* RTC Timestamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
@@ -845,24 +868,27 @@
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+#if defined(RTC_TAMPER3_SUPPORT)
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
+#endif /* RTC_TAMPER3_SUPPORT */
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#if defined(RTC_TAMPER3_SUPPORT)
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
-/* RTC Wake-up functions ******************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
- * @{
- */
-
+/** @addtogroup RTCEx_Exported_Functions_Group2
+ * @{
+ */
+/* RTC Wakeup functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
@@ -871,11 +897,10 @@
* @}
*/
+/** @addtogroup RTCEx_Exported_Functions_Group3
+ * @{
+ */
/* Extended Control functions ************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @{
- */
-
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
@@ -891,13 +916,12 @@
* @}
*/
+/** @addtogroup RTCEx_Exported_Functions_Group4
+ * @{
+ */
/* Extended RTC features functions *******************************************/
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
- * @{
- */
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-
/**
* @}
*/
@@ -909,7 +933,41 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19 /*!< External interrupt line 19 Connected to the RTC Tamper and Timestamp event */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+/* Masks Definition */
+#if defined(RTC_TAMPER3_SUPPORT)
+#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \
+ RTC_TAMPER_2 | \
+ RTC_TAMPER_3))
+
+#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \
+ RTC_FLAG_TAMP2F | \
+ RTC_FLAG_TAMP3F))
+#else /* RTC_TAMPER3_SUPPORT */
+#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \
+ RTC_TAMPER_2))
+
+#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \
+ RTC_FLAG_TAMP2F))
+#endif /* RTC_TAMPER3_SUPPORT */
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
+
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
* @{
*/
@@ -917,30 +975,35 @@
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
* @{
*/
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMA) || \
- ((OUTPUT) == RTC_OUTPUT_ALARMB) || \
- ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-
-#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & 0xFFFFFFD6U) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~RTC_TAMPER_ENABLE_BITS_MASK)) == 0x00U) && ((TAMPER) != 0U))
+#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
+#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT)
-
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+
+#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER) \
+ ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) \
+ && ( ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) \
+ || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \
+ || ( ((FILTER) == RTC_TAMPERFILTER_DISABLE) \
+ && ( ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) \
+ || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))))
+
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
@@ -949,14 +1012,18 @@
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
@@ -964,20 +1031,22 @@
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
-
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
((SEL) == RTC_SHIFTADD1S_SET))
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
+
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
+
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
@@ -1000,4 +1069,4 @@
}
#endif
-#endif /* __STM32F3xx_HAL_RTC_EX_H */
+#endif /* STM32F3xx_HAL_RTC_EX_H */
diff --git a/Inc/stm32f3xx_hal_smartcard.h b/Inc/stm32f3xx_hal_smartcard.h
index 4ab9a20..1c04277 100644
--- a/Inc/stm32f3xx_hal_smartcard.h
+++ b/Inc/stm32f3xx_hal_smartcard.h
@@ -1043,3 +1043,4 @@
#endif
#endif /* STM32F3xx_HAL_SMARTCARD_H */
+
diff --git a/Inc/stm32f3xx_hal_smartcard_ex.h b/Inc/stm32f3xx_hal_smartcard_ex.h
index ce4bcea..7167bf5 100644
--- a/Inc/stm32f3xx_hal_smartcard_ex.h
+++ b/Inc/stm32f3xx_hal_smartcard_ex.h
@@ -144,186 +144,189 @@
* @param __CLOCKSOURCE__ output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(STM32F302xE)|| defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) \
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\
break; \
- } \
+ } \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) \
+ || defined(STM32F302x8) || defined(STM32F318xx)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;\
break; \
- } \
+ } \
} \
else \
{ \
- (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#endif
+#endif /* STM32F302xE || STM32F303xE || STM32F398xx || STM32F302xC || STM32F303xC || STM32F358xx */
+
/** @brief Set the Transmission Completion flag
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
@@ -409,3 +412,4 @@
#endif
#endif /* STM32F3xx_HAL_SMARTCARD_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_smbus.h b/Inc/stm32f3xx_hal_smbus.h
index 4d19d76..19cef04 100644
--- a/Inc/stm32f3xx_hal_smbus.h
+++ b/Inc/stm32f3xx_hal_smbus.h
@@ -749,8 +749,8 @@
*/
/* Peripheral State and Errors functions **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
/**
* @}
diff --git a/Inc/stm32f3xx_hal_spi.h b/Inc/stm32f3xx_hal_spi.h
index bac566e..0b0e79e 100644
--- a/Inc/stm32f3xx_hal_spi.h
+++ b/Inc/stm32f3xx_hal_spi.h
@@ -777,7 +777,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+ pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
@@ -847,3 +848,4 @@
#endif
#endif /* STM32F3xx_HAL_SPI_H */
+
diff --git a/Inc/stm32f3xx_hal_spi_ex.h b/Inc/stm32f3xx_hal_spi_ex.h
index 4be551a..cd0f537 100644
--- a/Inc/stm32f3xx_hal_spi_ex.h
+++ b/Inc/stm32f3xx_hal_spi_ex.h
@@ -70,3 +70,4 @@
#endif
#endif /* STM32F3xx_HAL_SPI_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_sram.h b/Inc/stm32f3xx_hal_sram.h
index 52ef4f1..a130231 100644
--- a/Inc/stm32f3xx_hal_sram.h
+++ b/Inc/stm32f3xx_hal_sram.h
@@ -24,10 +24,10 @@
extern "C" {
#endif
-#if defined(FMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
+#if defined(FMC_BANK1)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
@@ -205,7 +205,7 @@
*/
/* SRAM State functions ******************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
/**
* @}
diff --git a/Inc/stm32f3xx_hal_tim.h b/Inc/stm32f3xx_hal_tim.h
index a1c8d88..2a782c5 100644
--- a/Inc/stm32f3xx_hal_tim.h
+++ b/Inc/stm32f3xx_hal_tim.h
@@ -754,6 +754,15 @@
* @}
*/
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+ * @{
+ */
+#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
@@ -803,16 +812,16 @@
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
-#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
+#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
+#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
+#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
+#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
-#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
-#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
-#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
/**
* @}
*/
@@ -1780,6 +1789,17 @@
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
+/** @brief Select the Capture/compare DMA request source.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __CCDMA__ specifies Capture/compare DMA request source
+ * This parameter can be one of the following values:
+ * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+ * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+ * @retval None
+ */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \
+ MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
/**
* @}
*/
@@ -1870,7 +1890,7 @@
#if defined(TIM_CR1_UIFREMAP)
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
- ((__MODE__) == TIM_UIFREMAP_ENALE))
+ ((__MODE__) == TIM_UIFREMAP_ENABLE))
#endif /* TIM_CR1_UIFREMAP */
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
@@ -1939,20 +1959,23 @@
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
+ ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3))
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
- ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
+ ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
@@ -2089,13 +2112,13 @@
((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
#endif /* TIM_CCMR1_OC1M_3 */
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
- ((__SELECTION__) == TIM_TS_ITR1) || \
- ((__SELECTION__) == TIM_TS_ITR2) || \
- ((__SELECTION__) == TIM_TS_ITR3) || \
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
+ ((__SELECTION__) == TIM_TS_ITR1) || \
+ ((__SELECTION__) == TIM_TS_ITR2) || \
+ ((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
- ((__SELECTION__) == TIM_TS_TI1FP1) || \
- ((__SELECTION__) == TIM_TS_TI2FP2) || \
+ ((__SELECTION__) == TIM_TS_TI1FP1) || \
+ ((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF))
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
@@ -2378,7 +2401,7 @@
* @{
*/
/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
diff --git a/Inc/stm32f3xx_hal_tim_ex.h b/Inc/stm32f3xx_hal_tim_ex.h
index 18f04f0..b95c503 100644
--- a/Inc/stm32f3xx_hal_tim_ex.h
+++ b/Inc/stm32f3xx_hal_tim_ex.h
@@ -316,7 +316,7 @@
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
diff --git a/Inc/stm32f3xx_hal_tsc.h b/Inc/stm32f3xx_hal_tsc.h
index 811eba5..365bafa 100644
--- a/Inc/stm32f3xx_hal_tsc.h
+++ b/Inc/stm32f3xx_hal_tsc.h
@@ -186,22 +186,38 @@
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{
*/
-#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
-#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
-#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
-#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
-#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
-#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
-#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
-#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
-#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
-#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
-#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
-#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
-#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
-#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
-#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
-#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
+#define TSC_CTPH_1CYCLE 0x00000000UL
+/*!< Charge transfer pulse high during 1 cycle (PGCLK) */
+#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0
+/*!< Charge transfer pulse high during 2 cycles (PGCLK) */
+#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1
+/*!< Charge transfer pulse high during 3 cycles (PGCLK) */
+#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 4 cycles (PGCLK) */
+#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2
+/*!< Charge transfer pulse high during 5 cycles (PGCLK) */
+#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 6 cycles (PGCLK) */
+#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 7 cycles (PGCLK) */
+#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 8 cycles (PGCLK) */
+#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3
+/*!< Charge transfer pulse high during 9 cycles (PGCLK) */
+#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 10 cycles (PGCLK) */
+#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 11 cycles (PGCLK) */
+#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 12 cycles (PGCLK) */
+#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2)
+/*!< Charge transfer pulse high during 13 cycles (PGCLK) */
+#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 14 cycles (PGCLK) */
+#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1)
+/*!< Charge transfer pulse high during 15 cycles (PGCLK) */
+#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0)
+/*!< Charge transfer pulse high during 16 cycles (PGCLK) */
/**
* @}
*/
@@ -209,22 +225,38 @@
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{
*/
-#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
-#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
-#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
-#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
-#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
-#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
-#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
-#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
-#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
-#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
-#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
-#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
-#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
-#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
-#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
-#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
+#define TSC_CTPL_1CYCLE 0x00000000UL
+/*!< Charge transfer pulse low during 1 cycle (PGCLK) */
+#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0
+/*!< Charge transfer pulse low during 2 cycles (PGCLK) */
+#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1
+/*!< Charge transfer pulse low during 3 cycles (PGCLK) */
+#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 4 cycles (PGCLK) */
+#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2
+/*!< Charge transfer pulse low during 5 cycles (PGCLK) */
+#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 6 cycles (PGCLK) */
+#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 7 cycles (PGCLK) */
+#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 8 cycles (PGCLK) */
+#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3
+/*!< Charge transfer pulse low during 9 cycles (PGCLK) */
+#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 10 cycles (PGCLK) */
+#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 11 cycles (PGCLK) */
+#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 12 cycles (PGCLK) */
+#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2)
+/*!< Charge transfer pulse low during 13 cycles (PGCLK) */
+#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 14 cycles (PGCLK) */
+#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1)
+/*!< Charge transfer pulse low during 15 cycles (PGCLK) */
+#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0)
+/*!< Charge transfer pulse low during 16 cycles (PGCLK) */
/**
* @}
*/
@@ -288,8 +320,11 @@
/** @defgroup TSC_Acquisition_Mode Acquisition Mode
* @{
*/
-#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
-#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
+#define TSC_ACQ_MODE_NORMAL 0x00000000UL
+/*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
+#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM
+/*!< Synchronized acquisition mode (acquisition starts if START bit is set and
+when the selected signal is detected on the SYNC input pin) */
/**
* @}
*/
@@ -382,10 +417,10 @@
* @retval None
*/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
-#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_TSC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
@@ -655,7 +690,7 @@
((__VALUE__) == TSC_MCV_2047) || \
((__VALUE__) == TSC_MCV_4095) || \
((__VALUE__) == TSC_MCV_8191) || \
- ((__VALUE__) == TSC_MCV_16383))
+ ((__VALUE__) == TSC_MCV_16383))
#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
@@ -740,8 +775,8 @@
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
+uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index);
/**
* @}
*/
@@ -750,7 +785,7 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config);
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
/**
* @}
@@ -766,8 +801,8 @@
*/
/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* TSC IRQHandler and Callbacks used in Interrupt mode */
void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
diff --git a/Inc/stm32f3xx_hal_uart.h b/Inc/stm32f3xx_hal_uart.h
index b422a60..d57ae55 100644
--- a/Inc/stm32f3xx_hal_uart.h
+++ b/Inc/stm32f3xx_hal_uart.h
@@ -216,7 +216,7 @@
UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint16_t TxXferSize; /*!< UART Tx Transfer size */
@@ -1585,3 +1585,4 @@
#endif
#endif /* STM32F3xx_HAL_UART_H */
+
diff --git a/Inc/stm32f3xx_hal_uart_ex.h b/Inc/stm32f3xx_hal_uart_ex.h
index fca1c43..058c49e 100644
--- a/Inc/stm32f3xx_hal_uart_ex.h
+++ b/Inc/stm32f3xx_hal_uart_ex.h
@@ -160,13 +160,14 @@
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) \
+ || defined(STM32F303xC) || defined(STM32F358xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
@@ -182,12 +183,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -203,12 +204,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -224,12 +225,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
- switch(__HAL_RCC_GET_UART4_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -245,12 +246,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
- switch(__HAL_RCC_GET_UART5_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -266,20 +267,21 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) \
+ || defined(STM32F302x8) || defined(STM32F318xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -295,7 +297,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
@@ -315,8 +317,8 @@
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
@@ -332,12 +334,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -353,12 +355,12 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
@@ -374,7 +376,7 @@
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
@@ -508,3 +510,4 @@
#endif
#endif /* STM32F3xx_HAL_UART_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_usart.h b/Inc/stm32f3xx_hal_usart.h
index c694c11..e4f6046 100644
--- a/Inc/stm32f3xx_hal_usart.h
+++ b/Inc/stm32f3xx_hal_usart.h
@@ -725,7 +725,8 @@
*/
/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
@@ -786,3 +787,4 @@
#endif
#endif /* STM32F3xx_HAL_USART_H */
+
diff --git a/Inc/stm32f3xx_hal_usart_ex.h b/Inc/stm32f3xx_hal_usart_ex.h
index 7994f4b..aec3688 100644
--- a/Inc/stm32f3xx_hal_usart_ex.h
+++ b/Inc/stm32f3xx_hal_usart_ex.h
@@ -51,7 +51,7 @@
#elif defined(USART_CR1_M)
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M) /*!< 9-bit long USART frame */
-#endif
+#endif /* USART_CR1_M0 && USART_CR1_M */
/**
* @}
*/
@@ -76,183 +76,185 @@
* @param __CLOCKSOURCE__ output variable.
* @retval USART clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) \
+ || defined(STM32F303xC) || defined(STM32F358xx)
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) \
+ || defined(STM32F302x8) || defined(STM32F318xx)
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
-#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
- switch(__HAL_RCC_GET_USART1_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
case RCC_USART1CLKSOURCE_PCLK2: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
- switch(__HAL_RCC_GET_USART2_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
case RCC_USART2CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
- switch(__HAL_RCC_GET_USART3_SOURCE()) \
- { \
+ switch(__HAL_RCC_GET_USART3_SOURCE()) \
+ { \
case RCC_USART3CLKSOURCE_PCLK1: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
- } \
+ } \
} \
else \
{ \
- (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || STM32F302xC || STM32F303xC || STM32F358xx */
@@ -336,7 +338,7 @@
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
-#endif
+#endif /* USART_CR1_M0 && USART_CR1_M */
/**
* @brief Ensure that USART frame length is valid.
@@ -350,7 +352,7 @@
#elif defined(USART_CR1_M)
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
-#endif
+#endif /* USART_CR1_M0 && USART_CR1_M */
/**
@@ -399,3 +401,4 @@
#endif
#endif /* STM32F3xx_HAL_USART_EX_H */
+
diff --git a/Inc/stm32f3xx_hal_wwdg.h b/Inc/stm32f3xx_hal_wwdg.h
index 1513db6..1960f39 100644
--- a/Inc/stm32f3xx_hal_wwdg.h
+++ b/Inc/stm32f3xx_hal_wwdg.h
@@ -183,7 +183,7 @@
/**
* @brief Enable the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
+ * @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
diff --git a/Inc/stm32f3xx_ll_adc.h b/Inc/stm32f3xx_ll_adc.h
index 4d992b4..fa1d43e 100644
--- a/Inc/stm32f3xx_ll_adc.h
+++ b/Inc/stm32f3xx_ll_adc.h
@@ -31,7 +31,7 @@
* @{
*/
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. */
+/* Note: Devices of STM32F3 series embed 1 out of 2 different ADC IP. */
/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
/* features (refer to reference manual). */
@@ -431,7 +431,7 @@
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
- @note On this STM32 serie, if ADC group injected is used, some
+ @note On this STM32 series, if ADC group injected is used, some
clock ratio constraints between ADC clock and AHB clock
must be respected. Refer to reference manual.
@@ -518,7 +518,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
@@ -578,7 +578,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
@@ -709,7 +709,7 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
@@ -732,7 +732,7 @@
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -1444,7 +1444,7 @@
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
+/* STM32 series: */
/* - ADC calibration time: maximum delay is 112/fADC. */
/* (refer to device datasheet, parameter "tCAL") */
/* - ADC enable time: maximum delay is 1 conversion cycle. */
@@ -1475,7 +1475,7 @@
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 120U) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles */
/* are required between ADC end of calibration and ADC enable. */
/* Wait time can be computed in user application by waiting for the */
/* equivalent number of CPU cycles, by taking into account */
@@ -2293,7 +2293,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -2343,7 +2343,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -2527,11 +2527,11 @@
/**
* @brief Set parameter common to several ADC: Clock source and prescaler.
- * @note On this STM32 serie, if ADC group injected is used, some
+ * @note On this STM32 series, if ADC group injected is used, some
* clock ratio constraints between ADC clock and AHB clock
* must be respected.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2587,7 +2587,7 @@
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2657,7 +2657,7 @@
* both calibration factors must be concatenated.
* To perform this processing, use helper macro
* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
@@ -2707,7 +2707,7 @@
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2746,7 +2746,7 @@
* @brief Set ADC conversion data alignment.
* @note Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2817,7 +2817,7 @@
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2899,7 +2899,7 @@
* to disable state using function LL_ADC_SetOffsetState().
* @note If a channel is mapped on several offsets numbers, only the offset
* with the lowest value is considered for the subtraction.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3071,7 +3071,7 @@
* @note This function should be needed only in case of offset to be
* enabled-disabled dynamically, and should not be needed in other cases:
* function LL_ADC_SetOffset() automatically enables the offset.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3136,7 +3136,7 @@
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external IP (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -3144,7 +3144,7 @@
* function @ref LL_ADC_REG_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3325,7 +3325,7 @@
/**
* @brief Set ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3387,7 +3387,7 @@
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3479,7 +3479,7 @@
* continuous mode and sequencer discontinuous mode.
* @note It is not possible to enable both ADC auto-injected mode
* and ADC group regular sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3532,17 +3532,17 @@
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3632,7 +3632,7 @@
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
@@ -3739,7 +3739,7 @@
* conversions launched successively automatically.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3794,7 +3794,7 @@
* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3856,7 +3856,7 @@
* The default setting of overrun is data preserved.
* Therefore, for compatibility with all devices, parameter
* overrun should be set to data overwritten.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3898,22 +3898,22 @@
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external IP (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
* In case of need to modify trigger edge, use
* function @ref LL_ADC_INJ_SetTriggerEdge().
- * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * @note Caution to ADC group injected contexts queue: On this STM32 series,
* using successively several times this function will appear has
* having no effect.
* This is due to ADC group injected contexts queue (this feature
- * cannot be disabled on this STM32 serie).
+ * cannot be disabled on this STM32 series).
* To set several features of ADC group injected, use
* function @ref LL_ADC_INJ_ConfigQueueContext().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4080,7 +4080,7 @@
/**
* @brief Set ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4120,14 +4120,14 @@
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * @note Caution to ADC group injected contexts queue: On this STM32 series,
* using successively several times this function will appear has
* having no effect.
* This is due to ADC group injected contexts queue (this feature
- * cannot be disabled on this STM32 serie).
+ * cannot be disabled on this STM32 series).
* To set several features of ADC group injected, use
* function @ref LL_ADC_INJ_ConfigQueueContext().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4204,18 +4204,18 @@
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * @note Caution to ADC group injected contexts queue: On this STM32 series,
* using successively several times this function will appear has
* having no effect.
* This is due to ADC group injected contexts queue (this feature
- * cannot be disabled on this STM32 serie).
+ * cannot be disabled on this STM32 series).
* To set several features of ADC group injected, use
* function @ref LL_ADC_INJ_ConfigQueueContext().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4367,7 +4367,7 @@
* from ADC group regular.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4425,7 +4425,7 @@
* on either groups regular or injected.
* @note A modification of the context mode (bit JQDIS) causes the contexts
* queue to be flushed and the register JSQR is cleared.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4471,11 +4471,11 @@
* @arg @ref LL_ADC_INJ_GetTriggerSource()
* @arg @ref LL_ADC_INJ_GetTriggerEdge()
* @arg @ref LL_ADC_INJ_GetSequencerRanks()
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4742,7 +4742,7 @@
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -4751,7 +4751,7 @@
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4839,7 +4839,7 @@
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -4939,7 +4939,7 @@
* @note For ADC channels configured in differential mode, both inputs
* should be biased at (Vref+)/2 +/-200mV.
* (Vref+ is the analog voltage reference)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @note One or several values can be selected.
@@ -5047,7 +5047,7 @@
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5068,7 +5068,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5205,7 +5205,7 @@
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5226,7 +5226,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5369,7 +5369,7 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5390,7 +5390,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5431,7 +5431,7 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5452,7 +5452,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5540,7 +5540,7 @@
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -5619,7 +5619,7 @@
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled
* or enabled without conversion on going on group regular.
@@ -5693,7 +5693,7 @@
* - ADC resolution 10 bits can have maximum delay of 10 cycles.
* - ADC resolution 8 bits can have maximum delay of 8 cycles.
* - ADC resolution 6 bits can have maximum delay of 6 cycles.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -5764,12 +5764,12 @@
/**
* @brief Enable ADC instance internal voltage regulator.
- * @note On this STM32 serie, after ADC internal voltage regulator enable,
+ * @note On this STM32 series, after ADC internal voltage regulator enable,
* a delay for ADC internal voltage regulator stabilization
* is required before performing a ADC calibration or ADC enable.
* Refer to device datasheet, parameter tADCVREG_STUP.
* Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
@@ -5793,7 +5793,7 @@
/**
* @brief Disable ADC internal voltage regulator.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
@@ -5818,14 +5818,14 @@
/**
* @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
+ * @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled and ADC internal voltage regulator enabled.
* @rmtoll CR ADEN LL_ADC_Enable
@@ -5844,7 +5844,7 @@
/**
* @brief Disable the selected ADC instance.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be not disabled. Must be enabled without conversion on going
* on either groups regular or injected.
@@ -5864,7 +5864,7 @@
/**
* @brief Get the selected ADC instance enable state.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll CR ADEN LL_ADC_IsEnabled
@@ -5890,7 +5890,7 @@
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
- * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * @note On this STM32 series, a minimum number of ADC clock cycles
* are required between ADC end of calibration and ADC enable.
* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
* @note For devices with differential mode available:
@@ -5899,7 +5899,7 @@
* (calibration run must be performed for each of these
* differential modes, if used afterwards and if the application
* requires their calibration).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
@@ -5941,14 +5941,14 @@
/**
* @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
@@ -5969,7 +5969,7 @@
/**
* @brief Stop ADC group regular conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group regular,
* without ADC disable command on going.
@@ -6124,14 +6124,14 @@
/**
* @brief Start ADC group injected conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group injected,
* without conversion stop command on going on group injected,
@@ -6152,7 +6152,7 @@
/**
* @brief Stop ADC group injected conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group injected,
* without ADC disable command on going.
@@ -6336,7 +6336,7 @@
/**
* @brief Get flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
@@ -6460,7 +6460,7 @@
/**
* @brief Clear flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
@@ -7570,8 +7570,8 @@
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or external from timer or external interrupt.
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
- (only trigger polarity available on this STM32 serie).
+ @note On this STM32 series, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 series).
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
@@ -7624,8 +7624,8 @@
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or external from timer or external interrupt.
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
- (only trigger polarity available on this STM32 serie).
+ @note On this STM32 series, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 series).
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
@@ -7665,9 +7665,9 @@
* @{
*/
#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
-#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
-#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
/**
* @}
@@ -7677,8 +7677,8 @@
* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
* @{
*/
-#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
-#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
/**
* @}
@@ -7703,7 +7703,7 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
/**
@@ -7722,7 +7722,7 @@
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -8058,7 +8058,7 @@
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
+/* STM32 series: */
/* - ADC enable time: maximum delay is 1us */
/* (refer to device datasheet, parameter "tSTAB") */
/* - ADC conversion time: duration depending on ADC clock and ADC */
@@ -8072,7 +8072,7 @@
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /*!< Delay for internal voltage reference stabilization time */
/* Delay required between ADC disable and ADC calibration start. */
-/* Note: On this STM32 serie, before starting a calibration, */
+/* Note: On this STM32 series, before starting a calibration, */
/* ADC must be disabled. */
/* A minimum number of ADC clock cycles are required */
/* between ADC disable state and calibration start. */
@@ -8479,7 +8479,7 @@
* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */
/* This macro has been kept anyway for compatibility with other */
/* STM32 families featuring different ADC resolutions. */
#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
@@ -8501,7 +8501,7 @@
* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */
/* This macro has been kept anyway for compatibility with other */
/* STM32 families featuring different ADC resolutions. */
#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
@@ -8615,7 +8615,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -8663,7 +8663,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -8965,8 +8965,8 @@
/**
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or external from timer or external interrupt.
- * @note On this STM32 serie, external trigger is set with trigger polarity:
- * rising edge (only trigger polarity available on this STM32 serie).
+ * @note On this STM32 series, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 series).
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
@@ -8984,7 +8984,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
-/* Note: On this STM32 serie, ADC group regular external trigger edge */
+/* Note: On this STM32 series, ADC group regular external trigger edge */
/* is used to perform a ADC conversion start. */
/* This function does not set external trigger edge. */
/* This feature is set using function */
@@ -9064,7 +9064,7 @@
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
- * @note On this STM32 serie, group regular sequencer configuration
+ * @note On this STM32 series, group regular sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -9125,7 +9125,7 @@
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
- * @note On this STM32 serie, group regular sequencer configuration
+ * @note On this STM32 series, group regular sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -9215,13 +9215,13 @@
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
@@ -9300,7 +9300,7 @@
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
@@ -9499,8 +9499,8 @@
/**
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or external from timer or external interrupt.
- * @note On this STM32 serie, external trigger is set with trigger polarity:
- * rising edge (only trigger polarity available on this STM32 serie).
+ * @note On this STM32 series, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 series).
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
@@ -9518,7 +9518,7 @@
*/
__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
-/* Note: On this STM32 serie, ADC group injected external trigger edge */
+/* Note: On this STM32 series, ADC group injected external trigger edge */
/* is used to perform a ADC conversion start. */
/* This function does not set external trigger edge. */
/* This feature is set using function */
@@ -9576,7 +9576,7 @@
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
- * @note On this STM32 serie, group injected sequencer configuration
+ * @note On this STM32 series, group injected sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -9604,7 +9604,7 @@
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
- * @note On this STM32 serie, group injected sequencer configuration
+ * @note On this STM32 series, group injected sequencer configuration
* is conditioned to ADC instance sequencer mode.
* If ADC instance sequencer mode is disabled, sequencers of
* all groups (group regular, group injected) can be configured
@@ -9663,7 +9663,7 @@
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
@@ -9902,7 +9902,7 @@
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
* Refer to reference manual for ADC processing time of
- * this STM32 serie.
+ * this STM32 series.
* @note In case of ADC conversion of internal channel (VrefInt,
* temperature sensor, ...), a sampling time minimum value
* is required.
@@ -9980,7 +9980,7 @@
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
* Refer to reference manual for ADC processing time of
- * this STM32 serie.
+ * this STM32 series.
* @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
@@ -10060,7 +10060,7 @@
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -10162,7 +10162,7 @@
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -10241,7 +10241,7 @@
/**
* @brief Set ADC analog watchdog threshold value of threshold
* high or low.
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * @note On this STM32 series, there is only 1 kind of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -10297,7 +10297,7 @@
/**
* @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
+ * @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
@@ -10335,12 +10335,12 @@
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
- * @note On this STM32 serie, before starting a calibration,
+ * @note On this STM32 series, before starting a calibration,
* ADC must be disabled.
* A minimum number of ADC clock cycles are required
* between ADC disable state and calibration start.
* Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
- * @note On this STM32 serie, hardware prerequisite before starting a calibration:
+ * @note On this STM32 series, hardware prerequisite before starting a calibration:
the ADC must have been in power-on state for at least
two ADC clock cycles.
* @rmtoll CR2 CAL LL_ADC_StartCalibration
@@ -10373,7 +10373,7 @@
/**
* @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
@@ -10397,7 +10397,7 @@
* @note No more ADC conversion will start at next trigger event
* following the ADC stop conversion command.
* If a conversion is on-going, it will be completed.
- * @note On this STM32 serie, there is no specific command
+ * @note On this STM32 series, there is no specific command
* to stop a conversion on-going or to stop ADC converting
* in continuous mode. These actions can be performed
* using function @ref LL_ADC_Disable().
@@ -10449,7 +10449,7 @@
/**
* @brief Start ADC group injected conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
@@ -10473,7 +10473,7 @@
* @note No more ADC conversion will start at next trigger event
* following the ADC stop conversion command.
* If a conversion is on-going, it will be completed.
- * @note On this STM32 serie, there is no specific command
+ * @note On this STM32 series, there is no specific command
* to stop a conversion on-going or to stop ADC converting
* in continuous mode. These actions can be performed
* using function @ref LL_ADC_Disable().
@@ -10555,7 +10555,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* Note: on this STM32 series, there is no flag ADC group regular */
/* end of unitary conversion. */
/* Flag noted as "EOC" is corresponding to flag "EOS" */
/* in other STM32 families). */
@@ -10571,7 +10571,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -10597,7 +10597,7 @@
*/
__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* Note: on this STM32 series, there is no flag ADC group regular */
/* end of unitary conversion. */
/* Flag noted as "EOC" is corresponding to flag "EOS" */
/* in other STM32 families). */
@@ -10613,7 +10613,7 @@
*/
__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -10647,7 +10647,7 @@
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* Note: on this STM32 series, there is no flag ADC group regular */
/* end of unitary conversion. */
/* Flag noted as "EOC" is corresponding to flag "EOS" */
/* in other STM32 families). */
@@ -10663,7 +10663,7 @@
*/
__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -10689,7 +10689,7 @@
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* Note: on this STM32 series, there is no flag ADC group regular */
/* end of unitary conversion. */
/* Flag noted as "EOC" is corresponding to flag "EOS" */
/* in other STM32 families). */
@@ -10705,7 +10705,7 @@
*/
__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -10732,7 +10732,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* Note: on this STM32 series, there is no flag ADC group regular */
/* end of unitary conversion. */
/* Flag noted as "EOC" is corresponding to flag "EOS" */
/* in other STM32 families). */
@@ -10749,7 +10749,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* Note: on this STM32 series, there is no flag ADC group injected */
/* end of unitary conversion. */
/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
/* in other STM32 families). */
@@ -10825,3 +10825,4 @@
#endif
#endif /* __STM32F3xx_LL_ADC_H */
+
diff --git a/Inc/stm32f3xx_ll_bus.h b/Inc/stm32f3xx_ll_bus.h
index 28a9f64..92e1407 100644
--- a/Inc/stm32f3xx_ll_bus.h
+++ b/Inc/stm32f3xx_ll_bus.h
@@ -26,10 +26,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -1058,3 +1057,4 @@
#endif
#endif /* __STM32F3xx_LL_BUS_H */
+
diff --git a/Inc/stm32f3xx_ll_comp.h b/Inc/stm32f3xx_ll_comp.h
index 2166ab3..655e57e 100644
--- a/Inc/stm32f3xx_ll_comp.h
+++ b/Inc/stm32f3xx_ll_comp.h
@@ -31,7 +31,7 @@
* @{
*/
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
+/* Note: Devices of STM32F3 series embed 1 out of 2 different comparator IP. */
/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
/* COMP IP from 3 to 7 instances and other specific features */
/* (comparator output blanking, ...) (refer to reference manual). */
@@ -234,7 +234,7 @@
*/
#define LL_COMP_OUTPUT_NONE ((uint32_t)0x00000000) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) (specific to COMP instance: COMP2) */
#if defined(COMP_CSR_COMPxOUT)
-/* Note: Output redirection common to all COMP instances, all STM32F3 serie */
+/* Note: Output redirection common to all COMP instances, all STM32F3 series */
/* devices. */
#define LL_COMP_OUTPUT_TIM1_BKIN (COMP_CSR_COMPxOUTSEL_0) /*!< COMP output connected to TIM1 break input (BKIN) */
#define LL_COMP_OUTPUT_TIM1_BKIN2 (COMP_CSR_COMPxOUTSEL_1) /*!< COMP output connected to TIM1 break input 2 (BKIN2) */
@@ -259,7 +259,7 @@
/* Refer to literal definitions above for COMP instance constraints. */
/* Note: Some output redirections cannot have a generic naming, */
/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
+/* (For example: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
@@ -298,7 +298,7 @@
/* Refer to literal definitions above for COMP instance constraints. */
/* Note: Some output redirections cannot have a generic naming, */
/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
+/* (For example: LL_COMP_OUTPUT_TIM2_OCCLR_COMP2 and */
/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
@@ -342,7 +342,7 @@
/* Refer to literal definitions above for COMP instance constraints. */
/* Note: Some output redirections cannot have a generic naming, */
/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 and */
+/* (For example: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2 and */
/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
#define LL_COMP_OUTPUT_TIM1_OCCLR LL_COMP_OUTPUT_TIM1_OCCLR_COMP1_2 /*!< COMP output connected to TIM1 OCREF clear. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
@@ -419,7 +419,7 @@
/* Refer to literal definitions above for COMP instance constraints. */
/* Note: Some output redirections cannot have a generic naming, */
/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 and */
+/* (For example: LL_COMP_OUTPUT_TIM2_OCCLR_COMP1_2_3 and */
/* LL_COMP_OUTPUT_TIM2_OCCLR_COMP6). */
#define LL_COMP_OUTPUT_TIM1_IC1 LL_COMP_OUTPUT_TIM1_IC1_COMP1_2 /*!< COMP output connected to TIM1 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
#define LL_COMP_OUTPUT_TIM1_IC2 LL_COMP_OUTPUT_TIM1_IC2_COMP7 /*!< COMP output connected to TIM2 input capture 1. Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
@@ -637,7 +637,7 @@
* @retval COMP common instance or value "0" if there is no COMP common instance.
*/
#if defined(COMP1) && defined(COMP2) && defined(COMP3) && defined(COMP4) && defined(COMP5) && defined(COMP6) && defined(COMP7)
-/* Note: On STM32F3 serie devices with 7 comparator instances, */
+/* Note: On STM32F3 series devices with 7 comparator instances, */
/* COMP instance COMP7 has no other comparator instance to work */
/* in pair with: window mode is not available for COMP7. */
#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
@@ -674,7 +674,7 @@
) \
)
#elif defined(COMP2) && defined(COMP4) && defined(COMP6)
-/* Note: On STM32F3 serie devices with 3 comparator instances (COMP2, 4, 6) */
+/* Note: On STM32F3 series devices with 3 comparator instances (COMP2, 4, 6) */
/* COMP instances have no other comparator instance to work */
/* in pair with: window mode is not available for all COMP instances. */
#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \
@@ -817,7 +817,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, a voltage scaler is used
+ * @note On this STM32 series, a voltage scaler is used
* when COMP input is based on VrefInt (VrefInt or subdivision
* of VrefInt):
* Voltage scaler requires a delay for voltage stabilization.
@@ -952,7 +952,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, a voltage scaler is used
+ * @note On this STM32 series, a voltage scaler is used
* when COMP input is based on VrefInt (VrefInt or subdivision
* of VrefInt):
* Voltage scaler requires a delay for voltage stabilization.
@@ -1621,7 +1621,7 @@
/* Refer to literal definitions above for COMP instance constraints. */
/* Note: Some output redirections cannot have a generic naming, */
/* due to literal value different depending on COMP instance. */
-/* (For exemple: LL_COMP_OUTPUT_TIM3_IC1_COMP1 and */
+/* (For example: LL_COMP_OUTPUT_TIM3_IC1_COMP1 and */
/* LL_COMP_OUTPUT_TIM3_IC1_COMP2). */
#define LL_COMP_OUTPUT_TIM15_BKIN LL_COMP_OUTPUT_TIM15_BKIN_COMP1 /*!< COMP output connected to TIM15 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
#define LL_COMP_OUTPUT_TIM16_BKIN LL_COMP_OUTPUT_TIM16_BKIN_COMP2 /*!< COMP output connected to TIM16 break input (BKIN). Caution: Parameter specific to COMP instances, defined with generic naming, not taking into account COMP instance constraints. Refer to literal definitions above for COMP instance constraints. */
@@ -2256,3 +2256,5 @@
#endif
#endif /* __STM32F3xx_LL_COMP_H */
+
+
diff --git a/Inc/stm32f3xx_ll_cortex.h b/Inc/stm32f3xx_ll_cortex.h
index 8a4e967..a16dc62 100644
--- a/Inc/stm32f3xx_ll_cortex.h
+++ b/Inc/stm32f3xx_ll_cortex.h
@@ -25,8 +25,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -635,3 +635,4 @@
#endif
#endif /* __STM32F3xx_LL_CORTEX_H */
+
diff --git a/Inc/stm32f3xx_ll_crc.h b/Inc/stm32f3xx_ll_crc.h
index 4ac54c1..f7e195a 100644
--- a/Inc/stm32f3xx_ll_crc.h
+++ b/Inc/stm32f3xx_ll_crc.h
@@ -235,7 +235,7 @@
}
/**
- * @brief Configure the reversal of the bit order of the Output data
+ * @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
diff --git a/Inc/stm32f3xx_ll_dac.h b/Inc/stm32f3xx_ll_dac.h
index 94866a2..dae22fb 100644
--- a/Inc/stm32f3xx_ll_dac.h
+++ b/Inc/stm32f3xx_ll_dac.h
@@ -449,7 +449,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval 1...2 (value "2" depending on DAC channel 2 availability)
*/
@@ -469,7 +469,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
*/
#if defined(DAC_CHANNEL2_SUPPORT)
@@ -573,7 +573,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
@@ -616,7 +616,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
@@ -655,7 +655,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param WaveAutoGeneration This parameter can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
@@ -680,7 +680,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
@@ -709,7 +709,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param NoiseLFSRMask This parameter can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
@@ -743,7 +743,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
@@ -781,7 +781,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param TriangleAmplitude This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
@@ -815,7 +815,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
@@ -847,7 +847,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param OutputBuffer This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
@@ -878,7 +878,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
@@ -918,7 +918,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -939,7 +939,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -959,7 +959,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
@@ -996,7 +996,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Register This parameter can be one of the following values:
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
@@ -1030,7 +1030,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1049,7 +1049,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1069,7 +1069,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
@@ -1097,7 +1097,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1116,7 +1116,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1136,7 +1136,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
@@ -1165,7 +1165,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval None
*/
@@ -1186,7 +1186,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
@@ -1211,7 +1211,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
@@ -1236,7 +1236,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
@@ -1322,7 +1322,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
@@ -1505,3 +1505,4 @@
#endif
#endif /* __STM32F3xx_LL_DAC_H */
+
diff --git a/Inc/stm32f3xx_ll_dma.h b/Inc/stm32f3xx_ll_dma.h
index 785c553..b770c2b 100644
--- a/Inc/stm32f3xx_ll_dma.h
+++ b/Inc/stm32f3xx_ll_dma.h
@@ -9,8 +9,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -943,7 +943,7 @@
/**
* @brief Configure the Source and Destination addresses.
* @note This API must not be called when the DMA channel is enabled.
- * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
+ * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
* CMAR MA LL_DMA_ConfigAddresses
* @param DMAx DMAx Instance
@@ -1991,3 +1991,4 @@
#endif
#endif /* __STM32F3xx_LL_DMA_H */
+
diff --git a/Inc/stm32f3xx_ll_exti.h b/Inc/stm32f3xx_ll_exti.h
index f4cbd4c..59ed70f 100644
--- a/Inc/stm32f3xx_ll_exti.h
+++ b/Inc/stm32f3xx_ll_exti.h
@@ -1378,3 +1378,4 @@
#endif
#endif /* __STM32F3xx_LL_EXTI_H */
+
diff --git a/Inc/stm32f3xx_ll_fmc.h b/Inc/stm32f3xx_ll_fmc.h
index f2f0e4f..6b1328d 100644
--- a/Inc/stm32f3xx_ll_fmc.h
+++ b/Inc/stm32f3xx_ll_fmc.h
@@ -87,7 +87,7 @@
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
#endif /* FMC_BANK1 */
-#if defined(FMC_BANK3)
+#if defined(FMC_BANK3)
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
@@ -283,7 +283,7 @@
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
} FMC_NAND_InitTypeDef;
-#endif
+#endif /* FMC_BANK3 */
#if defined(FMC_BANK3) || defined(FMC_BANK4)
/**
@@ -335,7 +335,7 @@
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FMC_PCCARD_InitTypeDef;
-#endif
+#endif /* FMC_BANK4 */
/**
* @}
@@ -534,7 +534,7 @@
*/
#if defined(FMC_BANK4)
#define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
-#endif
+#endif /* FMC_BANK4 */
#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
@@ -574,7 +574,7 @@
/**
* @}
*/
-#endif /* FMC_BANK3 */
+#endif /* FMC_BANK3 || FMC_BANK4 */
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
@@ -584,7 +584,7 @@
#define FMC_IT_RISING_EDGE (0x00000008U)
#define FMC_IT_LEVEL (0x00000010U)
#define FMC_IT_FALLING_EDGE (0x00000020U)
-#endif /* FMC_BANK3 */
+#endif /* FMC_BANK3 || FMC_BANK4 */
/**
* @}
*/
@@ -597,7 +597,7 @@
#define FMC_FLAG_LEVEL (0x00000002U)
#define FMC_FLAG_FALLING_EDGE (0x00000004U)
#define FMC_FLAG_FEMPT (0x00000040U)
-#endif /* FMC_BANK3 */
+#endif /* FMC_BANK3 || FMC_BANK4 */
/**
* @}
*/
@@ -670,7 +670,7 @@
/**
* @}
*/
-#endif
+#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
diff --git a/Inc/stm32f3xx_ll_gpio.h b/Inc/stm32f3xx_ll_gpio.h
index 0e23e7e..3de5970 100644
--- a/Inc/stm32f3xx_ll_gpio.h
+++ b/Inc/stm32f3xx_ll_gpio.h
@@ -975,3 +975,4 @@
#endif
#endif /* __STM32F3xx_LL_GPIO_H */
+
diff --git a/Inc/stm32f3xx_ll_hrtim.h b/Inc/stm32f3xx_ll_hrtim.h
index cdc65a2..218f8e4 100644
--- a/Inc/stm32f3xx_ll_hrtim.h
+++ b/Inc/stm32f3xx_ll_hrtim.h
@@ -378,10 +378,10 @@
* @{
* @brief Constants defining the source and event to be sent on the synchronization output.
*/
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
/**
* @}
*/
@@ -10597,3 +10597,5 @@
#endif
#endif /* STM32F3xx_LL_HRTIM_H */
+
+
diff --git a/Inc/stm32f3xx_ll_i2c.h b/Inc/stm32f3xx_ll_i2c.h
index 26ba7ba..01dcc22 100644
--- a/Inc/stm32f3xx_ll_i2c.h
+++ b/Inc/stm32f3xx_ll_i2c.h
@@ -451,7 +451,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
}
@@ -500,7 +500,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
}
@@ -535,7 +535,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
}
@@ -568,7 +568,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
}
@@ -601,7 +601,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
}
@@ -616,7 +616,7 @@
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
{
uint32_t data_reg_addr;
@@ -664,7 +664,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
}
@@ -697,7 +697,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
}
@@ -737,7 +737,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
}
@@ -772,7 +772,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}
@@ -800,7 +800,7 @@
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
*/
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
}
@@ -849,7 +849,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
}
@@ -905,7 +905,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
}
@@ -930,7 +930,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
}
@@ -941,7 +941,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
}
@@ -952,7 +952,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
}
@@ -963,7 +963,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
}
@@ -974,7 +974,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
}
@@ -1011,7 +1011,7 @@
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
*/
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
}
@@ -1060,7 +1060,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
}
@@ -1099,7 +1099,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
}
@@ -1150,7 +1150,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
}
@@ -1182,7 +1182,7 @@
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
}
@@ -1210,7 +1210,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
}
@@ -1264,7 +1264,7 @@
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
(ClockTimeout)) ? 1UL : 0UL);
@@ -1306,7 +1306,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
}
@@ -1339,7 +1339,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
}
@@ -1372,7 +1372,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
}
@@ -1405,7 +1405,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
}
@@ -1438,7 +1438,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
}
@@ -1477,7 +1477,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
}
@@ -1528,7 +1528,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
}
@@ -1549,7 +1549,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
}
@@ -1562,7 +1562,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
}
@@ -1575,7 +1575,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
}
@@ -1588,7 +1588,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
}
@@ -1601,7 +1601,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
}
@@ -1614,7 +1614,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
}
@@ -1627,7 +1627,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
}
@@ -1640,7 +1640,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
}
@@ -1653,7 +1653,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
}
@@ -1666,7 +1666,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
}
@@ -1679,7 +1679,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
}
@@ -1694,7 +1694,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
}
@@ -1709,7 +1709,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
}
@@ -1725,7 +1725,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
}
@@ -1738,7 +1738,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
}
@@ -1899,7 +1899,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
}
@@ -1934,7 +1934,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
}
@@ -1958,7 +1958,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
}
@@ -2035,7 +2035,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
}
@@ -2063,7 +2063,7 @@
* @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
}
@@ -2087,7 +2087,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
}
@@ -2150,7 +2150,7 @@
* @arg @ref LL_I2C_DIRECTION_WRITE
* @arg @ref LL_I2C_DIRECTION_READ
*/
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
}
@@ -2161,7 +2161,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
}
@@ -2191,7 +2191,7 @@
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
}
@@ -2204,7 +2204,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
}
@@ -2215,7 +2215,7 @@
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
{
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
}
@@ -2241,8 +2241,8 @@
* @{
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
diff --git a/Inc/stm32f3xx_ll_opamp.h b/Inc/stm32f3xx_ll_opamp.h
index 89d8198..d82e5a3 100644
--- a/Inc/stm32f3xx_ll_opamp.h
+++ b/Inc/stm32f3xx_ll_opamp.h
@@ -172,7 +172,7 @@
*/
#define LL_OPAMP_INPUT_INVERT_IO0 (0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VMSEL_0) /*!< OPAMP inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering). Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
+#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering). Note: On this STM32 series, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
/**
* @}
*/
@@ -241,7 +241,7 @@
*/
/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
- * @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+ * @note Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
@@ -783,7 +783,7 @@
/**
* @brief Enable OPAMP instance.
* @note After enable from off state, OPAMP requires a delay
- * to fullfill wake up time specification.
+ * to fulfill wake up time specification.
* Refer to device datasheet, parameter "tWAKEUP".
* @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
* @param OPAMPx OPAMP instance
@@ -881,3 +881,4 @@
#endif
#endif /* STM32F3xx_LL_OPAMP_H */
+
diff --git a/Inc/stm32f3xx_ll_rcc.h b/Inc/stm32f3xx_ll_rcc.h
index 4ab76ae..4fbff15 100644
--- a/Inc/stm32f3xx_ll_rcc.h
+++ b/Inc/stm32f3xx_ll_rcc.h
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
@@ -2837,3 +2836,4 @@
#endif
#endif /* __STM32F3xx_LL_RCC_H */
+
diff --git a/Inc/stm32f3xx_ll_rtc.h b/Inc/stm32f3xx_ll_rtc.h
index fedac3b..6449bc8 100644
--- a/Inc/stm32f3xx_ll_rtc.h
+++ b/Inc/stm32f3xx_ll_rtc.h
@@ -17,8 +17,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F3xx_LL_RTC_H
-#define __STM32F3xx_LL_RTC_H
+#ifndef STM32F3xx_LL_RTC_H
+#define STM32F3xx_LL_RTC_H
#ifdef __cplusplus
extern "C" {
@@ -45,7 +45,7 @@
*/
/* Masks Definition */
#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
+#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
/* Write protection defines */
#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU)
@@ -167,7 +167,7 @@
This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
- or @ref LL_RTC_ALMB_SetMask() for ALARM B
+ or @ref LL_RTC_ALMB_SetMask() for ALARM B.
*/
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
@@ -204,8 +204,8 @@
/** @defgroup RTC_LL_EC_FORMAT FORMAT
* @{
*/
-#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */
+#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */
/**
* @}
*/
@@ -235,7 +235,9 @@
* @{
*/
#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
+#if defined(RTC_TAMPER3_SUPPORT)
#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
+#endif /* RTC_TAMPER3_SUPPORT */
#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
@@ -391,11 +393,11 @@
/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
* @{
*/
-#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B */
#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
-#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
+#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
/**
* @}
@@ -431,12 +433,8 @@
/** @defgroup RTC_LL_EC_TAMPER TAMPER
* @{
*/
-#if defined(RTC_TAMPER1_SUPPORT)
#define LL_RTC_TAMPER_1 RTC_TAFCR_TAMP1E /*!< RTC_TAMP1 input detection */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
#define LL_RTC_TAMPER_2 RTC_TAFCR_TAMP2E /*!< RTC_TAMP2 input detection */
-#endif /* RTC_TAMPER2_SUPPORT */
#if defined(RTC_TAMPER3_SUPPORT)
#define LL_RTC_TAMPER_3 RTC_TAFCR_TAMP3E /*!< RTC_TAMP3 input detection */
#endif /* RTC_TAMPER3_SUPPORT */
@@ -444,39 +442,6 @@
* @}
*/
-/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAFCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
- * @{
- */
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAFCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
-#endif /* RTC_TAMPER3_SUPPORT */
-/**
- * @}
- */
-
-#if defined(RTC_TAFCR_TAMPPRCH)
/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
* @{
*/
@@ -487,9 +452,7 @@
/**
* @}
*/
-#endif /* RTC_TAFCR_TAMPPRCH */
-#if defined(RTC_TAFCR_TAMPFLT)
/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
* @{
*/
@@ -500,9 +463,7 @@
/**
* @}
*/
-#endif /* RTC_TAFCR_TAMPFLT */
-#if defined(RTC_TAFCR_TAMPFREQ)
/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
* @{
*/
@@ -517,19 +478,14 @@
/**
* @}
*/
-#endif /* RTC_TAFCR_TAMPFREQ */
/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
* @{
*/
-#if defined(RTC_TAMPER1_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER1_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPER2_SUPPORT */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#if defined(RTC_TAMPER3_SUPPORT)
-#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAFCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
@@ -548,7 +504,6 @@
* @}
*/
-#if defined(RTC_BACKUP_SUPPORT)
/** @defgroup RTC_LL_EC_BKP BACKUP
* @{
*/
@@ -557,7 +512,7 @@
#define LL_RTC_BKP_DR2 0x00000002U
#define LL_RTC_BKP_DR3 0x00000003U
#define LL_RTC_BKP_DR4 0x00000004U
-#if RTC_BKP_NUMBER > 5
+#if RTC_BKP_NUMBER > 5U
#define LL_RTC_BKP_DR5 0x00000005U
#define LL_RTC_BKP_DR6 0x00000006U
#define LL_RTC_BKP_DR7 0x00000007U
@@ -569,16 +524,12 @@
#define LL_RTC_BKP_DR13 0x0000000DU
#define LL_RTC_BKP_DR14 0x0000000EU
#define LL_RTC_BKP_DR15 0x0000000FU
-#endif /* RTC_BKP_NUMBER > 5 */
-
-#if RTC_BKP_NUMBER > 16
+#if RTC_BKP_NUMBER > 16U
#define LL_RTC_BKP_DR16 0x00000010U
#define LL_RTC_BKP_DR17 0x00000011U
#define LL_RTC_BKP_DR18 0x00000012U
#define LL_RTC_BKP_DR19 0x00000013U
-#endif /* RTC_BKP_NUMBER > 16 */
-
-#if RTC_BKP_NUMBER > 20
+#if RTC_BKP_NUMBER > 20U
#define LL_RTC_BKP_DR20 0x00000014U
#define LL_RTC_BKP_DR21 0x00000015U
#define LL_RTC_BKP_DR22 0x00000016U
@@ -591,11 +542,12 @@
#define LL_RTC_BKP_DR29 0x0000001DU
#define LL_RTC_BKP_DR30 0x0000001EU
#define LL_RTC_BKP_DR31 0x0000001FU
-#endif /* RTC_BKP_NUMBER > 20 */
+#endif /* RTC_BKP_NUMBER > 20U */
+#endif /* RTC_BKP_NUMBER > 16U */
+#endif /* RTC_BKP_NUMBER > 5U */
/**
* @}
*/
-#endif /* RTC_BACKUP_SUPPORT */
/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
* @{
@@ -877,8 +829,8 @@
* @note PC13 forced to push-pull output if all RTC alternate functions are disabled
* @note PC14 and PC15 forced to push-pull output if LSE is disabled
* @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n
- * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
- * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode
+ * TAFCR PC14MODE LL_RTC_EnablePushPullMode\n
+ * TAFCR PC15MODE LL_RTC_EnablePushPullMode
* @param RTCx RTC Instance
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_PIN_PC13
@@ -1028,7 +980,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD));
+ return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);
}
/**
@@ -1295,12 +1247,12 @@
*/
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- uint32_t temp = 0U;
+ uint32_t temp;
- temp = Format12_24 | \
- (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
+ (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
}
@@ -1323,12 +1275,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
- uint32_t temp = 0U;
-
- temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
- return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
- (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
- ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
+ return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)));
}
/**
@@ -1363,7 +1310,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
+ return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);
}
/**
@@ -1391,17 +1338,18 @@
}
/**
- * @brief Get Sub second value in the synchronous prescaler counter.
+ * @brief Get subseconds value in the synchronous prescaler counter.
* @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
* LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
* SubSeconds value in second fraction ratio with time unit following
* generic formula:
- * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
+ * ==> Seconds fraction ratio * time_unit =
+ * [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
* This conversion can be performed only if no shift operation is pending
* (ie. SHFP=0) when PREDIV_S >= SS.
* @rmtoll SSR SS LL_RTC_TIME_GetSubSecond
* @param RTCx RTC Instance
- * @retval Sub second value (number between 0 and 65535)
+ * @retval Subseconds value (number between 0 and 65535)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
{
@@ -1625,12 +1573,12 @@
*/
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
{
- uint32_t temp = 0U;
+ uint32_t temp;
- temp = (WeekDay << RTC_DR_WDU_Pos) | \
- (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
+ temp = ( WeekDay << RTC_DR_WDU_Pos) | \
+ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
(((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
- (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
+ (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
}
@@ -1653,13 +1601,14 @@
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
- uint32_t temp = 0U;
+ uint32_t temp;
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
- return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
- (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
- (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
- ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
+
+ return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
+ (((temp & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos) << RTC_OFFSET_DAY) | \
+ (((temp & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos) << RTC_OFFSET_MONTH) | \
+ ((temp & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos));
}
/**
@@ -1953,11 +1902,12 @@
*/
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- uint32_t temp = 0U;
+ uint32_t temp;
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
+ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
}
@@ -1981,7 +1931,8 @@
}
/**
- * @brief Set Alarm A Mask the most-significant bits starting at this bit
+ * @brief Mask the most-significant bits of the subseconds field starting from
+ * the bit specified in parameter Mask
* @note This register can be written only when ALRAE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
@@ -1995,7 +1946,7 @@
}
/**
- * @brief Get Alarm A Mask the most-significant bits starting at this bit
+ * @brief Get Alarm A subseconds mask
* @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xF
@@ -2006,7 +1957,7 @@
}
/**
- * @brief Set Alarm A Sub seconds value
+ * @brief Set Alarm A subseconds value
* @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond
* @param RTCx RTC Instance
* @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
@@ -2018,7 +1969,7 @@
}
/**
- * @brief Get Alarm A Sub seconds value
+ * @brief Get Alarm A subseconds value
* @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
@@ -2319,11 +2270,12 @@
*/
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- uint32_t temp = 0U;
+ uint32_t temp;
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
- (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
+ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
}
@@ -2347,7 +2299,8 @@
}
/**
- * @brief Set Alarm B Mask the most-significant bits starting at this bit
+ * @brief Mask the most-significant bits of the subseconds field starting from
+ * the bit specified in parameter Mask
* @note This register can be written only when ALRBE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
@@ -2361,7 +2314,7 @@
}
/**
- * @brief Get Alarm B Mask the most-significant bits starting at this bit
+ * @brief Get Alarm B subseconds mask
* @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xF
@@ -2372,7 +2325,7 @@
}
/**
- * @brief Set Alarm B Sub seconds value
+ * @brief Set Alarm B subseconds value
* @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
* @param RTCx RTC Instance
* @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
@@ -2384,7 +2337,7 @@
}
/**
- * @brief Get Alarm B Sub seconds value
+ * @brief Get Alarm B subseconds value
* @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
@@ -2601,7 +2554,7 @@
}
/**
- * @brief Get time-stamp sub second value
+ * @brief Get time-stamp subseconds value
* @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
@@ -2654,7 +2607,7 @@
* @arg @ref LL_RTC_TAMPER_2
* @arg @ref LL_RTC_TAMPER_3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2673,7 +2626,7 @@
* @arg @ref LL_RTC_TAMPER_2
* @arg @ref LL_RTC_TAMPER_3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2681,7 +2634,6 @@
CLEAR_BIT(RTCx->TAFCR, Tamper);
}
-#if defined(RTC_TAFCR_TAMPPUDIS)
/**
* @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
* @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
@@ -2703,9 +2655,7 @@
{
CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS);
}
-#endif /* RTC_TAFCR_TAMPPUDIS */
-#if defined(RTC_TAFCR_TAMPPRCH)
/**
* @brief Set RTC_TAMPx precharge duration
* @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
@@ -2736,9 +2686,7 @@
{
return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH));
}
-#endif /* RTC_TAFCR_TAMPPRCH */
-#if defined(RTC_TAFCR_TAMPFLT)
/**
* @brief Set RTC_TAMPx filter count
* @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
@@ -2769,9 +2717,7 @@
{
return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT));
}
-#endif /* RTC_TAFCR_TAMPFLT */
-#if defined(RTC_TAFCR_TAMPFREQ)
/**
* @brief Set Tamper sampling frequency
* @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
@@ -2810,7 +2756,6 @@
{
return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ));
}
-#endif /* RTC_TAFCR_TAMPFREQ */
/**
* @brief Enable Active level for Tamper input
@@ -2823,7 +2768,7 @@
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2842,7 +2787,7 @@
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
@@ -2854,7 +2799,6 @@
* @}
*/
-#if defined(RTC_WAKEUP_SUPPORT)
/** @defgroup RTC_LL_EF_Wakeup Wakeup
* @{
*/
@@ -2891,13 +2835,13 @@
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);
}
/**
* @brief Select Wakeup clock
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
+ * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1
* @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock
* @param RTCx RTC Instance
* @param WakeupClock This parameter can be one of the following values:
@@ -2933,7 +2877,7 @@
/**
* @brief Set Wakeup auto-reload value
- * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
+ * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR
* @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload
* @param RTCx RTC Instance
* @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
@@ -2958,9 +2902,7 @@
/**
* @}
*/
-#endif /* RTC_WAKEUP_SUPPORT */
-#if defined(RTC_BACKUP_SUPPORT)
/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
* @{
*/
@@ -3003,19 +2945,19 @@
* @arg @ref LL_RTC_BKP_DR30 (*)
* @arg @ref LL_RTC_BKP_DR31 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
- uint32_t tmp = 0U;
+ uint32_t temp;
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
+ temp = (uint32_t)(&(RTCx->BKP0R));
+ temp += (BackupRegister * 4U);
/* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
+ *(__IO uint32_t *)temp = (uint32_t)Data;
}
/**
@@ -3056,24 +2998,23 @@
* @arg @ref LL_RTC_BKP_DR30 (*)
* @arg @ref LL_RTC_BKP_DR31 (*)
*
- * (*) value not defined in all devices.
+ * (*) value not applicable to all devices.
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
- uint32_t tmp = 0U;
+ uint32_t temp;
- tmp = (uint32_t)(&(RTCx->BKP0R));
- tmp += (BackupRegister * 4U);
+ temp = (uint32_t)(&(RTCx->BKP0R));
+ temp += (BackupRegister * 4U);
/* Read the specified register */
- return (*(__IO uint32_t *)tmp);
+ return (*(__IO uint32_t *)temp);
}
/**
* @}
*/
-#endif /* RTC_BACKUP_SUPPORT */
/** @defgroup RTC_LL_EF_Calibration Calibration
* @{
@@ -3089,6 +3030,7 @@
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ *
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
@@ -3105,6 +3047,7 @@
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
+ *
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
{
@@ -3114,7 +3057,7 @@
/**
* @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
+ * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
* @rmtoll CALR CALP LL_RTC_CAL_SetPulse
* @param RTCx RTC Instance
* @param Pulse This parameter can be one of the following values:
@@ -3135,11 +3078,11 @@
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP));
+ return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);
}
/**
- * @brief Set the calibration cycle period
+ * @brief Set smooth calibration cycle period
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
* @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n
@@ -3157,7 +3100,7 @@
}
/**
- * @brief Get the calibration cycle period
+ * @brief Get smooth calibration cycle period
* @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n
* CALR CALW16 LL_RTC_CAL_GetPeriod
* @param RTCx RTC Instance
@@ -3172,7 +3115,7 @@
}
/**
- * @brief Set Calibration minus
+ * @brief Set smooth Calibration minus
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ISR
* @rmtoll CALR CALM LL_RTC_CAL_SetMinus
@@ -3186,7 +3129,7 @@
}
/**
- * @brief Get Calibration minus
+ * @brief Get smooth Calibration minus
* @rmtoll CALR CALM LL_RTC_CAL_GetMinus
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
@@ -3212,7 +3155,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);
}
#if defined(RTC_TAMPER3_SUPPORT)
@@ -3224,11 +3167,10 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);
}
#endif /* RTC_TAMPER3_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
/**
* @brief Get RTC_TAMP2 detection flag
* @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2
@@ -3237,11 +3179,9 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);
}
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER1_SUPPORT)
/**
* @brief Get RTC_TAMP1 detection flag
* @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1
@@ -3250,9 +3190,8 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);
}
-#endif /* RTC_TAMPER1_SUPPORT */
/**
* @brief Get Time-stamp overflow flag
@@ -3262,7 +3201,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);
}
/**
@@ -3273,10 +3212,9 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);
}
-#if defined(RTC_WAKEUP_SUPPORT)
/**
* @brief Get Wakeup timer flag
* @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT
@@ -3285,9 +3223,8 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);
}
-#endif /* RTC_WAKEUP_SUPPORT */
/**
* @brief Get Alarm B flag
@@ -3297,7 +3234,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);
}
/**
@@ -3308,7 +3245,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);
}
#if defined(RTC_TAMPER3_SUPPORT)
@@ -3324,7 +3261,6 @@
}
#endif /* RTC_TAMPER3_SUPPORT */
-#if defined(RTC_TAMPER2_SUPPORT)
/**
* @brief Clear RTC_TAMP2 detection flag
* @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2
@@ -3335,9 +3271,7 @@
{
WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
}
-#endif /* RTC_TAMPER2_SUPPORT */
-#if defined(RTC_TAMPER1_SUPPORT)
/**
* @brief Clear RTC_TAMP1 detection flag
* @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1
@@ -3348,7 +3282,6 @@
{
WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
}
-#endif /* RTC_TAMPER1_SUPPORT */
/**
* @brief Clear Time-stamp overflow flag
@@ -3372,7 +3305,6 @@
WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
}
-#if defined(RTC_WAKEUP_SUPPORT)
/**
* @brief Clear Wakeup timer flag
* @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT
@@ -3383,7 +3315,6 @@
{
WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));
}
-#endif /* RTC_WAKEUP_SUPPORT */
/**
* @brief Clear Alarm B flag
@@ -3415,7 +3346,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);
}
/**
@@ -3426,7 +3357,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);
}
/**
@@ -3448,7 +3379,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);
}
/**
@@ -3459,10 +3390,9 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);
}
-#if defined(RTC_WAKEUP_SUPPORT)
/**
* @brief Get Wakeup timer write flag
* @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW
@@ -3471,9 +3401,8 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);
}
-#endif /* RTC_WAKEUP_SUPPORT */
/**
* @brief Get Alarm B write flag
@@ -3483,7 +3412,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);
}
/**
@@ -3494,7 +3423,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF));
+ return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
}
/**
@@ -3529,7 +3458,6 @@
CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
}
-#if defined(RTC_WAKEUP_SUPPORT)
/**
* @brief Enable Wakeup timer interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
@@ -3553,7 +3481,6 @@
{
CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
}
-#endif /* RTC_WAKEUP_SUPPORT */
/**
* @brief Enable Alarm B interrupt
@@ -3633,10 +3560,9 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);
}
-#if defined(RTC_WAKEUP_SUPPORT)
/**
* @brief Check if Wakeup timer interrupt is enabled or not
* @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT
@@ -3645,9 +3571,8 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);
}
-#endif /* RTC_WAKEUP_SUPPORT */
/**
* @brief Check if Alarm B interrupt is enabled or not
@@ -3657,7 +3582,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);
}
/**
@@ -3668,7 +3593,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE));
+ return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
}
/**
@@ -3679,8 +3604,8 @@
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
{
- return (READ_BIT(RTCx->TAFCR,
- RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE));
+ return ((READ_BIT(RTCx->TAFCR,
+ RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE)) ? 1UL : 0UL);
}
/**
@@ -3730,4 +3655,4 @@
}
#endif
-#endif /* __STM32F3xx_LL_RTC_H */
+#endif /* STM32F3xx_LL_RTC_H */
diff --git a/Inc/stm32f3xx_ll_spi.h b/Inc/stm32f3xx_ll_spi.h
index 4ce010c..f35fb1d 100644
--- a/Inc/stm32f3xx_ll_spi.h
+++ b/Inc/stm32f3xx_ll_spi.h
@@ -2249,3 +2249,4 @@
#endif
#endif /* STM32F3xx_LL_SPI_H */
+
diff --git a/Inc/stm32f3xx_ll_system.h b/Inc/stm32f3xx_ll_system.h
index 79721bb..52daf8c 100644
--- a/Inc/stm32f3xx_ll_system.h
+++ b/Inc/stm32f3xx_ll_system.h
@@ -3,6 +3,18 @@
* @file stm32f3xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,16 +28,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@@ -1103,7 +1105,7 @@
*/
__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
{
- MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
+ MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
}
/**
@@ -1203,7 +1205,7 @@
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
{
- return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
}
/**
@@ -1719,3 +1721,5 @@
#endif
#endif /* __STM32F3xx_LL_SYSTEM_H */
+
+
diff --git a/Inc/stm32f3xx_ll_tim.h b/Inc/stm32f3xx_ll_tim.h
index 7c9cffe..9ffea64 100644
--- a/Inc/stm32f3xx_ll_tim.h
+++ b/Inc/stm32f3xx_ll_tim.h
@@ -1255,6 +1255,7 @@
*/
#endif /* TIM_SMCR_OCCS*/
+
/**
* @}
*/
@@ -1287,10 +1288,6 @@
* @}
*/
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
- * @{
- */
-
/**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
@@ -1393,11 +1390,6 @@
* @}
*/
-
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
* @{
@@ -1999,7 +1991,7 @@
* @note CH5 and CH6 channels are not available for all F3 devices
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
{
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
@@ -2415,7 +2407,7 @@
* @note CH5 and CH6 channels are not available for all F3 devices
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2521,7 +2513,7 @@
* @note CH5 and CH6 channels are not available for all F3 devices
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2636,7 +2628,7 @@
* @note CH5 and CH6 channels are not available for all F3 devices
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -3234,7 +3226,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
@@ -5030,7 +5022,7 @@
* @{
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
diff --git a/Inc/stm32f3xx_ll_usart.h b/Inc/stm32f3xx_ll_usart.h
index 866be24..0e4725f 100644
--- a/Inc/stm32f3xx_ll_usart.h
+++ b/Inc/stm32f3xx_ll_usart.h
@@ -31,7 +31,7 @@
* @{
*/
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5)
/** @defgroup USART_LL USART
* @{
@@ -41,6 +41,12 @@
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
@@ -262,7 +268,7 @@
#else
#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-#endif/* USART_7BITS_SUPPORT */
+#endif /* USART_7BITS_SUPPORT */
/**
* @}
*/
@@ -1272,7 +1278,7 @@
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
*/
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
}
@@ -3641,3 +3647,4 @@
#endif
#endif /* STM32F3xx_LL_USART_H */
+
diff --git a/Inc/stm32f3xx_ll_usb.h b/Inc/stm32f3xx_ll_usb.h
index 6fc0ae7..cd73e72 100644
--- a/Inc/stm32f3xx_ll_usb.h
+++ b/Inc/stm32f3xx_ll_usb.h
@@ -22,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
@@ -42,15 +42,14 @@
* @brief USB Mode definition
*/
-
-
typedef enum
{
- USB_DEVICE_MODE = 0
+ USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
+
/**
- * @brief USB Initialization Structure definition
+ * @brief USB Instance Initialization Structure definition
*/
typedef struct
{
@@ -69,71 +68,63 @@
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
+ uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
-
- uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */
} USB_CfgTypeDef;
typedef struct
{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type */
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_LL_EP_Type */
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint16_t pmaadress; /*!< PMA Address
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t pmaaddr0; /*!< PMA Address0
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t pmaaddr1; /*!< PMA Address1
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint8_t doublebuffer; /*!< Double buffer enable
- This parameter can be 0 or 1 */
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral
- This parameter is added to ensure compatibility across USB peripherals */
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint32_t xfer_len; /*!< Current transfer length */
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+ uint32_t xfer_len; /*!< Current transfer length */
- uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
- uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
+ uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
+ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-
-
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
@@ -165,6 +156,7 @@
* @}
*/
+
#define BTABLE_ADDRESS 0x000U
#if defined(STM32F303xC) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F302xC)
#define PMA_ACCESS 2U
@@ -179,7 +171,17 @@
/* STM32F302xC || */
/* STM32F302x8 */
+#ifndef USB_EP_RX_STRX
+#define USB_EP_RX_STRX (0x3U << 12)
+#endif /* USB_EP_RX_STRX */
+
#define EP_ADDR_MSK 0x7U
+
+#ifndef USE_USB_DOUBLE_BUFFER
+#define USE_USB_DOUBLE_BUFFER 1U
+#endif /* USE_USB_DOUBLE_BUFFER */
+
+
/**
* @}
*/
@@ -243,7 +245,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32F3xx_LL_USB_H */
diff --git a/Inc/stm32f3xx_ll_utils.h b/Inc/stm32f3xx_ll_utils.h
index e6849ee..93613bb 100644
--- a/Inc/stm32f3xx_ll_utils.h
+++ b/Inc/stm32f3xx_ll_utils.h
@@ -3,6 +3,17 @@
* @file stm32f3xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,16 +27,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
diff --git a/README.md b/README.md
index 4616789..8890735 100644
--- a/README.md
+++ b/README.md
@@ -27,20 +27,12 @@
## Compatibility information
-In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
-
-It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table.
-
-HAL Driver F3 | CMSIS Device F3 | CMSIS Core | Was delivered in the full MCU package
-------------- | --------------- | ---------- | -------------------------------------
-Tag v1.5.2 | Tag v2.3.3 | Tag v4.5_cm4 | Tag v1.10.0 (and following, if any, till next HAL tag)
-Tag v1.5.3 | Tag v2.3.4 | Tag v5.4.0_cm4 | Tag v1.11.0 (and following, if any, till next HAL tag)
-Tag v1.5.4 | Tag v2.3.4 | Tag v5.4.0_cm4 | Tag v1.11.1 (and following, if any, till next HAL tag)
-Tag v1.5.5 | Tag v2.3.5 | Tag v5.4.0_cm4 | Tag v1.11.2 (and following, if any, till next HAL tag)
-Tag v1.5.6 | Tag v2.3.6 | Tag v5.4.0_cm4 | Tag v1.11.3 (and following, if any, till next HAL tag)
+It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeF3/blob/master/Release_Notes.html) release note.
The full **STM32CubeF3** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeF3).
## Troubleshooting
-Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide.
+If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32f3xx_hal_driver/issues/new/choose).
+
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index 08eee69..dc1e461 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -11,41 +11,172 @@
span.underline{text-decoration: underline;}
div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
- <link rel="stylesheet" href="_htmresc/mini-st.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
+ <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
</head>
<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
<center>
-<h1 id="release-notes-for-stm32f3xx-hal-drivers"><strong>Release Notes for STM32F3xx HAL Drivers</strong></h1>
-<p>Copyright © 2016 STMicroelectronics<br />
-</p>
-<a href="https://www.st.com" class="logo"><img src="../../_htmresc/st_logo.png" alt="ST logo" /></a>
+<h1 id="release-notes-forstm32f3xx-hal-drivers"><small>Release Notes for</small><mark>STM32F3xx HAL Drivers</mark></h1>
+<p>Copyright © 2016 STMicroelectronics</p>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
-</div>
-</div>
-<h1 id="license"><strong>License</strong></h1>
-This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
-<center>
-<a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
-</center>
+<h1 id="purpose">Purpose</h1>
+<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
+<p>The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code re-usability and guarantees an easy portability on other devices and STM32 families.</p>
+<p>The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provide basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not Fully Portable across the STM32 families; the availability of some functions depend on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:</p>
+<ul>
+<li>New set of inline function for direct and atomic register access</li>
+<li>One-shot operations that can be used by the HAL drivers or from application level.</li>
+<li>Fully Independent from HAL and can be used in standalone usage (without HAL drivers)</li>
+<li>Full features coverage of the all the supported peripherals.</li>
+</ul>
</div>
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section1_5_6" checked aria-hidden="true"> <label for="collapse-section1_5_6" aria-hidden="true"><strong>V1.5.6 / 23-July-2021</strong></label>
+<input type="checkbox" id="collapse-section1_5_7" checked aria-hidden="true"> <label for="collapse-section1_5_7" aria-hidden="true"><strong>V1.5.7 / 27-January-2023</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
-<li>General updates to fix known defects and enhancements implementation.</li>
+<li>General updates to fix known defects and implementation enhancements.</li>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</li>
</ul>
<h2 id="contents">Contents</h2>
<ul>
+<li><strong>HAL Generic</strong> update
+<ul>
+<li>Allow redefinition of macro UNUSED(x).</li>
+</ul></li>
+<li><strong>HAL RCC</strong> update
+<ul>
+<li>Add ‘static’ storage-class specifier to ‘const’ arrays.</li>
+</ul></li>
+<li><strong>HAL EXTI</strong> update
+<ul>
+<li>Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine()</li>
+</ul></li>
+<li><strong>HAL CRC</strong> update
+<ul>
+<li>Add filter in HAL_CRCEx_Polynomial_Set() to exclude even polynomials.</li>
+</ul></li>
+<li><strong>HAL ADC</strong> update
+<ul>
+<li>Remove multiple volatile reads or writes in interrupt handler for better performance.</li>
+</ul></li>
+<li><strong>HAL CEC</strong> update
+<ul>
+<li>Better performance by removing multiple volatile reads or writes in interrupt handler.</li>
+</ul></li>
+<li><strong>HAL SDADC</strong>
+<ul>
+<li>Better performance by removing multiple volatile reads or writes in interrupt handler.</li>
+</ul></li>
+<li><strong>LL/HAL TIM</strong> update
+<ul>
+<li>Fix HAL_TIMEx_RemapConfig() lock issue: __HAL_LOCK is called before calls to assert_param().</li>
+<li>__LL_TIM_CALC_PSC() macro update to round up the evaluate value when the fractional part of the division is greater than 0.5.</li>
+<li>Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() to fix Break Filter configuration problem with specific TIM instances</li>
+</ul></li>
+<li><strong>HAL CAN</strong> update
+<ul>
+<li>Removal of never reached code</li>
+<li>Improve protection against bad inputs</li>
+</ul></li>
+<li><strong>HAL RTC_BKP</strong> update
+<ul>
+<li>Use bits definitions from CMSIS Device header file instead of hard-coded values.</li>
+<li>Wrap comments to be 80-character long and correct typos.</li>
+<li>Move constants RTC_IT_TAMP. from hal_rtc.h to hal_rtc_ex.h.</li>
+<li>Gather all instructions related to exiting the init mode into new function RTC_ExitInitMode().</li>
+<li>Add new macro assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)) to check tamper filtering is disabled in case tamper events are triggered on signal edges.</li>
+<li>Rework functions HAL_RTCEx_SetTamper() and HAL_RTCEx_SetTamper_IT() to:
+<ul>
+<li>Write in TAFCR register in one single access instead of two.</li>
+<li>Avoid modifying user structure sTamper.</li>
+</ul></li>
+<li>Check if the RTC calendar has been previously initialized before entering initialization mode.</li>
+</ul></li>
+<li><strong>HAL NOR</strong> update
+<ul>
+<li>Align HAL_NOR_Init() API with core of the function when write operation is disabled to avoid HardFault.</li>
+<li>FMC_WRITE_OPERATION_DISABLE for NOR cause Hardfault for Read operations</li>
+</ul></li>
+<li><strong>HAL UART</strong> update
+<ul>
+<li>Improve header description of UART_WaitOnFlagUntilTimeout() function</li>
+<li>Add a check on the UART parity before enabling the parity error interruption.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig().</li>
+<li>Add a new API HAL_UARTEx_GetRxEventType() that could be used to retrieve the type of event that has led the RxEventCallback() execution</li>
+<li>Removal of HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs</li>
+<li>Disable the Receiver Timeout Interrupt when data reception is completed.</li>
+<li>Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong> update
+<ul>
+<li>Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().</li>
+</ul></li>
+<li><strong>HAL IRDA</strong> update
+<ul>
+<li>Improve header description of IRDA_WaitOnFlagUntilTimeout() function</li>
+<li>Add a check on the IRDA parity before enabling the parity error interrupt.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li>
+</ul></li>
+<li><strong>LL/HAL USART</strong> update
+<ul>
+<li>Improve header description of USART_WaitOnFlagUntilTimeout() function</li>
+<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
+<li>Add const qualifier for read only pointers.</li>
+<li>Fix compilation warnings generated with ARMV6 compiler.</li>
+</ul></li>
+<li><strong>HAL SPI</strong> update
+<ul>
+<li>Fix driver to don’t update state in case of error. (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT).</li>
+</ul></li>
+<li><strong>HAL I2C</strong> update
+<ul>
+<li>Improve header description of I2C_WaitOnFlagUntilTimeout() function</li>
+<li>Update I2C_TransferConfig() API to Fix written reserved bit 28 in I2C_CR2 register.</li>
+<li>Update to handle errors in polling mode.
+<ul>
+<li>Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs.</li>
+</ul></li>
+<li>Update to fix issue detected due to low system frequency execution (HSI).</li>
+<li>Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA</li>
+<li>Timeout issue using HAL MEM interface through FreeRTOS</li>
+<li>I2C_IsErrorOccurred does not return error if timeout is detected.</li>
+<li>Clear the ADDRF flag only when direction is confirmed as changed, to prevent that the ADDRF flag is cleared too early when the restart is received</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> update
+<ul>
+<li>Add flushing of TX register to fix issue of mismatching data received by master in case data size to be transmitted by the slave is greater than the data size to be received by the master.</li>
+</ul></li>
+<li><strong>HAL USB_FS</strong> update
+<ul>
+<li>PCD: add supporting multi packets transfer on Interrupt endpoint</li>
+<li>HAL: PCD: software correction added to avoid unexpected STALL condition during EP0 multi packet OUT transfer.</li>
+<li>hal_pcd.h: add a mask for USB RX bytes count</li>
+</ul></li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1_5_6" aria-hidden="true"> <label for="collapse-section1_5_6" aria-hidden="true"><strong>V1.5.6 / 23-July-2021</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>General updates to fix known defects and enhancements implementation.</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<ul>
<li><strong>HAL GPIO</strong> driver
<ul>
<li>Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.</li>
@@ -137,11 +268,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_5" aria-hidden="true"> <label for="collapse-section1_5_5" aria-hidden="true"><strong>V1.5.5 / 10-November-2020</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation.</li>
</ul>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<ul>
<li><strong>HAL</strong> driver update
<ul>
@@ -365,11 +496,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_4" aria-hidden="true"> <label for="collapse-section1_5_4" aria-hidden="true"><strong>V1.5.4 / 23-July-2020</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
</ul>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<ul>
<li><strong>HAL/LL GPIO</strong> update
<ul>
@@ -407,7 +538,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_3" aria-hidden="true"> <label for="collapse-section1_5_3" aria-hidden="true"><strong>V1.5.3 / 12-September-2019</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li>Add support of HAL callback registration feature</li>
@@ -437,7 +568,7 @@
</ul></li>
<li><strong>HAL CRC</strong> update
<ul>
-<li>Remove extra call to HAL_LOCK/HAL_UNLOCK from the followings API’s:
+<li>Remove extra call to HAL_LOCK/HAL_UNLOCK from the following API’s:
<ul>
<li>HAL_CRC_Accumulate()</li>
<li>HAL_CRC_Calculate()</li>
@@ -673,7 +804,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_2" aria-hidden="true"> <label for="collapse-section1_5_2" aria-hidden="true"><strong>V1.5.2 / 12-June-2018</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>Generic drivers changes</strong></li>
@@ -769,7 +900,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_1" aria-hidden="true"> <label for="collapse-section1_5_1" aria-hidden="true"><strong>V1.5.1 / 11-May-2018</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL Drivers changes</strong></li>
@@ -870,7 +1001,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_5_0" aria-hidden="true"> <label for="collapse-section1_5_0" aria-hidden="true"><strong>V1.5.0 / 23-June-2017</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>Generic drivers changes</strong></li>
@@ -1009,7 +1140,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_4_0" aria-hidden="true"> <label for="collapse-section1_4_0" aria-hidden="true"><strong>V1.4.0 / 16-December-2016</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation</strong></li>
<li><strong>HAL Drivers changes</strong></li>
@@ -1221,7 +1352,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_3_0" aria-hidden="true"> <label for="collapse-section1_3_0" aria-hidden="true"><strong>V1.3.0 / 01-July-2016</strong></label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li><strong>First official release supporting the Low Level drivers for the STM32F3xx series:</strong>
<ul>
@@ -1307,7 +1438,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_1" aria-hidden="true"> <label for="collapse-section1_2_1" aria-hidden="true"><strong>V1.2.1 / 29-April-2016</strong></label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li><strong>Maintenance release to fix known defects and enhancements implementation.</strong></li>
<li><strong>HAL generic</strong>
@@ -1393,7 +1524,7 @@
<li>Modified reset of Backup domain only if the RTC Clock source selection is modified from reset value.</li>
<li>Updated HAL_RCC_OscConfig() function (Reset HSEON/LSEON and HSEBYP/LSEBYP bits before configuring the HSE/LSE).</li>
<li>Corrected updates of SystemCoreClock variable within the HAL drivers.</li>
-<li>Corrected invertion in LSE drive capability Bit definition.</li>
+<li>Corrected inversion in LSE drive capability Bit definition.</li>
<li>Modified AHBPrescTable and APBPrescTable in HAL.</li>
<li>Removed RCC_CFGR_PLLNODIV bit definition from STM32F358xx, STM32F303xC and STM32F302xC devices.</li>
<li>Removed RCC_CSR_VREGRSTF bit definition in RCC_CSR register for STM32F303xC and STM32F303xE devices.</li>
@@ -1454,7 +1585,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_0" aria-hidden="true"> <label for="collapse-section1_2_0" aria-hidden="true"><strong>V1.2.0 / 13-November-2015</strong></label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li><strong>Performed HAL API alignment (macros/functions/constants renaming).</strong></li>
<li><strong>HAL generic</strong>
@@ -1636,7 +1767,7 @@
</ul></li>
<li><strong>HAL SDADC</strong>
<ul>
-<li>Applied ReferenceVoltage parameter in HAL_SDADC_Init() wathever instance.</li>
+<li>Applied ReferenceVoltage parameter in HAL_SDADC_Init() whatever instance.</li>
<li>Added new macros __HAL_SDADC_ENABLE_IT(), __HAL_SDADC_GET_IT_SOURCE(), __HAL_SDADC_GET_FLAG().</li>
</ul></li>
<li><strong>HAL SMARTCARD</strong>
@@ -1717,7 +1848,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_1" aria-hidden="true"> <label for="collapse-section1_1_1" aria-hidden="true"><strong>V1.1.1 / 19-June-2015</strong></label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>Fixed compilation warnings reported by TrueSTUDIO and SW4STM32 toolchains.</li>
</ul>
@@ -1726,7 +1857,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_0" aria-hidden="true"> <label for="collapse-section1_1_0" aria-hidden="true"><strong>V1.1.0 / 12-September-2014</strong></label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li><strong>First official release of STM32F3xx HAL drivers for STM32F303xE, STM32F302xE and STM32F398xx devices.</strong></li>
<li><strong>HAL generic</strong> update
@@ -1779,7 +1910,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_1_0_rc2" aria-hidden="true"> <label for="collapse-section1_1_0_rc2" aria-hidden="true"><strong>V1.5.2RC2 / 25-August-2014</strong></label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong> update
<ul>
@@ -1918,7 +2049,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_0_1" aria-hidden="true"> <label for="collapse-section1_0_1" aria-hidden="true"><strong>V1.0.1 / 18-June-2014</strong></label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li><strong>HAL generic</strong> update
<ul>
@@ -2032,7 +2163,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1_0_0" aria-hidden="true"> <label for="collapse-section1_0_0" aria-hidden="true"><strong>V1.0.0 / 06-May-2014</strong></label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<ul>
<li>First official release of STM32F3xx HAL drivers for <strong>STM32F301x6/x8, STM32F302x6/x8, STM32F302xB/xC, STM32F303x6/x8, STM32F373xB/xC, STM32F334x4/x6/x8, STM32F318xx, STM32F328xx, STM32F358xx and STM32F378xx devices.</strong></li>
</ul>
diff --git a/Src/Legacy/stm32f3xx_hal_can.c b/Src/Legacy/stm32f3xx_hal_can.c
index df78a16..e66d0a4 100644
--- a/Src/Legacy/stm32f3xx_hal_can.c
+++ b/Src/Legacy/stm32f3xx_hal_can.c
@@ -86,6 +86,7 @@
(@) You can refer to the CAN Legacy HAL driver header file for more useful macros
@endverbatim
+
******************************************************************************
*/
diff --git a/Src/stm32f3xx_hal.c b/Src/stm32f3xx_hal.c
index 6f3ba97..68d8338 100644
--- a/Src/stm32f3xx_hal.c
+++ b/Src/stm32f3xx_hal.c
@@ -52,11 +52,11 @@
* @{
*/
/**
- * @brief STM32F3xx HAL Driver version number V1.5.6
+ * @brief STM32F3xx HAL Driver version number V1.5.7
*/
#define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */
-#define __STM32F3xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */
+#define __STM32F3xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\
@@ -129,7 +129,7 @@
* @note The Systick configuration is based on HSI clock, as HSI is the clock
* used after a system Reset and the NVIC configuration is set to Priority group 4
*
- * @note The time base configuration is based on MSI clock when exting from Reset.
+ * @note The time base configuration is based on MSI clock when exiting from Reset.
* Once done, time base tick start incrementing.
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
@@ -334,7 +334,8 @@
/**
* @brief Return tick frequency.
- * @retval tick period in Hz
+ * @retval Tick frequency.
+ * Value of @ref HAL_TickFreqTypeDef.
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
@@ -342,7 +343,7 @@
}
/**
- * @brief This function provides accurate delay (in milliseconds) based
+ * @brief This function provides accurate delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
@@ -527,3 +528,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f3xx_hal_adc.c b/Src/stm32f3xx_hal_adc.c
index 80e1492..7f322d6 100644
--- a/Src/stm32f3xx_hal_adc.c
+++ b/Src/stm32f3xx_hal_adc.c
@@ -6,17 +6,8 @@
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
* + Initialization and de-initialization functions
- * ++ Initialization and Configuration of ADC
- * + Operation functions
- * ++ Start, stop, get result of conversions of regular
- * group, using 3 possible modes: polling, interruption or DMA.
- * + Control functions
- * ++ Channels configuration on regular group
- * ++ Channels configuration on injected group
- * ++ Analog Watchdog configuration
- * + State functions
- * ++ ADC state machine management
- * ++ Interrupts and flags management
+ * + Peripheral Control functions
+ * + Peripheral State functions
* Other functions (extended functions) are available in file
* "stm32f3xx_hal_adc_ex.c".
*
@@ -392,8 +383,7 @@
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
- @endverbatim
- ******************************************************************************
+ @endverbatim
*/
/* Includes ------------------------------------------------------------------*/
@@ -796,7 +786,7 @@
* should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
* @note: Case of multimode enabled (for devices with several ADCs): This
* function must be called for ADC master first, then ADC slave.
- * For ADC master, converson is stopped and ADC is disabled.
+ * For ADC master, conversion is stopped and ADC is disabled.
* For ADC slave, ADC is disabled only (conversion stop of ADC master
* has already stopped conversion of ADC slave).
* @param hadc ADC handle
@@ -1095,7 +1085,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes channel into regular group, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -1122,7 +1112,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes the selected analog watchdog, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -1210,3 +1200,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_adc_ex.c b/Src/stm32f3xx_hal_adc_ex.c
index c3981cb..ff1f54e 100644
--- a/Src/stm32f3xx_hal_adc_ex.c
+++ b/Src/stm32f3xx_hal_adc_ex.c
@@ -5,16 +5,10 @@
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
- * + Operation functions
- * ++ Start, stop, get result of conversions of injected
- * group, using 2 possible modes: polling, interruption.
- * ++ Multimode feature (available on devices with 2 ADCs or more)
- * ++ Calibration (ADC automatic self-calibration)
- * + Control functions
- * ++ Channels configuration on injected group
+ * + Peripheral Control functions
* Other functions (generic functions) are available in file
* "stm32f3xx_hal_adc.c".
- *
+ *
******************************************************************************
* @attention
*
@@ -32,7 +26,6 @@
available in file of generic functions "stm32f3xx_hal_adc.c".
[..]
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -5543,7 +5536,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes channel into regular group, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -5877,7 +5870,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes channel into regular group, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
+ * of structure "ADC_ChannelConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -5983,7 +5976,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes injected group, following calls to this
* function can be used to reconfigure some parameters of structure
- * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
+ * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_InjectionConfTypeDef".
@@ -6508,7 +6501,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes injected group, following calls to this
* function can be used to reconfigure some parameters of structure
- * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
+ * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
* The setting of these parameters is conditioned to ADC state:
* this function must be called when ADC is not under conversion.
* @note In case of usage of internal measurement channels:
@@ -6761,7 +6754,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes the selected analog watchdog, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
+ * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -6896,7 +6889,7 @@
{
/* Set the Analog watchdog channel or group of channels. This also */
/* enables the watchdog. */
- /* Note: Conditionnal register reset, because several channels can be */
+ /* Note: Conditional register reset, because several channels can be */
/* set by successive calls of this function. */
if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
{
@@ -7044,7 +7037,7 @@
* @note Possibility to update parameters on the fly:
* This function initializes multimode parameters, following
* calls to this function can be used to reconfigure some parameters
- * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
+ * of structure "ADC_MultiModeTypeDef" on the fly, without resetting
* the ADCs (both ADCs of the common group).
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
@@ -7094,7 +7087,7 @@
/* control registers) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
- /* If multimode is selected, configure all multimode paramaters. */
+ /* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if(multimode->Mode != ADC_MODE_INDEPENDENT)
@@ -7631,3 +7624,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_can.c b/Src/stm32f3xx_hal_can.c
index cecb73c..1d572f3 100644
--- a/Src/stm32f3xx_hal_can.c
+++ b/Src/stm32f3xx_hal_can.c
@@ -676,7 +676,7 @@
/**
* @brief Unregister a CAN CallBack.
- * CAN callabck is redirected to the weak predefined callback
+ * CAN callback is redirected to the weak predefined callback
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for CAN module
* @param CallbackID ID of the callback to be unregistered
@@ -1236,15 +1236,6 @@
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
- /* Check transmit mailbox value */
- if (transmitmailbox > 2U)
- {
- /* Update error code */
- hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
-
- return HAL_ERROR;
- }
-
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
@@ -1517,7 +1508,15 @@
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
- pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
+ {
+ /* Truncate DLC to 8 if received field is over range */
+ pHeader->DLC = 8U;
+ }
+ else
+ {
+ pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ }
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
diff --git a/Src/stm32f3xx_hal_cec.c b/Src/stm32f3xx_hal_cec.c
index 3145951..7838bf6 100644
--- a/Src/stm32f3xx_hal_cec.c
+++ b/Src/stm32f3xx_hal_cec.c
@@ -10,6 +10,7 @@
* + IO operation function
* + Peripheral Control function
*
+ *
******************************************************************************
* @attention
*
@@ -104,7 +105,6 @@
When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
-
@endverbatim
******************************************************************************
*/
@@ -233,7 +233,8 @@
/* Write to CEC Control Register */
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
- hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
+ hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
+ hcec->Init.BroadcastMsgNoErrorBitGen | \
hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
hcec->Init.ListenMode;
@@ -412,10 +413,10 @@
* @param hcec CEC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
- * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
- * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
- * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -497,14 +498,14 @@
/**
* @brief Unregister an CEC Callback
- * CEC callabck is redirected to the weak predefined callback
+ * CEC callback is redirected to the weak predefined callback
* @param hcec uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
- * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
- * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
- * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+ * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+ * @arg HAL_CEC_ERROR_CB_ID Error callback ID
+ * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+ * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval status
*/
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
@@ -829,7 +830,7 @@
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* In all cases transmit the byte */
- hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr;
+ hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
hcec->pTxBuffPtr++;
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
@@ -855,7 +856,7 @@
/* ----------------------------Rx/Tx Error Management----------------------------------*/
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
- CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
+ CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
{
hcec->ErrorCode = itflag;
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
@@ -959,7 +960,8 @@
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
{
- uint32_t temp1, temp2;
+ uint32_t temp1;
+ uint32_t temp2;
temp1 = hcec->gState;
temp2 = hcec->RxState;
diff --git a/Src/stm32f3xx_hal_comp.c b/Src/stm32f3xx_hal_comp.c
index 8f97b63..0300186 100644
--- a/Src/stm32f3xx_hal_comp.c
+++ b/Src/stm32f3xx_hal_comp.c
@@ -6,8 +6,6 @@
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
* + Initialization and de-initialization functions
- * + Start/Stop operation functions in polling mode.
- * + Start/Stop operation functions in interrupt mode.
* + Peripheral Control functions
* + Peripheral State functions
*
@@ -162,7 +160,6 @@
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
- @endverbatim
******************************************************************************
*/
@@ -1073,3 +1070,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_cortex.c b/Src/stm32f3xx_hal_cortex.c
index a7ead32..0998036 100644
--- a/Src/stm32f3xx_hal_cortex.c
+++ b/Src/stm32f3xx_hal_cortex.c
@@ -8,18 +8,7 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
- @verbatim
+ * @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
@@ -78,6 +67,16 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
*/
/*
@@ -509,3 +508,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_crc.c b/Src/stm32f3xx_hal_crc.c
index 123bfae..b41de22 100644
--- a/Src/stm32f3xx_hal_crc.c
+++ b/Src/stm32f3xx_hal_crc.c
@@ -200,7 +200,7 @@
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+ __HAL_CRC_SET_IDR(hcrc, 0);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
diff --git a/Src/stm32f3xx_hal_crc_ex.c b/Src/stm32f3xx_hal_crc_ex.c
index 88e5086..0a82d93 100644
--- a/Src/stm32f3xx_hal_crc_ex.c
+++ b/Src/stm32f3xx_hal_crc_ex.c
@@ -94,44 +94,53 @@
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
- /* check polynomial definition vs polynomial size:
- * polynomial length must be aligned with polynomial
- * definition. HAL_ERROR is reported if Pol degree is
- * larger than that indicated by PolyLength.
- * Look for MSB position: msb will contain the degree of
- * the second to the largest polynomial member. E.g., for
- * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ /* Ensure that the generating polynomial is odd */
+ if ((Pol & (uint32_t)(0x1U)) == 0U)
{
+ status = HAL_ERROR;
}
-
- switch (PolyLength)
+ else
{
- case CRC_POLYLENGTH_7B:
- if (msb >= HAL_CRC_LENGTH_7B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_8B:
- if (msb >= HAL_CRC_LENGTH_8B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_16B:
- if (msb >= HAL_CRC_LENGTH_16B)
- {
- status = HAL_ERROR;
- }
- break;
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ {
+ }
- case CRC_POLYLENGTH_32B:
- /* no polynomial definition vs. polynomial length issue possible */
- break;
- default:
- status = HAL_ERROR;
- break;
+ switch (PolyLength)
+ {
+
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
}
if (status == HAL_OK)
{
diff --git a/Src/stm32f3xx_hal_dac.c b/Src/stm32f3xx_hal_dac.c
index acb5963..ebcfa89 100644
--- a/Src/stm32f3xx_hal_dac.c
+++ b/Src/stm32f3xx_hal_dac.c
@@ -3,12 +3,12 @@
* @file stm32f3xx_hal_dac.c
* @author MCD Application Team
* @brief DAC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
* + Initialization and de-initialization functions
- * + IO operation functions
* + Peripheral Control functions
- * + Peripheral State and Errors functions
+ * + Peripheral State and Errors functions
+ *
*
******************************************************************************
* @attention
@@ -21,132 +21,132 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- @verbatim
+ @verbatim
==============================================================================
##### DAC Peripheral features #####
==============================================================================
- [..]
+ [..]
*** DAC Channels ***
- ====================
- [..]
- The device integrates up to 3 12-bit Digital Analog Converters that can
+ ====================
+ [..]
+ The device integrates up to 3 12-bit Digital Analog Converters that can
be used independently or simultaneously (dual mode):
(#) DAC1 channel1 with DAC1_OUT1 (PA4) as output
- (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
+ (#) DAC1 channel2 with DAC1_OUT2 (PA5) as output
(for STM32F3 devices having 2 channels on DAC1)
- (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
+ (#) DAC2 channel1 with DAC2_OUT1 (PA6) as output
(for STM32F3 devices having 2 DAC)
*** DAC Triggers ***
====================
[..]
Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
- and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
- [..]
+ and DAC1_OUT1/DAC1_OUT2/DAC2_OUT1 is available once writing to DHRx register.
+ [..]
Digital to Analog conversion can be triggered by:
(#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
The used pin (GPIOx_PIN_9) must be configured in input mode.
-
- (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
+
+ (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
(DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
-
+
(#) Software using DAC_TRIGGER_SOFTWARE
-
+
*** DAC Buffer mode feature ***
- ===============================
- [..]
- Each DAC channel integrates an output buffer that can be used to
+ ===============================
+ [..]
+ Each DAC channel integrates an output buffer that can be used to
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
- To enable, the output buffer use
+ To enable, the output buffer use
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
Or
- An output switch
+ An output switch
(in STM32F303x4, STM32F303x6, STM32F303x8
c, STM32F334x6, STM32F334x8
& STM32F334xx).
To enable, the output switch
sConfig.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE;
- [..]
- (@) Refer to the device datasheet for more details about output
+ [..]
+ (@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
*** GPIO configurations guidelines ***
=====================
- [..]
- When a DAC channel is used (ex channel1 on PA4) and the other is not
+ [..]
+ When a DAC channel is used (ex channel1 on PA4) and the other is not
(ex channel2 on PA5 is configured in Analog and disabled).
Channel1 may disturb channel2 as coupling effect.
Note that there is no coupling on channel2 as soon as channel2 is turned on.
Coupling on adjacent channel could be avoided as follows:
- when unused PA5 is configured as INPUT PULL-UP or DOWN.
- PA5 is configured in ANALOG just before it is turned on.
+ when unused PA5 is configured as INPUT PULL-UP or DOWN.
+ PA5 is configured in ANALOG just before it is turned on.
-
+
*** DAC wave generation feature ***
- ===================================
- [..]
+ ===================================
+ [..]
Both DAC channels of DAC1 can be used to generate
note that wave generation is not available in DAC2.
(#) Noise wave
(#) Triangle wave
-
+
Wave generation is NOT available in DAC2.
*** DAC data format ***
=======================
- [..]
+ [..]
The DAC data format can be:
(#) 8-bit right alignment using DAC_ALIGN_8B_R
(#) 12-bit left alignment using DAC_ALIGN_12B_L
(#) 12-bit right alignment using DAC_ALIGN_12B_R
-
- *** DAC data value to voltage correspondance ***
- ================================================
- [..]
+
+ *** DAC data value to voltage correspondence ***
+ ================================================
+ [..]
The analog output voltage on each DAC channel pin is determined
- by the following equation:
- [..]
- DAC_OUTx = VREF+ * DOR / 4095
+ by the following equation:
+ [..]
+ DAC_OUTx = VREF+ * DOR / 4095
(+) with DOR is the Data Output Register
- [..]
+ [..]
VEF+ is the input voltage reference (refer to the device datasheet)
- [..]
+ [..]
e.g. To set DAC_OUT1 to 0.7V, use
(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3U * 868U) / 4095U = 0.7V
-
+
*** DMA requests ***
=====================
- [..]
- A DMA1 or DMA2 request can be generated when an external trigger
- (but not a software trigger) occurs if DMA1 or DMA2 requests are
+ [..]
+ A DMA1 or DMA2 request can be generated when an external trigger
+ (but not a software trigger) occurs if DMA1 or DMA2 requests are
enabled using HAL_DAC_Start_DMA().
[..]
DMA1 requests are mapped as following:
(#) DAC1 channel1: mapped either on
- (++) DMA1 channel3
+ (++) DMA1 channel3
(++) or DMA2 channel3 (for STM32F3 devices having 2 DMA)
which must be already configured
- (#) DAC1 channel2:
+ (#) DAC1 channel2:
(for STM32F3 devices having 2 channels on DAC1)
mapped either on
- (++) DMA1 channel4
+ (++) DMA1 channel4
(++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
which must be already configured
-
- (#) DAC2 channel1: mapped either on
- (for STM32F3 devices having 2 DAC)
- (++) DMA1 channel4
- (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
- which must be already configured
-
- (@) For Dual mode and specific signal (Triangle and noise) generation please
- refer to Extended Features Driver description
+ (#) DAC2 channel1: mapped either on
+ (for STM32F3 devices having 2 DAC)
+ (++) DMA1 channel4
+ (++) or DMA2 channel4 (for STM32F3 devices having 2 DMA)
+ which must be already configured
+
+
+ (@) For Dual mode and specific signal (Triangle and noise) generation please
+ refer to Extended Features Driver description
##### How to use this driver #####
==============================================================================
- [..]
+ [..]
(+) DAC APB clock must be enabled to get write access to DAC
registers using HAL_DAC_Init()
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
@@ -155,27 +155,27 @@
*** Polling mode IO operation ***
=================================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start()
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start()
(+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
-
- *** DMA mode IO operation ***
+
+ *** DMA mode IO operation ***
==============================
- [..]
- (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+ [..]
+ (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
- (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
+ (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
+ (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
- (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
+ (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
(+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
- HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
- function is executed and user can add his own code by customization of function pointer
+ HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+ function is executed and user can add his own code by customization of function pointer
HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
@@ -188,38 +188,38 @@
Use Functions HAL_DAC_RegisterCallback() to register a user callback,
it allows to register following callbacks:
- (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
- (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
- (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
- (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
- (+) MspInitCallback : DAC MspInit.
+ (+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
- (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
+ weak (overridden) function. It allows to reset following callbacks:
+ (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
(+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
- (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
- (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
- (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
+ (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
+ (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+ (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
(+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
- (+) MspInitCallback : DAC MspInit.
+ (+) MspInitCallback : DAC MspInit.
(+) MspDeInitCallback : DAC MspdeInit.
(+) All Callbacks
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
+ reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -229,28 +229,28 @@
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
+ using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
or HAL_DAC_Init function.
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ not defined, the callback registering feature is not available
+ and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in DAC HAL driver.
-
+
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
- (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-
+ (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
[..]
- (@) You can refer to the DAC HAL driver header file for more useful macros
-
- @endverbatim
+ (@) You can refer to the DAC HAL driver header file for more useful macros
+
+ @endverbatim
******************************************************************************
*/
@@ -265,8 +265,8 @@
/** @defgroup DAC DAC
* @brief DAC HAL module driver
* @{
- */
-
+ */
+
#ifdef HAL_DAC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
@@ -289,22 +289,22 @@
*/
/* Exported functions -------------------------------------------------------*/
-
+
/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
*/
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Initialize and configure the DAC.
- (+) De-initialize the DAC.
-
+ (+) Initialize and configure the DAC.
+ (+) De-initialize the DAC.
+
@endverbatim
* @{
*/
@@ -317,7 +317,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{
+{
/* Check DAC handle */
if(hdac == NULL)
{
@@ -325,20 +325,20 @@
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
+
if(hdac->State == HAL_DAC_STATE_RESET)
- {
+ {
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the DAC Callback settings */
- hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
#if defined(DAC_CHANNEL2_SUPPORT)
- hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+ hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
- hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
- hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+ hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+ hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
#endif /* DAC_CHANNEL2_SUPPORT */
if(hdac->MspInitCallback == NULL)
{
@@ -349,7 +349,7 @@
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
+
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
@@ -361,16 +361,16 @@
HAL_DAC_MspInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
-
+
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
-
+
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
+
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -394,7 +394,7 @@
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
-
+
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
if(hdac->MspDeInitCallback == NULL)
{
@@ -402,15 +402,15 @@
}
/* DeInit the low level hardware */
hdac->MspDeInitCallback(hdac);
-
-#else
+
+#else
/* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
+
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_RESET;
@@ -434,13 +434,13 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
- */
+ */
}
/**
* @brief DeInitialize the DAC MSP.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
- * the configuration information for the specified DAC.
+ * the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
@@ -450,7 +450,7 @@
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
- */
+ */
}
/**
@@ -458,12 +458,12 @@
*/
/** @defgroup DAC_Exported_Functions_Group2 Input and Output operation functions
- * @brief IO operation functions
+ * @brief IO operation functions
*
-@verbatim
+@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
@@ -471,7 +471,7 @@
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
(+) Get result of dual mode conversion.
-
+
@endverbatim
* @{
*/
@@ -480,11 +480,11 @@
* @brief Enables DAC and starts conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
@@ -495,7 +495,7 @@
/* Note : This function is defined into this file for library reference */
/* Function content is located into file stm32f3xx_hal_dac_ex.c */
-
+
/* Return function status */
return HAL_ERROR;
}
@@ -504,24 +504,24 @@
* @brief Disables DAC and stop conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
+
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
-
+
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
-
+
/* Return function status */
return HAL_OK;
}
@@ -530,33 +530,33 @@
* @brief Disables DAC and stop conversion of channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
-
+
/* Disable the selected DAC channel DMA request */
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-
+
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
-
+
/* Disable the DMA channel */
/* Channel1 is used */
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
-
+ status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
}
@@ -566,25 +566,25 @@
else /* Channel2 is used */
{
/* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
-
+ status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
#endif /* DAC_CHANNEL2_SUPPORT */
-
+
/* Check if DMA Channel effectively disabled */
if (status != HAL_OK)
{
/* Update DAC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
+ hdac->State = HAL_DAC_STATE_ERROR;
}
else
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
}
-
+
/* Return function status */
return status;
}
@@ -593,11 +593,11 @@
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
- * @param Channel The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
* @retval The selected DAC channel data output value.
*/
__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
@@ -634,21 +634,21 @@
/**
* @}
*/
-
+
/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
+ * @brief Peripheral Control functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral Control functions #####
- ==============================================================================
+ ==============================================================================
[..] This section provides functions allowing to:
- (+) Configure channels.
+ (+) Configure channels.
(+) Configure Triangle wave generation.
(+) Configure Noise wave generation.
(+) Set the specified data holding register value for DAC channel.
(+) Set the specified data holding register value for Dual DAC channels.
-
+
@endverbatim
* @{
*/
@@ -658,11 +658,11 @@
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig DAC configuration structure.
- * @param Channel The selected DAC channel.
+ * @param Channel The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC1 Channel1 selected
- * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
- * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
+ * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
+ * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
* @retval HAL status
*/
@@ -678,7 +678,7 @@
}
__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{
+{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
UNUSED(Channel);
@@ -693,7 +693,7 @@
}
__weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{
+{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
UNUSED(Alignment);
@@ -712,18 +712,18 @@
*/
/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Error functions
- * @brief DAC Peripheral State and Error functions
+ * @brief DAC Peripheral State and Error functions
*
-@verbatim
+@verbatim
==============================================================================
##### DAC Peripheral State and Error functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DAC state.
(+) Check the DAC Errors.
-
+
@endverbatim
* @{
*/
@@ -760,7 +760,7 @@
*/
/**
- * @brief Conversion complete callback in non blocking mode for Channel1
+ * @brief Conversion complete callback in non blocking mode for Channel1
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
@@ -776,7 +776,7 @@
}
/**
- * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
+ * @brief Conversion half DMA transfer callback in non blocking mode for Channel1
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
@@ -835,7 +835,7 @@
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
* @param hdac : DAC handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -844,12 +844,12 @@
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
- * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
- * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
- * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
- * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
- * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
- * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
*
* @param pCallback : pointer to the Callback function
* @retval status
@@ -867,7 +867,7 @@
/* Process locked */
__HAL_LOCK(hdac);
-
+
if(hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackId)
@@ -904,7 +904,7 @@
break;
default :
/* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -922,7 +922,7 @@
break;
default :
/* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -931,7 +931,7 @@
else
{
/* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -943,20 +943,20 @@
/**
* @brief Unregister a User DAC Callback
- * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * DAC Callback is redirected to the weak (overridden) predefined callback
* @param hdac : DAC handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
- * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
- * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
- * @arg @ref HAL_DMA_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
- * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
- * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
- * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
- * @arg @ref HAL_DMA_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
- * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
- * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
+ * @arg @ref HAL_DMA_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
+ * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
+ * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
+ * @arg @ref HAL_DMA_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
+ * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
* @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
* @retval status
*/
@@ -966,7 +966,7 @@
/* Process locked */
__HAL_LOCK(hdac);
-
+
if(hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackId)
@@ -1019,7 +1019,7 @@
break;
default :
/* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1037,7 +1037,7 @@
break;
default :
/* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
break;
@@ -1046,7 +1046,7 @@
else
{
/* Update the error code */
- hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
/* update return status */
status = HAL_ERROR;
}
@@ -1066,3 +1066,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_dac_ex.c b/Src/stm32f3xx_hal_dac_ex.c
index 61ec9ad..11b100e 100644
--- a/Src/stm32f3xx_hal_dac_ex.c
+++ b/Src/stm32f3xx_hal_dac_ex.c
@@ -6,6 +6,7 @@
* This file provides firmware functions to manage the extended
* functionalities of the DAC peripheral.
*
+ *
******************************************************************************
* @attention
*
@@ -28,7 +29,7 @@
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
- @endverbatim
+ @endverbatim
******************************************************************************
*/
@@ -1157,3 +1158,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_dma.c b/Src/stm32f3xx_hal_dma.c
index dcd7fb6..252d1df 100644
--- a/Src/stm32f3xx_hal_dma.c
+++ b/Src/stm32f3xx_hal_dma.c
@@ -9,18 +9,6 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
- *
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
@@ -73,7 +61,17 @@
@endverbatim
******************************************************************************
- */
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -653,7 +651,7 @@
* @brief Register callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callback function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
@@ -706,7 +704,7 @@
* @brief UnRegister callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
@@ -897,3 +895,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_exti.c b/Src/stm32f3xx_hal_exti.c
index 093447d..bf792a5 100644
--- a/Src/stm32f3xx_hal_exti.c
+++ b/Src/stm32f3xx_hal_exti.c
@@ -80,7 +80,6 @@
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -343,7 +342,7 @@
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
- pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+ pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
@@ -617,3 +616,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_flash.c b/Src/stm32f3xx_hal_flash.c
index 5f89421..9fc21ee 100644
--- a/Src/stm32f3xx_hal_flash.c
+++ b/Src/stm32f3xx_hal_flash.c
@@ -9,17 +9,6 @@
* + Memory Control functions
* + Peripheral State functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### FLASH peripheral features #####
@@ -79,6 +68,15 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -691,3 +689,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_flash_ex.c b/Src/stm32f3xx_hal_flash_ex.c
index d3271c3..9222cea 100644
--- a/Src/stm32f3xx_hal_flash_ex.c
+++ b/Src/stm32f3xx_hal_flash_ex.c
@@ -10,17 +10,6 @@
* + Extended I/O operation functions
* + Extended Peripheral Control functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### Flash peripheral extended features #####
@@ -37,6 +26,15 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -979,3 +977,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_gpio.c b/Src/stm32f3xx_hal_gpio.c
index 63a0d06..c56cee7 100644
--- a/Src/stm32f3xx_hal_gpio.c
+++ b/Src/stm32f3xx_hal_gpio.c
@@ -251,23 +251,6 @@
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
SYSCFG->EXTICR[position >> 2u] = temp;
- /* Clear EXTI line configuration */
- temp = EXTI->IMR;
- temp &= ~(iocurrent);
- if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->IMR = temp;
-
- temp = EXTI->EMR;
- temp &= ~(iocurrent);
- if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
- {
- temp |= iocurrent;
- }
- EXTI->EMR = temp;
-
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
temp &= ~(iocurrent);
@@ -284,6 +267,23 @@
temp |= iocurrent;
}
EXTI->FTSR = temp;
+
+ temp = EXTI->EMR;
+ temp &= ~(iocurrent);
+ if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->EMR = temp;
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ temp &= ~(iocurrent);
+ if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
+ {
+ temp |= iocurrent;
+ }
+ EXTI->IMR = temp;
}
}
@@ -328,8 +328,8 @@
EXTI->EMR &= ~((uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
+ EXTI->RTSR &= ~((uint32_t)iocurrent);
/* Configure the External Interrupt or event for the current IO */
tmp = 0x0FuL << (4u * (position & 0x03u));
@@ -443,7 +443,7 @@
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- /* get current Ouput Data Register value */
+ /* get current Output Data Register value */
odr = GPIOx->ODR;
/* Set selected pins that were at low level, and reset ones that were high */
@@ -538,3 +538,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_hrtim.c b/Src/stm32f3xx_hal_hrtim.c
index 47a781b..03b613d 100644
--- a/Src/stm32f3xx_hal_hrtim.c
+++ b/Src/stm32f3xx_hal_hrtim.c
@@ -83,6 +83,8 @@
operates in waveform mode, all the HRTIM features are accessible without
any restriction. HRTIM waveform modes are managed through the set of
functions named HAL_HRTIM_Waveform<Function>
+
+==============================================================================
##### How to use this driver #####
==============================================================================
[..]
@@ -1773,11 +1775,11 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ if(hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
@@ -2390,11 +2392,11 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ if(hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
{
@@ -5484,7 +5486,7 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMERID(Timers));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
@@ -5919,11 +5921,11 @@
/* Check the parameters */
assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
- if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
+ if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
{
return HAL_BUSY;
}
- if((hhrtim->State == HAL_HRTIM_STATE_READY))
+ if(hhrtim->State == HAL_HRTIM_STATE_READY)
{
if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
{
@@ -6256,6 +6258,9 @@
/* Check parameters */
assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(TimerIdx);
+
/* Set output state according to output control status and output disable status */
switch (Output)
{
@@ -8379,7 +8384,7 @@
case HRTIM_OUTPUT_TD1:
case HRTIM_OUTPUT_TE1:
{
- /* Retreives actual OC mode and set interrupt accordingly */
+ /* Retrieves actual OC mode and set interrupt accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
@@ -8414,7 +8419,7 @@
case HRTIM_OUTPUT_TD2:
case HRTIM_OUTPUT_TE2:
{
- /* Retreives actual OC mode and set interrupt accordingly */
+ /* Retrieves actual OC mode and set interrupt accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
@@ -8485,7 +8490,7 @@
case HRTIM_OUTPUT_TD1:
case HRTIM_OUTPUT_TE1:
{
- /* Retreives actual OC mode and set dma_request accordingly */
+ /* Retrieves actual OC mode and set dma_request accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
@@ -8520,7 +8525,7 @@
case HRTIM_OUTPUT_TD2:
case HRTIM_OUTPUT_TE2:
{
- /* Retreives actual OC mode and set dma_request accordingly */
+ /* Retrieves actual OC mode and set dma_request accordingly */
hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
diff --git a/Src/stm32f3xx_hal_i2c.c b/Src/stm32f3xx_hal_i2c.c
index ca9b71e..2b5836c 100644
--- a/Src/stm32f3xx_hal_i2c.c
+++ b/Src/stm32f3xx_hal_i2c.c
@@ -317,7 +317,6 @@
(@) You can refer to the I2C HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -401,7 +400,16 @@
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Macro
+ * @{
+ */
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+/**
+ * @}
+ */
+
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -416,6 +424,7 @@
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
@@ -436,10 +445,14 @@
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources);
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
uint32_t ITSources);
@@ -452,7 +465,8 @@
uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+ uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
@@ -704,6 +718,8 @@
/**
* @brief Register a User I2C Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be registered
@@ -734,8 +750,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -824,14 +838,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
/**
* @brief Unregister an I2C Callback
* I2C callback is redirected to the weak predefined callback
+ * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+ * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param CallbackID ID of the callback to be unregistered
@@ -854,9 +868,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
switch (CallbackID)
@@ -944,8 +955,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -968,8 +977,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2c);
if (HAL_I2C_STATE_READY == hi2c->State)
{
@@ -984,8 +991,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -1000,9 +1005,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2c);
-
if (HAL_I2C_STATE_READY == hi2c->State)
{
hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
@@ -1016,8 +1018,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2c);
return status;
}
@@ -1386,6 +1386,19 @@
return HAL_ERROR;
}
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@@ -1431,22 +1444,27 @@
hi2c->XferCount--;
}
+ /* Wait until AF flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
/* Wait until STOP flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- }
- else
- {
- return HAL_ERROR;
- }
+ return HAL_ERROR;
}
/* Clear STOP flag */
@@ -1511,6 +1529,7 @@
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
+ hi2c->XferSize = hi2c->XferCount;
hi2c->XferISR = NULL;
/* Enable Address Acknowledge */
@@ -1553,6 +1572,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
return HAL_ERROR;
@@ -1565,6 +1585,7 @@
hi2c->pBuffPtr++;
hi2c->XferCount--;
+ hi2c->XferSize--;
}
/* Wait until STOP flag is set */
@@ -1774,6 +1795,20 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_IT;
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2172,39 +2207,88 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Slave_ISR_DMA;
- if (hi2c->hdmatx != NULL)
+ /* Preload TX data if no stretch enable */
+ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
- /* Set the I2C DMA transfer complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
- /* Set the unused DMA callbacks to NULL */
- hi2c->hdmatx->XferHalfCpltCallback = NULL;
- hi2c->hdmatx->XferAbortCallback = NULL;
+ hi2c->XferCount--;
+ hi2c->XferSize--;
+ }
- /* Enable the DMA channel */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ if (hi2c->XferCount != 0U)
+ {
+ if (hi2c->hdmatx != NULL)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
+ (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+ hi2c->XferSize);
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
+
+ if (dmaxferstatus == HAL_OK)
+ {
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, STOP, NACK, ADDR interrupts */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update I2C state */
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Update I2C error code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
else
{
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
- }
-
- if (dmaxferstatus == HAL_OK)
- {
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -2212,27 +2296,10 @@
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
- }
- else
- {
- /* Update I2C state */
- hi2c->State = HAL_I2C_STATE_LISTEN;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Update I2C error code */
- hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
}
return HAL_OK;
@@ -2346,6 +2413,7 @@
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2636,9 +2704,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2658,9 +2723,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2669,30 +2731,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2730,9 +2791,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
-
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
@@ -2752,9 +2810,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2763,29 +2818,29 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_IT;
+ hi2c->XferISR = I2C_Mem_ISR_IT;
+ hi2c->Devaddress = DevAddress;
- if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
}
+ /* If Memory address size is 16Bit */
else
{
- hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
- }
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
/* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
-
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2798,7 +2853,7 @@
/* possible to enable all of these */
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
- I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+ I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
return HAL_OK;
}
@@ -2807,6 +2862,7 @@
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2822,8 +2878,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2845,9 +2899,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2856,28 +2907,36 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart)
- != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+ }
if (hi2c->hdmatx != NULL)
{
@@ -2912,12 +2971,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2925,11 +2980,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -2969,8 +3024,6 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
- uint32_t tickstart;
- uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -2992,9 +3045,6 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Init tickstart for timeout management*/
- tickstart = HAL_GetTick();
-
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -3003,25 +3053,35 @@
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- hi2c->XferISR = I2C_Master_ISR_DMA;
+ hi2c->XferISR = I2C_Mem_ISR_DMA;
+ hi2c->Devaddress = DevAddress;
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- xfermode = I2C_RELOAD_MODE;
}
else
{
hi2c->XferSize = hi2c->XferCount;
- xfermode = I2C_AUTOEND_MODE;
}
- /* Send Slave Address and Memory Address */
- if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ /* If Memory address size is 8Bit */
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ /* Prefetch Memory Address */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+ hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+ /* Prepare Memaddress buffer for LSB part */
+ hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
}
if (hi2c->hdmarx != NULL)
@@ -3057,11 +3117,8 @@
if (dmaxferstatus == HAL_OK)
{
- /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
- /* Update XferCount value */
- hi2c->XferCount -= hi2c->XferSize;
+ /* Send Slave Address and Memory Address */
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3069,11 +3126,11 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
- /* Enable ERR and NACK interrupts */
- I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
}
else
{
@@ -3316,6 +3373,10 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+ I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
return HAL_OK;
@@ -3763,7 +3824,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
+ FlagStatus tmp;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3825,7 +3886,7 @@
hi2c->XferISR = I2C_Slave_ISR_IT;
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -3863,8 +3924,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
-
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -3899,7 +3959,7 @@
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA RX */
@@ -3921,7 +3981,7 @@
if (hi2c->hdmatx != NULL)
{
/* Set the I2C DMA Abort callback :
- will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
/* Abort DMA TX */
@@ -4007,7 +4067,7 @@
}
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4017,15 +4077,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* Enable ERR, STOP, NACK, ADDR interrupts */
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
return HAL_OK;
}
else
@@ -4048,7 +4108,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
+ FlagStatus tmp;
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -4110,7 +4170,7 @@
hi2c->XferISR = I2C_Slave_ISR_IT;
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4148,7 +4208,7 @@
uint32_t XferOptions)
{
/* Declaration of tmp to prevent undefined behavior of volatile usage */
- uint32_t tmp;
+ FlagStatus tmp;
HAL_StatusTypeDef dmaxferstatus;
/* Check the parameters */
@@ -4291,7 +4351,7 @@
}
tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- if ((tmp != RESET) && (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT))
+ if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
@@ -4301,15 +4361,15 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Enable DMA Request */
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
/* REnable ADDR interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
- /* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
return HAL_OK;
}
else
@@ -4443,7 +4503,7 @@
* the configuration information for the specified I2C.
* @retval None
*/
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
@@ -4696,7 +4756,7 @@
* the configuration information for the specified I2C.
* @retval HAL state
*/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
{
/* Return I2C handle state */
return hi2c->State;
@@ -4708,7 +4768,7 @@
* the configuration information for I2C module
* @retval HAL mode
*/
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
{
return hi2c->Mode;
}
@@ -4719,7 +4779,7 @@
* the configuration information for the specified I2C.
* @retval I2C Error Code
*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
}
@@ -4883,6 +4943,143 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+ uint32_t tmpITFlags = ITFlags;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ /* No need to generate STOP, it is automatically done */
+ /* Error callback will be send during stop flag treatment */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+ {
+ /* Remove RXNE flag on temporary variable as read done */
+ tmpITFlags &= ~I2C_FLAG_RXNE;
+
+ /* Read data from RXDR */
+ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ if (hi2c->Memaddress == 0xFFFFFFFFU)
+ {
+ /* Write data to TXDR */
+ hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+ /* Increment Buffer pointer */
+ hi2c->pBuffPtr++;
+
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+ {
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, tmpITFlags);
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -5164,6 +5361,145 @@
}
/**
+ * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param ITFlags Interrupt flags to handle.
+ * @param ITSources Interrupt sources enabled.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+ uint32_t ITSources)
+{
+ uint32_t direction = I2C_GENERATE_START_WRITE;
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+ {
+ /* Clear NACK Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Set corresponding Error Code */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+ /* No need to generate STOP, it is automatically done */
+ /* But enable STOP interrupt, to treat it */
+ /* Error callback will be send during stop flag treatment */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+ {
+ /* Write LSB part of Memory Address */
+ hi2c->Instance->TXDR = hi2c->Memaddress;
+
+ /* Reset Memaddress content */
+ hi2c->Memaddress = 0xFFFFFFFFU;
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ /* Enable only Error interrupt */
+ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+ if (hi2c->XferCount != 0U)
+ {
+ /* Prepare the new XferSize to transfer */
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else
+ {
+ /* Wrong size Status regarding TCR flag event */
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+ {
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ direction = I2C_GENERATE_START_READ;
+ }
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
+ {
+ hi2c->XferSize = MAX_NBYTE_SIZE;
+
+ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_RELOAD_MODE, direction);
+ }
+ else
+ {
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Set NBYTES to write and generate RESTART */
+ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+ I2C_AUTOEND_MODE, direction);
+ }
+
+ /* Update XferCount value */
+ hi2c->XferCount -= hi2c->XferSize;
+
+ /* Enable DMA Request */
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+ }
+ else
+ {
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ }
+ }
+ else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+ {
+ /* Call I2C Master complete process */
+ I2C_ITMasterCplt(hi2c, ITFlags);
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_OK;
+}
+
+/**
* @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
@@ -5204,7 +5540,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
{
treatdmanack = 1U;
}
@@ -5216,7 +5552,7 @@
{
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
{
- if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
{
treatdmanack = 1U;
}
@@ -5827,7 +6163,7 @@
if (hi2c->hdmatx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
}
}
else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
@@ -5837,7 +6173,7 @@
if (hi2c->hdmarx != NULL)
{
- hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
}
}
else
@@ -5998,6 +6334,7 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
uint32_t tmppreviousstate;
/* Reset handle parameters */
@@ -6025,18 +6362,36 @@
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Check if a STOPF is detected */
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ {
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+ }
+
}
hi2c->XferISR = NULL;
}
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
+
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
@@ -6211,6 +6566,7 @@
}
}
+
/**
* @brief DMA I2C slave transmit process complete callback.
* @param hdma DMA handle
@@ -6239,6 +6595,7 @@
}
}
+
/**
* @brief DMA I2C master receive process complete callback.
* @param hdma DMA handle
@@ -6289,6 +6646,7 @@
}
}
+
/**
* @brief DMA I2C slave receive process complete callback.
* @param hdma DMA handle
@@ -6300,7 +6658,7 @@
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
uint32_t tmpoptions = hi2c->XferOptions;
- if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+ if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
(tmpoptions != I2C_NO_OPTION_FRAME))
{
/* Disable DMA Request */
@@ -6317,6 +6675,7 @@
}
}
+
/**
* @brief DMA I2C communication error callback.
* @param hdma DMA handle
@@ -6334,6 +6693,7 @@
I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
}
+
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
@@ -6358,6 +6718,7 @@
I2C_TreatErrorCallback(hi2c);
}
+
/**
* @brief This function handles I2C Communication Timeout. It waits
* until a flag is no longer in the specified status.
@@ -6506,13 +6867,22 @@
}
else
{
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ {
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ }
+ else
+ {
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -6554,15 +6924,15 @@
HAL_StatusTypeDef status = HAL_OK;
uint32_t itflag = hi2c->Instance->ISR;
uint32_t error_code = 0;
+ uint32_t tickstart = Tickstart;
+ uint32_t tmp1;
+ HAL_I2C_ModeTypeDef tmp2;
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
{
- /* In case of Soft End condition, generate the STOP condition */
- if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
- }
+ /* Clear NACKF Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
/* Wait until STOP Flag is set or timeout occurred */
/* AutoEnd should be initiate after AF */
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
@@ -6570,11 +6940,35 @@
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- error_code |= HAL_I2C_ERROR_TIMEOUT;
+ tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+ tmp2 = hi2c->Mode;
- status = HAL_ERROR;
+ /* In case of I2C still busy, try to regenerate a STOP manually */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+ (tmp1 != I2C_CR2_STOP) && \
+ (tmp2 != HAL_I2C_MODE_SLAVE))
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR2 |= I2C_CR2_STOP;
+
+ /* Update Tick with new reference */
+ tickstart = HAL_GetTick();
+ }
+
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+ {
+ error_code |= HAL_I2C_ERROR_TIMEOUT;
+
+ status = HAL_ERROR;
+
+ break;
+ }
+ }
}
}
}
@@ -6586,9 +6980,6 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear NACKF Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
error_code |= HAL_I2C_ERROR_AF;
status = HAL_ERROR;
@@ -6597,7 +6988,7 @@
/* Refresh Content of Status register */
itflag = hi2c->Instance->ISR;
- /* Then verify if an additionnal errors occurs */
+ /* Then verify if an additional errors occurs */
/* Check if a Bus error occurred */
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
{
@@ -6648,7 +7039,7 @@
}
return status;
- }
+}
/**
* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
@@ -6677,14 +7068,16 @@
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
/* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2,
+ MODIFY_REG(hi2c->Instance->CR2, \
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
- I2C_CR2_START | I2C_CR2_STOP)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
- (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request));
+ I2C_CR2_START | I2C_CR2_STOP)), tmp);
}
/**
@@ -6698,8 +7091,9 @@
{
uint32_t tmpisr = 0U;
- if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Mem_ISR_DMA))
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
@@ -6707,32 +7101,6 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if (InterruptRequest == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if (InterruptRequest == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
- }
-
- if (InterruptRequest == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
- }
- else
- {
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
@@ -6745,6 +7113,12 @@
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
if (InterruptRequest == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
@@ -6752,6 +7126,45 @@
}
}
+ else
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+ }
+
+ if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+ }
+
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
diff --git a/Src/stm32f3xx_hal_i2c_ex.c b/Src/stm32f3xx_hal_i2c_ex.c
index b3fa157..3fc652b 100644
--- a/Src/stm32f3xx_hal_i2c_ex.c
+++ b/Src/stm32f3xx_hal_i2c_ex.c
@@ -45,7 +45,6 @@
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f3xx_hal_i2s.c b/Src/stm32f3xx_hal_i2s.c
index ddf1f1f..945678f 100644
--- a/Src/stm32f3xx_hal_i2s.c
+++ b/Src/stm32f3xx_hal_i2s.c
@@ -8,7 +8,6 @@
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
- *
******************************************************************************
* @attention
*
@@ -181,7 +180,7 @@
and weak (surcharged) callbacks are used.
@endverbatim
- ******************************************************************************
+
*/
/* Includes ------------------------------------------------------------------*/
@@ -2119,3 +2118,4 @@
#endif /* SPI_I2S_SUPPORT */
#endif /* HAL_I2S_MODULE_ENABLED */
+
diff --git a/Src/stm32f3xx_hal_i2s_ex.c b/Src/stm32f3xx_hal_i2s_ex.c
index e839bfa..7989c79 100644
--- a/Src/stm32f3xx_hal_i2s_ex.c
+++ b/Src/stm32f3xx_hal_i2s_ex.c
@@ -6,7 +6,6 @@
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
* + Extension features Functions
- *
******************************************************************************
* @attention
*
@@ -84,8 +83,6 @@
| | I2Sx_ext |------------------->I2Sx_extSD(in/out)
+----->| |
+-----------------------+
-
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1135,3 +1132,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_irda.c b/Src/stm32f3xx_hal_irda.c
index 59a15ea..e8e8714 100644
--- a/Src/stm32f3xx_hal_irda.c
+++ b/Src/stm32f3xx_hal_irda.c
@@ -471,6 +471,8 @@
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -499,8 +501,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_READY)
{
@@ -585,15 +585,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
+ * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -613,9 +612,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hirda);
-
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
@@ -701,9 +697,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
@@ -1060,8 +1053,16 @@
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+ }
+ else
+ {
+ /* Enable the IRDA Data Register not empty Interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE);
+ }
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1202,8 +1203,11 @@
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1295,7 +1299,10 @@
__HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
- SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ if (hirda->Init.Parity != IRDA_PARITY_NONE)
+ {
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ }
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Enable the IRDA DMA Rx request */
@@ -2419,7 +2426,6 @@
hirda->gState = HAL_IRDA_STATE_READY;
}
-
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
@@ -2895,3 +2901,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f3xx_hal_iwdg.c b/Src/stm32f3xx_hal_iwdg.c
index 2bb6ffd..d0e9971 100644
--- a/Src/stm32f3xx_hal_iwdg.c
+++ b/Src/stm32f3xx_hal_iwdg.c
@@ -97,7 +97,6 @@
the reload register
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -125,7 +124,7 @@
the LSI_VALUE constant. The value of this constant can be changed by the user
to take into account possible LSI clock period variations.
The timeout value is multiplied by 1000 to be converted in milliseconds.
- LSI startup time is also considered here by adding LSI_STARTUP_TIMEOUT
+ LSI startup time is also considered here by adding LSI_STARTUP_TIME
converted in milliseconds. */
#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
diff --git a/Src/stm32f3xx_hal_msp_template.c b/Src/stm32f3xx_hal_msp_template.c
index 6713a54..981949e 100644
--- a/Src/stm32f3xx_hal_msp_template.c
+++ b/Src/stm32f3xx_hal_msp_template.c
@@ -5,7 +5,7 @@
* @brief HAL MSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
- *
+ *
******************************************************************************
* @attention
*
@@ -18,14 +18,14 @@
*
******************************************************************************
@verbatim
- ===============================================================================
+ ===============================================================================
##### How to use this driver #####
- ===============================================================================
+ ===============================================================================
[..]
@endverbatim
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -97,3 +97,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f3xx_hal_nand.c b/Src/stm32f3xx_hal_nand.c
index 9fa4837..442609f 100644
--- a/Src/stm32f3xx_hal_nand.c
+++ b/Src/stm32f3xx_hal_nand.c
@@ -529,8 +529,8 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -694,8 +694,8 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -869,8 +869,8 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -878,7 +878,7 @@
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
- uint8_t *buff = pBuffer;
+ const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1029,8 +1029,8 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1038,7 +1038,7 @@
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
- uint16_t *buff = pBuffer;
+ const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1200,8 +1200,8 @@
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumSpareAreaToRead)
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -1372,7 +1372,7 @@
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
@@ -1544,8 +1544,8 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1554,7 +1554,7 @@
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
- uint8_t *buff = pBuffer;
+ const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1714,8 +1714,8 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1724,7 +1724,7 @@
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
- uint16_t *buff = pBuffer;
+ const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1882,7 +1882,7 @@
* @param pAddress pointer to NAND address structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress;
@@ -1945,7 +1945,7 @@
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
@@ -2256,7 +2256,7 @@
* the configuration information for NAND module.
* @retval HAL state
*/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
{
return hnand->State;
}
@@ -2267,7 +2267,7 @@
* the configuration information for NAND module.
* @retval NAND status
*/
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
{
uint32_t data;
uint32_t deviceaddress;
diff --git a/Src/stm32f3xx_hal_nor.c b/Src/stm32f3xx_hal_nor.c
index 10ec4e7..4ffc324 100644
--- a/Src/stm32f3xx_hal_nor.c
+++ b/Src/stm32f3xx_hal_nor.c
@@ -106,7 +106,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
-#if defined(FMC_BANK1)
+#if defined(FMC_BANK1)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
@@ -127,6 +127,11 @@
*/
/* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA
+#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA
+#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA
+
#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
@@ -230,6 +235,7 @@
FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR handle parameter */
if (hnor == NULL)
@@ -263,7 +269,8 @@
(void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
/* Initialize NOR extended mode timing Interface */
- (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+ (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
+ hnor->Init.NSBank, hnor->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
@@ -299,11 +306,32 @@
deviceaddress = NOR_MEMORY_ADRESS4;
}
- /* Get the value of the command set */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
- hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+ if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
+ {
+ (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
- return HAL_NOR_ReturnToReadMode(hnor);
+ /* Update the NOR controller state */
+ hnor->State = HAL_NOR_STATE_PROTECTED;
+ }
+ else
+ {
+ /* Get the value of the command set */
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+ NOR_CMD_DATA_CFI);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ }
+
+ hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ status = HAL_NOR_ReturnToReadMode(hnor);
+ }
+
+ return status;
}
/**
@@ -378,7 +406,7 @@
* @param Timeout Maximum timeout value
* @retval None
*/
-__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
+__weak void HAL_NOR_MspWait(const NOR_HandleTypeDef *hnor, uint32_t Timeout)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
@@ -426,7 +454,11 @@
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -455,9 +487,22 @@
/* Send read ID command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_AUTO_SELECT);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -513,7 +558,11 @@
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -587,7 +636,11 @@
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -616,9 +669,22 @@
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_READ_RESET);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_READ_RESET);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -697,9 +763,21 @@
/* Send program data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_PROGRAM);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -756,7 +834,11 @@
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -785,9 +867,22 @@
/* Send read data command */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_READ_RESET);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_READ_RESET);
+ }
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
{
@@ -880,10 +975,20 @@
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ }
+ else
+ {
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ }
/* Write Buffer Load Command */
NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
@@ -983,14 +1088,26 @@
/* Send block erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ }
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
}
else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
@@ -1068,15 +1185,28 @@
/* Send NOR chip erase command sequence */
if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
- NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+ NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+ NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
+ NOR_CMD_DATA_CHIP_ERASE);
+ }
}
else
{
@@ -1116,7 +1246,11 @@
{
return HAL_BUSY;
}
- else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+ else if (state == HAL_NOR_STATE_PROTECTED)
+ {
+ return HAL_ERROR;
+ }
+ else if (state == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1143,8 +1277,15 @@
}
/* Send read CFI query command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
+ if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+ NOR_CMD_DATA_CFI);
+ }
+ else
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ }
/* read the NOR CFI information */
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
@@ -1378,7 +1519,7 @@
* the configuration information for NOR module.
* @retval NOR controller state
*/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
{
return hnor->State;
}
@@ -1392,7 +1533,7 @@
* @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(const NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmpsr1;
diff --git a/Src/stm32f3xx_hal_opamp.c b/Src/stm32f3xx_hal_opamp.c
index 91e353f..39995cd 100644
--- a/Src/stm32f3xx_hal_opamp.c
+++ b/Src/stm32f3xx_hal_opamp.c
@@ -4,11 +4,7 @@
* @author MCD Application Team
* @brief OPAMP HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the operational amplifiers (OPAMP1,...OPAMP4)
- * peripheral:
- * + OPAMP Configuration
- * + OPAMP calibration
- * Thanks to
+ * functionalities of the operational amplifiers peripheral:
* + Initialization/de-initialization functions
* + I/O operation functions
* + Peripheral Control functions
@@ -681,7 +677,7 @@
delta >>= 1U;
}
- /* Still need to check if righ calibration is current value or un step below */
+ /* Still need to check if right calibration is current value or un step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen << OPAMP_INPUT_INVERTING);
@@ -730,7 +726,7 @@
delta >>= 1U;
}
- /* Still need to check if righ calibration is current value or un step below */
+ /* Still need to check if right calibration is current value or un step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
/* Set candidate trimming */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep << OPAMP_INPUT_NONINVERTING);
@@ -759,7 +755,7 @@
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
/* Self calibration is successful */
- /* Store calibration(user timming) results in init structure. */
+ /* Store calibration(user trimming) results in init structure. */
/* Write calibration result N */
hopamp->Init.TrimmingValueN = trimmingvaluen;
@@ -767,7 +763,7 @@
/* Write calibration result P */
hopamp->Init.TrimmingValueP = trimmingvaluep;
- /* Select user timming mode */
+ /* Select user trimming mode */
/* And updated with calibrated settings */
hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep << OPAMP_INPUT_NONINVERTING);
@@ -915,7 +911,7 @@
oldtrimmingvaluen = (hopamp->Instance->CSR & OPAMP_CSR_TRIMOFFSETN) >> OPAMP_INPUT_INVERTING;
}
- /* Set factory timming mode */
+ /* Set factory trimming mode */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
/* Get factory trimming */
@@ -1099,3 +1095,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f3xx_hal_opamp_ex.c b/Src/stm32f3xx_hal_opamp_ex.c
index d23e1de..6476bc5 100644
--- a/Src/stm32f3xx_hal_opamp_ex.c
+++ b/Src/stm32f3xx_hal_opamp_ex.c
@@ -5,10 +5,11 @@
* @brief Extended OPAMP HAL module driver.
*
* This file provides firmware functions to manage the following
- * functionalities of the Power Controller (OPAMP) peripheral:
+ * functionalities of the operational amplifier(s) peripheral:
* + Extended Initialization and de-initialization functions
* + Extended Peripheral Control functions
*
+ @verbatim
******************************************************************************
* @attention
*
@@ -20,8 +21,6 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- @verbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -174,7 +173,7 @@
delta >>= 1U;
}
- // Still need to check if righ calibration is current value or un step below
+ // Still need to check if right calibration is current value or un step below
// Indeed the first value that causes the OUTCAL bit to change from 1 to 0
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
@@ -245,7 +244,7 @@
delta >>= 1U;
}
- // Still need to check if righ calibration is current value or un step below
+ // Still need to check if right calibration is current value or un step below
// Indeed the first value that causes the OUTCAL bit to change from 1 to 0
/* Set candidate trimming */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
@@ -285,8 +284,8 @@
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
/* Self calibration is successful */
- /* Store calibration(user timming) results in init structure. */
- /* Select user timming mode */
+ /* Store calibration(user trimming) results in init structure. */
+ /* Select user trimming mode */
/* Write calibration result N */
hopamp1->Init.TrimmingValueN = trimmingvaluen1;
@@ -300,7 +299,7 @@
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
- /* Select user timming mode */
+ /* Select user trimming mode */
/* And updated with calibrated settings */
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
@@ -477,7 +476,7 @@
delta >>= 1U;
}
- /* Still need to check if righ calibration is current value or un step below */
+ /* Still need to check if right calibration is current value or un step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
@@ -593,7 +592,7 @@
delta >>= 1U;
}
- /* Still need to check if righ calibration is current value or un step below */
+ /* Still need to check if right calibration is current value or un step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0U */
/* Set candidate trimming */
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
@@ -657,8 +656,8 @@
CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
/* Self calibration is successful */
- /* Store calibration(user timming) results in init structure. */
- /* Select user timming mode */
+ /* Store calibration(user trimming) results in init structure. */
+ /* Select user trimming mode */
/* Write calibration result N */
hopamp1->Init.TrimmingValueN = trimmingvaluen1;
@@ -672,7 +671,7 @@
hopamp3->Init.TrimmingValueP = trimmingvaluep3;
hopamp4->Init.TrimmingValueP = trimmingvaluep4;
- /* Select user timming mode */
+ /* Select user trimming mode */
/* And updated with calibrated settings */
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
@@ -713,3 +712,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_pcd.c b/Src/stm32f3xx_hal_pcd.c
index 45ddd4c..0824d96 100644
--- a/Src/stm32f3xx_hal_pcd.c
+++ b/Src/stm32f3xx_hal_pcd.c
@@ -37,7 +37,7 @@
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
+ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -88,8 +88,10 @@
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+#if (USE_USB_DOUBLE_BUFFER == 1U)
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/**
* @}
@@ -165,9 +167,6 @@
hpcd->State = HAL_PCD_STATE_BUSY;
- /* DMA Not supported for FS instance, Force to Zero */
- hpcd->Init.dma_enable = 0U;
-
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -177,7 +176,6 @@
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
hpcd->IN_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0U;
@@ -286,7 +284,7 @@
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
@@ -390,7 +388,7 @@
/**
* @brief Unregister an USB PCD Callback
- * USB PCD callabck is redirected to the weak predefined callback
+ * USB PCD callback is redirected to the weak predefined callback
* @param hpcd USB PCD handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -400,7 +398,7 @@
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
@@ -860,14 +858,18 @@
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_CTR))
+ uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance);
+
+ if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR)
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
(void)PCD_EP_ISR_Handler(hpcd);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_RESET))
+ if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
@@ -878,19 +880,25 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)HAL_PCD_SetAddress(hpcd, 0U);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_PMAOVR))
+ if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ERR))
+ if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_WKUP))
+ if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP)
{
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_LPMODE);
hpcd->Instance->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
@@ -902,9 +910,11 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SUSP))
+ if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP)
{
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= (uint16_t)USB_CNTR_FSUSP;
@@ -919,9 +929,11 @@
#else
HAL_PCD_SuspendCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_SOF))
+ if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF)
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF);
@@ -930,12 +942,16 @@
#else
HAL_PCD_SOFCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ return;
}
- if (__HAL_PCD_GET_FLAG(hpcd, USB_ISTR_ESOF))
+ if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF)
{
/* clear ESOF flag in ISTR */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF);
+
+ return;
}
}
@@ -1221,11 +1237,6 @@
ep->maxpacket = ep_mps;
ep->type = ep_type;
- if (ep->is_in != 0U)
- {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = ep->num;
- }
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
{
@@ -1259,7 +1270,7 @@
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
- ep->num = ep_addr & EP_ADDR_MSK;
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
@@ -1289,14 +1300,7 @@
ep->is_in = 0U;
ep->num = ep_addr & EP_ADDR_MSK;
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- }
- else
- {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
@@ -1334,14 +1338,7 @@
ep->is_in = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- }
- else
- {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
@@ -1532,9 +1529,16 @@
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
- uint16_t count, wIstr, wEPVal, TxByteNbre;
+ uint16_t count;
+ uint16_t wIstr;
+ uint16_t wEPVal;
+ uint16_t TxPctSize;
uint8_t epindex;
+#if (USE_USB_DOUBLE_BUFFER != 1U)
+ count = 0U;
+#endif /* USE_USB_DOUBLE_BUFFER */
+
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
{
@@ -1622,7 +1626,9 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
- if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
+ wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
+
+ if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID))
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
@@ -1652,6 +1658,7 @@
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* manage double buffer bulk out */
@@ -1662,7 +1669,7 @@
else /* manage double buffer iso out */
{
/* free EP OUT Buffer */
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
@@ -1686,6 +1693,8 @@
}
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
+
/* multi-packet on the NON control OUT endpoint */
ep->xfer_count += count;
ep->xfer_buff += count;
@@ -1701,7 +1710,7 @@
}
else
{
- (void) USB_EPStartXfer(hpcd->Instance, ep);
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
@@ -1712,18 +1721,23 @@
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- if (ep->type != EP_TYPE_BULK)
+ if (ep->type == EP_TYPE_ISOC)
{
ep->xfer_len = 0U;
- if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ if (ep->doublebuffer != 0U)
{
- PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+ {
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ }
+ else
+ {
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
+ }
}
- else
- {
- PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
- }
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
@@ -1733,43 +1747,47 @@
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
- /* Manage Bulk Single Buffer Transaction */
- if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))
{
- /* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+ /* Manage Single Buffer Transaction */
+ if ((wEPVal & USB_EP_KIND) == 0U)
+ {
+ /* multi-packet on the NON control IN endpoint */
+ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len > TxByteNbre)
- {
- ep->xfer_len -= TxByteNbre;
- }
- else
- {
- ep->xfer_len = 0U;
- }
+ if (ep->xfer_len > TxPctSize)
+ {
+ ep->xfer_len -= TxPctSize;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
- /* Zero Length Packet? */
- if (ep->xfer_len == 0U)
- {
- /* TX COMPLETE */
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ /* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
+ hpcd->DataInStageCallback(hpcd, ep->num);
#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Transfer is not yet Done */
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+ }
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
else
{
- /* Transfer is not yet Done */
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
- (void)USB_EPStartXfer(hpcd->Instance, ep);
+ (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
}
- }
- /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */
- else
- {
- (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
}
}
}
@@ -1779,6 +1797,7 @@
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
/**
* @brief Manage double buffer bulk out transaction from ISR
* @param hpcd PCD handle
@@ -1812,10 +1831,10 @@
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
- /* Check if Buffer1 is in blocked sate which requires to toggle */
+ /* Check if Buffer1 is in blocked state which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
@@ -1847,7 +1866,7 @@
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
@@ -1871,22 +1890,23 @@
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
uint32_t len;
- uint16_t TxByteNbre;
+ uint16_t TxPctSize;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
/* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len > TxByteNbre)
+ if (ep->xfer_len > TxPctSize)
{
- ep->xfer_len -= TxByteNbre;
+ ep->xfer_len -= TxPctSize;
}
else
{
ep->xfer_len = 0U;
}
+
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
@@ -1902,7 +1922,7 @@
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
@@ -1910,14 +1930,14 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
@@ -1927,7 +1947,7 @@
}
else if (ep->xfer_len_db == 0U)
{
- len = TxByteNbre;
+ len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
@@ -1949,11 +1969,11 @@
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
- TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+ TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_len >= TxByteNbre)
+ if (ep->xfer_len >= TxPctSize)
{
- ep->xfer_len -= TxByteNbre;
+ ep->xfer_len -= TxPctSize;
}
else
{
@@ -1976,7 +1996,7 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
@@ -1984,14 +2004,14 @@
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
- ep->xfer_buff += TxByteNbre;
- ep->xfer_count += TxByteNbre;
+ ep->xfer_buff += TxPctSize;
+ ep->xfer_count += TxPctSize;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
@@ -2001,7 +2021,7 @@
}
else if (ep->xfer_len_db == 0U)
{
- len = TxByteNbre;
+ len = TxPctSize;
ep->xfer_fill_db = 0U;
}
else
@@ -2025,6 +2045,7 @@
return HAL_OK;
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
diff --git a/Src/stm32f3xx_hal_pcd_ex.c b/Src/stm32f3xx_hal_pcd_ex.c
index 18e1903..944cc34 100644
--- a/Src/stm32f3xx_hal_pcd_ex.c
+++ b/Src/stm32f3xx_hal_pcd_ex.c
@@ -100,6 +100,7 @@
/* Configure the PMA */
ep->pmaadress = (uint16_t)pmaadress;
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else /* USB_DBL_BUF */
{
/* Double Buffer Endpoint */
@@ -108,6 +109,7 @@
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
diff --git a/Src/stm32f3xx_hal_pwr.c b/Src/stm32f3xx_hal_pwr.c
index c063944..77d5c2e 100644
--- a/Src/stm32f3xx_hal_pwr.c
+++ b/Src/stm32f3xx_hal_pwr.c
@@ -19,8 +19,6 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- @verbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -271,7 +269,7 @@
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
* @note This parameter has no effect in F3 family and is just maintained to
- * offer full portability of other STM32 families softwares.
+ * offer full portability of other STM32 families software.
* @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
* When WFI entry is used, tick interrupt have to be disabled if not desired as
* the interrupt wake up source.
diff --git a/Src/stm32f3xx_hal_rcc.c b/Src/stm32f3xx_hal_rcc.c
index 260ba6b..aca0e18 100644
--- a/Src/stm32f3xx_hal_rcc.c
+++ b/Src/stm32f3xx_hal_rcc.c
@@ -8,17 +8,6 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
- ******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
@verbatim
==============================================================================
##### RCC specific features #####
@@ -57,6 +46,15 @@
@endverbatim
******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -1220,3 +1218,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_rcc_ex.c b/Src/stm32f3xx_hal_rcc_ex.c
index 8fdca7e..8966adb 100644
--- a/Src/stm32f3xx_hal_rcc_ex.c
+++ b/Src/stm32f3xx_hal_rcc_ex.c
@@ -13,12 +13,11 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -1579,3 +1578,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_rtc.c b/Src/stm32f3xx_hal_rtc.c
index c93fbbe..3a2a41c 100644
--- a/Src/stm32f3xx_hal_rtc.c
+++ b/Src/stm32f3xx_hal_rtc.c
@@ -5,15 +5,11 @@
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A and Alarm B) configuration
- * + WakeUp Timer configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + RTC Tamper and TimeStamp Pins Selection
- * + Interrupts and flags management
+ * + Initialization and de-initialization functions
+ * + RTC Calendar (Time and Date) configuration functions
+ * + RTC Alarms (Alarm A and Alarm B) configuration functions
+ * + Peripheral Control functions
+ * + Peripheral State functions
*
******************************************************************************
* @attention
@@ -27,151 +23,122 @@
*
******************************************************************************
@verbatim
+ ==============================================================================
+ ##### RTC and Backup Domain Operating Condition #####
+ ==============================================================================
+ [..] The real-time clock (RTC) and the RTC backup registers can be powered
+ from the VBAT voltage when the main VDD supply is powered off.
+ To retain the content of the RTC backup registers and supply the RTC when
+ VDD is turned off, VBAT pin can be connected to an optional standby
+ voltage supplied by a battery or by another source.
- ===============================================================================
- ##### RTC Operating Condition #####
- ===============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
+ [..] To allow the RTC operating even when the main digital supply (VDD) is turned
+ off, the VBAT pin powers the following blocks:
+ (#) The RTC
+ (#) The LSE oscillator
+ (#) PC13 to PC15 I/Os, plus PA0 and PE6 I/Os (when available)
- [..] To allow the RTC to operate even when the main digital supply (VDD)
- is turned off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) PC13 to PC15 I/Os (when available)
+ [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
+ the following pins are available:
+ (#) PC14 and PC15 can be used as either GPIO or LSE pins
+ (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
+ (#) PA0 can be used as a GPIO or as the RTC_AF2 pin
+ (#) PE6 can be used as a GPIO or as the RTC_AF3 pin
- [..] When the backup domain is supplied by VDD (analog switch connected
- to VDD), the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_OUT pin
+ [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT
+ because VDD is not present), the following pins are available:
+ (#) PC14 and PC15 can be used as LSE pins only
+ (#) PC13 can be used as the RTC_AF1 pin
+ (#) PA0 can be used as the RTC_AF2 pin
+ (#) PE6 can be used as the RTC_AF3 pin
- [..] When the backup domain is supplied by VBAT (analog switch connected
- to VBAT because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_OUT pin
-
- ##### Backup Domain Reset #####
- ===============================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR
- register to their reset values.
- A backup domain reset is generated when one of the following events
- occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR).
- (#) VDD or VBAT power on, if both supplies have previously been
- powered off.
+ ##### Backup Domain Reset #####
+ ==================================================================
+ [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
+ to their reset values.
+ [..] A backup domain reset is generated when one of the following events occurs:
+ (#) Software reset, triggered by setting the BDRST bit in the
+ RCC Backup domain control register (RCC_BDCR).
+ (#) VDD or VBAT power on, if both supplies have previously been powered off.
##### Backup Domain Access #####
- ===================================================================
- [..] After reset, the backup domain (RTC registers, RTC backup data
- registers and backup SRAM) is protected against possible unwanted write
- accesses.
+ ==================================================================
+ [..] After reset, the backup domain (RTC registers, RTC backup data registers
+ is protected against possible unwanted write accesses.
+ [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
+ (+) Enable the Power Controller (PWR) APB1 interface clock using the
+ __HAL_RCC_PWR_CLK_ENABLE() macro.
+ (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() macro.
+ (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro.
- [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
- (#) Enable the Power Controller (PWR) APB1 interface clock using the
- __HAL_RCC_PWR_CLK_ENABLE() function.
- (#) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
- (#) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
- (#) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (+) Enable the RTC domain access (see description in the section above).
+ (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
+ format using the HAL_RTC_Init() function.
+ *** Time and Date configuration ***
+ ===================================
+ [..]
+ (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
+ and HAL_RTC_SetDate() functions.
+ (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate()
+ functions.
+ (+) To manage the RTC summer or winter time change, use the following
+ functions:
+ (++) HAL_RTC_DST_Add1Hour() or HAL_RTC_DST_Sub1Hour to add or subtract
+ 1 hour from the calendar time.
+ (++) HAL_RTC_DST_SetStoreOperation() or HAL_RTC_DST_ClearStoreOperation
+ to memorize whether the time change has been performed or not.
- ##### How to use RTC Driver #####
- ===================================================================
- [..]
- (+) Enable the RTC domain access (see description in the section above).
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour
- format using the HAL_RTC_Init() function.
-
- *** Time and Date configuration ***
- ===================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime()
- and HAL_RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions.
-
- *** Alarm configuration ***
- ===========================
- [..]
- (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
- You can also configure the RTC Alarm with interrupt mode using the
- HAL_RTC_SetAlarm_IT() function.
- (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-
- *** RTC Wakeup configuration ***
- ================================
- [..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
- using the HAL_RTC_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer()
- function.
-
- *** TimeStamp configuration ***
- ===============================
- [..]
- (+) Configure the RTC_AF trigger and enables the RTC TimeStamp using the
- HAL_RTC_SetTimeStamp() function. You can also configure the RTC TimeStamp with
- interrupt mode using the HAL_RTC_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTC_GetTimeStamp()
- function.
-
- *** Tamper configuration ***
- ============================
- [..]
- (+) Enable the RTC Tamper and Configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTC_SetTamper() function. You can configure RTC Tamper with interrupt
- mode using HAL_RTC_SetTamper_IT() function.
-
- *** Backup Data Registers configuration ***
- ===========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the HAL_RTC_BKUPWrite()
- function.
- (+) To read the RTC Backup Data registers, use the HAL_RTC_BKUPRead()
- function.
-
+ *** Alarm configuration ***
+ ===========================
+ [..]
+ (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function.
+ You can also configure the RTC Alarm with interrupt mode using the
+ HAL_RTC_SetAlarm_IT() function.
+ (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
##### RTC and low power modes #####
- ===================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
- RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop and
- Standby low power modes.
- [..] The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm
- or the RTC wakeup events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC clock source
- is LSE or LSI.
+ ==================================================================
+ [..] The MCU can be woken up from a low power mode by an RTC alternate
+ function.
+ [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
+ RTC wakeup, RTC tamper event detection and RTC timestamp event detection.
+ These RTC alternate functions can wake up the system from the Stop and
+ Standby low power modes.
+ [..] The system can also wake up from low power modes without depending
+ on an external interrupt (Auto-wakeup mode), by using the RTC alarm
+ or the RTC wakeup events.
+ [..] The RTC provides a programmable time base for waking up from the
+ Stop or Standby mode at regular intervals.
+ Wakeup from STOP and STANDBY modes is possible only when the RTC clock
+ source is LSE or LSI.
*** Callback registration ***
=============================================
-
+ [..]
The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
-
+ [..]
Function HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback.
- (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) TimeStampEventCallback : RTC Timestamp Event callback.
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
(+) Tamper3EventCallback : RTC Tamper 3 Event callback.
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
-
+ [..]
Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@@ -179,34 +146,35 @@
This function allows to reset following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback.
- (+) TimeStampEventCallback : RTC TimeStamp Event callback.
+ (+) TimeStampEventCallback : RTC Timestamp Event callback.
(+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback.
(+) Tamper1EventCallback : RTC Tamper 1 Event callback.
(+) Tamper2EventCallback : RTC Tamper 2 Event callback.
(+) Tamper3EventCallback : RTC Tamper 3 Event callback.
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
-
+ [..]
By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
- all callbacks are set to the corresponding weak functions :
+ all callbacks are set to the corresponding weak functions:
examples AlarmAEventCallback(), WakeUpTimerEventCallback().
- Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
- in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
- (not registered beforehand).
- If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
+ Exception done for MspInit() and MspDeInit() callbacks that are reset to the
+ legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only
+ when these callbacks are null (not registered beforehand).
+ If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
+ keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand).
+ [..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
- Exception done MspInit/MspDeInit that can be registered/unregistered
- in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
- thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
+ Exception done MspInit()/MspDeInit() that can be registered/unregistered
+ in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state.
+ Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the
+ Init/DeInit.
+ In that case first register the MspInit()/MspDeInit() user callbacks
using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
- or HAL_RTC_Init() function.
-
+ or HAL_RTC_Init() functions.
+ [..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registration feature is not available and all callbacks
- are set to the corresponding weak functions.
+ not defined, the callback registration feature is not available and all
+ callbacks are set to the corresponding weak functions.
@endverbatim
******************************************************************************
@@ -219,8 +187,8 @@
* @{
*/
-/** @addtogroup RTC
- * @brief RTC HAL module driver
+/** @defgroup RTC RTC
+ * @brief RTC HAL module driver
* @{
*/
@@ -231,15 +199,15 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
-/** @addtogroup RTC_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- *
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -264,7 +232,7 @@
the software must first clear the RSF flag. The software must then
wait until it is set again before reading the calendar, which means
that the calendar registers have been correctly copied into the
- RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function
+ RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function
implements the above software sequence (RSF clear and RSF check).
@endverbatim
@@ -272,14 +240,16 @@
*/
/**
- * @brief Initialize the RTC according to the specified parameters
- * in the RTC_InitTypeDef structure and initialize the associated handle.
- * @param hrtc RTC handle
+ * @brief Initializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
- /* Check the RTC peripheral state */
+ HAL_StatusTypeDef status = HAL_ERROR;
+
+ /* Check RTC handler validity */
if (hrtc == NULL)
{
return HAL_ERROR;
@@ -295,7 +265,7 @@
assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- if(hrtc->State == HAL_RTC_STATE_RESET)
+ if (hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrtc->Lock = HAL_UNLOCKED;
@@ -310,19 +280,19 @@
hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
#endif /* RTC_TAMPER3_SUPPORT */
- if(hrtc->MspInitCallback == NULL)
+ if (hrtc->MspInitCallback == NULL)
{
hrtc->MspInitCallback = HAL_RTC_MspInit;
}
/* Init the low level hardware */
hrtc->MspInitCallback(hrtc);
- if(hrtc->MspDeInitCallback == NULL)
+ if (hrtc->MspDeInitCallback == NULL)
{
hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
}
}
-#else
+#else /* USE_HAL_RTC_REGISTER_CALLBACKS */
if (hrtc->State == HAL_RTC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -331,75 +301,68 @@
/* Initialize RTC MSP */
HAL_RTC_MspInit(hrtc);
}
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ /* Check whether the calendar needs to be initialized */
+ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+
+ if (status == HAL_OK)
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos);
+
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ if (status == HAL_OK)
+ {
+ hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL;
+ hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
+ }
+
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
}
else
{
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
- /* Set RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
- /* Configure the RTC PRER */
- hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
-
- hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
- hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
+ /* The calendar is already initialized */
+ status = HAL_OK;
}
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ return status;
}
/**
- * @brief DeInitialize the RTC peripheral.
- * @param hrtc RTC handle
- * @note This function doesn't reset the RTC Backup Data registers.
+ * @brief DeInitializes the RTC peripheral
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This function does not reset the RTC Backup Data registers.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
{
- uint32_t tickstart = 0U;
+ HAL_StatusTypeDef status = HAL_ERROR;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
@@ -410,115 +373,76 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- else
+ if (status == HAL_OK)
{
- /* Reset TR, DR and CR registers */
+ /* Reset RTC registers */
hrtc->Instance->TR = 0x00000000U;
hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0);
- /* Reset All CR bits except CR[2:0] */
- hrtc->Instance->CR &= RTC_CR_WUCKSEL;
-
- tickstart = HAL_GetTick();
-
- /* Wait till WUTWF flag is set and if Time out is reached exit */
- while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- return HAL_TIMEOUT;
- }
- }
-
- /* Reset all RTC CR register bits */
- hrtc->Instance->CR &= 0x00000000U;
+ hrtc->Instance->CR &= 0x00000000U;
hrtc->Instance->WUTR = RTC_WUTR_WUT;
- hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
- hrtc->Instance->ALRMAR = 0x00000000U;
- hrtc->Instance->ALRMBR = 0x00000000U;
- hrtc->Instance->SHIFTR = 0x00000000U;
- hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->PRER = (uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU);
+ hrtc->Instance->ALRMAR = 0x00000000U;
+ hrtc->Instance->ALRMBR = 0x00000000U;
+ hrtc->Instance->CALR = 0x00000000U;
+ hrtc->Instance->SHIFTR = 0x00000000U;
hrtc->Instance->ALRMASSR = 0x00000000U;
hrtc->Instance->ALRMBSSR = 0x00000000U;
- /* Reset ISR register and exit initialization mode */
- hrtc->Instance->ISR = 0x00000000U;
-
- /* Reset Tamper and alternate functions configuration register */
- hrtc->Instance->TAFCR = 0x00000000U;
-
- /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
- }
+ /* Exit Initialization mode */
+ status = RTC_ExitInitMode(hrtc);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- if(hrtc->MspDeInitCallback == NULL)
+ if (status == HAL_OK)
{
- hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ /* Reset Tamper and alternate functions configuration register */
+ hrtc->Instance->TAFCR = 0x00000000U;
+
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ if (hrtc->MspDeInitCallback == NULL)
+ {
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ }
+
+ /* DeInit the low level hardware: CLOCK, NVIC.*/
+ hrtc->MspDeInitCallback(hrtc);
+#else /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ /* De-Initialize RTC MSP */
+ HAL_RTC_MspDeInit(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+
+ hrtc->State = HAL_RTC_STATE_RESET;
}
- /* DeInit the low level hardware: CLOCK, NVIC.*/
- hrtc->MspDeInitCallback(hrtc);
-
-#else
- /* De-Initialize RTC MSP */
- HAL_RTC_MspDeInit(hrtc);
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
- hrtc->State = HAL_RTC_STATE_RESET;
-
/* Release Lock */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
- * @brief Register a User RTC Callback
+ * @brief Registers a User RTC Callback
* To be used instead of the weak predefined callback
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
* @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
- * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
- * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices.
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
@@ -526,7 +450,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -534,70 +458,70 @@
/* Process locked */
__HAL_LOCK(hrtc);
- if(HAL_RTC_STATE_READY == hrtc->State)
+ if (HAL_RTC_STATE_READY == hrtc->State)
{
switch (CallbackID)
{
- case HAL_RTC_ALARM_A_EVENT_CB_ID :
- hrtc->AlarmAEventCallback = pCallback;
- break;
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = pCallback;
+ break;
- case HAL_RTC_ALARM_B_EVENT_CB_ID :
- hrtc->AlarmBEventCallback = pCallback;
- break;
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ hrtc->AlarmBEventCallback = pCallback;
+ break;
- case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
- hrtc->TimeStampEventCallback = pCallback;
- break;
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = pCallback;
+ break;
- case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
- hrtc->WakeUpTimerEventCallback = pCallback;
- break;
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = pCallback;
+ break;
- case HAL_RTC_TAMPER1_EVENT_CB_ID :
- hrtc->Tamper1EventCallback = pCallback;
- break;
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = pCallback;
+ break;
- case HAL_RTC_TAMPER2_EVENT_CB_ID :
- hrtc->Tamper2EventCallback = pCallback;
- break;
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = pCallback;
+ break;
#if defined(RTC_TAMPER3_SUPPORT)
- case HAL_RTC_TAMPER3_EVENT_CB_ID :
- hrtc->Tamper3EventCallback = pCallback;
- break;
-
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ hrtc->Tamper3EventCallback = pCallback;
+ break;
#endif /* RTC_TAMPER3_SUPPORT */
- case HAL_RTC_MSPINIT_CB_ID :
- hrtc->MspInitCallback = pCallback;
- break;
- case HAL_RTC_MSPDEINIT_CB_ID :
- hrtc->MspDeInitCallback = pCallback;
- break;
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_RTC_STATE_RESET == hrtc->State)
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
{
switch (CallbackID)
{
- case HAL_RTC_MSPINIT_CB_ID :
- hrtc->MspInitCallback = pCallback;
- break;
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = pCallback;
+ break;
- case HAL_RTC_MSPDEINIT_CB_ID :
- hrtc->MspDeInitCallback = pCallback;
- break;
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -613,20 +537,22 @@
}
/**
- * @brief Unregister an RTC Callback
- * RTC callabck is redirected to the weak predefined callback
- * @param hrtc RTC handle
+ * @brief Unregisters an RTC Callback
+ * RTC callback is redirected to the weak predefined callback
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
- * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
- * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID
+ * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID
+ * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
+ * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
@@ -636,70 +562,70 @@
/* Process locked */
__HAL_LOCK(hrtc);
- if(HAL_RTC_STATE_READY == hrtc->State)
+ if (HAL_RTC_STATE_READY == hrtc->State)
{
switch (CallbackID)
{
- case HAL_RTC_ALARM_A_EVENT_CB_ID :
- hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
- break;
+ case HAL_RTC_ALARM_A_EVENT_CB_ID :
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ break;
- case HAL_RTC_ALARM_B_EVENT_CB_ID :
- hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
- break;
+ case HAL_RTC_ALARM_B_EVENT_CB_ID :
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
+ break;
- case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
- hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
- break;
+ case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ break;
- case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
- hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
- break;
+ case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
+ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
+ break;
- case HAL_RTC_TAMPER1_EVENT_CB_ID :
- hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
- break;
+ case HAL_RTC_TAMPER1_EVENT_CB_ID :
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ break;
- case HAL_RTC_TAMPER2_EVENT_CB_ID :
- hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
- break;
+ case HAL_RTC_TAMPER2_EVENT_CB_ID :
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+ break;
#if defined(RTC_TAMPER3_SUPPORT)
- case HAL_RTC_TAMPER3_EVENT_CB_ID :
- hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
- break;
-
+ case HAL_RTC_TAMPER3_EVENT_CB_ID :
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
+ break;
#endif /* RTC_TAMPER3_SUPPORT */
- case HAL_RTC_MSPINIT_CB_ID :
- hrtc->MspInitCallback = HAL_RTC_MspInit;
- break;
- case HAL_RTC_MSPDEINIT_CB_ID :
- hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
- break;
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(HAL_RTC_STATE_RESET == hrtc->State)
+ else if (HAL_RTC_STATE_RESET == hrtc->State)
{
switch (CallbackID)
{
- case HAL_RTC_MSPINIT_CB_ID :
- hrtc->MspInitCallback = HAL_RTC_MspInit;
- break;
+ case HAL_RTC_MSPINIT_CB_ID :
+ hrtc->MspInitCallback = HAL_RTC_MspInit;
+ break;
- case HAL_RTC_MSPDEINIT_CB_ID :
- hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
- break;
+ case HAL_RTC_MSPDEINIT_CB_ID :
+ hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
+ break;
- default :
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -716,8 +642,9 @@
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
- * @brief Initialize the RTC MSP.
- * @param hrtc RTC handle
+ * @brief Initializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc)
@@ -725,14 +652,15 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspInit could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitialize the RTC MSP.
- * @param hrtc RTC handle
+ * @brief DeInitializes the RTC MSP.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc)
@@ -740,8 +668,8 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_MspDeInit could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTC_MspDeInit could be implemented in the user file
*/
}
@@ -749,9 +677,9 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group2
- * @brief RTC Time and Date functions
- *
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
+ * @brief RTC Time and Date functions
+ *
@verbatim
===============================================================================
##### RTC Time and Date functions #####
@@ -764,11 +692,12 @@
*/
/**
- * @brief Set RTC current time.
- * @param hrtc RTC handle
+ * @brief Sets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sTime Pointer to Time structure
* @note DayLightSaving and StoreOperation interfaces are deprecated.
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions.
- * @param sTime Pointer to Time structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
@@ -778,6 +707,7 @@
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg = 0U;
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -791,7 +721,7 @@
if (Format == RTC_FORMAT_BIN)
{
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
{
assert_param(IS_RTC_HOUR12(sTime->Hours));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
@@ -804,14 +734,14 @@
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
- (((uint32_t)sTime->TimeFormat) << 16U));
+ tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
+ (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos));
}
else
{
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
{
assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
@@ -823,85 +753,69 @@
}
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
- tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
- ((uint32_t)(sTime->Minutes) << 8U) | \
- ((uint32_t)sTime->Seconds) | \
- ((uint32_t)(sTime->TimeFormat) << 16U));
+ tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \
+ ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \
+ ((uint32_t) sTime->Seconds) | \
+ ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos));
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ if (status == HAL_OK)
{
/* Set the RTC_TR register */
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
- hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK);
+ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
/* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+ status = RTC_ExitInitMode(hrtc);
}
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
}
/**
- * @brief Get RTC current time.
- * @param hrtc RTC handle
+ * @brief Gets RTC current time.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTime Pointer to Time structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
- * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds
- * value in second fraction ratio with time unit following generic formula:
- * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
- * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS
- * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values
- * in the higher-order calendar shadow registers.
+ * @note You can use SubSeconds and SecondFraction (sTime structure fields
+ * returned) to convert SubSeconds value in second fraction ratio with
+ * time unit following generic formula:
+ * Second fraction ratio * time_unit =
+ * [(SecondFraction - SubSeconds) / (SecondFraction + 1)] * time_unit
+ * This conversion can be performed only if no shift operation is pending
+ * (ie. SHFP=0) when PREDIV_S >= SS
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the
+ * values in the higher-order calendar shadow registers to ensure
+ * consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers
+ * until current date is read to ensure consistency between the time and
+ * date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
@@ -911,7 +825,7 @@
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- /* Get subseconds structure field from the corresponding register*/
+ /* Get subseconds value from the corresponding register */
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
/* Get SecondFraction structure field from the corresponding register field*/
@@ -921,10 +835,10 @@
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
- sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
- sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
- sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
+ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos);
+ sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
+ sTime->Seconds = (uint8_t)( tmpreg & (RTC_TR_ST | RTC_TR_SU));
+ sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos);
/* Check the input parameters format */
if (Format == RTC_FORMAT_BIN)
@@ -939,8 +853,9 @@
}
/**
- * @brief Set RTC current date.
- * @param hrtc RTC handle
+ * @brief Sets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate Pointer to date structure
* @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
@@ -951,6 +866,7 @@
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg = 0U;
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -973,10 +889,10 @@
assert_param(IS_RTC_MONTH(sDate->Month));
assert_param(IS_RTC_DATE(sDate->Date));
- datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
- ((uint32_t)sDate->WeekDay << 13U));
+ datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
+ ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos));
}
else
{
@@ -984,74 +900,56 @@
assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));
- datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
- (((uint32_t)sDate->Month) << 8U) | \
- ((uint32_t)sDate->Date) | \
- (((uint32_t)sDate->WeekDay) << 13U));
+ datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \
+ (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \
+ ((uint32_t) sDate->Date) | \
+ (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos));
}
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ if (status == HAL_OK)
{
/* Set the RTC_DR register */
hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
- /* If CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
+ status = RTC_ExitInitMode(hrtc);
}
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
}
/**
- * @brief Get RTC current date.
- * @param hrtc RTC handle
+ * @brief Gets RTC current date.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sDate Pointer to Date structure
* @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN : Binary data format
- * @arg RTC_FORMAT_BCD : BCD data format
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the
+ * values in the higher-order calendar shadow registers to ensure
+ * consistency between the time and date values.
+ * Reading RTC current time locks the values in calendar shadow registers
+ * until current date is read to ensure consistency between the time and
+ * date values.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
@@ -1065,24 +963,749 @@
datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
/* Fill the structure fields with the read parameters */
- sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
- sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
- sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
- sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
+ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos);
+ sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos);
+ sDate->Date = (uint8_t) (datetmpreg & (RTC_DR_DT | RTC_DR_DU));
+ sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos);
/* Check the input parameters format */
if (Format == RTC_FORMAT_BIN)
{
/* Convert the date structure parameters to Binary format */
- sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
+ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
- sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
+ sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
}
return HAL_OK;
}
/**
- * @brief Daylight Saving Time, adda one hour to the calendar in one
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
+ * @brief RTC Alarm functions
+ *
+@verbatim
+ ===============================================================================
+ ##### RTC Alarm functions #####
+ ===============================================================================
+
+ [..] This section provides functions allowing to configure Alarm feature
+
+@endverbatim
+ * @{
+ */
+/**
+ * @brief Sets the specified RTC Alarm.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ uint32_t tickstart = 0U;
+ uint32_t tmpreg = 0U;
+ uint32_t subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ /* Change RTC state to BUSY */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Check the data format (binary or BCD) and store the Alarm time and date
+ configuration accordingly */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t) sAlarm->AlarmMask));
+ }
+
+ /* Store the Alarm subseconds configuration */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \
+ (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if (sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case interrupt mode is used, the interrupt source must be disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Subseconds register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ }
+ else
+ {
+ /* Disable the Alarm B */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case interrupt mode is used, the interrupt source must be disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Subseconds register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state back to READY */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Sets the specified RTC Alarm with Interrupt.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @note The Alarm register can only be written when the corresponding Alarm
+ * is disabled (Use the HAL_RTC_DeactivateAlarm()).
+ * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
+{
+ __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
+ uint32_t tmpreg = 0U;
+ uint32_t subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(sAlarm->Alarm));
+ assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
+ assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ /* Change RTC state to BUSY */
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Check the data format (binary or BCD) and store the Alarm time and date
+ configuration accordingly */
+ if (Format == RTC_FORMAT_BIN)
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
+ }
+ assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
+ assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
+ }
+
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t)sAlarm->AlarmMask));
+ }
+ else
+ {
+ if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
+ {
+ assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
+ }
+ else
+ {
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
+ assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
+ }
+
+ assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
+ assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+
+ if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+ else
+ {
+ assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
+ }
+
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \
+ ((uint32_t) sAlarm->AlarmTime.Seconds) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \
+ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \
+ ((uint32_t) sAlarm->AlarmMask));
+ }
+
+ /* Store the Alarm subseconds configuration */
+ subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \
+ (uint32_t)(sAlarm->AlarmSubSecondMask));
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Configure the Alarm register */
+ if (sAlarm->Alarm == RTC_ALARM_A)
+ {
+ /* Disable the Alarm A */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
+ do
+ {
+ count = count - 1U;
+ if (count == 0U)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U);
+
+ hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
+ /* Configure the Alarm A Subseconds register */
+ hrtc->Instance->ALRMASSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMA_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
+ }
+ else
+ {
+ /* Disable the Alarm B */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ /* Reload the counter */
+ count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
+
+ /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
+ do
+ {
+ count = count - 1U;
+ if (count == 0U)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U);
+
+ hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
+ /* Configure the Alarm B Subseconds register */
+ hrtc->Instance->ALRMBSSR = subsecondtmpreg;
+ /* Configure the Alarm state: Enable Alarm */
+ __HAL_RTC_ALARMB_ENABLE(hrtc);
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
+ }
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Change RTC state back to READY */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Deactivates the specified RTC Alarm.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: Alarm A
+ * @arg RTC_ALARM_B: Alarm B
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
+{
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ /* Process Locked */
+ __HAL_LOCK(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_BUSY;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ if (Alarm == RTC_ALARM_A)
+ {
+ /* Disable Alarm A */
+ __HAL_RTC_ALARMA_DISABLE(hrtc);
+
+ /* In case interrupt mode is used, the interrupt source must be disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ /* Disable Alarm B */
+ __HAL_RTC_ALARMB_DISABLE(hrtc);
+
+ /* In case interrupt mode is used, the interrupt source must be disabled */
+ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the RTC Alarm value and masks.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
+ * This parameter can be one of the following values:
+ * @arg RTC_ALARM_A: Alarm A
+ * @arg RTC_ALARM_B: Alarm B
+ * @param Format Specifies the format of the entered parameters.
+ * This parameter can be one of the following values:
+ * @arg RTC_FORMAT_BIN: Binary data format
+ * @arg RTC_FORMAT_BCD: BCD data format
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
+{
+ uint32_t tmpreg = 0U;
+ uint32_t subsecondtmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_FORMAT(Format));
+ assert_param(IS_RTC_ALARM(Alarm));
+
+ if (Alarm == RTC_ALARM_A)
+ {
+ sAlarm->Alarm = RTC_ALARM_A;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
+ }
+ else
+ {
+ sAlarm->Alarm = RTC_ALARM_B;
+
+ tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
+ subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
+ }
+
+ /* Fill the structure with the read parameters */
+ sAlarm->AlarmTime.Hours = (uint8_t) ((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos);
+ sAlarm->AlarmTime.Minutes = (uint8_t) ((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos);
+ sAlarm->AlarmTime.Seconds = (uint8_t) ( tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
+ sAlarm->AlarmTime.TimeFormat = (uint8_t) ((tmpreg & RTC_ALRMAR_PM) >> RTC_TR_PM_Pos);
+ sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
+ sAlarm->AlarmDateWeekDay = (uint8_t) ((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos);
+ sAlarm->AlarmDateWeekDaySel = (uint32_t) (tmpreg & RTC_ALRMAR_WDSEL);
+ sAlarm->AlarmMask = (uint32_t) (tmpreg & RTC_ALARMMASK_ALL);
+
+ if (Format == RTC_FORMAT_BIN)
+ {
+ sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
+ sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
+ sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
+ sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles Alarm interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
+{
+ /* Clear the EXTI's line Flag for RTC Alarm */
+ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
+
+ /* Get the Alarm A interrupt source enable status */
+ if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
+ {
+ /* Get the pending status of the Alarm A Interrupt */
+ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U)
+ {
+ /* Clear the Alarm A interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Alarm A callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmAEventCallback(hrtc);
+#else
+ HAL_RTC_AlarmAEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Get the Alarm B interrupt source enable status */
+ if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
+ {
+ /* Get the pending status of the Alarm B Interrupt */
+ if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U)
+ {
+ /* Clear the Alarm B interrupt pending bit */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
+
+ /* Alarm B callback */
+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
+ hrtc->AlarmBEventCallback(hrtc);
+#else
+ HAL_RTCEx_AlarmBEventCallback(hrtc);
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+ }
+ }
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+}
+
+/**
+ * @brief Alarm A callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval None
+ */
+__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTC_AlarmAEventCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Handles Alarm A Polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param Timeout Timeout duration
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRAF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
+ {
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Clear the Alarm flag */
+ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
+
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
+ * @brief Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides functions allowing to
+ (+) Wait for RTC Time and Date Synchronization
+ (+) Manage RTC Summer or Winter time change
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
+ * synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
+ * @note To read the calendar through the shadow registers after Calendar
+ * initialization, calendar update or after wakeup from low power modes
+ * the software must first clear the RSF flag.
+ * The software must then wait until it is set again before reading
+ * the calendar, which means that the calendar registers have been
+ * correctly copied into the RTC_TR and RTC_DR shadow registers.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
+{
+ uint32_t tickstart = 0U;
+
+ /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
+ hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK));
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the registers to be synchronised */
+ while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Daylight Saving Time, adds one hour to the calendar in one
* single operation without going through the initialization procedure.
* @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
@@ -1150,689 +1773,9 @@
* @}
*/
-/** @addtogroup RTC_Exported_Functions_Group3
- * @brief RTC Alarm functions
- *
-@verbatim
- ===============================================================================
- ##### RTC Alarm functions #####
- ===============================================================================
-
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
- * @{
- */
-/**
- * @brief Set the specified RTC Alarm.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Alarm structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0U;
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if (Format == RTC_FORMAT_BIN)
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
-
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
-
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
-
- /* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Alarm register */
- if (sAlarm->Alarm == RTC_ALARM_A)
- {
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
- }
- else
- {
- /* Disable the Alarm B interrupt */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Sub Second register */
- hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMB_ENABLE(hrtc);
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Set the specified RTC Alarm with Interrupt.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Alarm structure
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the HAL_RTC_DeactivateAlarm()).
- * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
- uint32_t tickstart = 0U;
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(sAlarm->Alarm));
- assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- if (Format == RTC_FORMAT_BIN)
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
- }
- assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
- assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
- }
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- else
- {
- if ((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
- }
- else
- {
- sAlarm->AlarmTime.TimeFormat = 0x00U;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-
- if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay)));
- }
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
- ((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
- ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
- ((uint32_t)sAlarm->AlarmMask));
- }
- /* Configure the Alarm A or Alarm B Sub Second registers */
- subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Configure the Alarm register */
- if (sAlarm->Alarm == RTC_ALARM_A)
- {
- /* Disable the Alarm A interrupt */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* Clear flag alarm A */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
- /* Configure the Alarm A Sub Second register */
- hrtc->Instance->ALRMASSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMA_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA);
- }
- else
- {
- /* Disable the Alarm B interrupt */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* Clear flag alarm B */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
- tickstart = HAL_GetTick();
- /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
- hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
- /* Configure the Alarm B Sub Second register */
- hrtc->Instance->ALRMBSSR = subsecondtmpreg;
- /* Configure the Alarm state: Enable Alarm */
- __HAL_RTC_ALARMB_ENABLE(hrtc);
- /* Configure the Alarm interrupt */
- __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
- }
-
- /* RTC Alarm Interrupt Configuration: EXTI configuration */
- __HAL_RTC_ALARM_EXTI_ENABLE_IT();
-
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Deactivate the specified RTC Alarm.
- * @param hrtc RTC handle
- * @param Alarm Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A : AlarmA
- * @arg RTC_ALARM_B : AlarmB
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
- uint32_t tickstart = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(Alarm));
-
- /* Process Locked */
- __HAL_LOCK(hrtc);
-
- hrtc->State = HAL_RTC_STATE_BUSY;
-
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- if (Alarm == RTC_ALARM_A)
- {
- /* AlarmA */
- __HAL_RTC_ALARMA_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- /* AlarmB */
- __HAL_RTC_ALARMB_DISABLE(hrtc);
-
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param hrtc RTC handle
- * @param sAlarm Pointer to Date structure
- * @param Alarm Specifies the Alarm.
- * This parameter can be one of the following values:
- * @arg RTC_ALARM_A: AlarmA
- * @arg RTC_ALARM_B: AlarmB
- * @param Format Specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_FORMAT_BIN: Binary data format
- * @arg RTC_FORMAT_BCD: BCD data format
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
- uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(Format));
- assert_param(IS_RTC_ALARM(Alarm));
-
- if (Alarm == RTC_ALARM_A)
- {
- /* AlarmA */
- sAlarm->Alarm = RTC_ALARM_A;
-
- tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
- }
- else
- {
- sAlarm->Alarm = RTC_ALARM_B;
-
- tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
- subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
- }
-
- /* Fill the structure with the read parameters */
- sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U);
- sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U);
- sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
- sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U);
- sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
- sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U);
- sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-
- if (Format == RTC_FORMAT_BIN)
- {
- sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
- sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
- sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
- sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle Alarm interrupt request.
- * @param hrtc RTC handle
- * @retval None
- */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
-{
- /* Get the AlarmA interrupt source enable status */
- if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != RESET)
- {
- /* Get the pending status of the AlarmA Interrupt */
- if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != RESET)
- {
- /* AlarmA callback */
- #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- hrtc->AlarmAEventCallback(hrtc);
- #else
- HAL_RTC_AlarmAEventCallback(hrtc);
- #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the AlarmA interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
- }
- }
-
- /* Get the AlarmB interrupt source enable status */
- if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != RESET)
- {
- /* Get the pending status of the AlarmB Interrupt */
- if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != RESET)
- {
- /* AlarmB callback */
- #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- hrtc->AlarmBEventCallback(hrtc);
- #else
- HAL_RTCEx_AlarmBEventCallback(hrtc);
- #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the AlarmB interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
- }
- }
-
- /* Clear the EXTI's line Flag for RTC Alarm */
- __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
- * @brief Alarm A callback.
- * @param hrtc RTC handle
- * @retval None
- */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hrtc);
-
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTC_AlarmAEventCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief Handle AlarmA Polling request.
- * @param hrtc RTC handle
- * @param Timeout Timeout duration
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-
- uint32_t tickstart = HAL_GetTick();
-
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
- {
- if (Timeout != HAL_MAX_DELAY)
- {
- if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
- {
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Clear the Alarm interrupt pending bit */
- __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @@addtogroup RTC_Exported_Functions_Group4 Peripheral Control functions
- * @brief Peripheral Control functions
- *
-@verbatim
- ===============================================================================
- ##### Peripheral Control functions #####
- ===============================================================================
- [..]
- This subsection provides functions allowing to
- (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc RTC handle
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
-{
- uint32_t tickstart = 0U;
-
- /* Clear RSF flag */
- hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-
- tickstart = HAL_GetTick();
-
- /* Wait the registers to be synchronised */
- while ((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @}
- */
-
-/** @@addtogroup RTC_Exported_Functions_Group5 Peripheral State functions
- * @brief Peripheral State functions
- *
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -1845,13 +1788,13 @@
* @{
*/
/**
- * @brief Return the RTC handle state.
- * @param hrtc RTC handle
+ * @brief Returns the RTC state.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL state
*/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc)
{
- /* Return RTC handle state */
return hrtc->State;
}
@@ -1859,88 +1802,118 @@
* @}
*/
+
/**
* @}
*/
-/** @@addtogroup RTC_Private_Functions RTC Private Functions
+/** @addtogroup RTC_Private_Functions
* @{
*/
/**
- * @brief Enter the RTC Initialization mode.
+ * @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc RTC handle
- * @retval An ErrorStatus enumeration value:
- * - HAL_OK : RTC is in Init mode
- * - HAL_TIMEOUT : RTC is not in Init mode and in Timeout
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
+ HAL_StatusTypeDef status = HAL_OK;
- /* Check if the Initialization mode is set */
- if ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ /* Check that Initialization mode is not already set */
+ if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U)
{
- /* Set the Initialization mode */
- hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
+ /* Set INIT bit to enter Initialization mode */
+ SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- while ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+
+ /* Wait till RTC is in INIT state and if timeout is reached exit */
+ while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR))
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+ status = HAL_ERROR;
}
}
}
- return HAL_OK;
+ return status;
}
+/**
+ * @brief Exits the RTC Initialization mode.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Clear INIT bit to exit Initialization mode */
+ CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro */
+ if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+}
/**
- * @brief Convert a 2 digit decimal to BCD format.
- * @param Value Byte to be converted
+ * @brief Converts a 2-digit number from decimal to BCD format.
+ * @param number decimal-formatted number (from 0 to 99) to be converted
* @retval Converted byte
*/
-uint8_t RTC_ByteToBcd2(uint8_t Value)
+uint8_t RTC_ByteToBcd2(uint8_t number)
{
uint32_t bcdhigh = 0U;
- while (Value >= 10U)
+ while (number >= 10U)
{
bcdhigh++;
- Value -= 10U;
+ number -= 10U;
}
- return ((uint8_t)(bcdhigh << 4U) | Value);
+ return ((uint8_t)(bcdhigh << 4U) | number);
}
/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value BCD value to be converted
+ * @brief Converts a 2-digit number from BCD to decimal format.
+ * @param number BCD-formatted number (from 00 to 99) to be converted
* @retval Converted word
*/
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
+uint8_t RTC_Bcd2ToByte(uint8_t number)
{
- uint32_t tmp = 0U;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U;
- return (tmp + (Value & (uint8_t)0x0FU));
+ uint32_t tens = 0U;
+ tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U;
+ return (uint8_t)(tens + ((uint32_t)number & 0x0FU));
}
+
/**
* @}
*/
#endif /* HAL_RTC_MODULE_ENABLED */
-
/**
* @}
*/
-
/**
* @}
*/
diff --git a/Src/stm32f3xx_hal_rtc_ex.c b/Src/stm32f3xx_hal_rtc_ex.c
index 488a3d9..44c5f91 100644
--- a/Src/stm32f3xx_hal_rtc_ex.c
+++ b/Src/stm32f3xx_hal_rtc_ex.c
@@ -4,10 +4,10 @@
* @author MCD Application Team
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
- * functionalities of the Real Time Clock (RTC) Extended peripheral:
- * + RTC Time Stamp functions
+ * functionalities of the Real-Time Clock (RTC) Extended peripheral:
+ * + RTC Timestamp functions
* + RTC Tamper functions
- * + RTC Wake-up functions
+ * + RTC Wakeup functions
* + Extended Control functions
* + Extended RTC features functions
*
@@ -24,7 +24,7 @@
******************************************************************************
@verbatim
==============================================================================
- ##### How to use this driver #####
+ ##### How to use this driver #####
==============================================================================
[..]
(+) Enable the RTC domain access.
@@ -34,31 +34,35 @@
*** RTC Wakeup configuration ***
================================
[..]
- (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
- function. You can also configure the RTC Wakeup timer with interrupt mode
- using the HAL_RTCEx_SetWakeUpTimer_IT() function.
- (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
+ (+) To configure the RTC Wakeup Clock source and Counter use the
+ HAL_RTCEx_SetWakeUpTimer() function.
+ You can also configure the RTC Wakeup timer in interrupt mode using the
+ HAL_RTCEx_SetWakeUpTimer_IT() function.
+ (+) To read the RTC Wakeup Counter register, use the HAL_RTCEx_GetWakeUpTimer()
function.
- *** TimeStamp configuration ***
+ *** Timestamp configuration ***
===============================
[..]
- (+) Configure the RTC_AF trigger and enable the RTC TimeStamp using the
- HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
- interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
- (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
- function.
- (+) The TIMESTAMP alternate function is mapped to RTC_AF1 (PC13U).
+ (+) To configure the RTC Timestamp use the HAL_RTCEx_SetTimeStamp() function.
+ You can also configure the RTC Timestamp with interrupt mode using the
+ HAL_RTCEx_SetTimeStamp_IT() function.
+ (+) To read the RTC Timestamp Time and Date register, use the
+ HAL_RTCEx_GetTimeStamp() function.
+ (+) The Timestamp alternate function is mapped to RTC_AF1 (PC13).
*** Tamper configuration ***
============================
[..]
- (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge
- or Level according to the Tamper filter (if equal to 0 Edge else Level)
- value, sampling frequency, precharge or discharge and Pull-UP using the
- HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
- mode using HAL_RTCEx_SetTamper_IT() function.
- (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13U).
+ (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger
+ Edge or Level according to the Tamper filter value (if equal to 0 Edge
+ else Level), sampling frequency, precharge or discharge and Pull-UP use
+ the HAL_RTCEx_SetTamper() function.
+ You can configure RTC Tamper in interrupt mode using HAL_RTCEx_SetTamper_IT()
+ function.
+ (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13).
+ (+) The TAMPER2 alternate function is mapped to RTC_AF2 (PA0).
+ (+) The TAMPER3 alternate function is mapped to RTC_AF3 (PE6).
*** Backup Data Registers configuration ***
===========================================
@@ -68,7 +72,23 @@
(+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
function.
- @endverbatim
+ *** Smooth Digital Calibration configuration ***
+ ================================================
+ [..]
+ (+) RTC frequency can be digitally calibrated with a resolution of about
+ 0.954 ppm with a range from -487.1 ppm to +488.5 ppm.
+ The correction of the frequency is performed using a series of small
+ adjustments (adding and/or subtracting individual RTCCLK pulses).
+ (+) The smooth digital calibration is performed during a cycle of about 2^20
+ RTCCLK pulses (or 32 seconds) when the input frequency is 32,768 Hz.
+ This cycle is maintained by a 20-bit counter clocked by RTCCLK.
+ (+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK
+ clock cycles to be masked during the 32-second cycle.
+ (+) The RTC Smooth Digital Calibration value and the corresponding calibration
+ cycle period (32s, 16s, or 8s) can be calibrated using the
+ HAL_RTCEx_SetSmoothCalib() function.
+
+ @endverbatim
******************************************************************************
*/
@@ -79,10 +99,8 @@
* @{
*/
-
-
-/** @addtogroup RTCEx
- * @brief RTC Extended HAL module driver
+/** @defgroup RTCEx RTCEx
+ * @brief RTC Extended HAL module driver
* @{
*/
@@ -93,73 +111,88 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
+/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
-
-/** @addtogroup RTCEx_Exported_Functions_Group1
- * @brief RTC TimeStamp and Tamper functions
- *
+/** @defgroup RTCEx_Exported_Functions_Group1 RTC Timestamp and Tamper functions
+ * @brief RTC Timestamp and Tamper functions
+ *
@verbatim
===============================================================================
- ##### RTC TimeStamp and Tamper functions #####
+ ##### RTC Timestamp and Tamper functions #####
===============================================================================
- [..] This section provides functions allowing to configure TimeStamp feature
+ [..] This section provides functions allowing to configure Timestamp feature
@endverbatim
* @{
*/
/**
- * @brief Set TimeStamp.
- * @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc RTC handle
- * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * @brief Sets Timestamp.
+ * @note This API must be called before enabling the Timestamp feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is
* activated.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on
+ * the rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on
+ * the falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin.
+ * @note Although unused, parameter RTC_TimeStampPin has been kept for portability
+ * reasons.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge));
assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+ /* Prevent compilation warning due to unused argument(s) if assert_param check
+ is disabled */
+ UNUSED(RTC_TimeStampPin);
+
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state to BUSY */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
- tmpreg |= TimeStampEdge;
+ /* Configure the Timestamp TSEDGE bit */
+ tmpreg |= RTC_TimeStampEdge;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Time Stamp TSEDGE and Enable bits */
+ /* Copy the desired configuration into the CR register */
hrtc->Instance->CR = (uint32_t)tmpreg;
+ /* Clear RTC Timestamp flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ /* Clear RTC Timestamp overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Enable the Timestamp saving */
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
+ /* Change RTC state back to READY */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -169,58 +202,74 @@
}
/**
- * @brief Set TimeStamp with Interrupt.
- * @param hrtc RTC handle
- * @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
+ * @brief Sets Timestamp with Interrupt.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @note This API must be called before enabling the Timestamp feature.
+ * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is
* activated.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
- * rising edge of the related pin.
- * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on
+ * the rising edge of the related pin.
+ * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on
+ * the falling edge of the related pin.
+ * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin.
* This parameter can be one of the following values:
- * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
+ * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin.
+ * @note Although unused, parameter RTC_TimeStampPin has been kept for portability
+ * reasons.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin)
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
- assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
+ assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge));
assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+ /* Prevent compilation warning due to unused argument(s) if assert_param check
+ is disabled */
+ UNUSED(RTC_TimeStampPin);
+
/* Process Locked */
__HAL_LOCK(hrtc);
+ /* Change RTC state to BUSY */
hrtc->State = HAL_RTC_STATE_BUSY;
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
- tmpreg |= TimeStampEdge;
+ /* Configure the Timestamp TSEDGE bit */
+ tmpreg |= RTC_TimeStampEdge;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Configure the Time Stamp TSEDGE and Enable bits */
+ /* Copy the desired configuration into the CR register */
hrtc->Instance->CR = (uint32_t)tmpreg;
+ /* Clear RTC Timestamp flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
+
+ /* Clear RTC Timestamp overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Enable the Timestamp saving */
__HAL_RTC_TIMESTAMP_ENABLE(hrtc);
- /* Enable IT timestamp */
+ /* Enable IT Timestamp */
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
- /* RTC timestamp Interrupt Configuration: EXTI configuration */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
-
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* RTC Timestamp Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
+
+ /* Change RTC state back to READY */
hrtc->State = HAL_RTC_STATE_READY;
/* Process Unlocked */
@@ -230,8 +279,9 @@
}
/**
- * @brief Deactivate TimeStamp.
- * @param hrtc RTC handle
+ * @brief Deactivates Timestamp.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
@@ -252,7 +302,7 @@
/* Get the RTC_CR register and clear the bits to be configured */
tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
- /* Configure the Time Stamp TSEDGE and Enable bits */
+ /* Configure the Timestamp TSEDGE and Enable bits */
hrtc->Instance->CR = (uint32_t)tmpreg;
/* Enable the write protection for RTC registers */
@@ -267,8 +317,9 @@
}
/**
- * @brief Get the RTC TimeStamp value.
- * @param hrtc RTC handle
+ * @brief Gets the RTC Timestamp value.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTimeStamp Pointer to Time structure
* @param sTimeStampDate Pointer to Date structure
* @param Format specifies the format of the entered parameters.
@@ -279,52 +330,54 @@
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
{
- uint32_t tmptime = 0U, tmpdate = 0U;
+ uint32_t tmptime = 0U;
+ uint32_t tmpdate = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
- /* Get the TimeStamp time and date registers values */
+ /* Get the Timestamp time and date registers values */
tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
/* Fill the Time structure fields with the read parameters */
- sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
- sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
- sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos);
+ sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos);
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos);
sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
/* Fill the Date structure fields with the read parameters */
- sTimeStampDate->Year = 0U;
- sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
- sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos);
+ sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos);
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos);
/* Check the input parameters format */
if (Format == RTC_FORMAT_BIN)
{
- /* Convert the TimeStamp structure parameters to Binary format */
- sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
+ /* Convert the Timestamp structure parameters to Binary format */
+ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
/* Convert the DateTimeStamp structure parameters to Binary format */
- sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
- sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
+ sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
+ sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
}
- /* Clear the TIMESTAMP Flag */
+ /* Clear the Timestamp Flag */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
return HAL_OK;
}
/**
- * @brief Set Tamper
- * @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc RTC handle
+ * @brief Sets Tamper.
+ * @note By calling this API the tamper global interrupt will be disabled.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper Pointer to Tamper Structure.
* @retval HAL status
*/
@@ -336,6 +389,7 @@
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
@@ -346,20 +400,44 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ /* Copy control register into temporary variable */
+ tmpreg = hrtc->Instance->TAFCR;
+
+ /* Enable selected tamper */
+ tmpreg |= (sTamper->Tamper);
+
+ /* Configure the tamper trigger bit (this bit is just on the right of the
+ tamper enable bit, hence the one-time right shift before updating it) */
+ if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)
{
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
+ /* Set the tamper trigger bit (case of falling edge or high level) */
+ tmpreg |= (uint32_t)(sTamper->Tamper << 1U);
+ }
+ else
+ {
+ /* Clear the tamper trigger bit (case of rising edge or low level) */
+ tmpreg &= (uint32_t)~(sTamper->Tamper << 1U);
}
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
- (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+ /* Clear remaining fields before setting them */
+ tmpreg &= ~(RTC_TAMPERFILTER_MASK | \
+ RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \
+ RTC_TAMPERPRECHARGEDURATION_MASK | \
+ RTC_TAMPER_PULLUP_MASK | \
+ RTC_TIMESTAMPONTAMPERDETECTION_MASK);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS | \
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
- (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
+ /* Set remaining parameters of desired configuration into temporary variable */
+ tmpreg |= ((uint32_t)sTamper->Filter | \
+ (uint32_t)sTamper->SamplingFrequency | \
+ (uint32_t)sTamper->PrechargeDuration | \
+ (uint32_t)sTamper->TamperPullUp | \
+ (uint32_t)sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR |= tmpreg;
+ /* Disable tamper global interrupt in case it is enabled */
+ tmpreg &= (uint32_t)~RTC_TAFCR_TAMPIE;
+
+ /* Copy desired configuration into configuration register */
+ hrtc->Instance->TAFCR = tmpreg;
hrtc->State = HAL_RTC_STATE_READY;
@@ -370,9 +448,10 @@
}
/**
- * @brief Set Tamper with interrupt.
- * @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc RTC handle
+ * @brief Sets Tamper with interrupt.
+ * @note By calling this API the tamper global interrupt will be enabled.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param sTamper Pointer to RTC Tamper.
* @retval HAL status
*/
@@ -384,6 +463,7 @@
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));
+ assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger));
assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
@@ -394,28 +474,47 @@
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Configure the tamper trigger */
- if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
+ /* Copy control register into temporary variable */
+ tmpreg = hrtc->Instance->TAFCR;
+
+ /* Enable selected tamper */
+ tmpreg |= (sTamper->Tamper);
+
+ /* Configure the tamper trigger bit (this bit is just on the right of the
+ tamper enable bit, hence the one-time right shift before updating it) */
+ if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)
{
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
+ /* Set the tamper trigger bit (case of falling edge or high level) */
+ tmpreg |= (uint32_t)(sTamper->Tamper << 1U);
+ }
+ else
+ {
+ /* Clear the tamper trigger bit (case of rising edge or low level) */
+ tmpreg &= (uint32_t)~(sTamper->Tamper << 1U);
}
- tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \
- (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
- (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
+ /* Clear remaining fields before setting them */
+ tmpreg &= ~(RTC_TAMPERFILTER_MASK | \
+ RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \
+ RTC_TAMPERPRECHARGEDURATION_MASK | \
+ RTC_TAMPER_PULLUP_MASK | \
+ RTC_TIMESTAMPONTAMPERDETECTION_MASK);
- hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS | \
- (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \
- (uint32_t)RTC_TAFCR_TAMPPUDIS);
+ /* Set remaining parameters of desired configuration into temporary variable */
+ tmpreg |= ((uint32_t)sTamper->Filter | \
+ (uint32_t)sTamper->SamplingFrequency | \
+ (uint32_t)sTamper->PrechargeDuration | \
+ (uint32_t)sTamper->TamperPullUp | \
+ (uint32_t)sTamper->TimeStampOnTamperDetection);
- hrtc->Instance->TAFCR |= tmpreg;
+ /* Enable global tamper interrupt */
+ tmpreg |= (uint32_t)RTC_TAFCR_TAMPIE;
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
+ /* Copy desired configuration into configuration register */
+ hrtc->Instance->TAFCR = tmpreg;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
hrtc->State = HAL_RTC_STATE_READY;
@@ -427,11 +526,16 @@
}
/**
- * @brief Deactivate Tamper.
- * @param hrtc RTC handle
+ * @brief Deactivates Tamper.
+ * @note The tamper global interrupt bit will remain unchanged.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Tamper Selected tamper pin.
- * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 (*)
- * @note (*) RTC_TAMPER_3 not present on all the devices
+ * This parameter can be any combination of the following values:
+ * @arg RTC_TAMPER_1: Tamper 1
+ * @arg RTC_TAMPER_2: Tamper 2
+ * @arg RTC_TAMPER_3: Tamper 3
+ * @note RTC_TAMPER_3 is not applicable to all devices.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
@@ -455,96 +559,99 @@
}
/**
- * @brief Handle TimeStamp interrupt request.
- * @param hrtc RTC handle
+ * @brief Handles Timestamp and Tamper interrupt request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Get the TimeStamp interrupt source enable status */
- if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != RESET)
+ /* Clear the EXTI's Flag for RTC Timestamp and Tamper */
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
+
+ /* Get the Timestamp interrupt source enable status */
+ if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U)
{
- /* Get the pending status of the TIMESTAMP Interrupt */
- if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != RESET)
+ /* Get the pending status of the Timestamp Interrupt */
+ if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U)
{
- /* TIMESTAMP callback */
+ /* Timestamp callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->TimeStampEventCallback(hrtc);
#else
HAL_RTCEx_TimeStampEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
- /* Clear the TIMESTAMP interrupt pending bit */
+ /* Clear the Timestamp interrupt pending bit after returning from callback
+ as RTC_TSTR and RTC_TSDR registers are cleared when TSF bit is reset */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
}
}
- /* Get the Tamper interrupts source enable status */
- if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ /* Get the Tamper 1 interrupt source enable status */
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U)
{
- /* Get the pending status of the Tamper1 Interrupt */
- if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != RESET)
+ /* Get the pending status of the Tamper 1 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
{
- /* Tamper1 callback */
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
+
+ /* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper1EventCallback(hrtc);
#else
HAL_RTCEx_Tamper1EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the Tamper1 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
}
}
- /* Get the Tamper interrupts source enable status */
- if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ /* Get the Tamper 2 interrupt source enable status */
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U)
{
- /* Get the pending status of the Tamper2 Interrupt */
- if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != RESET)
+ /* Get the pending status of the Tamper 2 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
{
- /* Tamper2 callback */
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
+
+ /* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper2EventCallback(hrtc);
#else
HAL_RTCEx_Tamper2EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the Tamper2 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
}
}
#if defined(RTC_TAMPER3_SUPPORT)
- /* Get the Tamper interrupts source enable status */
- if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP))
+ /* Get the Tamper 3 interrupt source enable status */
+ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U)
{
- /* Get the pending status of the Tamper3 Interrupt */
- if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != RESET)
+ /* Get the pending status of the Tamper 3 Interrupt */
+ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U)
{
- /* Tamper3 callback */
+ /* Clear the Tamper interrupt pending bit */
+ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
+
+ /* Tamper callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->Tamper3EventCallback(hrtc);
#else
HAL_RTCEx_Tamper3EventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the Tamper3 interrupt pending bit */
- __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
}
}
#endif /* RTC_TAMPER3_SUPPORT */
- /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
-
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
- * @brief TimeStamp callback.
- * @param hrtc RTC handle
+ * @brief Timestamp callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
@@ -552,14 +659,15 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
*/
}
/**
* @brief Tamper 1 callback.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
@@ -567,14 +675,15 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
*/
}
/**
* @brief Tamper 2 callback.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
@@ -582,15 +691,16 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
*/
}
#if defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Tamper 3 callback.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
@@ -598,35 +708,28 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
*/
}
#endif /* RTC_TAMPER3_SUPPORT */
/**
- * @brief Handle TimeStamp polling request.
- * @param hrtc RTC handle
+ * @brief Handles Timestamp polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
- while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U)
{
- if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
- {
- /* Clear the TIMESTAMP OverRun Flag */
- __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
- /* Change TIMESTAMP state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- return HAL_ERROR;
- }
-
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
@@ -635,6 +738,17 @@
return HAL_TIMEOUT;
}
}
+
+ if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U)
+ {
+ /* Clear the Timestamp Overrun Flag */
+ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
+
+ /* Change Timestamp state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
}
/* Change RTC state */
@@ -644,17 +758,21 @@
}
/**
- * @brief Handle Tamper 1 Polling.
- * @param hrtc RTC handle
+ * @brief Handles Tamper 1 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
@@ -676,17 +794,21 @@
}
/**
- * @brief Handle Tamper 2 Polling.
- * @param hrtc RTC handle
+ * @brief Handles Tamper 2 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
@@ -709,8 +831,9 @@
#if defined(RTC_TAMPER3_SUPPORT)
/**
- * @brief Handle Tamper 3 Polling.
- * @param hrtc RTC handle
+ * @brief Handles Tamper 3 Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
@@ -719,7 +842,7 @@
uint32_t tickstart = HAL_GetTick();
/* Get the status of the Interrupt */
- while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == RESET)
+ while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
@@ -745,25 +868,26 @@
* @}
*/
-/** @addtogroup RTCEx_Exported_Functions_Group2
- * @brief RTC Wake-up functions
+/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wakeup functions
+ * @brief RTC Wakeup functions
*
@verbatim
===============================================================================
- ##### RTC Wake-up functions #####
+ ##### RTC Wakeup functions #####
===============================================================================
- [..] This section provides functions allowing to configure Wake-up feature
+ [..] This section provides functions allowing to configure Wakeup feature
@endverbatim
* @{
*/
/**
- * @brief Set wake up timer.
- * @param hrtc RTC handle
- * @param WakeUpCounter Wake up counter
- * @param WakeUpClock Wake up clock
+ * @brief Sets wakeup timer.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter Wakeup counter
+ * @param WakeUpClock Wakeup clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -782,13 +906,13 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ /* Check RTC WUTWF flag is reset only when wakeup timer enabled*/
+ if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
{
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -805,12 +929,17 @@
}
}
+ /* Disable the Wakeup timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
+ /* Clear the Wakeup flag */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ /* Wait till RTC WUTWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -850,15 +979,16 @@
}
/**
- * @brief Set wake up timer with interrupt.
- * @param hrtc RTC handle
- * @param WakeUpCounter Wake up counter
- * @param WakeUpClock Wake up clock
+ * @brief Sets wakeup timer with interrupt.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param WakeUpCounter Wakeup counter
+ * @param WakeUpClock Wakeup clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
- uint32_t tickstart = 0U;
+ __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
@@ -872,15 +1002,14 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /*Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if ((hrtc->Instance->CR & RTC_CR_WUTE) != RESET)
+ /* Check RTC WUTWF flag is reset only when wakeup timer enabled */
+ if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U)
{
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET)
+ /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */
+ do
{
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ count = count - 1U;
+ if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -892,21 +1021,23 @@
return HAL_TIMEOUT;
}
- }
+ } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U);
}
- /* Disable the Wake-Up timer */
+ /* Disable the Wakeup timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
- /* Clear flag Wake-Up */
+ /* Clear the Wakeup flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
- tickstart = HAL_GetTick();
+ /* Reload the counter */
+ count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U);
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+ /* Wait till RTC WUTWF flag is set and if timeout is reached exit */
+ do
{
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+ count = count - 1U;
+ if (count == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -918,10 +1049,7 @@
return HAL_TIMEOUT;
}
- }
-
- /* Configure the Wakeup Timer counter */
- hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+ } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U);
/* Clear the Wakeup Timer clock source bits in CR register */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
@@ -929,12 +1057,14 @@
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
- /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+ /* Configure the Wakeup Timer counter */
+ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
+ /* RTC wakeup timer Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
- /* Configure the Interrupt in the RTC_CR register */
+ /* Configure the interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT);
/* Enable the Wakeup Timer */
@@ -952,11 +1082,12 @@
}
/**
- * @brief Deactivate wake up timer counter.
- * @param hrtc RTC handle
+ * @brief Deactivates wakeup timer counter.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart = 0U;
@@ -974,9 +1105,11 @@
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
+
+ /* Wait till RTC WUTWF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -1004,8 +1137,9 @@
}
/**
- * @brief Get wake up timer counter.
- * @param hrtc RTC handle
+ * @brief Gets wakeup timer counter.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval Counter value
*/
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
@@ -1015,36 +1149,43 @@
}
/**
- * @brief Handle Wake Up Timer interrupt request.
- * @param hrtc RTC handle
+ * @brief Handles Wakeup Timer interrupt request.
+ * @note Unlike alarm interrupt line (shared by Alarms A and B) or tamper
+ * interrupt line (shared by timestamp and tampers) wakeup timer
+ * interrupt line is exclusive to the wakeup timer.
+ * There is no need in this case to check on the interrupt enable
+ * status via __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE().
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
- /* Get the pending status of the WAKEUPTIMER Interrupt */
- if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != RESET)
+ /* Clear the EXTI's line Flag for RTC WakeUpTimer */
+ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
+
+ /* Get the pending status of the Wakeup timer Interrupt */
+ if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
{
- /* WAKEUPTIMER callback */
+ /* Clear the Wakeup timer interrupt pending bit */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Wakeup timer callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- hrtc->WakeUpTimerEventCallback(hrtc);
+ hrtc->WakeUpTimerEventCallback(hrtc);
#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
- /* Clear the WAKEUPTIMER interrupt pending bit */
- __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
}
- /* Clear the EXTI's line Flag for RTC WakeUpTimer */
- __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
-
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;
}
/**
- * @brief Wake Up Timer callback.
- * @param hrtc RTC handle
+ * @brief Wakeup Timer callback.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1052,35 +1193,38 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
*/
}
/**
- * @brief Handle Wake Up Timer Polling.
- * @param hrtc RTC handle
+ * @brief Handles Wakeup Timer Polling.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
- while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
return HAL_TIMEOUT;
}
}
}
- /* Clear the WAKEUPTIMER Flag */
+ /* Clear the Wakeup timer Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
/* Change RTC state */
@@ -1093,8 +1237,7 @@
* @}
*/
-
-/** @addtogroup RTCEx_Exported_Functions_Group3
+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @brief Extended Peripheral Control functions
*
@verbatim
@@ -1105,8 +1248,6 @@
This subsection provides functions allowing to
(+) Write a data in a specified RTC Backup data register
(+) Read a data in a specified RTC Backup data register
- (+) Set the Coarse calibration parameters.
- (+) Deactivate the Coarse calibration parameters
(+) Set the Smooth calibration parameters.
(+) Configure the Synchronization Shift Control Settings.
(+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
@@ -1121,11 +1262,15 @@
*/
/**
- * @brief Write a data in a specified RTC Backup data register.
- * @param hrtc RTC handle
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
+ * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 15)
+ * to specify the register.
+ * @note The range of values possible for parameter BackupRegister depends on
+ * the total number of Backup data Registers. This total number is not
+ * the same on all devices.
* @param Data Data to be written in the specified RTC Backup data register.
* @retval None
*/
@@ -1145,10 +1290,14 @@
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param BackupRegister RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
+ * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 15)
+ * to specify the register.
+ * @note The range of values possible for parameter BackupRegister depends on
+ * the total number of Backup data Registers. This total number is not
+ * the same on all devices.
* @retval Read value
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
@@ -1166,10 +1315,11 @@
}
/**
- * @brief Set the Smooth calibration parameters.
- * @param hrtc RTC handle
+ * @brief Sets the Smooth calibration parameters.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param SmoothCalibPeriod Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values :
+ * This parameter can be can be one of the following values:
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
@@ -1181,7 +1331,7 @@
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
- * SmoothCalibMinusPulsesValue mut be equal to 0.
+ * SmoothCalibMinusPulsesValue must be equal to 0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue)
@@ -1202,12 +1352,13 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* check if a calibration is pending*/
- if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
{
+ /* Get tick */
tickstart = HAL_GetTick();
/* check if a calibration is pending*/
- while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
+ while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -1226,7 +1377,9 @@
}
/* Configure the Smooth calibration settings */
- hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | \
+ (uint32_t)SmoothCalibPlusPulses | \
+ (uint32_t)SmoothCalibMinusPulsesValue);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1241,11 +1394,12 @@
}
/**
- * @brief Configure the Synchronization Shift Control Settings.
+ * @brief Configures the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc RTC handle
- * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
- * This parameter can be one of the following values :
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param ShiftAdd1S Select to add or not 1 second to the time calendar.
+ * This parameter can be one of the following values:
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
* @arg RTC_SHIFTADD1S_RESET: No effect.
* @param ShiftSubFS Select the number of Second Fractions to substitute.
@@ -1268,10 +1422,11 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+ /* Get tick */
tickstart = HAL_GetTick();
- /* Wait until the shift is completed*/
- while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
+ /* Wait until the shift is completed */
+ while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -1288,13 +1443,13 @@
}
/* Check if the reference clock detection is disabled */
- if ((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
+ if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U)
{
/* Configure the Shift settings */
hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
- /* If RTC_CR_BYPSHAD bit = 0U, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
{
if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
{
@@ -1337,9 +1492,10 @@
}
/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc RTC handle
- * @param CalibOutput Select the Calibration output Selection .
+ * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
+ * @param CalibOutput Select the Calibration output Selection.
* This parameter can be one of the following values:
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
@@ -1379,8 +1535,9 @@
}
/**
- * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc RTC handle
+ * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc)
@@ -1408,12 +1565,15 @@
}
/**
- * @brief Enable the RTC reference clock detection.
- * @param hrtc RTC handle
+ * @brief Enables the RTC reference clock detection.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
{
+ HAL_StatusTypeDef status;
+
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1422,47 +1582,42 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+
+ if (status == HAL_OK)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
+ /* Enable the reference clock detection */
__HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
{
+ HAL_StatusTypeDef status;
+
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1471,43 +1626,36 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+
+ if (status == HAL_OK)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
- {
+ /* Disable the reference clock detection */
__HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
/* Exit Initialization mode */
- hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
/**
- * @brief Enable the Bypass Shadow feature.
- * @param hrtc RTC handle
+ * @brief Enables the Bypass Shadow feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1538,8 +1686,9 @@
}
/**
- * @brief Disable the Bypass Shadow feature.
- * @param hrtc RTC handle
+ * @brief Disables the Bypass Shadow feature.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
* @retval HAL status
@@ -1555,7 +1704,7 @@
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Reset the BYPSHAD bit */
- hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD);
+ hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1573,7 +1722,7 @@
* @}
*/
-/** @addtogroup RTCEx_Exported_Functions_Group4 Extended features functions
+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
* @brief Extended features functions
*
@verbatim
@@ -1581,7 +1730,7 @@
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) RTC Alram B callback
+ (+) RTC Alarm B callback
(+) RTC Poll for Alarm B request
@endverbatim
@@ -1590,7 +1739,8 @@
/**
* @brief Alarm B callback.
- * @param hrtc RTC handle
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @retval None
*/
__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
@@ -1598,22 +1748,27 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hrtc);
- /* NOTE : This function should not be modified, when the callback is needed,
- the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
*/
}
/**
- * @brief This function handles AlarmB Polling request.
- * @param hrtc RTC handle
+ * @brief Handles Alarm B Polling request.
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
+ * the configuration information for RTC.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = HAL_GetTick();
+ uint32_t tickstart = 0U;
- while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait till RTC ALRBF flag is set and if timeout is reached exit */
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U)
{
if (Timeout != HAL_MAX_DELAY)
{
@@ -1625,7 +1780,7 @@
}
}
- /* Clear the Alarm Flag */
+ /* Clear the Alarm flag */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
/* Change RTC state */
diff --git a/Src/stm32f3xx_hal_sdadc.c b/Src/stm32f3xx_hal_sdadc.c
index c5b8d8d..24b912f 100644
--- a/Src/stm32f3xx_hal_sdadc.c
+++ b/Src/stm32f3xx_hal_sdadc.c
@@ -11,7 +11,6 @@
* + Power saving
* + Regular/Injected Channels DMA Configuration
* + Interrupts and flags management
- *
******************************************************************************
* @attention
*
@@ -234,9 +233,8 @@
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
- @endverbatim
- ******************************************************************************
- */
+ @endverbatim
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal.h"
@@ -2355,9 +2353,10 @@
void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc)
{
uint32_t tmp_isr = hsdadc->Instance->ISR;
+ uint32_t tmp_cr1 = hsdadc->Instance->CR1;
/* Check if end of regular conversion */
- if(((hsdadc->Instance->CR1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE) &&
+ if(((tmp_cr1 & SDADC_CR1_REOCIE) == SDADC_CR1_REOCIE) &&
((tmp_isr & SDADC_ISR_REOCF) == SDADC_ISR_REOCF))
{
/* Call regular conversion complete callback */
@@ -2380,7 +2379,7 @@
}
}
/* Check if end of injected conversion */
- else if(((hsdadc->Instance->CR1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE) &&
+ else if(((tmp_cr1 & SDADC_CR1_JEOCIE) == SDADC_CR1_JEOCIE) &&
((tmp_isr & SDADC_ISR_JEOCF) == SDADC_ISR_JEOCF))
{
/* Call injected conversion complete callback */
@@ -2412,7 +2411,7 @@
}
}
/* Check if end of calibration */
- else if(((hsdadc->Instance->CR1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE) &&
+ else if(((tmp_cr1 & SDADC_CR1_EOCALIE) == SDADC_CR1_EOCALIE) &&
((tmp_isr & SDADC_ISR_EOCALF) == SDADC_ISR_EOCALF))
{
/* Clear EOCALIE bit in SDADC_CR1 register */
@@ -2432,7 +2431,7 @@
hsdadc->State = HAL_SDADC_STATE_READY;
}
/* Check if overrun occurs during regular conversion */
- else if(((hsdadc->Instance->CR1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE) &&
+ else if(((tmp_cr1 & SDADC_CR1_ROVRIE) == SDADC_CR1_ROVRIE) &&
((tmp_isr & SDADC_ISR_ROVRF) == SDADC_ISR_ROVRF))
{
/* Set CLRROVRF bit in SDADC_CLRISR register */
@@ -2449,7 +2448,7 @@
#endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
}
/* Check if overrun occurs during injected conversion */
- else if(((hsdadc->Instance->CR1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE) &&
+ else if(((tmp_cr1 & SDADC_CR1_JOVRIE) == SDADC_CR1_JOVRIE) &&
((tmp_isr & SDADC_ISR_JOVRF) == SDADC_ISR_JOVRF))
{
/* Set CLRJOVRF bit in SDADC_CLRISR register */
@@ -2782,7 +2781,7 @@
/* Set RSWSTART bit in SDADC_CR2 register */
hsdadc->Instance->CR2 |= SDADC_CR2_RSWSTART;
}
- else /* synchronuous trigger */
+ else /* synchronous trigger */
{
/* Enter init mode */
if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
@@ -2841,7 +2840,7 @@
return HAL_TIMEOUT;
}
}
- /* Check if trigger is synchronuous */
+ /* Check if trigger is synchronous */
if(hsdadc->RegularTrigger == SDADC_SYNCHRONOUS_TRIGGER)
{
/* Enter init mode */
@@ -2899,7 +2898,7 @@
/* Set JSWSTART bit in SDADC_CR2 register */
hsdadc->Instance->CR2 |= SDADC_CR2_JSWSTART;
}
- else /* external or synchronuous trigger */
+ else /* external or synchronous trigger */
{
/* Enter init mode */
if(SDADC_EnterInitMode(hsdadc) != HAL_OK)
@@ -2977,7 +2976,7 @@
}
else
{
- /* Check if trigger is synchronuous */
+ /* Check if trigger is synchronous */
if(hsdadc->InjectedTrigger == SDADC_SYNCHRONOUS_TRIGGER)
{
/* Clear JSYNC bit in SDADC_CR1 register */
diff --git a/Src/stm32f3xx_hal_smartcard.c b/Src/stm32f3xx_hal_smartcard.c
index 08aa17d..a2baef9 100644
--- a/Src/stm32f3xx_hal_smartcard.c
+++ b/Src/stm32f3xx_hal_smartcard.c
@@ -198,7 +198,7 @@
#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */
#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+ USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
@@ -461,6 +461,9 @@
/**
* @brief Register a User SMARTCARD Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -488,8 +491,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmartcard);
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
@@ -568,15 +569,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
/**
* @brief Unregister an SMARTCARD callback
* SMARTCARD callback is redirected to the weak predefined callback
+ * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -595,9 +596,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmartcard);
-
if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
{
switch (CallbackID)
@@ -676,9 +674,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -2934,3 +2929,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_smartcard_ex.c b/Src/stm32f3xx_hal_smartcard_ex.c
index 5fa0dcb..1c29305 100644
--- a/Src/stm32f3xx_hal_smartcard_ex.c
+++ b/Src/stm32f3xx_hal_smartcard_ex.c
@@ -29,7 +29,6 @@
(#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
auto-retry counter,...) in the hsmartcard AdvancedInit structure.
-
@endverbatim
******************************************************************************
*/
@@ -195,3 +194,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_smbus.c b/Src/stm32f3xx_hal_smbus.c
index f0531dc..78f8d27 100644
--- a/Src/stm32f3xx_hal_smbus.c
+++ b/Src/stm32f3xx_hal_smbus.c
@@ -167,7 +167,6 @@
(@) You can refer to the SMBUS HAL driver header file for more useful macros
@endverbatim
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -585,6 +584,9 @@
/**
* @brief Register a User SMBUS Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be registered
@@ -614,9 +616,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -692,14 +691,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
/**
* @brief Unregister an SMBUS Callback
* SMBUS callback is redirected to the weak predefined callback
+ * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
+ * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+ * HAL_SMBUS_MSPDEINIT_CB_ID
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
* @param CallbackID ID of the callback to be unregistered
@@ -720,9 +720,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
switch (CallbackID)
@@ -798,8 +795,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -823,8 +818,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmbus);
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
@@ -839,8 +832,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -855,9 +846,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmbus);
-
if (HAL_SMBUS_STATE_READY == hsmbus->State)
{
hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */
@@ -871,8 +859,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmbus);
return status;
}
@@ -1827,7 +1813,7 @@
* the configuration information for the specified SMBUS.
* @retval HAL state
*/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus)
{
/* Return SMBUS handle state */
return hsmbus->State;
@@ -1839,7 +1825,7 @@
* the configuration information for the specified SMBUS.
* @retval SMBUS Error Code
*/
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus)
{
return hsmbus->ErrorCode;
}
diff --git a/Src/stm32f3xx_hal_spi.c b/Src/stm32f3xx_hal_spi.c
index da5189f..87442fe 100644
--- a/Src/stm32f3xx_hal_spi.c
+++ b/Src/stm32f3xx_hal_spi.c
@@ -9,7 +9,6 @@
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State functions
- *
******************************************************************************
* @attention
*
@@ -195,7 +194,6 @@
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -910,6 +908,7 @@
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -959,6 +958,7 @@
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -988,9 +988,12 @@
{
errorcode = HAL_ERROR;
}
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
error:
- hspi->State = HAL_SPI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hspi);
return errorcode;
@@ -1009,12 +1012,18 @@
{
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK;
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1028,12 +1037,6 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
@@ -1111,6 +1114,7 @@
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1134,6 +1138,7 @@
if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1228,9 +1233,12 @@
{
errorcode = HAL_ERROR;
}
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
error :
- hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1257,7 +1265,7 @@
__IO uint32_t tmpreg = 0U;
uint32_t spi_cr1;
uint32_t spi_cr2;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
@@ -1389,6 +1397,7 @@
if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1471,6 +1480,7 @@
if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
{
errorcode = HAL_TIMEOUT;
+ hspi->State = HAL_SPI_STATE_READY;
goto error;
}
}
@@ -1540,8 +1550,16 @@
hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
}
+ if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ }
+
error :
- hspi->State = HAL_SPI_STATE_READY;
__HAL_UNLOCK(hspi);
return errorcode;
}
@@ -1643,6 +1661,13 @@
{
HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -1653,12 +1678,6 @@
/* Process Locked */
__HAL_LOCK(hspi);
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
@@ -1947,7 +1966,6 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -1986,7 +2004,13 @@
/* Check rx dma handle */
assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
-
+
+ if (hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
hspi->State = HAL_SPI_STATE_BUSY_RX;
@@ -2001,12 +2025,6 @@
/* Process Locked */
__HAL_LOCK(hspi);
- if (hspi->State != HAL_SPI_STATE_READY)
- {
- errorcode = HAL_BUSY;
- goto error;
- }
-
if ((pData == NULL) || (Size == 0U))
{
errorcode = HAL_ERROR;
@@ -2101,7 +2119,6 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -2279,7 +2296,6 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -2301,7 +2317,6 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
errorcode = HAL_ERROR;
- hspi->State = HAL_SPI_STATE_READY;
goto error;
}
@@ -3093,7 +3108,7 @@
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
@@ -3210,7 +3225,7 @@
uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
#endif /* USE_SPI_CRC */
@@ -3587,7 +3602,7 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
@@ -3707,7 +3722,7 @@
/* Read 16bit CRC to flush Data Register */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
- UNUSED(tmpreg);
+ UNUSED(tmpreg);
/* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@@ -3762,7 +3777,7 @@
*/
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
@@ -3979,7 +3994,7 @@
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
- if(count == 0U)
+ if (count == 0U)
{
tmp_timeout = 0U;
}
@@ -4006,7 +4021,7 @@
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
- __IO uint8_t * ptmpreg8;
+ __IO uint8_t *ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Adjust Timeout value in case of end of transfer */
@@ -4061,10 +4076,10 @@
return HAL_TIMEOUT;
}
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
- if(count == 0U)
+ if (count == 0U)
{
tmp_timeout = 0U;
- }
+ }
count--;
}
}
@@ -4454,3 +4469,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_sram.c b/Src/stm32f3xx_hal_sram.c
index bdf2d70..5dab15c 100644
--- a/Src/stm32f3xx_hal_sram.c
+++ b/Src/stm32f3xx_hal_sram.c
@@ -133,9 +133,15 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SRAM_Private_Functions SRAM Private Functions
+ * @{
+ */
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
@@ -1018,7 +1024,7 @@
* the configuration information for SRAM module.
* @retval HAL state
*/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
{
return hsram->State;
}
@@ -1031,6 +1037,10 @@
* @}
*/
+/** @addtogroup SRAM_Private_Functions SRAM Private Functions
+ * @{
+ */
+
/**
* @brief DMA SRAM process complete callback.
* @param hdma : DMA handle
@@ -1101,6 +1111,10 @@
* @}
*/
+/**
+ * @}
+ */
+
#endif /* HAL_SRAM_MODULE_ENABLED */
/**
diff --git a/Src/stm32f3xx_hal_tim.c b/Src/stm32f3xx_hal_tim.c
index f05de37..95edbb3 100644
--- a/Src/stm32f3xx_hal_tim.c
+++ b/Src/stm32f3xx_hal_tim.c
@@ -29,7 +29,6 @@
* + Commutation Event configuration with Interruption and DMA
* + TIM OCRef clear configuration
* + TIM External Clock configuration
- *
******************************************************************************
* @attention
*
@@ -283,6 +282,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -544,7 +544,7 @@
}
else if (htim->State == HAL_TIM_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -666,6 +666,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -1073,7 +1074,7 @@
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1336,6 +1337,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -1743,7 +1745,7 @@
}
else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -2005,6 +2007,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -2398,7 +2401,7 @@
else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -2654,6 +2657,7 @@
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
@@ -3031,7 +3035,7 @@
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;
@@ -3057,6 +3061,7 @@
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
if (htim->State == HAL_TIM_STATE_RESET)
{
@@ -3566,7 +3571,7 @@
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData1 == NULL) && (Length > 0U))
+ if ((pData1 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -3591,7 +3596,7 @@
else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData2 == NULL) && (Length > 0U))
+ if ((pData2 == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -3620,7 +3625,7 @@
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+ if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -4559,8 +4564,8 @@
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR
* @arg TIM_DMABASE_CCMR3 (*)
- * @arg TIM_DMABASE_CCR5 (*)
- * @arg TIM_DMABASE_CCR6 (*)
+ * @arg TIM_DMABASE_CCR5 (*)
+ * @arg TIM_DMABASE_CCR6 (*)
* (*) value not defined in all devices
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
@@ -4580,13 +4585,11 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status;
- if (status == HAL_OK)
- {
- status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
- }
+ status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
return status;
@@ -4617,8 +4620,8 @@
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR
* @arg TIM_DMABASE_CCMR3 (*)
- * @arg TIM_DMABASE_CCR5 (*)
- * @arg TIM_DMABASE_CCR6 (*)
+ * @arg TIM_DMABASE_CCR5 (*)
+ * @arg TIM_DMABASE_CCR6 (*)
* (*) value not defined in all devices
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
@@ -4908,8 +4911,8 @@
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR
* @arg TIM_DMABASE_CCMR3 (*)
- * @arg TIM_DMABASE_CCR5 (*)
- * @arg TIM_DMABASE_CCR6 (*)
+ * @arg TIM_DMABASE_CCR5 (*)
+ * @arg TIM_DMABASE_CCR6 (*)
* (*) value not defined in all devices
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
@@ -4929,13 +4932,11 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
- HAL_StatusTypeDef status = HAL_OK;
+ HAL_StatusTypeDef status;
- if (status == HAL_OK)
- {
- status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
- ((BurstLength) >> 8U) + 1U);
- }
+ status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+
return status;
}
@@ -4965,8 +4966,8 @@
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_OR
* @arg TIM_DMABASE_CCMR3 (*)
- * @arg TIM_DMABASE_CCR5 (*)
- * @arg TIM_DMABASE_CCR6 (*)
+ * @arg TIM_DMABASE_CCR5 (*)
+ * @arg TIM_DMABASE_CCR6 (*)
* (*) value not defined in all devices
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
@@ -5324,8 +5325,8 @@
{
/* Clear the OCREF clear selection bit */
CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
+ break;
}
- break;
#endif /* TIM_SMCR_OCCS */
case TIM_CLEARINPUTSOURCE_ETR:
@@ -6017,8 +6018,6 @@
{
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(htim);
if (htim->State == HAL_TIM_STATE_READY)
{
@@ -6216,9 +6215,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
@@ -6264,9 +6260,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(htim);
-
if (htim->State == HAL_TIM_STATE_READY)
{
switch (CallbackID)
@@ -6505,9 +6498,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
diff --git a/Src/stm32f3xx_hal_tim_ex.c b/Src/stm32f3xx_hal_tim_ex.c
index fa1ff9d..8394b57 100644
--- a/Src/stm32f3xx_hal_tim_ex.c
+++ b/Src/stm32f3xx_hal_tim_ex.c
@@ -12,7 +12,6 @@
* + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
* + Time OCRef clear configuration
* + Timer remapping capabilities configuration
- *
******************************************************************************
* @attention
*
@@ -154,6 +153,7 @@
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+ assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -504,7 +504,7 @@
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -885,7 +885,7 @@
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -1367,7 +1367,7 @@
}
else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
{
- if ((pData == NULL) && (Length > 0U))
+ if ((pData == NULL) || (Length == 0U))
{
return HAL_ERROR;
}
@@ -2190,7 +2190,7 @@
/* Check parameters */
assert_param(IS_TIM_REMAP(htim->Instance, Remap));
-
+
__HAL_LOCK(htim);
/* Set the Timer remapping configuration */
@@ -2378,7 +2378,7 @@
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
diff --git a/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c b/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
index e39a62a..3537aaa 100644
--- a/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32f3xx_hal_timebase_rtc_alarm_template.c
@@ -5,10 +5,10 @@
*
* This file override the native HAL time base functions (defined as weak)
* to use the RTC ALARM for time base generation:
- * + Intializes the RTC peripheral to increment the seconds registers each 1ms
+ * + Initializes the RTC peripheral to increment the seconds registers each 1ms
* + The alarm is configured to assert an interrupt when the RTC reaches 1ms
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
- * + HSE (default), LSE or LSI can be selected as RTC clock source
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
*
******************************************************************************
* @attention
@@ -317,3 +317,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
index b6b947f..ccdbc3f 100644
--- a/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32f3xx_hal_timebase_rtc_wakeup_template.c
@@ -5,7 +5,7 @@
*
* This file overrides the native HAL time base functions (defined as weak)
* to use the RTC WAKEUP for the time base generation:
- * + Intializes the RTC peripheral and configures the wakeup timer to be
+ * + Initializes the RTC peripheral and configures the wakeup timer to be
* incremented each 1ms
* + The wakeup feature is configured to assert an interrupt each 1ms
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
@@ -294,3 +294,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f3xx_hal_timebase_tim_template.c b/Src/stm32f3xx_hal_timebase_tim_template.c
index e019302..04aed21 100644
--- a/Src/stm32f3xx_hal_timebase_tim_template.c
+++ b/Src/stm32f3xx_hal_timebase_tim_template.c
@@ -5,7 +5,7 @@
*
* This file override the native HAL time base functions (defined as weak)
* the TIM time base:
- * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
+ * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
******************************************************************************
@@ -174,3 +174,5 @@
/**
* @}
*/
+
+
diff --git a/Src/stm32f3xx_hal_tsc.c b/Src/stm32f3xx_hal_tsc.c
index 7c5c437..6f400ad 100644
--- a/Src/stm32f3xx_hal_tsc.c
+++ b/Src/stm32f3xx_hal_tsc.c
@@ -191,7 +191,7 @@
| PB8 (AF) | TSC_SYNC |
| PB10 (AF) | |
+--------------------------------+
- ******************************************************************************
+
*/
/* Includes ------------------------------------------------------------------*/
@@ -821,7 +821,7 @@
* @param gx_index Index of the group
* @retval Group status
*/
-TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index)
+TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
@@ -838,7 +838,7 @@
* @param gx_index Index of the group
* @retval Acquisition measure
*/
-uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index)
+uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
@@ -873,7 +873,7 @@
* @param config Pointer to the configuration structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config)
+HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config)
{
/* Check the parameters */
assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance));
@@ -1122,3 +1122,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_uart.c b/Src/stm32f3xx_hal_uart.c
index 0a2c8a1..253bae8 100644
--- a/Src/stm32f3xx_hal_uart.c
+++ b/Src/stm32f3xx_hal_uart.c
@@ -9,6 +9,7 @@
* + IO operation functions
* + Peripheral Control functions
*
+ *
******************************************************************************
* @attention
*
@@ -176,7 +177,7 @@
USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE |\
- USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+ USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */
@@ -678,6 +679,9 @@
/**
* @brief Register a User UART Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -707,8 +711,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_READY)
{
switch (CallbackID)
@@ -791,14 +793,15 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
/**
* @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback
+ * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -819,8 +822,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- __HAL_LOCK(huart);
-
if (HAL_UART_STATE_READY == huart->gState)
{
switch (CallbackID)
@@ -904,8 +905,6 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -1257,7 +1256,7 @@
return HAL_ERROR;
}
- huart->pTxBuffPtr = (uint8_t *) pData;
+ huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
huart->TxISR = NULL;
@@ -1344,7 +1343,7 @@
return HAL_ERROR;
}
- huart->pTxBuffPtr = (uint8_t *) pData;
+ huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1481,7 +1480,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (huart->Init.Parity != UART_PARITY_NONE)
- {
+ {
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -1585,9 +1584,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1610,9 +1610,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1673,9 +1674,10 @@
/* Disable TXEIE and TCIE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1732,9 +1734,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1832,7 +1835,7 @@
}
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
@@ -1856,9 +1859,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -1938,9 +1942,10 @@
/* Disable interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
@@ -2029,9 +2034,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2208,9 +2214,10 @@
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
@@ -2978,7 +2985,7 @@
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
- huart->Instance->BRR = usartdiv;
+ huart->Instance->BRR = (uint16_t)usartdiv;
}
else
{
@@ -3239,7 +3246,7 @@
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
- {
+ {
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
@@ -3766,7 +3773,7 @@
*/
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
- uint16_t *tmp;
+ const uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
@@ -3781,7 +3788,7 @@
}
else
{
- tmp = (uint16_t *) huart->pTxBuffPtr;
+ tmp = (const uint16_t *) huart->pTxBuffPtr;
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
@@ -4005,3 +4012,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_uart_ex.c b/Src/stm32f3xx_hal_uart_ex.c
index ccd2379..0aa30fe 100644
--- a/Src/stm32f3xx_hal_uart_ex.c
+++ b/Src/stm32f3xx_hal_uart_ex.c
@@ -8,6 +8,7 @@
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
+ *
******************************************************************************
* @attention
*
@@ -726,7 +727,7 @@
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
{
/* Return Rx Event type value, as stored in UART handle */
- return(huart->RxEventType);
+ return (huart->RxEventType);
}
/**
@@ -771,3 +772,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_usart.c b/Src/stm32f3xx_hal_usart.c
index 12f5d7f..f762db4 100644
--- a/Src/stm32f3xx_hal_usart.c
+++ b/Src/stm32f3xx_hal_usart.c
@@ -405,6 +405,8 @@
/**
* @brief Register a User USART Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+ * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -432,8 +434,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(husart);
if (husart->State == HAL_USART_STATE_READY)
{
@@ -515,15 +515,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(husart);
-
return status;
}
/**
* @brief Unregister an USART Callback
* USART callaback is redirected to the weak predefined callback
+ * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+ * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -542,9 +541,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(husart);
-
if (HAL_USART_STATE_READY == husart->State)
{
switch (CallbackID)
@@ -625,9 +621,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(husart);
-
return status;
}
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -728,7 +721,8 @@
* @param Timeout Timeout duration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+ uint32_t Timeout)
{
const uint8_t *ptxdata8bits;
const uint16_t *ptxdata16bits;
@@ -1182,7 +1176,7 @@
/* Enable the USART Parity Error and Data Register not empty Interrupts */
if (husart->Init.Parity != USART_PARITY_NONE)
- {
+ {
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
@@ -1265,7 +1259,7 @@
/* Enable the USART Parity Error and USART Data Register not empty Interrupts */
if (husart->Init.Parity != USART_PARITY_NONE)
- {
+ {
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
}
else
@@ -1685,7 +1679,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (husart->Init.Parity != USART_PARITY_NONE)
- {
+ {
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
}
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1777,9 +1771,10 @@
CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the USART DMA Tx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
/* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1802,9 +1797,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1899,7 +1895,7 @@
}
}
- /* Disable the USART DMA Tx request if enabled */
+ /* Abort the USART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at USART level */
@@ -1923,9 +1919,10 @@
}
}
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
/* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2082,9 +2079,10 @@
Disable Interrupts, and disable DMA requests, if ongoing */
USART_EndTransfer(husart);
- /* Disable the USART DMA Rx request if enabled */
+ /* Abort the USART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the USART DMA Rx request if enabled */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
/* Abort the USART DMA Tx channel */
@@ -3134,3 +3132,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_usart_ex.c b/Src/stm32f3xx_hal_usart_ex.c
index e339275..44eadfe 100644
--- a/Src/stm32f3xx_hal_usart_ex.c
+++ b/Src/stm32f3xx_hal_usart_ex.c
@@ -7,6 +7,7 @@
* functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART).
* + Peripheral Control functions
*
+ *
******************************************************************************
* @attention
*
@@ -133,3 +134,4 @@
/**
* @}
*/
+
diff --git a/Src/stm32f3xx_hal_wwdg.c b/Src/stm32f3xx_hal_wwdg.c
index 7e41e37..288739f 100644
--- a/Src/stm32f3xx_hal_wwdg.c
+++ b/Src/stm32f3xx_hal_wwdg.c
@@ -7,7 +7,6 @@
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and Configuration functions
* + IO operation functions
- *
******************************************************************************
* @attention
*
@@ -52,7 +51,7 @@
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) at 36MHz (PCLK1) with zero prescaler:
- max timeout before reset: approximately 113.78µs
+ max timeout before reset: approximately 113.78us
(++) Counter max (T[5;0] = 0x3F) at 36MHz (PCLK1) with prescaler
dividing by 8:
max timeout before reset: approximately 58.25ms
@@ -67,7 +66,7 @@
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Configure the WWDG prescaler, refresh window value, counter value and early
interrupt status using HAL_WWDG_Init() function. This will automatically
- enable WWDG and start its downcounter. Time reference can be taken from
+ enable WWDG and start its downcounter. Time reference can be taken from
function exit. Care must be taken to provide a counter value
greater than 0x40 to prevent generation of immediate reset.
(+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
diff --git a/Src/stm32f3xx_ll_adc.c b/Src/stm32f3xx_ll_adc.c
index 49b6483..6d714e3 100644
--- a/Src/stm32f3xx_ll_adc.c
+++ b/Src/stm32f3xx_ll_adc.c
@@ -31,7 +31,7 @@
* @{
*/
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. b */
+/* Note: Devices of STM32F3 series embed 1 out of 2 different ADC IP. b */
/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
/* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
/* features (refer to reference manual). */
@@ -570,7 +570,7 @@
* the same ADC common instance to their default reset values.
* @note This function is performing a hard reset, using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* To de-initialize only 1 ADC instance, use
@@ -655,7 +655,7 @@
/* Note: Hardware constraint (refer to description of functions */
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
- /* On this STM32 serie, setting of these features is conditioned to */
+ /* On this STM32 series, setting of these features is conditioned to */
/* ADC state: */
/* All ADC instances of the ADC common group must be disabled. */
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
@@ -740,7 +740,7 @@
* is in an unknown state.
* In this case, perform a hard reset using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* Refer to function @ref LL_ADC_CommonDeInit().
@@ -974,10 +974,10 @@
/* ADC instance is in an unknown state */
/* Need to performing a hard reset of ADC instance, using high level */
/* clock source RCC ADC reset. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
status = ERROR;
@@ -1139,7 +1139,7 @@
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* - Set ADC group regular overrun behavior */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
@@ -1201,7 +1201,7 @@
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
@@ -1237,11 +1237,11 @@
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
- * @note Caution to ADC group injected contexts queue: On this STM32 serie,
+ * @note Caution to ADC group injected contexts queue: On this STM32 series,
* using successively several times this function will appear has
* having no effect.
* This is due to ADC group injected contexts queue (this feature
- * cannot be disabled on this STM32 serie).
+ * cannot be disabled on this STM32 series).
* To set several features of ADC group injected, use
* function @ref LL_ADC_INJ_ConfigQueueContext().
* @param ADCx ADC instance
@@ -1279,7 +1279,7 @@
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
@@ -1783,7 +1783,7 @@
/* - Set ADC group regular continuous mode */
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* Note: On this STM32 series, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
@@ -1844,7 +1844,7 @@
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* Note: On this STM32 series, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
@@ -1911,7 +1911,7 @@
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* Note: On this STM32 series, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
@@ -1995,3 +1995,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_comp.c b/Src/stm32f3xx_ll_comp.c
index 17cd06c..7e760ed 100644
--- a/Src/stm32f3xx_ll_comp.c
+++ b/Src/stm32f3xx_ll_comp.c
@@ -30,7 +30,7 @@
* @{
*/
-/* Note: Devices of STM32F3 serie embed 1 out of 2 different comparator IP. */
+/* Note: Devices of STM32F3 series embed 1 out of 2 different comparator IP. */
/* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
/* COMP IP from 3 to 7 instances and other specific features */
/* (comparator output blanking, ...) (refer to reference manual). */
@@ -71,7 +71,7 @@
((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED)
#endif
-/* Note: On this STM32 serie, comparator input plus parameters are */
+/* Note: On this STM32 series, comparator input plus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
@@ -765,7 +765,7 @@
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
)
-/* Note: On this STM32 serie, comparator input plus parameters are */
+/* Note: On this STM32 series, comparator input plus parameters are */
/* the different depending on COMP instances. */
#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
(((__COMP_INSTANCE__) == COMP1) \
@@ -779,7 +779,7 @@
) \
)
-/* Note: On this STM32 serie, comparator input minus parameters are */
+/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
@@ -1030,3 +1030,5 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/Src/stm32f3xx_ll_dac.c b/Src/stm32f3xx_ll_dac.c
index b556a2b..8132e4b 100644
--- a/Src/stm32f3xx_ll_dac.c
+++ b/Src/stm32f3xx_ll_dac.c
@@ -227,7 +227,7 @@
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
- * (1) On this STM32 serie, parameter not available on all devices.
+ * (1) On this STM32 series, parameter not available on all devices.
* Refer to device datasheet for channels availability.
* @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@@ -332,3 +332,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_dma.c b/Src/stm32f3xx_ll_dma.c
index 5cc1aa9..9da429e 100644
--- a/Src/stm32f3xx_ll_dma.c
+++ b/Src/stm32f3xx_ll_dma.c
@@ -9,8 +9,8 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@@ -331,3 +331,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_exti.c b/Src/stm32f3xx_ll_exti.c
index 4fd13b9..80b85e3 100644
--- a/Src/stm32f3xx_ll_exti.c
+++ b/Src/stm32f3xx_ll_exti.c
@@ -296,3 +296,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_fmc.c b/Src/stm32f3xx_ll_fmc.c
index f973cd8..092481a 100644
--- a/Src/stm32f3xx_ll_fmc.c
+++ b/Src/stm32f3xx_ll_fmc.c
@@ -10,6 +10,17 @@
* + Peripheral Control functions
* + Peripheral State functions
*
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
@verbatim
==============================================================================
##### FMC peripheral features #####
@@ -40,16 +51,6 @@
@endverbatim
******************************************************************************
- * @attention
- *
- * Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.
- *
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
- * If no LICENSE file comes with this software, it is provided AS-IS.
- *
- ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
diff --git a/Src/stm32f3xx_ll_i2c.c b/Src/stm32f3xx_ll_i2c.c
index 2bee221..8758191 100644
--- a/Src/stm32f3xx_ll_i2c.c
+++ b/Src/stm32f3xx_ll_i2c.c
@@ -83,7 +83,7 @@
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
@@ -135,7 +135,7 @@
* - SUCCESS: I2C registers are initialized
* - ERROR: Not applicable
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
diff --git a/Src/stm32f3xx_ll_opamp.c b/Src/stm32f3xx_ll_opamp.c
index 437a16c..364157c 100644
--- a/Src/stm32f3xx_ll_opamp.c
+++ b/Src/stm32f3xx_ll_opamp.c
@@ -233,3 +233,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_rcc.c b/Src/stm32f3xx_ll_rcc.c
index 275ffdf..7d43975 100644
--- a/Src/stm32f3xx_ll_rcc.c
+++ b/Src/stm32f3xx_ll_rcc.c
@@ -9,10 +9,9 @@
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
- * This software is licensed under terms that can be found in the LICENSE file
- * in the root directory of this software component.
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
- *
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
@@ -1127,3 +1126,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_rtc.c b/Src/stm32f3xx_ll_rtc.c
index 9968af4..2b7b31a 100644
--- a/Src/stm32f3xx_ll_rtc.c
+++ b/Src/stm32f3xx_ll_rtc.c
@@ -84,11 +84,11 @@
|| ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
-#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
+#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
-#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
+#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
@@ -104,14 +104,12 @@
|| ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
|| ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
-
#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
-
/**
* @}
*/
@@ -127,7 +125,7 @@
/**
* @brief De-Initializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * @note This function does not reset the RTC Clock source and RTC Backup Data
* registers.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
@@ -149,21 +147,17 @@
{
/* Reset TR, DR and CR registers */
LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
-#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
-#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+ LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
+
/* Reset All CR bits except CR[2:0] */
-#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
-#else
- LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
-#endif /* RTC_WAKEUP_SUPPORT */
- LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
+
+ LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U);
- LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
+ LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
@@ -367,7 +361,7 @@
if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
{
- RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+ RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
}
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
@@ -782,7 +776,7 @@
* synchronized with RTC APB clock.
* @note The RTC Resynchronization mode is write protected, use the
* @ref LL_RTC_DisableWriteProtection before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
+ * @note To read the calendar through the shadow registers after calendar
* initialization, calendar update or after wakeup from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
@@ -807,7 +801,7 @@
/* Wait the registers to be synchronised */
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- while ((timeout != 0U) && (tmp != 0U))
+ while ((timeout != 0U) && (tmp != 1U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
@@ -820,24 +814,6 @@
}
}
- if (status != ERROR)
- {
- timeout = RTC_SYNCHRO_TIMEOUT;
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- while ((timeout != 0U) && (tmp != 1U))
- {
- if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
- {
- timeout--;
- }
- tmp = LL_RTC_IsActiveFlag_RS(RTCx);
- if (timeout == 0U)
- {
- status = ERROR;
- }
- }
- }
-
return (status);
}
diff --git a/Src/stm32f3xx_ll_spi.c b/Src/stm32f3xx_ll_spi.c
index 3c533fb..2312771 100644
--- a/Src/stm32f3xx_ll_spi.c
+++ b/Src/stm32f3xx_ll_spi.c
@@ -637,3 +637,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_tim.c b/Src/stm32f3xx_ll_tim.c
index cdf6904..f85986f 100644
--- a/Src/stm32f3xx_ll_tim.c
+++ b/Src/stm32f3xx_ll_tim.c
@@ -54,7 +54,7 @@
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-#if defined(TIM_CCMR1_OC1M_3)
+#if defined(TIM_CCMR1_OC1M_3)
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
|| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
@@ -78,7 +78,7 @@
|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
|| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_PWM2))
-#endif
+#endif /* TIM_CCMR1_OC1M_3 */
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
@@ -232,7 +232,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: invalid TIMx instance
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
{
ErrorStatus result = SUCCESS;
@@ -1451,3 +1451,4 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
diff --git a/Src/stm32f3xx_ll_usart.c b/Src/stm32f3xx_ll_usart.c
index dad817e..69b01cc 100644
--- a/Src/stm32f3xx_ll_usart.c
+++ b/Src/stm32f3xx_ll_usart.c
@@ -31,7 +31,7 @@
* @{
*/
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5)
/** @addtogroup USART_LL
* @{
@@ -40,6 +40,17 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+ * @{
+ */
+
+/* Definition of default baudrate value used for USART initialisation */
+#define USART_DEFAULT_BAUDRATE (9600U)
+
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
@@ -196,7 +207,7 @@
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
#if (!defined(RCC_CFGR3_USART2SW)||!defined (RCC_CFGR3_USART3SW))
LL_RCC_ClocksTypeDef RCC_Clocks;
-#endif
+#endif /* USART clock selection flags */
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
@@ -254,7 +265,7 @@
/* USART2 clock is PCLK */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
+#endif /* USART2 Clock selector flag */
}
else if (USARTx == USART3)
{
@@ -264,7 +275,7 @@
/* USART3 clock is PCLK */
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
periphclk = RCC_Clocks.PCLK1_Frequency;
-#endif
+#endif /* USART3 Clock selector flag */
}
#if defined(UART4)
else if (USARTx == UART4)
@@ -315,7 +326,7 @@
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
{
/* Set USART_InitStruct fields to default values */
- USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE;
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
@@ -427,3 +438,5 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+
+
diff --git a/Src/stm32f3xx_ll_usb.c b/Src/stm32f3xx_ll_usb.c
index 9c02b66..930aece 100644
--- a/Src/stm32f3xx_ll_usb.c
+++ b/Src/stm32f3xx_ll_usb.c
@@ -11,18 +11,6 @@
* + Peripheral Control functions
* + Peripheral State functions
*
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
- (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
-
- (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
-
- @endverbatim
******************************************************************************
* @attention
*
@@ -34,6 +22,20 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
+
+ (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
+
+ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
+
+ @endverbatim
+
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -52,7 +54,6 @@
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
/**
* @brief Initializes the USB Core
* @param USBx USB Instance
@@ -241,10 +242,19 @@
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure VALID status for the Endpoint */
- PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ if (ep->num == 0U)
+ {
+ /* Configure VALID status for EP0 */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
+ }
+ else
+ {
+ /* Configure NAK status for OUT Endpoint */
+ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK);
+ }
}
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
/* Double Buffer */
else
{
@@ -291,6 +301,7 @@
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return ret;
}
@@ -309,18 +320,20 @@
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
+ /* Configure DISABLE status for the Endpoint */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
+
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
- /* Configure DISABLE status for the Endpoint*/
+ /* Configure DISABLE status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
- /*Double Buffer*/
+#if (USE_USB_DOUBLE_BUFFER == 1U)
+ /* Double Buffer */
else
{
if (ep->is_in == 0U)
@@ -347,6 +360,7 @@
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
return HAL_OK;
}
@@ -360,8 +374,10 @@
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
uint32_t len;
+#if (USE_USB_DOUBLE_BUFFER == 1U)
uint16_t pmabuffer;
uint16_t wEPVal;
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
/* IN endpoint */
if (ep->is_in == 1U)
@@ -382,6 +398,7 @@
USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len);
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* double buffer bulk management */
@@ -493,6 +510,7 @@
}
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
}
@@ -514,6 +532,7 @@
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
+#if (USE_USB_DOUBLE_BUFFER == 1U)
else
{
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
@@ -532,7 +551,7 @@
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
{
- PCD_FreeUserBuffer(USBx, ep->num, 0U);
+ PCD_FREE_USER_BUFFER(USBx, ep->num, 0U);
}
}
}
@@ -557,6 +576,7 @@
return HAL_ERROR;
}
}
+#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@@ -739,9 +759,9 @@
/**
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
- * @retval HAL status
+ * @retval USB Global Interrupt status
*/
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
{
uint32_t tmpreg;
@@ -785,25 +805,26 @@
{
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i, temp1, temp2;
+ uint32_t count;
+ uint16_t WrVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
- for (i = n; i != 0U; i--)
+ for (count = n; count != 0U; count--)
{
- temp1 = *pBuf;
- pBuf++;
- temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
- *pdwVal = (uint16_t)temp2;
+ WrVal = pBuf[0];
+ WrVal |= (uint16_t)pBuf[1] << 8;
+ *pdwVal = (WrVal & 0xFFFFU);
pdwVal++;
#if PMA_ACCESS > 1U
pdwVal++;
-#endif
+#endif /* PMA_ACCESS */
pBuf++;
+ pBuf++;
}
}
@@ -819,30 +840,31 @@
{
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
- uint32_t i, temp;
+ uint32_t count;
+ uint32_t RdVal;
__IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
- for (i = n; i != 0U; i--)
+ for (count = n; count != 0U; count--)
{
- temp = *(__IO uint16_t *)pdwVal;
+ RdVal = *(__IO uint16_t *)pdwVal;
pdwVal++;
- *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
pBuf++;
- *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
+ *pBuf = (uint8_t)((RdVal >> 8) & 0xFFU);
pBuf++;
#if PMA_ACCESS > 1U
pdwVal++;
-#endif
+#endif /* PMA_ACCESS */
}
if ((wNBytes % 2U) != 0U)
{
- temp = *pdwVal;
- *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
+ RdVal = *pdwVal;
+ *pBuf = (uint8_t)((RdVal >> 0) & 0xFFU);
}
}
diff --git a/Src/stm32f3xx_ll_utils.c b/Src/stm32f3xx_ll_utils.c
index d69016e..11ee50c 100644
--- a/Src/stm32f3xx_ll_utils.c
+++ b/Src/stm32f3xx_ll_utils.c
@@ -284,10 +284,6 @@
{
status = ERROR;
}
- else
- {
- status = SUCCESS;
- }
}
}
diff --git a/_htmresc/favicon.png b/_htmresc/favicon.png
new file mode 100644
index 0000000..06713ee
--- /dev/null
+++ b/_htmresc/favicon.png
Binary files differ
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st_2020.css
similarity index 77%
rename from _htmresc/mini-st.css
rename to _htmresc/mini-st_2020.css
index 71fbc14..3d9e81a 100644
--- a/_htmresc/mini-st.css
+++ b/_htmresc/mini-st_2020.css
@@ -1,39 +1,39 @@
@charset "UTF-8";
/*
- Flavor name: Default (mini-default)
- Author: Angelos Chalaris (chalarangelo@gmail.com)
- Maintainers: Angelos Chalaris
- mini.css version: v3.0.0-alpha.3
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
*/
/*
Browsers resets and base typography.
*/
/* Core module CSS variable definitions */
:root {
- --fore-color: #111;
- --secondary-fore-color: #444;
- --back-color: #f8f8f8;
- --secondary-back-color: #f0f0f0;
- --blockquote-color: #f57c00;
- --pre-color: #1565c0;
- --border-color: #aaa;
- --secondary-border-color: #ddd;
- --heading-ratio: 1.19;
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
--universal-margin: 0.5rem;
- --universal-padding: 0.125rem;
- --universal-border-radius: 0.125rem;
- --a-link-color: #0277bd;
- --a-visited-color: #01579b; }
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
html {
- font-size: 14px; }
+ font-size: 13.5px; }
a, b, del, em, i, ins, q, span, strong, u {
font-size: 1em; }
html, * {
- font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
- line-height: 1.4;
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
-webkit-text-size-adjust: 100%; }
* {
@@ -42,7 +42,10 @@
body {
margin: 0;
color: var(--fore-color);
- background: var(--back-color); }
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
details {
display: block; }
@@ -62,9 +65,9 @@
height: auto; }
h1, h2, h3, h4, h5, h6 {
- line-height: 1.2;
+ line-height: 1.25;
margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
- font-weight: 500; }
+ font-weight: 400; }
h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
color: var(--secondary-fore-color);
display: block;
@@ -74,21 +77,15 @@
font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
h2 {
- font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
- background: var(--mark-back-color);
- font-weight: 600;
- padding: 0.1em 0.5em 0.2em 0.5em;
- color: var(--mark-fore-color); }
-
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
h3 {
- font-size: calc(1rem * var(--heading-ratio));
- padding-left: calc(2 * var(--universal-margin));
- /* background: var(--border-color); */
- }
+ font-size: calc(1rem * var(--heading-ratio) ); }
h4 {
- font-size: 1rem;);
- padding-left: calc(4 * var(--universal-margin)); }
+ font-size: calc(1rem * var(--heading-ratio)); }
h5 {
font-size: 1rem; }
@@ -101,7 +98,7 @@
ol, ul {
margin: var(--universal-margin);
- padding-left: calc(6 * var(--universal-margin)); }
+ padding-left: calc(3 * var(--universal-margin)); }
b, strong {
font-weight: 700; }
@@ -111,7 +108,7 @@
border: 0;
line-height: 1.25em;
margin: var(--universal-margin);
- height: 0.0625rem;
+ height: 0.0714285714rem;
background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
blockquote {
@@ -121,16 +118,16 @@
color: var(--secondary-fore-color);
margin: var(--universal-margin);
padding: calc(3 * var(--universal-padding));
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.375rem solid var(--blockquote-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
blockquote:before {
position: absolute;
top: calc(0rem - var(--universal-padding));
left: 0;
font-family: sans-serif;
- font-size: 3rem;
- font-weight: 700;
+ font-size: 2rem;
+ font-weight: 800;
content: "\201c";
color: var(--blockquote-color); }
blockquote[cite]:after {
@@ -160,8 +157,8 @@
background: var(--secondary-back-color);
padding: calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.25rem solid var(--pre-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
sup, sub, code, kbd {
@@ -204,7 +201,8 @@
box-sizing: border-box;
display: flex;
flex: 0 1 auto;
- flex-flow: row wrap; }
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
.col-sm,
[class^='col-sm-'],
@@ -565,9 +563,9 @@
order: 999; } }
/* Card component CSS variable definitions */
:root {
- --card-back-color: #f8f8f8;
- --card-fore-color: #111;
- --card-border-color: #ddd; }
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
.card {
display: flex;
@@ -578,7 +576,7 @@
width: 100%;
background: var(--card-back-color);
color: var(--card-fore-color);
- border: 0.0625rem solid var(--card-border-color);
+ border: 0.0714285714rem solid var(--card-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
overflow: hidden; }
@@ -592,7 +590,7 @@
margin: 0;
border: 0;
border-radius: 0;
- border-bottom: 0.0625rem solid var(--card-border-color);
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
padding: var(--universal-padding);
width: 100%; }
.card > .sectione.media {
@@ -617,17 +615,18 @@
width: auto; }
.card.warning {
-/* --card-back-color: #ffca28; */
--card-back-color: #e5b8b7;
- --card-border-color: #e8b825; }
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
.card.error {
- --card-back-color: #b71c1c;
- --card-fore-color: #f8f8f8;
- --card-border-color: #a71a1a; }
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
.card > .sectione.dark {
- --card-back-color: #e0e0e0; }
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
.card > .sectione.double-padded {
padding: calc(1.5 * var(--universal-padding)); }
@@ -637,12 +636,12 @@
*/
/* Input_control module CSS variable definitions */
:root {
- --form-back-color: #f0f0f0;
- --form-fore-color: #111;
- --form-border-color: #ddd;
- --input-back-color: #f8f8f8;
- --input-fore-color: #111;
- --input-border-color: #ddd;
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
--input-focus-color: #0288d1;
--input-invalid-color: #d32f2f;
--button-back-color: #e2e2e2;
@@ -655,13 +654,13 @@
form {
background: var(--form-back-color);
color: var(--form-fore-color);
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
fieldset {
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 4);
padding: var(--universal-padding); }
@@ -671,7 +670,7 @@
display: table;
max-width: 100%;
white-space: normal;
- font-weight: 700;
+ font-weight: 500;
padding: calc(var(--universal-padding) / 2); }
label {
@@ -716,7 +715,7 @@
box-sizing: border-box;
background: var(--input-back-color);
color: var(--input-fore-color);
- border: 0.0625rem solid var(--input-border-color);
+ border: 0.0714285714rem solid var(--input-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 2);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
@@ -763,8 +762,8 @@
[type="radio"]:checked:before {
border-radius: 100%;
content: '';
- top: calc(0.0625rem + var(--universal-padding) / 2);
- left: calc(0.0625rem + var(--universal-padding) / 2);
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
background: var(--input-fore-color);
width: 0.5rem;
height: 0.5rem; }
@@ -793,7 +792,7 @@
display: inline-block;
background: var(--button-back-color);
color: var(--button-fore-color);
- border: 0.0625rem solid var(--button-border-color);
+ border: 0.0714285714rem solid var(--button-border-color);
border-radius: var(--universal-border-radius);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
@@ -814,7 +813,7 @@
.button-group {
display: flex;
- border: 0.0625rem solid var(--button-group-border-color);
+ border: 0.0714285714rem solid var(--button-group-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
.button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
@@ -826,13 +825,13 @@
border-radius: 0;
box-shadow: none; }
.button-group > :not(:first-child) {
- border-left: 0.0625rem solid var(--button-group-border-color); }
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
@media screen and (max-width: 499px) {
.button-group {
flex-direction: column; }
.button-group > :not(:first-child) {
border: 0;
- border-top: 0.0625rem solid var(--button-group-border-color); } }
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
/*
Custom elements for forms and input elements.
@@ -874,29 +873,29 @@
*/
/* Navigation module CSS variable definitions */
:root {
- --header-back-color: #f8f8f8;
- --header-hover-back-color: #f0f0f0;
- --header-fore-color: #444;
- --header-border-color: #ddd;
- --nav-back-color: #f8f8f8;
- --nav-hover-back-color: #f0f0f0;
- --nav-fore-color: #444;
- --nav-border-color: #ddd;
- --nav-link-color: #0277bd;
- --footer-fore-color: #444;
- --footer-back-color: #f8f8f8;
- --footer-border-color: #ddd;
- --footer-link-color: #0277bd;
- --drawer-back-color: #f8f8f8;
- --drawer-hover-back-color: #f0f0f0;
- --drawer-border-color: #ddd;
- --drawer-close-color: #444; }
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
header {
- height: 3.1875rem;
+ height: 2.75rem;
background: var(--header-back-color);
color: var(--header-fore-color);
- border-bottom: 0.0625rem solid var(--header-border-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
padding: calc(var(--universal-padding) / 4) 0;
white-space: nowrap;
overflow-x: auto;
@@ -927,7 +926,7 @@
nav {
background: var(--nav-back-color);
color: var(--nav-fore-color);
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
nav * {
@@ -946,10 +945,10 @@
nav .sublink-1:before {
position: absolute;
left: calc(var(--universal-padding) - 1 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
nav .sublink-2 {
position: relative;
@@ -957,16 +956,16 @@
nav .sublink-2:before {
position: absolute;
left: calc(var(--universal-padding) - 3 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
footer {
background: var(--footer-back-color);
color: var(--footer-fore-color);
- border-top: 0.0625rem solid var(--footer-border-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
padding: calc(2 * var(--universal-padding)) var(--universal-padding);
font-size: 0.875rem; }
footer a, footer a:visited {
@@ -1013,7 +1012,7 @@
height: 100vh;
overflow-y: auto;
background: var(--drawer-back-color);
- border: 0.0625rem solid var(--drawer-border-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
border-radius: 0;
margin: 0;
z-index: 1110;
@@ -1060,38 +1059,36 @@
*/
/* Table module CSS variable definitions. */
:root {
- --table-border-color: #aaa;
- --table-border-separator-color: #666;
- --table-head-back-color: #e6e6e6;
- --table-head-fore-color: #111;
- --table-body-back-color: #f8f8f8;
- --table-body-fore-color: #111;
- --table-body-alt-back-color: #eee; }
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
table {
border-collapse: separate;
border-spacing: 0;
- : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ margin: 0;
display: flex;
flex: 0 1 auto;
flex-flow: row wrap;
padding: var(--universal-padding);
- padding-top: 0;
- margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
+ padding-top: 0; }
table caption {
- font-size: 1.25 * rem;
+ font-size: 1rem;
margin: calc(2 * var(--universal-margin)) 0;
max-width: 100%;
- flex: 0 0 100%;
- text-align: left;}
+ flex: 0 0 100%; }
table thead, table tbody {
display: flex;
flex-flow: row wrap;
- border: 0.0625rem solid var(--table-border-color); }
+ border: 0.0714285714rem solid var(--table-border-color); }
table thead {
z-index: 999;
border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
- border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
table tbody {
border-top: 0;
margin-top: calc(0 - var(--universal-margin));
@@ -1109,11 +1106,11 @@
table td {
background: var(--table-body-back-color);
color: var(--table-body-fore-color);
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table:not(.horizontal) {
overflow: auto;
- max-height: 850px; }
+ max-height: 100%; }
table:not(.horizontal) thead, table:not(.horizontal) tbody {
max-width: 100%;
flex: 0 0 100%; }
@@ -1134,32 +1131,33 @@
border: 0; }
table.horizontal thead, table.horizontal tbody {
border: 0;
+ flex: .2 0 0;
flex-flow: row nowrap; }
table.horizontal tbody {
overflow: auto;
justify-content: space-between;
- flex: 1 0 0;
- margin-left: calc( 4 * var(--universal-margin));
+ flex: .8 0 0;
+ margin-left: 0;
padding-bottom: calc(var(--universal-padding) / 4); }
table.horizontal tr {
flex-direction: column;
flex: 1 0 auto; }
table.horizontal th, table.horizontal td {
- width: 100%;
+ width: auto;
border: 0;
- border-bottom: 0.0625rem solid var(--table-border-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
border-top: 0; }
table.horizontal th {
text-align: right;
- border-left: 0.0625rem solid var(--table-border-color);
- border-right: 0.0625rem solid var(--table-border-separator-color); }
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
table.horizontal thead tr:first-child {
padding-left: 0; }
table.horizontal th:first-child, table.horizontal td:first-child {
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td {
- border-right: 0.0625rem solid var(--table-border-color); }
+ border-right: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td:first-child {
border-top-right-radius: 0.25rem; }
table.horizontal tbody tr:last-child td:last-child {
@@ -1191,12 +1189,12 @@
display: table-row-group; }
table tr, table.horizontal tr {
display: block;
- border: 0.0625rem solid var(--table-border-color);
+ border: 0.0714285714rem solid var(--table-border-color);
border-radius: var(--universal-border-radius);
- background: #fafafa;
+ background: #ffffff;
padding: var(--universal-padding);
margin: var(--universal-margin);
- margin-bottom: calc(2 * var(--universal-margin)); }
+ margin-bottom: calc(1 * var(--universal-margin)); }
table th, table td, table.horizontal th, table.horizontal td {
width: auto; }
table td, table.horizontal td {
@@ -1211,9 +1209,6 @@
border-top: 0; }
table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
border-right: 0; } }
-:root {
- --table-body-alt-back-color: #eee; }
-
table tr:nth-of-type(2n) > td {
background: var(--table-body-alt-back-color); }
@@ -1234,8 +1229,8 @@
*/
/* Contextual module CSS variable definitions */
:root {
- --mark-back-color: #0277bd;
- --mark-fore-color: #fafafa; }
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
mark {
background: var(--mark-back-color);
@@ -1243,11 +1238,11 @@
font-size: 0.95em;
line-height: 1em;
border-radius: var(--universal-border-radius);
- padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
mark.inline-block {
display: inline-block;
font-size: 1em;
- line-height: 1.5;
+ line-height: 1.4;
padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
:root {
@@ -1314,8 +1309,8 @@
:root {
--modal-overlay-color: rgba(0, 0, 0, 0.45);
- --modal-close-color: #444;
- --modal-close-hover-color: #f0f0f0; }
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
[type="checkbox"].modal {
height: 1px;
@@ -1368,13 +1363,14 @@
z-index: 1211; }
:root {
- --collapse-label-back-color: #e8e8e8;
- --collapse-label-fore-color: #212121;
- --collapse-label-hover-back-color: #f0f0f0;
- --collapse-selected-label-back-color: #ececec;
- --collapse-border-color: #ddd;
- --collapse-content-back-color: #fafafa;
- --collapse-selected-label-border-color: #0277bd; }
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
.collapse {
width: calc(100% - 2 * var(--universal-margin));
@@ -1395,13 +1391,13 @@
.collapse > label {
flex-grow: 1;
display: inline-block;
- height: 1.5rem;
+ height: 1.25rem;
cursor: pointer;
- transition: background 0.3s;
+ transition: background 0.2s;
color: var(--collapse-label-fore-color);
background: var(--collapse-label-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
- padding: calc(1.5 * var(--universal-padding)); }
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
.collapse > label:hover, .collapse > label:focus {
background: var(--collapse-label-hover-back-color); }
.collapse > label + div {
@@ -1418,7 +1414,7 @@
max-height: 1px; }
.collapse > :checked + label {
background: var(--collapse-selected-label-back-color);
- border-bottom-color: var(--collapse-selected-label-border-color); }
+ border-color: var(--collapse-selected-label-border-color); }
.collapse > :checked + label + div {
box-sizing: border-box;
position: relative;
@@ -1427,13 +1423,13 @@
overflow: auto;
margin: 0;
background: var(--collapse-content-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
border-top: 0;
padding: var(--universal-padding);
clip: auto;
-webkit-clip-path: inset(0%);
clip-path: inset(0%);
- max-height: 850px; }
+ max-height: 100%; }
.collapse > label:not(:first-of-type) {
border-top: 0; }
.collapse > label:first-of-type {
@@ -1450,11 +1446,8 @@
/*
Custom elements for contextual background elements, toasts and tooltips.
*/
-mark.secondary {
- --mark-back-color: #d32f2f; }
-
mark.tertiary {
- --mark-back-color: #308732; }
+ --mark-back-color: #3cb4e6; }
mark.tag {
padding: calc(var(--universal-padding)/2) var(--universal-padding);
@@ -1463,9 +1456,9 @@
/*
Definitions for progress elements and spinners.
*/
-/* Progess module CSS variable definitions */
+/* Progress module CSS variable definitions */
:root {
- --progress-back-color: #ddd;
+ --progress-back-color: #3cb4e6;
--progress-fore-color: #555; }
progress {
@@ -1558,45 +1551,45 @@
filter: invert(100%); }
span.icon-alert {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-bookmark {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-calendar {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-credit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-edit {
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+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
span.icon-link {
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+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-help {
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+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-home {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-info {
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+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-lock {
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+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-mail {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-location {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-phone {
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span.icon-rss {
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+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-search {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
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span.icon-settings {
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span.icon-share {
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span.icon-cart {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-upload {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-user {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
/*
Definitions for utilities and helper classes.
@@ -1604,7 +1597,7 @@
/* Utility module CSS variable definitions */
:root {
--generic-border-color: rgba(0, 0, 0, 0.3);
- --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
.hidden {
display: none !important; }
@@ -1622,7 +1615,7 @@
overflow: hidden !important; }
.bordered {
- border: 0.0625rem solid var(--generic-border-color) !important; }
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
.rounded {
border-radius: var(--universal-border-radius) !important; }
@@ -1697,4 +1690,14 @@
clip-path: inset(100%) !important;
overflow: hidden !important; } }
-/*# sourceMappingURL=mini-default.css.map */
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/_htmresc/st_logo.png b/_htmresc/st_logo.png
deleted file mode 100644
index 8b80057..0000000
--- a/_htmresc/st_logo.png
+++ /dev/null
Binary files differ
diff --git a/_htmresc/st_logo_2020.png b/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000..d6cebb5
--- /dev/null
+++ b/_htmresc/st_logo_2020.png
Binary files differ
