Release v1.8.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index ae83378..1cfd19b 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2019 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -105,6 +104,12 @@
#if defined(STM32H7)
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
/**
* @}
*/
@@ -214,10 +219,20 @@
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
/**
* @}
*/
+/** @defgroup CRC_Aliases CRC API aliases
+ * @{
+ */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/**
* @}
*/
@@ -252,6 +267,13 @@
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -394,6 +416,10 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -542,6 +568,7 @@
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+
/**
* @}
*/
@@ -637,6 +664,20 @@
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+
+#if defined(STM32U5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 */
+/**
+ * @}
+ */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -874,9 +915,19 @@
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+ * @{
+ */
+#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
+/**
+ * @}
+ */
+
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
#endif /* STM32U5 */
/**
* @}
@@ -1216,6 +1267,10 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
/**
* @}
*/
@@ -1646,6 +1701,79 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
+
/**
* @}
*/
@@ -3404,7 +3532,21 @@
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
#endif
+
/**
* @}
*/
@@ -3474,6 +3616,7 @@
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+
/**
* @}
*/
@@ -3836,5 +3979,4 @@
#endif /* STM32_HAL_LEGACY */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/Legacy/stm32f4xx_hal_can_legacy.h b/Inc/Legacy/stm32f4xx_hal_can_legacy.h
index aacf0f0..e4d774b 100644
--- a/Inc/Legacy/stm32f4xx_hal_can_legacy.h
+++ b/Inc/Legacy/stm32f4xx_hal_can_legacy.h
@@ -6,29 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -780,6 +763,3 @@
#endif
#endif /* __STM32F4xx_HAL_CAN_LEGACY_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/Legacy/stm32f4xx_hal_eth_legacy.h b/Inc/Legacy/stm32f4xx_hal_eth_legacy.h
new file mode 100644
index 0000000..ab84a46
--- /dev/null
+++ b/Inc/Legacy/stm32f4xx_hal_eth_legacy.h
@@ -0,0 +1,2209 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_eth_legacy.h
+ * @author MCD Application Team
+ * @brief Header file of ETH HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_ETH_LEGACY_H
+#define __STM32F4xx_HAL_ETH_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup ETH
+ * @{
+ */
+
+/** @addtogroup ETH_Private_Macros
+ * @{
+ */
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
+ ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
+ ((SPEED) == ETH_SPEED_100M))
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
+ ((MODE) == ETH_MODE_HALFDUPLEX))
+#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
+ ((MODE) == ETH_RXINTERRUPT_MODE))
+#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
+ ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
+#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
+ ((MODE) == ETH_MEDIA_INTERFACE_RMII))
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
+ ((CMD) == ETH_WATCHDOG_DISABLE))
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
+ ((CMD) == ETH_JABBER_DISABLE))
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
+ ((GAP) == ETH_INTERFRAMEGAP_40BIT))
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
+ ((CMD) == ETH_CARRIERSENCE_DISABLE))
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
+ ((CMD) == ETH_RECEIVEOWN_DISABLE))
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
+ ((CMD) == ETH_LOOPBACKMODE_DISABLE))
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
+ ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
+ ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
+ ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
+ ((LIMIT) == ETH_BACKOFFLIMIT_1))
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
+ ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEAll_DISABLE))
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
+ ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
+ ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
+ ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
+ ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
+ ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
+ ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
+ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
+ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
+ ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
+ ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
+ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
+ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS2) || \
+ ((ADDRESS) == ETH_MAC_ADDRESS3))
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
+ ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
+ ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
+ ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
+ ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
+ ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
+ ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
+ ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
+ ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
+ ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
+ ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
+ ((CMD) == ETH_FIXEDBURST_DISABLE))
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
+ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
+ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
+ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
+ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
+ ((BUFFER) == ETH_DMARXDESC_BUFFER2))
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
+ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
+ ((IT) != 0x00U))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
+
+/**
+ * @}
+ */
+
+/** @addtogroup ETH_Private_Defines
+ * @{
+ */
+/* Delay to wait when writing to some Ethernet registers */
+#define ETH_REG_WRITE_DELAY 0x00000001U
+
+/* ETHERNET Errors */
+#define ETH_SUCCESS 0U
+#define ETH_ERROR 1U
+
+/* ETHERNET DMA Tx descriptors Collision Count Shift */
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
+
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
+
+/* ETHERNET DMA Rx descriptors Frame Length Shift */
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
+
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
+
+/* ETHERNET DMA Rx descriptors Frame length Shift */
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
+
+/* ETHERNET MAC address offsets */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
+
+/* ETHERNET MACMIIAR register Mask */
+#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
+
+/* ETHERNET MACCR register Mask */
+#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
+
+/* ETHERNET MACFCR register Mask */
+#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
+
+/* ETHERNET DMAOMR register Mask */
+#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
+
+/* ETHERNET Remote Wake-up frame register length */
+#define ETH_WAKEUP_REGISTER_LENGTH 8U
+
+/* ETHERNET Missed frames counter Shift */
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
+ /**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
+ HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
+ HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
+ HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
+}HAL_ETH_StateTypeDef;
+
+/**
+ * @brief ETH Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
+ and the mode (half/full-duplex).
+ This parameter can be a value of @ref ETH_AutoNegotiation */
+
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
+ This parameter can be a value of @ref ETH_Speed */
+
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ This parameter can be a value of @ref ETH_Duplex_Mode */
+
+ uint16_t PhyAddress; /*!< Ethernet PHY address.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+ uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
+ This parameter can be a value of @ref ETH_Rx_Mode */
+
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
+ This parameter can be a value of @ref ETH_Checksum_Mode */
+
+ uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
+ This parameter can be a value of @ref ETH_Media_Interface */
+
+} ETH_InitTypeDef;
+
+
+ /**
+ * @brief ETH MAC Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t Watchdog; /*!< Selects or not the Watchdog timer
+ When enabled, the MAC allows no more then 2048 bytes to be received.
+ When disabled, the MAC can receive up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Watchdog */
+
+ uint32_t Jabber; /*!< Selects or not Jabber timer
+ When enabled, the MAC allows no more then 2048 bytes to be sent.
+ When disabled, the MAC can send up to 16384 bytes.
+ This parameter can be a value of @ref ETH_Jabber */
+
+ uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+
+ uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
+ This parameter can be a value of @ref ETH_Carrier_Sense */
+
+ uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
+ in Half-Duplex mode.
+ This parameter can be a value of @ref ETH_Receive_Own */
+
+ uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
+
+ uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
+ This parameter can be a value of @ref ETH_Checksum_Offload */
+
+ uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
+ when a collision occurs (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Retry_Transmission */
+
+ uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
+ This parameter can be a value of @ref ETH_Deferral_Check */
+
+ uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
+ This parameter can be a value of @ref ETH_Receive_All */
+
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
+
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
+
+ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
+
+ uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+
+ uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */
+
+ uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+
+ uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+
+ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
+
+ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
+
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
+
+ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+
+ uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
+ automatic retransmission of PAUSE Frame.
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
+ unicast address and unique multicast address).
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+
+ uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
+ disable its transmitter for a specified time (Pause Time)
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */
+
+ uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
+ or the MAC back-pressure operation (Half-Duplex mode)
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+
+ uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
+ comparison and filtering.
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+
+ uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
+
+} ETH_MACInitTypeDef;
+
+/**
+ * @brief ETH DMA Configuration Structure definition
+ */
+
+typedef struct
+{
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+
+ uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
+
+ uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
+
+ uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+
+ uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+
+ uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */
+
+ uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes) including pad-bytes and CRC)
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+
+ uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+
+ uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining the status for the first frame.
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */
+
+ uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+
+ uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
+ This parameter can be a value of @ref ETH_Fixed_Burst */
+
+ uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+ uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+ uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
+ This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
+
+ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+
+ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
+} ETH_DMAInitTypeDef;
+
+
+/**
+ * @brief ETH DMA Descriptors data structure definition
+ */
+
+typedef struct
+{
+ __IO uint32_t Status; /*!< Status */
+
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
+
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
+
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
+
+ /*!< Enhanced ETHERNET DMA PTP Descriptors */
+ uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
+
+ uint32_t Reserved1; /*!< Reserved */
+
+ uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
+
+ uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
+
+} ETH_DMADescTypeDef;
+
+/**
+ * @brief Received Frame Informations structure definition
+ */
+typedef struct
+{
+ ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
+
+ ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
+
+ uint32_t SegCount; /*!< Segment count */
+
+ uint32_t length; /*!< Frame length */
+
+ uint32_t buffer; /*!< Frame buffer */
+
+} ETH_DMARxFrameInfos;
+
+/**
+ * @brief ETH Handle Structure definition
+ */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+typedef struct __ETH_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+{
+ ETH_TypeDef *Instance; /*!< Register base address */
+
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
+
+ uint32_t LinkStatus; /*!< Ethernet link status */
+
+ ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
+
+ ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
+
+ ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
+
+ __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
+
+ HAL_LockTypeDef Lock; /*!< ETH Lock */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+ void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
+ void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
+ void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */
+ void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
+ void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+} ETH_HandleTypeDef;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL ETH Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
+ HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
+ HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
+ HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
+ HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
+
+}HAL_ETH_CallbackIDTypeDef;
+
+/**
+ * @brief HAL ETH Callback pointer definition
+ */
+typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+ /**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+ * @{
+ */
+
+/** @defgroup ETH_Buffers_setting ETH Buffers setting
+ * @{
+ */
+#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC 4U /*!< Ethernet CRC */
+#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
+
+ /* Ethernet driver receive buffers are organized in a chained linked-list, when
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+ to the driver receive buffers memory.
+
+ Depending on the size of the received ethernet packet and the size of
+ each ethernet driver receive buffer, the received packet can take one or more
+ ethernet driver receive buffer.
+
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+ and the total count of the driver receive buffers ETH_RXBUFNB.
+
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_RX_BUF_SIZE
+ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
+#ifndef ETH_RXBUFNB
+ #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#endif
+
+
+ /* Ethernet driver transmit buffers are organized in a chained linked-list, when
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+ driver transmit buffers memory to the TxFIFO.
+
+ Depending on the size of the Ethernet packet to be transmitted and the size of
+ each ethernet driver transmit buffer, the packet to be transmitted can take
+ one or more ethernet driver transmit buffer.
+
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+ and the total count of the driver transmit buffers ETH_TXBUFNB.
+
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
+
+/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
+ packet */
+#ifndef ETH_TX_BUF_SIZE
+ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#endif
+
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
+#ifndef ETH_TXBUFNB
+ #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+#endif
+
+ /**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
+ * @{
+ */
+
+/*
+ DMA Tx Descriptor
+ -----------------------------------------------------------------------------------------------
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES2 | Buffer1 Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ -----------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
+ */
+#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
+#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
+#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
+#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
+#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
+
+/**
+ * @brief Bit definition of TDES1 register
+ */
+#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
+
+/**
+ * @brief Bit definition of TDES2 register
+ */
+#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of TDES3 register
+ */
+#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+
+ /*---------------------------------------------------------------------------------------------
+ TDES6 | Transmit Time Stamp Low [31:0] |
+ -----------------------------------------------------------------------------------------------
+ TDES7 | Transmit Time Stamp High [31:0] |
+ ----------------------------------------------------------------------------------------------*/
+
+/* Bit definition of TDES6 register */
+ #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
+
+/* Bit definition of TDES7 register */
+ #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
+
+/**
+ * @}
+ */
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
+ * @{
+ */
+
+/*
+ DMA Rx Descriptor
+ --------------------------------------------------------------------------------------------------------------------
+ RDES0 | OWN(31) | Status [30:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES2 | Buffer1 Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
+ */
+#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+
+/**
+ * @brief Bit definition of RDES1 register
+ */
+#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
+
+/**
+ * @brief Bit definition of RDES2 register
+ */
+#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+
+/**
+ * @brief Bit definition of RDES3 register
+ */
+#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+
+/*---------------------------------------------------------------------------------------------------------------------
+ RDES4 | Reserved[31:15] | Extended Status [14:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES5 | Reserved[31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES6 | Receive Time Stamp Low [31:0] |
+ ---------------------------------------------------------------------------------------------------------------------
+ RDES7 | Receive Time Stamp High [31:0] |
+ --------------------------------------------------------------------------------------------------------------------*/
+
+/* Bit definition of RDES4 register */
+#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
+ #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
+ #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
+ #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
+ #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
+
+/* Bit definition of RDES6 register */
+#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
+
+/* Bit definition of RDES7 register */
+#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
+/**
+ * @}
+ */
+ /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
+ * @{
+ */
+#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
+#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
+
+/**
+ * @}
+ */
+/** @defgroup ETH_Speed ETH Speed
+ * @{
+ */
+#define ETH_SPEED_10M 0x00000000U
+#define ETH_SPEED_100M 0x00004000U
+
+/**
+ * @}
+ */
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+ * @{
+ */
+#define ETH_MODE_FULLDUPLEX 0x00000800U
+#define ETH_MODE_HALFDUPLEX 0x00000000U
+/**
+ * @}
+ */
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
+ * @{
+ */
+#define ETH_RXPOLLING_MODE 0x00000000U
+#define ETH_RXINTERRUPT_MODE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
+ * @{
+ */
+#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
+#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Media_Interface ETH Media Interface
+ * @{
+ */
+#define ETH_MEDIA_INTERFACE_MII 0x00000000U
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Watchdog ETH Watchdog
+ * @{
+ */
+#define ETH_WATCHDOG_ENABLE 0x00000000U
+#define ETH_WATCHDOG_DISABLE 0x00800000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Jabber ETH Jabber
+ * @{
+ */
+#define ETH_JABBER_ENABLE 0x00000000U
+#define ETH_JABBER_DISABLE 0x00400000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
+ * @{
+ */
+#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
+ * @{
+ */
+#define ETH_CARRIERSENCE_ENABLE 0x00000000U
+#define ETH_CARRIERSENCE_DISABLE 0x00010000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Own ETH Receive Own
+ * @{
+ */
+#define ETH_RECEIVEOWN_ENABLE 0x00000000U
+#define ETH_RECEIVEOWN_DISABLE 0x00002000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+ * @{
+ */
+#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
+#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
+ * @{
+ */
+#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
+#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
+ * @{
+ */
+#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
+#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
+ * @{
+ */
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
+ * @{
+ */
+#define ETH_BACKOFFLIMIT_10 0x00000000U
+#define ETH_BACKOFFLIMIT_8 0x00000020U
+#define ETH_BACKOFFLIMIT_4 0x00000040U
+#define ETH_BACKOFFLIMIT_1 0x00000060U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Deferral_Check ETH Deferral Check
+ * @{
+ */
+#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
+#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_All ETH Receive All
+ * @{
+ */
+#define ETH_RECEIVEALL_ENABLE 0x80000000U
+#define ETH_RECEIVEAll_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
+ * @{
+ */
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
+#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
+ * @{
+ */
+#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
+ * @{
+ */
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
+ * @{
+ */
+#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
+#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
+ * @{
+ */
+#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
+#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
+ * @{
+ */
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
+#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
+#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
+ * @{
+ */
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
+#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
+ * @{
+ */
+#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
+#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
+ * @{
+ */
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
+ * @{
+ */
+#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
+#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
+ * @{
+ */
+#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
+#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
+ * @{
+ */
+#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
+#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
+ * @{
+ */
+#define ETH_MAC_ADDRESS0 0x00000000U
+#define ETH_MAC_ADDRESS1 0x00000008U
+#define ETH_MAC_ADDRESS2 0x00000010U
+#define ETH_MAC_ADDRESS3 0x00000018U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
+ * @{
+ */
+#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
+#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
+ * @{
+ */
+#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
+ * @{
+ */
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
+ * @{
+ */
+#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
+#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
+ * @{
+ */
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
+ * @{
+ */
+#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
+#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
+ * @{
+ */
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
+ * @{
+ */
+#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
+#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
+ * @{
+ */
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
+ * @{
+ */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
+ * @{
+ */
+#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
+#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
+ * @{
+ */
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
+ * @{
+ */
+#define ETH_FIXEDBURST_ENABLE 0x00010000U
+#define ETH_FIXEDBURST_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
+ * @{
+ */
+#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
+ * @{
+ */
+#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
+ * @{
+ */
+#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
+#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
+ * @{
+ */
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
+#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
+ * @{
+ */
+#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
+ * @{
+ */
+#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
+ * @{
+ */
+#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_PMT_Flags ETH PMT Flags
+ * @{
+ */
+#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
+ * @{
+ */
+#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Flags ETH MAC Flags
+ * @{
+ */
+#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Flags ETH DMA Flags
+ * @{
+ */
+#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
+#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
+#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+ * @{
+ */
+#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+ * @{
+ */
+#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
+#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
+ * @{
+ */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
+ * @{
+ */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
+
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_overflow ETH DMA overflow
+ * @{
+ */
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+ * @{
+ */
+#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/** @brief Reset ETH handle state
+ * @param __HANDLE__ specifies the ETH handle.
+ * @retval None
+ */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
+#else
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of TDES0 to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of RDES0 to check.
+ * @retval the ETH_DMATxDescFlag (SET or RESET).
+ */
+#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
+
+/**
+ * @brief Enables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
+
+/**
+ * @brief Disables the specified DMA Rx Desc receive interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
+
+/**
+ * @brief Set the specified DMA Rx Desc Own bit.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
+
+/**
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
+ * @param __HANDLE__ ETH Handle
+ * @retval The Transmit descriptor collision counter value.
+ */
+#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
+
+/**
+ * @brief Set the specified DMA Tx Desc Own bit.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
+
+/**
+ * @brief Enables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
+
+/**
+ * @brief Disables the specified DMA Tx Desc Transmit interrupt.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
+
+/**
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
+ * @param __HANDLE__ ETH Handle
+ * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
+ * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
+
+/**
+ * @brief Enables the DMA Tx Desc CRC.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
+
+/**
+ * @brief Disables the DMA Tx Desc CRC.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
+
+/**
+ * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
+
+/**
+ * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
+
+/**
+ * @brief Enables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
+ * enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @retval None
+ */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
+
+/**
+ * @brief Initiate a Pause Control Frame (Full-duplex only).
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @retval The new state of flow control busy status bit (SET or RESET).
+ */
+#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
+
+/**
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @retval The state of ETHERNET MAC flag.
+ */
+#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Enables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
+ * enabled @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET DMA interrupts.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
+ * disabled. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
+
+/**
+ * @brief Clears the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+ * @retval None
+ */
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+* @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
+
+/**
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
+ * @param __HANDLE__ ETH Handle
+ * @param __OVERFLOW__ specifies the DMA overflow flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
+ * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
+ * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
+
+/**
+ * @brief Set the DMA Receive status watchdog timer register value
+ * @param __HANDLE__ ETH Handle
+ * @param __VALUE__ DMA Receive status watchdog timer register value
+ * @retval None
+ */
+#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
+
+/**
+ * @brief Enables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Disables any unicast packet filtered by the MAC address
+ * recognition to be a wake-up frame.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
+
+/**
+ * @brief Enables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Disables the MAC Wake-Up Frame Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Magic Packet Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
+
+/**
+ * @brief Disables the MAC Magic Packet Detection.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
+
+/**
+ * @brief Enables the MAC Power Down.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Disables the MAC Power Down.
+ * @param __HANDLE__ ETH Handle
+ * @retval None
+ */
+#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
+
+/**
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.
+ * @param __HANDLE__ ETH Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).
+ */
+#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
+
+/**
+ * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+
+/**
+ * @brief Enables the MMC Counter Freeze.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
+
+/**
+ * @brief Disables the MMC Counter Freeze.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
+
+/**
+ * @brief Enables the MMC Reset On Read.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
+
+/**
+ * @brief Disables the MMC Reset On Read.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
+
+/**
+ * @brief Enables the MMC Counter Stop Rollover.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
+
+/**
+ * @brief Disables the MMC Counter Stop Rollover.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
+
+/**
+ * @brief Resets the MMC Counters.
+ * @param __HANDLE__ ETH Handle.
+ * @retval None
+ */
+#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
+
+/**
+ * @brief Enables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
+/**
+ * @brief Disables the specified ETHERNET MMC Rx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
+/**
+ * @brief Enables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
+
+/**
+ * @brief Disables the specified ETHERNET MMC Tx interrupts.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * @retval None
+ */
+#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
+
+/**
+ * @brief Enables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enable event on ETH External event line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disable event on ETH External event line
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Get flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Clear flag of the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @brief Disables the rising edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Disables falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+
+/**
+ * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
+ }while(0U)
+
+/**
+ * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
+ * @retval None
+ */
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ }while(0U)
+
+/**
+ * @brief Generate a Software interrupt on selected EXTI line.
+ * @retval None.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
+
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup ETH_Exported_Functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions ****************************/
+
+/** @addtogroup ETH_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+/* IO operation functions ****************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
+/* Communication with PHY functions*/
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+/* Callback in non blocking modes (Interrupt) */
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
+
+/* Peripheral Control functions **********************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group3
+ * @{
+ */
+
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+/**
+ * @}
+ */
+
+/* Peripheral State functions ************************************************/
+
+/** @addtogroup ETH_Exported_Functions_Group4
+ * @{
+ */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
+ STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_ETH_LEGACY_H */
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index 4711b65..3ae73f0 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -8,13 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -54,4 +53,4 @@
#endif /* __STM32_ASSERT_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f4xx_hal.h b/Inc/stm32f4xx_hal.h
index 209864d..f7eb847 100644
--- a/Inc/stm32f4xx_hal.h
+++ b/Inc/stm32f4xx_hal.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -295,4 +294,4 @@
#endif /* __STM32F4xx_HAL_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f4xx_hal_adc.h b/Inc/stm32f4xx_hal_adc.h
index a041e76..ce95f08 100644
--- a/Inc/stm32f4xx_hal_adc.h
+++ b/Inc/stm32f4xx_hal_adc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -897,4 +896,3 @@
#endif /*__STM32F4xx_ADC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_adc_ex.h b/Inc/stm32f4xx_hal_adc_ex.h
index b0cdd2a..515435f 100644
--- a/Inc/stm32f4xx_hal_adc_ex.h
+++ b/Inc/stm32f4xx_hal_adc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -406,4 +405,3 @@
#endif /*__STM32F4xx_ADC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_can.h b/Inc/stm32f4xx_hal_can.h
index 062abd6..aa4a40d 100644
--- a/Inc/stm32f4xx_hal_can.h
+++ b/Inc/stm32f4xx_hal_can.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -843,6 +842,3 @@
#endif
#endif /* STM32F4xx_HAL_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_cec.h b/Inc/stm32f4xx_hal_cec.h
index 9041577..9d6c226 100644
--- a/Inc/stm32f4xx_hal_cec.h
+++ b/Inc/stm32f4xx_hal_cec.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -105,7 +104,7 @@
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
- uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
} CEC_InitTypeDef;
@@ -791,4 +790,3 @@
#endif /* STM32F4xxHAL_CEC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_conf_template.h b/Inc/stm32f4xx_hal_conf_template.h
index afa2f56..d32595f 100644
--- a/Inc/stm32f4xx_hal_conf_template.h
+++ b/Inc/stm32f4xx_hal_conf_template.h
@@ -8,13 +8,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -498,4 +497,4 @@
#endif /* __STM32F4xx_HAL_CONF_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f4xx_hal_cortex.h b/Inc/stm32f4xx_hal_cortex.h
index 95218cf..fdc96b5 100644
--- a/Inc/stm32f4xx_hal_cortex.h
+++ b/Inc/stm32f4xx_hal_cortex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -407,4 +405,3 @@
#endif /* __STM32F4xx_HAL_CORTEX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_crc.h b/Inc/stm32f4xx_hal_crc.h
index bbd58a5..41edbe3 100644
--- a/Inc/stm32f4xx_hal_crc.h
+++ b/Inc/stm32f4xx_hal_crc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -180,5 +179,3 @@
#endif
#endif /* STM32F4xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_cryp.h b/Inc/stm32f4xx_hal_cryp.h
index 8596fe7..960e1c7 100644
--- a/Inc/stm32f4xx_hal_cryp.h
+++ b/Inc/stm32f4xx_hal_cryp.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -682,4 +681,3 @@
#endif /* __STM32F4xx_HAL_CRYP_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_cryp_ex.h b/Inc/stm32f4xx_hal_cryp_ex.h
index 251e94b..dd12742 100644
--- a/Inc/stm32f4xx_hal_cryp_ex.h
+++ b/Inc/stm32f4xx_hal_cryp_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -141,4 +140,3 @@
#endif /* __STM32F4xx_HAL_CRYP_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dac.h b/Inc/stm32f4xx_hal_dac.h
index abd8544..a79ca73 100644
--- a/Inc/stm32f4xx_hal_dac.h
+++ b/Inc/stm32f4xx_hal_dac.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -479,4 +478,3 @@
#endif /* STM32F4xx_HAL_DAC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dac_ex.h b/Inc/stm32f4xx_hal_dac_ex.h
index 03159d4..db10990 100644
--- a/Inc/stm32f4xx_hal_dac_ex.h
+++ b/Inc/stm32f4xx_hal_dac_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -204,4 +203,3 @@
#endif /* STM32F4xx_HAL_DAC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dcmi.h b/Inc/stm32f4xx_hal_dcmi.h
index 2a9edb6..b7e82dc 100644
--- a/Inc/stm32f4xx_hal_dcmi.h
+++ b/Inc/stm32f4xx_hal_dcmi.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -563,5 +561,3 @@
#endif
#endif /* __STM32F4xx_HAL_DCMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dcmi_ex.h b/Inc/stm32f4xx_hal_dcmi_ex.h
index 9bc942d..b4f181c 100644
--- a/Inc/stm32f4xx_hal_dcmi_ex.h
+++ b/Inc/stm32f4xx_hal_dcmi_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -208,5 +206,3 @@
#endif
#endif /* __STM32F4xx_HAL_DCMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_def.h b/Inc/stm32f4xx_hal_def.h
index 975f70b..f9bbec2 100644
--- a/Inc/stm32f4xx_hal_def.h
+++ b/Inc/stm32f4xx_hal_def.h
@@ -7,13 +7,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -208,4 +207,4 @@
#endif /* ___STM32F4xx_HAL_DEF */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/Inc/stm32f4xx_hal_dfsdm.h b/Inc/stm32f4xx_hal_dfsdm.h
index 09c6551..016fd30 100644
--- a/Inc/stm32f4xx_hal_dfsdm.h
+++ b/Inc/stm32f4xx_hal_dfsdm.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -59,7 +58,7 @@
{
FunctionalState Activation; /*!< Output clock enable/disable */
uint32_t Selection; /*!< Output clock is system clock or audio clock.
- This parameter can be a value of @ref DFSDM_Channel_OuputClock */
+ This parameter can be a value of @ref DFSDM_Channel_OutputClock */
uint32_t Divider; /*!< Output clock divider.
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
}DFSDM_Channel_OutputClockTypeDef;
@@ -333,11 +332,11 @@
* @{
*/
-/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
+/** @defgroup DFSDM_Channel_OutputClock DFSDM channel output clock selection
* @{
*/
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */
/**
* @}
*/
@@ -1140,5 +1139,3 @@
#endif
#endif /* __STM32F4xx_HAL_DFSDM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dma.h b/Inc/stm32f4xx_hal_dma.h
index 90dd292..7ff3836 100644
--- a/Inc/stm32f4xx_hal_dma.h
+++ b/Inc/stm32f4xx_hal_dma.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -801,4 +800,3 @@
#endif /* __STM32F4xx_HAL_DMA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dma2d.h b/Inc/stm32f4xx_hal_dma2d.h
index 158ed67..8967141 100644
--- a/Inc/stm32f4xx_hal_dma2d.h
+++ b/Inc/stm32f4xx_hal_dma2d.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -279,15 +278,6 @@
* @}
*/
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
- * @{
- */
-#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
- for compatibility with legacy code */
-/**
- * @}
- */
-
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DMA2D common Callback ID enumeration definition
@@ -646,6 +636,3 @@
#endif
#endif /* STM32F4xx_HAL_DMA2D_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dma_ex.h b/Inc/stm32f4xx_hal_dma_ex.h
index 2e60aff..9858c74 100644
--- a/Inc/stm32f4xx_hal_dma_ex.h
+++ b/Inc/stm32f4xx_hal_dma_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -101,4 +100,3 @@
#endif /*__STM32F4xx_HAL_DMA_EX_H*/
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_dsi.h b/Inc/stm32f4xx_hal_dsi.h
index 716dea1..6da9668 100644
--- a/Inc/stm32f4xx_hal_dsi.h
+++ b/Inc/stm32f4xx_hal_dsi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -40,6 +39,9 @@
*/
/* Exported types ------------------------------------------------------------*/
+/** @defgroup DSI_Exported_Types DSI Exported Types
+ * @{
+ */
/**
* @brief DSI Init Structure definition
*/
@@ -61,14 +63,14 @@
*/
typedef struct
{
- uint32_t PLLNDIV; /*!< PLL Loop Division Factor
- This parameter must be a value between 10 and 125 */
+ uint32_t PLLNDIV; /*!< PLL Loop Division Factor
+ This parameter must be a value between 10 and 125 */
- uint32_t PLLIDF; /*!< PLL Input Division Factor
- This parameter can be any value of @ref DSI_PLL_IDF */
+ uint32_t PLLIDF; /*!< PLL Input Division Factor
+ This parameter can be any value of @ref DSI_PLL_IDF */
- uint32_t PLLODF; /*!< PLL Output Division Factor
- This parameter can be any value of @ref DSI_PLL_ODF */
+ uint32_t PLLODF; /*!< PLL Output Division Factor
+ This parameter can be any value of @ref DSI_PLL_ODF */
} DSI_PLLInitTypeDef;
@@ -346,6 +348,9 @@
typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DSI_Exported_Constants DSI Exported Constants
@@ -700,8 +705,8 @@
#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
-#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
- DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
+#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
+ DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
DSI_FLOW_CONTROL_EOTP_TX)
/**
* @}
@@ -841,18 +846,18 @@
* @{
*/
#define HAL_DSI_ERROR_NONE 0U
-#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */
-#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
-#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */
-#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */
-#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
-#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
-#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
-#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
-#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
-#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
+#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */
+#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */
+#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */
+#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */
+#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */
+#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */
+#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */
+#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */
+#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */
+#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
-#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
+#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
/**
* @}
@@ -912,6 +917,7 @@
* @}
*/
+
/**
* @}
*/
@@ -955,11 +961,11 @@
* @retval None.
*/
#define __HAL_DSI_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
- /* Delay after an DSI Host disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -968,11 +974,11 @@
* @retval None.
*/
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper enabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -981,11 +987,11 @@
* @retval None.
*/
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper disabling*/ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper disabling*/ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -994,11 +1000,11 @@
* @retval None.
*/
#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- /* Delay after an DSI PLL enabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1007,11 +1013,11 @@
* @retval None.
*/
#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- /* Delay after an DSI PLL disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1033,11 +1039,11 @@
* @retval None.
*/
#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
- __IO uint32_t tmpreg = 0x00U; \
- CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
- /* Delay after an DSI regulator disabling */ \
- tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
- UNUSED(tmpreg); \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
} while(0U)
/**
@@ -1121,23 +1127,41 @@
/** @defgroup DSI_Exported_Functions DSI Exported Functions
* @{
*/
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
-
-void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
-
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
pDSI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+/** @defgroup DSI_Group2 IO operation functions
+ * @brief IO operation functions
+ * @{
+ */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
+ * @{
+ */
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
@@ -1190,40 +1214,28 @@
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
+/**
+ * @}
+ */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ * @{
+ */
uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
-HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+
+/**
+ * @}
+ */
+
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
-/** @defgroup DSI_Private_Types DSI Private Types
- * @{
- */
-
-/**
- * @}
- */
-
/* Private defines -----------------------------------------------------------*/
-/** @defgroup DSI_Private_Defines DSI Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
/* Private variables ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Variables DSI Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
/* Private constants ---------------------------------------------------------*/
/** @defgroup DSI_Private_Constants DSI Private Constants
* @{
@@ -1249,45 +1261,73 @@
((ODF) == DSI_PLL_OUT_DIV2) || \
((ODF) == DSI_PLL_OUT_DIV4) || \
((ODF) == DSI_PLL_OUT_DIV8))
-#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
-#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\
+ || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\
+ || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
-#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
-#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
-#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
-#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\
+ || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
+#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
+ || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
+ || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
+ || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
((VideoModeType) == DSI_VID_MODE_BURST))
-#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
+#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\
+ || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
-#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
+#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\
+ || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
-#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
+#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\
+ || ((LPVActive) == DSI_LP_VACT_ENABLE))
#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
-#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
-#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
+#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\
+ || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
+#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\
+ || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
-#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
-#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
-#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
-#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
-#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
-#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
-#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
-#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
-#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
-#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
-#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
-#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
-#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
-#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
-#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
+#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\
+ || ((TEPolarity) == DSI_TE_FALLING_EDGE))
+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\
+ || ((AutomaticRefresh) == DSI_AR_ENABLE))
+#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\
+ || ((VSPolarity) == DSI_VSYNC_RISING))
+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\
+ || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\
+ || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\
+ || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
+#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\
+ || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
+#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\
+ || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
+#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\
+ || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
+#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\
+ || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
+#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\
+ || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
+#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\
+ || ((LP_GLW) == DSI_LP_GLW_ENABLE))
+#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\
+ || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
+#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\
+ || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
+#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\
+ || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
+#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\
+ || ((LP_DLW) == DSI_LP_DLW_ENABLE))
+#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\
+ || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
@@ -1299,10 +1339,14 @@
((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
-#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
+#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \
+ ((CommDelay) == DSI_SLEW_RATE_LPTX) || \
+ ((CommDelay) == DSI_HS_DELAY))
#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
-#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
-#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
+#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\
+ || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
+#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \
+ ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
((Timing) == DSI_TLPX_CLK ) || \
((Timing) == DSI_THS_EXIT ) || \
@@ -1317,24 +1361,6 @@
* @}
*/
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Functions DSI Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
/**
* @}
*/
@@ -1349,5 +1375,3 @@
#endif
#endif /* STM32F4xx_HAL_DSI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_eth.h b/Inc/stm32f4xx_hal_eth.h
index a0b0ad3..af84bcb 100644
--- a/Inc/stm32f4xx_hal_eth.h
+++ b/Inc/stm32f4xx_hal_eth.h
@@ -6,641 +6,589 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_ETH_H
-#define __STM32F4xx_HAL_ETH_H
+#ifndef STM32F4xx_HAL_ETH_H
+#define STM32F4xx_HAL_ETH_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
- defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
+#if defined(ETH)
+
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @addtogroup ETH
* @{
- */
-
-/** @addtogroup ETH_Private_Macros
- * @{
- */
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
-#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
- ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
-#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
- ((SPEED) == ETH_SPEED_100M))
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
- ((MODE) == ETH_MODE_HALFDUPLEX))
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
- ((MODE) == ETH_RXINTERRUPT_MODE))
-#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
- ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
-#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
- ((MODE) == ETH_MEDIA_INTERFACE_RMII))
-#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
- ((CMD) == ETH_WATCHDOG_DISABLE))
-#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
- ((CMD) == ETH_JABBER_DISABLE))
-#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_40BIT))
-#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
- ((CMD) == ETH_CARRIERSENCE_DISABLE))
-#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
- ((CMD) == ETH_RECEIVEOWN_DISABLE))
-#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
- ((CMD) == ETH_LOOPBACKMODE_DISABLE))
-#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
- ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
-#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
- ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
-#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
- ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
-#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_1))
-#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
- ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
-#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
- ((CMD) == ETH_RECEIVEAll_DISABLE))
-#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
-#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
-#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
- ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
-#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
- ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
-#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
- ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
-#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
-#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
-#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
- ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
-#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
-#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
- ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
-#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
-#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
-#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
- ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
-#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
- ((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
- ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
-#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
-#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
- ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
-#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
-#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
- ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
-#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
-#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
-#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
-#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
-#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
-#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
- ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
-#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
- ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
-#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
- ((CMD) == ETH_FIXEDBURST_DISABLE))
-#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
-#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
- ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
-#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
- ((FLAG) == ETH_DMATXDESC_IC) || \
- ((FLAG) == ETH_DMATXDESC_LS) || \
- ((FLAG) == ETH_DMATXDESC_FS) || \
- ((FLAG) == ETH_DMATXDESC_DC) || \
- ((FLAG) == ETH_DMATXDESC_DP) || \
- ((FLAG) == ETH_DMATXDESC_TTSE) || \
- ((FLAG) == ETH_DMATXDESC_TER) || \
- ((FLAG) == ETH_DMATXDESC_TCH) || \
- ((FLAG) == ETH_DMATXDESC_TTSS) || \
- ((FLAG) == ETH_DMATXDESC_IHE) || \
- ((FLAG) == ETH_DMATXDESC_ES) || \
- ((FLAG) == ETH_DMATXDESC_JT) || \
- ((FLAG) == ETH_DMATXDESC_FF) || \
- ((FLAG) == ETH_DMATXDESC_PCE) || \
- ((FLAG) == ETH_DMATXDESC_LCA) || \
- ((FLAG) == ETH_DMATXDESC_NC) || \
- ((FLAG) == ETH_DMATXDESC_LCO) || \
- ((FLAG) == ETH_DMATXDESC_EC) || \
- ((FLAG) == ETH_DMATXDESC_VF) || \
- ((FLAG) == ETH_DMATXDESC_CC) || \
- ((FLAG) == ETH_DMATXDESC_ED) || \
- ((FLAG) == ETH_DMATXDESC_UF) || \
- ((FLAG) == ETH_DMATXDESC_DB))
-#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
- ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
-#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
-#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
- ((FLAG) == ETH_DMARXDESC_AFM) || \
- ((FLAG) == ETH_DMARXDESC_ES) || \
- ((FLAG) == ETH_DMARXDESC_DE) || \
- ((FLAG) == ETH_DMARXDESC_SAF) || \
- ((FLAG) == ETH_DMARXDESC_LE) || \
- ((FLAG) == ETH_DMARXDESC_OE) || \
- ((FLAG) == ETH_DMARXDESC_VLAN) || \
- ((FLAG) == ETH_DMARXDESC_FS) || \
- ((FLAG) == ETH_DMARXDESC_LS) || \
- ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
- ((FLAG) == ETH_DMARXDESC_LC) || \
- ((FLAG) == ETH_DMARXDESC_FT) || \
- ((FLAG) == ETH_DMARXDESC_RWT) || \
- ((FLAG) == ETH_DMARXDESC_RE) || \
- ((FLAG) == ETH_DMARXDESC_DBE) || \
- ((FLAG) == ETH_DMARXDESC_CE) || \
- ((FLAG) == ETH_DMARXDESC_MAMPCE))
-#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
- ((BUFFER) == ETH_DMARXDESC_BUFFER2))
-#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
- ((FLAG) == ETH_PMT_FLAG_MPR))
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
-#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
- ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
- ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
- ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
- ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
- ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
- ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
- ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
- ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
- ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
- ((FLAG) == ETH_DMA_FLAG_T))
-#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
-#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
- ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
- ((IT) == ETH_MAC_IT_PMT))
-#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
- ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
- ((FLAG) == ETH_MAC_FLAG_PMT))
-#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
-#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
- ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
- ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
- ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
- ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
- ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
- ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
- ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
- ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
-#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
- ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
-#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
- ((IT) != 0x00U))
-#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
- ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
- ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
-#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
- ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
-
-/**
- * @}
*/
-/** @addtogroup ETH_Private_Defines
- * @{
- */
-/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY 0x00000001U
+/* Exported types ------------------------------------------------------------*/
+#ifndef ETH_TX_DESC_CNT
+#define ETH_TX_DESC_CNT 4U
+#endif /* ETH_TX_DESC_CNT */
-/* ETHERNET Errors */
-#define ETH_SUCCESS 0U
-#define ETH_ERROR 1U
+#ifndef ETH_RX_DESC_CNT
+#define ETH_RX_DESC_CNT 4U
+#endif /* ETH_RX_DESC_CNT */
-/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
-
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
-
-/* ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
-
-/* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
-
-/* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
-
-/* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
-
-/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8U
-
-/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
- /**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
+/*********************** Descriptors struct def section ************************/
/** @defgroup ETH_Exported_Types ETH Exported Types
* @{
*/
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
- HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
- HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
- HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
- HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_ETH_StateTypeDef;
-
-/**
- * @brief ETH Init Structure definition
+/**
+ * @brief ETH DMA Descriptor structure definition
*/
-
typedef struct
{
- uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
- The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
- and the mode (half/full-duplex).
- This parameter can be a value of @ref ETH_AutoNegotiation */
+ __IO uint32_t DESC0;
+ __IO uint32_t DESC1;
+ __IO uint32_t DESC2;
+ __IO uint32_t DESC3;
+ __IO uint32_t DESC4;
+ __IO uint32_t DESC5;
+ __IO uint32_t DESC6;
+ __IO uint32_t DESC7;
+ uint32_t BackupAddr0; /* used to store rx buffer 1 address */
+ uint32_t BackupAddr1; /* used to store rx buffer 2 address */
+} ETH_DMADescTypeDef;
+/**
+ *
+ */
- uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
+/**
+ * @brief ETH Buffers List structure definition
+ */
+typedef struct __ETH_BufferTypeDef
+{
+ uint8_t *buffer; /*<! buffer address */
+
+ uint32_t len; /*<! buffer length */
+
+ struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
+} ETH_BufferTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief DMA Transmit Descriptors Wrapper structure definition
+ */
+typedef struct
+{
+ uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */
+
+ uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
+
+ uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */
+
+ uint32_t *CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */
+
+ uint32_t BuffersInUse; /*<! Buffers in Use */
+
+ uint32_t releaseIndex; /*<! Release index */
+} ETH_TxDescListTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief Transmit Packet Configuration structure definition
+ */
+typedef struct
+{
+ uint32_t Attributes; /*!< Tx packet HW features capabilities.
+ This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
+
+ uint32_t Length; /*!< Total packet length */
+
+ ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */
+
+ uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control.
+ This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
+
+ uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control.
+ This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */
+
+ uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control.
+ This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */
+
+ uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
+ This parameter can be a value from 0x0 to 0x3FFF */
+
+ uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled.
+ This parameter can be a value from 0x0 to 0x3FFFF */
+
+ uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled.
+ This parameter can be a value from 0x5 to 0xF */
+
+ uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled.
+ This parameter can be a value from 0x0 to 0xFFFF*/
+
+ uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
+ This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
+
+ uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
+ This parameter can be a value from 0x0 to 0x3FFFF */
+
+ uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
+ This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */
+
+ void *pData; /*!< Specifies Application packet pointer to save */
+
+} ETH_TxPacketConfig;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Timestamp structure definition
+ */
+typedef struct
+{
+ uint32_t TimeStampLow;
+ uint32_t TimeStampHigh;
+
+} ETH_TimeStampTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Timeupdate structure definition
+ */
+typedef struct
+{
+ uint32_t Seconds;
+ uint32_t NanoSeconds;
+} ETH_TimeTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief DMA Receive Descriptors Wrapper structure definition
+ */
+typedef struct
+{
+ uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */
+
+ uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
+ If 0, DMA will not generate the Rx complete interrupt. */
+
+ uint32_t RxDescIdx; /*<! Current Rx descriptor. */
+
+ uint32_t RxDescCnt; /*<! Number of descriptors . */
+
+ uint32_t RxDataLength; /*<! Received Data Length. */
+
+ uint32_t RxBuildDescIdx; /*<! Current Rx Descriptor for building descriptors. */
+
+ uint32_t RxBuildDescCnt; /*<! Number of Rx Descriptors awaiting building. */
+
+ uint32_t pRxLastRxDesc; /*<! Last received descriptor. */
+
+ ETH_TimeStampTypeDef TimeStamp; /*<! Time Stamp Low value for receive. */
+
+ void *pRxStart; /*<! Pointer to the first buff. */
+
+ void *pRxEnd; /*<! Pointer to the last buff. */
+
+} ETH_RxDescListTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH MAC Configuration Structure definition
+ */
+typedef struct
+{
+ uint32_t
+ SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control.
+ This parameter can be a value of @ref ETH_Source_Addr_Control */
+
+ FunctionalState
+ ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
+
+ uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission.
+ This parameter can be a value of @ref ETH_Inter_Packet_Gap */
+
+ FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
+
+ FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
+
+ FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/
+
+ FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/
+
+ FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path.*/
+
+ FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path.*/
+
+ FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet
+ When enabled, the MAC allows jumbo packets of 9,018 bytes
+ without reporting a giant packet error */
+
+ uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
This parameter can be a value of @ref ETH_Speed */
- uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+ uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref ETH_Duplex_Mode */
-
- uint16_t PhyAddress; /*!< Ethernet PHY address.
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-
- uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-
- uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
- This parameter can be a value of @ref ETH_Rx_Mode */
-
- uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
- This parameter can be a value of @ref ETH_Checksum_Mode */
-
- uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
- This parameter can be a value of @ref ETH_Media_Interface */
-} ETH_InitTypeDef;
+ FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */
+ FunctionalState
+ CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
- /**
- * @brief ETH MAC Configuration Structure definition
+ FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */
+
+ FunctionalState
+ CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
+
+ FunctionalState
+ RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
+
+ uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
+ This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+ FunctionalState
+ DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */
+
+ uint32_t
+ PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
+ This parameter can be a value of @ref ETH_Preamble_Length */
+
+ FunctionalState
+ UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
+
+ FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */
+
+ FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */
+
+ uint32_t
+ GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
+ greater than the value programmed in this field in units of bytes
+ This parameter must be a number between
+ Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
+
+ FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */
+
+ uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission.
+ This parameter can be a value from 0x0 to 0xFF */
+
+ FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/
+
+ uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet
+ This parameter can be a value of @ref ETH_Watchdog_Timeout */
+
+ uint32_t
+ PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
+ This parameter must be a number between
+ Min_Data = 0x0 and Max_Data = 0xFFFF.*/
+
+ FunctionalState
+ ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
+
+ uint32_t
+ PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+ FunctionalState
+ TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
+ or the MAC back pressure operation in Half Duplex mode */
+
+ FunctionalState
+ UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
+
+ FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet
+ and disables its transmitter for a specified (Pause) time */
+
+ uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode.
+ This parameter can be a value of @ref ETH_Transmit_Mode */
+
+ uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode.
+ This parameter can be a value of @ref ETH_Receive_Mode */
+
+ FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
+
+ FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */
+
+ FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/
+} ETH_MACConfigTypeDef;
+/**
+ *
*/
-typedef struct
-{
- uint32_t Watchdog; /*!< Selects or not the Watchdog timer
- When enabled, the MAC allows no more then 2048 bytes to be received.
- When disabled, the MAC can receive up to 16384 bytes.
- This parameter can be a value of @ref ETH_Watchdog */
-
- uint32_t Jabber; /*!< Selects or not Jabber timer
- When enabled, the MAC allows no more then 2048 bytes to be sent.
- When disabled, the MAC can send up to 16384 bytes.
- This parameter can be a value of @ref ETH_Jabber */
-
- uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
- This parameter can be a value of @ref ETH_Inter_Frame_Gap */
-
- uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
- This parameter can be a value of @ref ETH_Carrier_Sense */
-
- uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
- ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
- in Half-Duplex mode.
- This parameter can be a value of @ref ETH_Receive_Own */
-
- uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
- This parameter can be a value of @ref ETH_Loop_Back_Mode */
-
- uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
- This parameter can be a value of @ref ETH_Checksum_Offload */
-
- uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
- when a collision occurs (Half-Duplex mode).
- This parameter can be a value of @ref ETH_Retry_Transmission */
-
- uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
- This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
-
- uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
- This parameter can be a value of @ref ETH_Back_Off_Limit */
-
- uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
- This parameter can be a value of @ref ETH_Deferral_Check */
-
- uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
- This parameter can be a value of @ref ETH_Receive_All */
-
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
- This parameter can be a value of @ref ETH_Source_Addr_Filter */
-
- uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
- This parameter can be a value of @ref ETH_Pass_Control_Frames */
-
- uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
- This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
-
- uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
- This parameter can be a value of @ref ETH_Destination_Addr_Filter */
-
- uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
- This parameter can be a value of @ref ETH_Promiscuous_Mode */
-
- uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
-
- uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
-
- uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
-
- uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
-
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
-
- uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
- This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
-
- uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
- automatic retransmission of PAUSE Frame.
- This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-
- uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
- unicast address and unique multicast address).
- This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
-
- uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
- disable its transmitter for a specified time (Pause Time)
- This parameter can be a value of @ref ETH_Receive_Flow_Control */
-
- uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
- or the MAC back-pressure operation (Half-Duplex mode)
- This parameter can be a value of @ref ETH_Transmit_Flow_Control */
-
- uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
- comparison and filtering.
- This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
-
- uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
-
-} ETH_MACInitTypeDef;
-
-/**
- * @brief ETH DMA Configuration Structure definition
+/**
+ * @brief ETH DMA Configuration Structure definition
*/
-
typedef struct
{
- uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
- This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+ uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
- uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
- This parameter can be a value of @ref ETH_Receive_Store_Forward */
+ FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned
+ burst transfers on Read and Write channels */
- uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
- This parameter can be a value of @ref ETH_Flush_Received_Frame */
+ uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
+ This parameter can be a value of @ref ETH_Burst_Mode */
- uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
- This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+ FunctionalState DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames */
+
+ FunctionalState ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode */
+
+ FunctionalState TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode */
+
+
+ uint32_t
+ TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
- This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
+ This parameter can be a value of
+ @ref ETH_Transmit_Threshold_Control */
- uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
- This parameter can be a value of @ref ETH_Forward_Error_Frames */
+ uint32_t
+ RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
- uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
- and length less than 64 bytes) including pad-bytes and CRC)
- This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
+ FunctionalState ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames */
+ FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */
+
+ FunctionalState
+ ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
+ and length less than 64 bytes)
+ including pad-bytes and CRC) */
uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
- This parameter can be a value of @ref ETH_Receive_Threshold_Control */
+ This parameter can be a value of
+ @ref ETH_Receive_Threshold_Control */
- uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
- frame of Transmit data even before obtaining the status for the first frame.
- This parameter can be a value of @ref ETH_Second_Frame_Operate */
+ FunctionalState
+ SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
+ frame of Transmit data even before obtaining
+ the status for the first frame */
- uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
- This parameter can be a value of @ref ETH_Address_Aligned_Beats */
+ FunctionalState EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format */
- uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
- This parameter can be a value of @ref ETH_Fixed_Burst */
-
- uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
- This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
-
- uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
- This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
-
- uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
- This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
-
- uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-
- uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
- This parameter can be a value of @ref ETH_DMA_Arbitration */
-} ETH_DMAInitTypeDef;
-
-
-/**
- * @brief ETH DMA Descriptors data structure definition
- */
-
-typedef struct
-{
- __IO uint32_t Status; /*!< Status */
-
- uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
-
- uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
-
- uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
-
- /*!< Enhanced ETHERNET DMA PTP Descriptors */
- uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
-
- uint32_t Reserved1; /*!< Reserved */
-
- uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
-
- uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
-
-} ETH_DMADescTypeDef;
-
-/**
- * @brief Received Frame Informations structure definition
- */
-typedef struct
-{
- ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
-
- ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
-
- uint32_t SegCount; /*!< Segment count */
-
- uint32_t length; /*!< Frame length */
-
- uint32_t buffer; /*!< Frame buffer */
-
-} ETH_DMARxFrameInfos;
-
-/**
- * @brief ETH Handle Structure definition
+ uint32_t
+ DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
+ This parameter must be a number between
+ Min_Data = 0 and Max_Data = 32 */
+} ETH_DMAConfigTypeDef;
+/**
+ *
*/
-
+
+/**
+ * @brief HAL ETH Media Interfaces enum definition
+ */
+typedef enum
+{
+ HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */
+ HAL_ETH_RMII_MODE = ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) /*!< Reduced Media Independent Interface */
+} ETH_MediaInterfaceTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH PTP Update type enum definition
+ */
+typedef enum
+{
+ HAL_ETH_PTP_POSITIVE_UPDATE = 0x00000000U, /*!< PTP positive time update */
+ HAL_ETH_PTP_NEGATIVE_UPDATE = 0x00000001U /*!< PTP negative time update */
+} ETH_PtpUpdateTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Init Structure definition
+ */
+typedef struct
+{
+
+ uint8_t
+ *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+ ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */
+
+ ETH_DMADescTypeDef
+ *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */
+
+ ETH_DMADescTypeDef
+ *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */
+
+ uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */
+
+} ETH_InitTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH PTP Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Timestamp; /*!< Enable Timestamp */
+ uint32_t TimestampUpdateMode; /*!< Fine or Coarse Timestamp Update */
+ uint32_t TimestampInitialize; /*!< Initialize Timestamp */
+ uint32_t TimestampUpdate; /*!< Timestamp Update */
+ uint32_t TimestampAddendUpdate; /*!< Timestamp Addend Update */
+ uint32_t TimestampAll; /*!< Enable Timestamp for All Packets */
+ uint32_t TimestampRolloverMode; /*!< Timestamp Digital or Binary Rollover Control */
+ uint32_t TimestampV2; /*!< Enable PTP Packet Processing for Version 2 Format */
+ uint32_t TimestampEthernet; /*!< Enable Processing of PTP over Ethernet Packets */
+ uint32_t TimestampIPv6; /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
+ uint32_t TimestampIPv4; /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
+ uint32_t TimestampEvent; /*!< Enable Timestamp Snapshot for Event Messages */
+ uint32_t TimestampMaster; /*!< Enable Timestamp Snapshot for Event Messages */
+ uint32_t TimestampFilter; /*!< Enable MAC Address for PTP Packet Filtering */
+ uint32_t TimestampClockType; /*!< Time stamp clock node type */
+ uint32_t TimestampAddend; /*!< Timestamp addend value */
+ uint32_t TimestampSubsecondInc; /*!< Subsecond Increment */
+
+} ETH_PTP_ConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef uint32_t HAL_ETH_StateTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Rx Get Buffer Function definition
+ */
+typedef void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer); /*!< pointer to an ETH Rx Get Buffer Function */
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Rx Set App Data Function definition
+ */
+typedef void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
+ uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Tx Free Function definition
+ */
+typedef void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer); /*!< pointer to an ETH Tx Free function */
+/**
+ *
+ */
+
+/**
+ * @brief HAL ETH Tx Free Function definition
+ */
+typedef void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
+ ETH_TimeStampTypeDef *timestamp); /*!< pointer to an ETH Tx Free function */
+/**
+ *
+ */
+
+/**
+ * @brief ETH Handle Structure definition
+ */
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
typedef struct __ETH_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
{
- ETH_TypeDef *Instance; /*!< Register base address */
-
- ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
-
- uint32_t LinkStatus; /*!< Ethernet link status */
-
- ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
-
- ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
-
- ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
-
- __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
-
- HAL_LockTypeDef Lock; /*!< ETH Lock */
+ ETH_TypeDef *Instance; /*!< Register base address */
+
+ ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
+
+ ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list
+ addresses and current descriptor index */
+
+ ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list
+ addresses and current descriptor index */
+
+#ifdef HAL_ETH_USE_PTP
+ ETH_TimeStampTypeDef TxTimestamp; /*!< Tx Timestamp */
+#endif /* HAL_ETH_USE_PTP */
+
+ __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
+ and also related to Tx operations. This parameter can
+ be a value of @ref HAL_ETH_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
+ This parameter can be a value of @ref ETH_Error_Code.*/
+
+ __IO uint32_t
+ DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
+ This parameter can be a combination of
+ @ref ETH_DMA_Status_Flags */
+
+ __IO uint32_t
+ MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
+ This parameter can be a combination of
+ @ref ETH_MAC_Rx_Tx_Status */
+
+ __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode
+ This parameter can be a value of
+ @ref ETH_MAC_Wake_Up_Event */
+
+ __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs.
+ This parameter can be a value of @ref ETHEx_LPI_Event */
+
+ __IO uint32_t IsPtpConfigured; /*!< Holds the PTP configuration status.
+ This parameter can be a value of
+ @ref ETH_PTP_Config_Status */
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
- void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
- void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */
- void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
- void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
+ void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */
+ void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */
+ void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Error Callback */
+ void (* PMTCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Power Management Callback */
+ void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Wake UP Callback */
+
+ void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */
+ void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+ pETH_rxAllocateCallbackTypeDef rxAllocateCallback; /*!< ETH Rx Get Buffer Function */
+ pETH_rxLinkCallbackTypeDef rxLinkCallback; /*!< ETH Rx Set App Data Function */
+ pETH_txFreeCallbackTypeDef txFreeCallback; /*!< ETH Tx Free Function */
+ pETH_txPtpCallbackTypeDef txPtpCallback; /*!< ETH Tx Handle Ptp Function */
+
} ETH_HandleTypeDef;
+/**
+ *
+ */
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/**
@@ -648,22 +596,76 @@
*/
typedef enum
{
- HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
- HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
- HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
- HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
- HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
+ HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
+ HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
-}HAL_ETH_CallbackIDTypeDef;
+ HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
+ HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
+ HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */
+ HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */
+ HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
+
+
+} HAL_ETH_CallbackIDTypeDef;
/**
* @brief HAL ETH Callback pointer definition
*/
-typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
- /**
+/**
+ * @brief ETH MAC filter structure definition
+ */
+typedef struct
+{
+ FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */
+
+ FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */
+
+ FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
+
+ FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */
+
+ FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */
+
+ FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */
+
+ FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */
+
+ FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */
+
+ FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
+
+ FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */
+
+ uint32_t ControlPacketsFilter; /*!< Set the control packets filter
+ This parameter can be a value of @ref ETH_Control_Packets_Filter */
+} ETH_MACFilterConfigTypeDef;
+/**
+ *
+ */
+
+/**
+ * @brief ETH Power Down structure definition
+ */
+typedef struct
+{
+ FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */
+
+ FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */
+
+ FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */
+
+ FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */
+
+} ETH_PowerDownConfigTypeDef;
+/**
+ *
+ */
+
+/**
* @}
*/
@@ -672,81 +674,12 @@
* @{
*/
-/** @defgroup ETH_Buffers_setting ETH Buffers setting
- * @{
- */
-#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC 4U /*!< Ethernet CRC */
-#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
-#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
-
- /* Ethernet driver receive buffers are organized in a chained linked-list, when
- an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
- to the driver receive buffers memory.
-
- Depending on the size of the received ethernet packet and the size of
- each ethernet driver receive buffer, the received packet can take one or more
- ethernet driver receive buffer.
-
- In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
- and the total count of the driver receive buffers ETH_RXBUFNB.
-
- The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
-
-/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
- packet */
-#ifndef ETH_RX_BUF_SIZE
- #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
-#endif
-
-/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
-#ifndef ETH_RXBUFNB
- #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
-#endif
-
-
- /* Ethernet driver transmit buffers are organized in a chained linked-list, when
- an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
- driver transmit buffers memory to the TxFIFO.
-
- Depending on the size of the Ethernet packet to be transmitted and the size of
- each ethernet driver transmit buffer, the packet to be transmitted can take
- one or more ethernet driver transmit buffer.
-
- In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
- and the total count of the driver transmit buffers ETH_TXBUFNB.
-
- The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
-
-/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
- packet */
-#ifndef ETH_TX_BUF_SIZE
- #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
-#endif
-
-/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
-#ifndef ETH_TXBUFNB
- #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
-#endif
-
- /**
- * @}
- */
-
-/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
+/** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
* @{
*/
/*
- DMA Tx Descriptor
+ DMA Tx Normal Descriptor Read Format
-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-----------------------------------------------------------------------------------------------
@@ -758,76 +691,78 @@
-----------------------------------------------------------------------------------------------
*/
-/**
+/**
* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
- */
-#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
-#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
-#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
-#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
-#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
-#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
+ */
+#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */
+#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */
+#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */
+#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */
+#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */
+#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */
-/**
+/**
* @brief Bit definition of TDES1 register
- */
-#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
+ */
+#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */
-/**
+/**
* @brief Bit definition of TDES2 register
- */
-#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+ */
+#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
-/**
+/**
* @brief Bit definition of TDES3 register
- */
-#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+ */
+#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
- /*---------------------------------------------------------------------------------------------
- TDES6 | Transmit Time Stamp Low [31:0] |
- -----------------------------------------------------------------------------------------------
- TDES7 | Transmit Time Stamp High [31:0] |
- ----------------------------------------------------------------------------------------------*/
+/*---------------------------------------------------------------------------------------------
+TDES6 | Transmit Time Stamp Low [31:0] |
+-----------------------------------------------------------------------------------------------
+TDES7 | Transmit Time Stamp High [31:0] |
+----------------------------------------------------------------------------------------------*/
/* Bit definition of TDES6 register */
- #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
+#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */
/* Bit definition of TDES7 register */
- #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
+#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */
/**
* @}
- */
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
+ */
+
+
+/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
* @{
*/
/*
- DMA Rx Descriptor
+ DMA Rx Normal Descriptor read format
--------------------------------------------------------------------------------------------------------------------
RDES0 | OWN(31) | Status [30:0] |
---------------------------------------------------------------------------------------------------------------------
@@ -839,47 +774,47 @@
---------------------------------------------------------------------------------------------------------------------
*/
-/**
+/**
* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
- */
-#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
-#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
-#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
-#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
-#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
-#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
-#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+ */
+#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-/**
+/**
* @brief Bit definition of RDES1 register
- */
-#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
+ */
+#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */
-/**
- * @brief Bit definition of RDES2 register
- */
-#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
+/**
+ * @brief Bit definition of RDES2 register
+ */
+#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */
-/**
- * @brief Bit definition of RDES3 register
- */
-#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
+/**
+ * @brief Bit definition of RDES3 register
+ */
+#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
/*---------------------------------------------------------------------------------------------------------------------
RDES4 | Reserved[31:15] | Extended Status [14:0] |
@@ -892,489 +827,210 @@
--------------------------------------------------------------------------------------------------------------------*/
/* Bit definition of RDES4 register */
-#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
-#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
-#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
- #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
- #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
- #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
- #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
- #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
- #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
- #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
-#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
-#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
-#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
-#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
-#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
-#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
- #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
- #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
- #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
+#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */
+#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */
+#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */
+#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message
+ (all clock types) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message
+ (peer-to-peer transparent clock)
+ or Announce message (Ordinary
+ or Boundary clock) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message
+ (peer-to-peer transparent clock)
+ or Management message (Ordinary
+ or Boundary clock) */
+#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message
+ (peer-to-peer transparent clock)
+ or Signaling message (Ordinary
+ or Boundary clock) */
+#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */
+#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */
+#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */
+#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */
+#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */
+#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */
+#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in
+ the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in
+ the IP datagram */
+#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in
+ the IP datagram */
/* Bit definition of RDES6 register */
-#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
+#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */
/* Bit definition of RDES7 register */
-#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
-/**
- * @}
- */
- /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
- * @{
- */
-#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
-#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
+#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */
/**
* @}
*/
-/** @defgroup ETH_Speed ETH Speed
- * @{
- */
-#define ETH_SPEED_10M 0x00000000U
-#define ETH_SPEED_100M 0x00004000U
-/**
- * @}
- */
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+/** @defgroup ETH_Frame_settings ETH frame settings
* @{
- */
-#define ETH_MODE_FULLDUPLEX 0x00000800U
-#define ETH_MODE_HALFDUPLEX 0x00000000U
-/**
- * @}
*/
-/** @defgroup ETH_Rx_Mode ETH Rx Mode
- * @{
- */
-#define ETH_RXPOLLING_MODE 0x00000000U
-#define ETH_RXINTERRUPT_MODE 0x00000001U
+#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
+#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
+#define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
/**
* @}
*/
-/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
+/** @defgroup ETH_Error_Code ETH Error Code
* @{
- */
-#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
-#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
+ */
+#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
+#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */
+#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */
+#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
+#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
+#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @defgroup ETH_Media_Interface ETH Media Interface
+/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
* @{
- */
-#define ETH_MEDIA_INTERFACE_MII 0x00000000U
-#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+ */
+#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
+#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
+#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
+#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
+#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
+#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
/**
* @}
*/
-/** @defgroup ETH_Watchdog ETH Watchdog
+/** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
* @{
- */
-#define ETH_WATCHDOG_ENABLE 0x00000000U
-#define ETH_WATCHDOG_DISABLE 0x00800000U
+ */
+#define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
+#define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
+#define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
/**
* @}
*/
-/** @defgroup ETH_Jabber ETH Jabber
+/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
* @{
- */
-#define ETH_JABBER_ENABLE 0x00000000U
-#define ETH_JABBER_DISABLE 0x00400000U
+ */
+#define ETH_CRC_PAD_DISABLE (uint32_t)(ETH_DMATXDESC_DP | ETH_DMATXDESC_DC)
+#define ETH_CRC_PAD_INSERT ((uint32_t)0x00000000U)
+#define ETH_CRC_INSERT ETH_DMATXDESC_DP
/**
* @}
*/
-/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
+/** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
* @{
- */
-#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
+ */
+#define ETH_CHECKSUM_DISABLE ETH_DMATXDESC_CIC_BYPASS
+#define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXDESC_CIC_IPV4HEADER
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXDESC_CIC_TCPUDPICMP_FULL
/**
* @}
*/
-/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
+/** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
* @{
- */
-#define ETH_CARRIERSENCE_ENABLE 0x00000000U
-#define ETH_CARRIERSENCE_DISABLE 0x00010000U
+ */
+#define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
+#define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
+#define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
+#define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
/**
* @}
*/
-/** @defgroup ETH_Receive_Own ETH Receive Own
+/** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
* @{
- */
-#define ETH_RECEIVEOWN_ENABLE 0x00000000U
-#define ETH_RECEIVEOWN_DISABLE 0x00002000U
+ */
+#define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
+#define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
+#define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
+#define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
/**
* @}
*/
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+
+/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
* @{
- */
-#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
-#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
+ */
+#define ETH_VLAN_FILTER_PASS ETH_DMARXDESC_VLAN
+#define ETH_DEST_ADDRESS_FAIL ETH_DMARXDESC_AFM
+#define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXDESC_SAF
/**
* @}
*/
-/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
+/** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
* @{
- */
-#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
-#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
+ */
+#define ETH_DRIBBLE_BIT_ERROR ETH_DMARXDESC_DBE
+#define ETH_RECEIVE_ERROR ETH_DMARXDESC_RE
+#define ETH_RECEIVE_OVERFLOW ETH_DMARXDESC_OE
+#define ETH_WATCHDOG_TIMEOUT ETH_DMARXDESC_RWT
+#define ETH_GIANT_PACKET ETH_DMARXDESC_IPV4HC
+#define ETH_CRC_ERROR ETH_DMARXDESC_CE
/**
* @}
*/
-/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
- */
-#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
-#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
+ */
+#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
+#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
+#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
+#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
+#define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
+#define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
+#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
+#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
+#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
+#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
+#define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
+#define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
+#define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
+#define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
+#define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
+#define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
/**
* @}
*/
-/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
- * @{
- */
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
- * @{
- */
-#define ETH_BACKOFFLIMIT_10 0x00000000U
-#define ETH_BACKOFFLIMIT_8 0x00000020U
-#define ETH_BACKOFFLIMIT_4 0x00000040U
-#define ETH_BACKOFFLIMIT_1 0x00000060U
-/**
- * @}
- */
-
-/** @defgroup ETH_Deferral_Check ETH Deferral Check
+/** @defgroup ETH_Burst_Mode ETH Burst Mode
* @{
*/
-#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
-#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_All ETH Receive All
- * @{
- */
-#define ETH_RECEIVEALL_ENABLE 0x80000000U
-#define ETH_RECEIVEAll_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
- * @{
- */
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
-#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
- * @{
- */
-#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
-/**
- * @}
- */
-
-/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
- * @{
- */
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
-/**
- * @}
- */
-
-/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
- * @{
- */
-#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
-#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
- * @{
- */
-#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
-#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
- * @{
- */
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
-#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
-#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
- * @{
- */
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
-#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
- * @{
- */
-#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
-#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
-/**
- * @}
- */
-
-/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
- * @{
- */
-#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
- * @{
- */
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
- * @{
- */
-#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
-#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
- * @{
- */
-#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
-#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
- * @{
- */
-#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
-#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses ETH MAC addresses
- * @{
- */
-#define ETH_MAC_ADDRESS0 0x00000000U
-#define ETH_MAC_ADDRESS1 0x00000008U
-#define ETH_MAC_ADDRESS2 0x00000010U
-#define ETH_MAC_ADDRESS3 0x00000018U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
- * @{
- */
-#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
-#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
- * @{
- */
-#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
-/**
- * @}
- */
-
-/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
- * @{
- */
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
- * @{
- */
-#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
-#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
- * @{
- */
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
- * @{
- */
-#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
-#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
- * @{
- */
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
- * @{
- */
-#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
-#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
- * @{
- */
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
- * @{
- */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-/**
- * @}
- */
-
-/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
- * @{
- */
-#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
-#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
- * @{
- */
-#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
-#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
- * @{
- */
-#define ETH_FIXEDBURST_ENABLE 0x00010000U
-#define ETH_FIXEDBURST_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
- * @{
- */
-#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_BURSTLENGTH_FIXED ETH_DMABMR_FB
+#define ETH_BURSTLENGTH_MIXED ETH_DMABMR_MB
+#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
/**
* @}
*/
/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
* @{
- */
+ */
#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
@@ -1391,18 +1047,579 @@
* @}
*/
-/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
* @{
- */
-#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
-#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
+ */
+#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+ * @{
+ */
+#define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
+#define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
+#define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
+#define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
+#define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
+#define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
+#define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
+#define ETH_DMA_RX_IT ETH_DMACIER_RIE
+#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
+#define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
+#define ETH_DMA_TX_IT ETH_DMACIER_TIE
+/**
+ * @}
+ */
+
+/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
+ * @{
+ */
+#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
+#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
+#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
+#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
+#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
+#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
+#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
+#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
+#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
+#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
+#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
+#define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
+#define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
+#define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
+#define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
+ * @{
+ */
+#define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
+#define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
+#define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
+#define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
+#define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
+#define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
+#define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
+#define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
+#define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Mode ETH Receive Mode
+ * @{
+ */
+#define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
+#define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
+#define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
+#define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
+#define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
+#define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
+#define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
+#define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
+#define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
+#define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
+ * @{
+ */
+#define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
+#define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
+#define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
+#define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
+#define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
+#define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
+#define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
+#define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
+#define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
+#define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
+#define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
+#define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
+#define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
+ * @{
+ */
+#define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
+#define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
+#define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
+#define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
+#define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
+#define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
+#define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
+#define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Speed ETH Speed
+ * @{
+ */
+#define ETH_SPEED_10M ((uint32_t)0x00000000U)
+#define ETH_SPEED_100M 0x00004000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+ * @{
+ */
+#define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
+#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
+ * @{
+ */
+#define ETH_BACKOFFLIMIT_10 0x00000000U
+#define ETH_BACKOFFLIMIT_8 0x00000020U
+#define ETH_BACKOFFLIMIT_4 0x00000040U
+#define ETH_BACKOFFLIMIT_1 0x00000060U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Preamble_Length ETH Preamble Length
+ * @{
+ */
+#define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
+#define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
+#define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
+ * @{
+ */
+#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
+#define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
+#define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
+#define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
+#define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
+ * @{
+ */
+#define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
+#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
+#define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
+#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
+/**
+ * @}
+ */
+
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
+ * @{
+ */
+#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
+#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
+ * @{
+ */
+#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
+#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
+#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
+#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+ * @{
+ */
+#define ETH_MAC_PMT_IT ETH_MACSR_PMTS
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
+ * @{
+ */
+#define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
+#define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
+ * @{
+ */
+#define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
+#define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
+#define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
+#define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
+#define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
+#define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
+#define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
+/**
+ * @}
+ */
+
+/** @defgroup HAL_ETH_StateTypeDef ETH States
+ * @{
+ */
+#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */
+#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */
+#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */
+#define HAL_ETH_STATE_STARTED ((uint32_t)0x00000023U) /*!< an internal process is started */
+#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
+ * @{
+ */
+#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
+#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
+
+/**
+ * @}
+ */
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
+ * @{
+ */
+#define ETH_RXPOLLING_MODE 0x00000000U
+#define ETH_RXINTERRUPT_MODE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
+ * @{
+ */
+#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
+#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Media_Interface ETH Media Interface
+ * @{
+ */
+#define ETH_MEDIA_INTERFACE_MII 0x00000000U
+#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Watchdog ETH Watchdog
+ * @{
+ */
+#define ETH_WATCHDOG_ENABLE 0x00000000U
+#define ETH_WATCHDOG_DISABLE 0x00800000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Jabber ETH Jabber
+ * @{
+ */
+#define ETH_JABBER_ENABLE 0x00000000U
+#define ETH_JABBER_DISABLE 0x00400000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
+ * @{
+ */
+#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
+ * @{
+ */
+#define ETH_CARRIERSENCE_ENABLE 0x00000000U
+#define ETH_CARRIERSENCE_DISABLE 0x00010000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Own ETH Receive Own
+ * @{
+ */
+#define ETH_RECEIVEOWN_ENABLE 0x00000000U
+#define ETH_RECEIVEOWN_DISABLE 0x00002000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+ * @{
+ */
+#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
+#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
+ * @{
+ */
+#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
+#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
+ * @{
+ */
+#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
+#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
+ * @{
+ */
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Deferral_Check ETH Deferral Check
+ * @{
+ */
+#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
+#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_All ETH Receive All
+ * @{
+ */
+#define ETH_RECEIVEALL_ENABLE 0x80000000U
+#define ETH_RECEIVEALL_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
+ * @{
+ */
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
+#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
+ * @{
+ */
+#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
+ * @{
+ */
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
+ * @{
+ */
+#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
+#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
+ * @{
+ */
+#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
+#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
+ * @{
+ */
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
+#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
+#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
+ * @{
+ */
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
+#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
+ * @{
+ */
+#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
+#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
+ * @{
+ */
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
+ * @{
+ */
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
+ * @{
+ */
+#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
+#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
+ * @{
+ */
+#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
+#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
+ * @{
+ */
+#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
+#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
+/**
+ * @}
+ */
+
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
+ * @{
+ */
+#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
+ * @{
+ */
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
+/**
+ * @}
+ */
+
+/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
+ * @{
+ */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
/**
* @}
*/
/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
- */
+ */
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
@@ -1414,7 +1631,7 @@
/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
* @{
- */
+ */
#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
/**
@@ -1423,7 +1640,7 @@
/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
* @{
- */
+ */
#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
@@ -1432,9 +1649,9 @@
* @}
*/
-/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
* @{
- */
+ */
#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
/**
@@ -1443,7 +1660,7 @@
/** @defgroup ETH_PMT_Flags ETH PMT Flags
* @{
- */
+ */
#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
@@ -1453,7 +1670,7 @@
/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
* @{
- */
+ */
#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
@@ -1473,7 +1690,7 @@
/** @defgroup ETH_MAC_Flags ETH MAC Flags
* @{
- */
+ */
#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
@@ -1485,7 +1702,7 @@
/** @defgroup ETH_DMA_Flags ETH DMA Flags
* @{
- */
+ */
#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
@@ -1511,9 +1728,9 @@
* @}
*/
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
* @{
- */
+ */
#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
@@ -1523,9 +1740,9 @@
* @}
*/
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
- */
+ */
#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
@@ -1548,9 +1765,9 @@
* @}
*/
-/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
* @{
- */
+ */
#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
@@ -1560,12 +1777,12 @@
/**
* @}
- */
+ */
-/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
* @{
- */
+ */
#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
@@ -1579,611 +1796,330 @@
/** @defgroup ETH_DMA_overflow ETH DMA overflow
* @{
- */
+ */
#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
/**
* @}
- */
-
-/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+ */
+/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
* @{
- */
-#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
-
+ */
+#define HAL_ETH_PTP_NOT_CONFIGURATED ((uint32_t)0x00000000U) /*!< ETH PTP Configuration not done */
+#define HAL_ETH_PTP_CONFIGURATED ((uint32_t)0x00000001U) /*!< ETH PTP Configuration done */
/**
* @}
*/
-
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ETH_Exported_Macros ETH Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
+ * @{
+ */
+
/** @brief Reset ETH handle state
- * @param __HANDLE__ specifies the ETH handle.
+ * @param __HANDLE__: specifies the ETH handle.
* @retval None
*/
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
+ } while(0)
#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
-/**
- * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag of TDES0 to check.
- * @retval the ETH_DMATxDescFlag (SET or RESET).
- */
-#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
-
/**
- * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag of RDES0 to check.
- * @retval the ETH_DMATxDescFlag (SET or RESET).
- */
-#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
-
-/**
- * @brief Enables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
-
-/**
- * @brief Disables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
-
-/**
- * @brief Set the specified DMA Rx Desc Own bit.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
-
-/**
- * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
- * @param __HANDLE__ ETH Handle
- * @retval The Transmit descriptor collision counter value.
- */
-#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
-
-/**
- * @brief Set the specified DMA Tx Desc Own bit.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
-
-/**
- * @brief Enables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
-
-/**
- * @brief Disables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
-
-/**
- * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
- * @param __HANDLE__ ETH Handle
- * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
- * This parameter can be one of the following values:
- * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
- * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
-
-/**
- * @brief Enables the DMA Tx Desc CRC.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
-
-/**
- * @brief Disables the DMA Tx Desc CRC.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
-
-/**
- * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
-
-/**
- * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
-
-/**
- * @brief Enables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
- * enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_IT_PMT : PMT interrupt
- * @retval None
- */
-#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
- * enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_IT_PMT : PMT interrupt
- * @retval None
- */
-#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
-
-/**
- * @brief Initiate a Pause Control Frame (Full-duplex only).
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Checks whether the ETHERNET flow control busy bit is set or not.
- * @param __HANDLE__ ETH Handle
- * @retval The new state of flow control busy status bit (SET or RESET).
- */
-#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Checks whether the specified ETHERNET MAC flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
- * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
- * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
- * @arg ETH_MAC_FLAG_MMC : MMC flag
- * @arg ETH_MAC_FLAG_PMT : PMT flag
- * @retval The state of ETHERNET MAC flag.
- */
-#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
-
-/**
* @brief Enables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
* enabled @ref ETH_DMA_Interrupts
* @retval None
*/
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \
+ |= (__INTERRUPT__))
/**
* @brief Disables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
* disabled. @ref ETH_DMA_Interrupts
* @retval None
*/
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \
+ &= ~(__INTERRUPT__))
+
+/**
+ * @brief Gets the ETHERNET DMA IT source enabled or disabled.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+ * @retval The ETH DMA IT Source enabled or disabled
+ */
+#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMAIER &\
+ (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+ * @brief Gets the ETHERNET DMA IT pending bit.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+ * @retval The state of ETH DMA IT (SET or RESET)
+ */
+#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMASR &\
+ (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the ETHERNET DMA IT pending bit.
- * @param __HANDLE__ ETH Handle
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
* @retval None
*/
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__))
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
-* @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
- * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+ * @retval The state of ETH DMA FLAG (SET or RESET).
*/
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &\
+ ( __FLAG__)) == ( __FLAG__))
/**
- * @brief Checks whether the specified ETHERNET DMA flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
- * @retval The new state of ETH_DMA_FLAG (SET or RESET).
+ * @brief Clears the specified ETHERNET DMA flag.
+ * @param __HANDLE__: ETH Handle
+ * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+ * @retval The state of ETH DMA FLAG (SET or RESET).
*/
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
/**
- * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
- * @param __HANDLE__ ETH Handle
- * @param __OVERFLOW__ specifies the DMA overflow flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
- * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
- * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
- */
-#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
-
-/**
- * @brief Set the DMA Receive status watchdog timer register value
- * @param __HANDLE__ ETH Handle
- * @param __VALUE__ DMA Receive status watchdog timer register value
+ * @brief Enables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled @ref ETH_MAC_Interrupts
* @retval None
*/
-#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
-
-/**
- * @brief Enables any unicast packet filtered by the MAC address
- * recognition to be a wake-up frame.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \
+ |= (__INTERRUPT__))
/**
- * @brief Disables any unicast packet filtered by the MAC address
- * recognition to be a wake-up frame.
- * @param __HANDLE__ ETH Handle.
+ * @brief Disables the specified ETHERNET MAC interrupts.
+ * @param __HANDLE__ : ETH Handle
+ * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * enabled @ref ETH_MAC_Interrupts
* @retval None
*/
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \
+ &= ~(__INTERRUPT__))
/**
- * @brief Enables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.
+ * @param __HANDLE__: ETH Handle
+ * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
+ * @retval The state of ETH MAC IT (SET or RESET).
*/
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\
+ ( __INTERRUPT__)) == ( __INTERRUPT__))
+
+/*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */
+#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00080000U)
/**
- * @brief Disables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Enables the MAC Magic Packet Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
-
-/**
- * @brief Disables the MAC Magic Packet Detection.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Enables the MAC Power Down.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
-
-/**
- * @brief Disables the MAC Power Down.
- * @param __HANDLE__ ETH Handle
- * @retval None
- */
-#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
-
-/**
- * @brief Checks whether the specified ETHERNET PMT flag is set or not.
- * @param __HANDLE__ ETH Handle.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
- * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
- * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
- * @retval The new state of ETHERNET PMT Flag (SET or RESET).
- */
-#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
-
-/**
- * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
- (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
-
-/**
- * @brief Enables the MMC Counter Freeze.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
-
-/**
- * @brief Disables the MMC Counter Freeze.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
-
-/**
- * @brief Enables the MMC Reset On Read.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
-
-/**
- * @brief Disables the MMC Reset On Read.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
-
-/**
- * @brief Enables the MMC Counter Stop Rollover.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
-
-/**
- * @brief Disables the MMC Counter Stop Rollover.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
-
-/**
- * @brief Resets the MMC Counters.
- * @param __HANDLE__ ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
-
-/**
- * @brief Enables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
-/**
- * @brief Disables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
-/**
- * @brief Enables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__ ETH Handle.
- * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
-
-/**
- * @brief Enables the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disables the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enable event on ETH External event line.
+ * @brief Enable the ETH WAKEUP Exti Line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
* @retval None.
*/
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR |= (__EXTI_LINE__))
/**
- * @brief Disable event on ETH External event line
+ * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+ * @arg ETH_WAKEUP_EXTI_LINE
+ * @retval EXTI ETH WAKEUP Line Status.
+ */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+ * @brief Clear the ETH WAKEUP Exti flag.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+ * @arg ETH_WAKEUP_EXTI_LINE
* @retval None.
*/
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
/**
- * @brief Get flag of the ETH External interrupt line.
+ * @brief enable rising edge interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \
+ (EXTI->RTSR |= (__EXTI_LINE__))
/**
- * @brief Clear flag of the ETH External interrupt line.
+ * @brief enable falling edge interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\
+ (EXTI->FTSR |= (__EXTI_LINE__))
/**
- * @brief Enables rising edge trigger to the ETH External interrupt line.
+ * @brief enable falling edge interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
-
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\
+ (EXTI->FTSR |= (__EXTI_LINE__))
+
/**
- * @brief Disables the rising edge trigger to the ETH External interrupt line.
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+ * @arg ETH_WAKEUP_EXTI_LINE
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-/**
- * @brief Enables falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \
+ (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-/**
- * @brief Disables falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
- }while(0U)
-
-/**
- * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- }while(0U)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
-
+#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__))
/**
* @}
*/
+
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ETH_Exported_Functions
* @{
*/
-/* Initialization and de-initialization functions ****************************/
-
/** @addtogroup ETH_Exported_Functions_Group1
* @{
*/
+/* Initialization and de initialization functions **********************************/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
-HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
+void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
+ pETH_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
/**
* @}
*/
-/* IO operation functions ****************************************************/
/** @addtogroup ETH_Exported_Functions_Group2
* @{
*/
-HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
-/* Communication with PHY functions*/
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
-/* Callback in non blocking modes (Interrupt) */
-void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
+
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
+HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
+ pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
+HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
+
+#ifdef HAL_ETH_USE_PTP
+HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
+ ETH_TimeTypeDef *timeoffset);
+HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
+#endif /* HAL_ETH_USE_PTP */
+
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
+
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+ uint32_t RegValue);
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+ uint32_t *pRegValue);
+
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
+void HAL_ETH_RxAllocateCallback(uint8_t **buff);
+void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
+void HAL_ETH_TxFreeCallback(uint32_t *buff);
+void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
/**
* @}
*/
-/* Peripheral Control functions **********************************************/
-
/** @addtogroup ETH_Exported_Functions_Group3
* @{
*/
+/* Peripheral Control functions **********************************************/
+/* MAC & DMA Configuration APIs **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
+/* MAC VLAN Processing APIs ************************************************/
+void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
+ uint32_t VLANIdentifier);
+
+/* MAC L2 Packet Filtering APIs **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
+
+/* MAC Power Down APIs *****************************************************/
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
+void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
+
/**
* @}
- */
-
-/* Peripheral State functions ************************************************/
+ */
/** @addtogroup ETH_Exported_Functions_Group4
* @{
*/
+/* Peripheral State functions **************************************************/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
/**
* @}
*/
@@ -2200,14 +2136,12 @@
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
- STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
+#endif /* ETH */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_ETH_H */
+#endif /* STM32F4xx_HAL_ETH_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_exti.h b/Inc/stm32f4xx_hal_exti.h
index 8570112..b18a228 100644
--- a/Inc/stm32f4xx_hal_exti.h
+++ b/Inc/stm32f4xx_hal_exti.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.Clause
*
******************************************************************************
*/
@@ -365,4 +364,3 @@
#endif /* STM32f4xx_HAL_EXTI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_flash.h b/Inc/stm32f4xx_hal_flash.h
index b817f63..26d789e 100644
--- a/Inc/stm32f4xx_hal_flash.h
+++ b/Inc/stm32f4xx_hal_flash.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -425,4 +423,3 @@
#endif /* __STM32F4xx_HAL_FLASH_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_flash_ex.h b/Inc/stm32f4xx_hal_flash_ex.h
index 4dbad67..1cf8c45 100644
--- a/Inc/stm32f4xx_hal_flash_ex.h
+++ b/Inc/stm32f4xx_hal_flash_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -1063,4 +1061,3 @@
#endif /* __STM32F4xx_HAL_FLASH_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_flash_ramfunc.h b/Inc/stm32f4xx_hal_flash_ramfunc.h
index 9fab0c9..05917ec 100644
--- a/Inc/stm32f4xx_hal_flash_ramfunc.h
+++ b/Inc/stm32f4xx_hal_flash_ramfunc.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -76,4 +74,3 @@
#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_fmpi2c.h b/Inc/stm32f4xx_hal_fmpi2c.h
index b7f370a..400b923 100644
--- a/Inc/stm32f4xx_hal_fmpi2c.h
+++ b/Inc/stm32f4xx_hal_fmpi2c.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -277,7 +276,7 @@
typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c);
/*!< pointer to an FMPI2C callback function */
typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection,
- uint16_t AddrMatchCode);
+ uint16_t AddrMatchCode);
/*!< pointer to an FMPI2C Address Match callback function */
#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */
@@ -621,13 +620,13 @@
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t Timeout);
+ uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData,
- uint16_t Size, uint32_t Timeout);
+ uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
- uint32_t Timeout);
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size,
- uint32_t Timeout);
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress,
@@ -783,9 +782,9 @@
FMPI2C_CR2_RD_WRN)))
#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \
- >> 16U))
+ >> 16U))
#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \
- >> 16U))
+ >> 16U))
#define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
#define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1))
#define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2))
@@ -836,5 +835,3 @@
#endif /* STM32F4xx_HAL_FMPI2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_fmpi2c_ex.h b/Inc/stm32f4xx_hal_fmpi2c_ex.h
index 6a5df0b..8b90f40 100644
--- a/Inc/stm32f4xx_hal_fmpi2c_ex.h
+++ b/Inc/stm32f4xx_hal_fmpi2c_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -149,5 +148,3 @@
#endif
#endif /* STM32F4xx_HAL_FMPI2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_fmpsmbus.h b/Inc/stm32f4xx_hal_fmpsmbus.h
index 9d5e030..6d1ff4b 100644
--- a/Inc/stm32f4xx_hal_fmpsmbus.h
+++ b/Inc/stm32f4xx_hal_fmpsmbus.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -373,9 +372,9 @@
#define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE
#define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE
#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \
- FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)
+ FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)
#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \
- FMPSMBUS_IT_RXI)
+ FMPSMBUS_IT_RXI)
#define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI)
#define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI)
/**
@@ -623,11 +622,11 @@
#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
(uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \
- FMPI2C_CR1_PECEN)))
+ FMPI2C_CR1_PECEN)))
#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \
- FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \
- FMPI2C_CR2_RD_WRN)))
+ FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \
+ FMPI2C_CR2_RD_WRN)))
#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \
@@ -677,13 +676,13 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
- HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
- pFMPSMBUS_CallbackTypeDef pCallback);
+ HAL_FMPSMBUS_CallbackIDTypeDef CallbackID,
+ pFMPSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
- HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
+ HAL_FMPSMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus,
- pFMPSMBUS_AddrCallbackTypeDef pCallback);
+ pFMPSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus);
#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */
/**
@@ -710,9 +709,9 @@
*/
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress,
- uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress,
- uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+ uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
@@ -789,5 +788,3 @@
#endif /* STM32F4xx_HAL_FMPSMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_fmpsmbus_ex.h b/Inc/stm32f4xx_hal_fmpsmbus_ex.h
index d5439e7..001dc54 100644
--- a/Inc/stm32f4xx_hal_fmpsmbus_ex.h
+++ b/Inc/stm32f4xx_hal_fmpsmbus_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -105,9 +104,9 @@
* @{
*/
#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \
- FMPSMBUS_FASTMODEPLUS_SCL) || \
+ FMPSMBUS_FASTMODEPLUS_SCL) || \
(((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \
- FMPSMBUS_FASTMODEPLUS_SDA))
+ FMPSMBUS_FASTMODEPLUS_SDA))
/**
* @}
*/
@@ -135,5 +134,3 @@
#endif
#endif /* STM32F4xx_HAL_FMPSMBUS_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_gpio.h b/Inc/stm32f4xx_hal_gpio.h
index cacfdee..5f3d749 100644
--- a/Inc/stm32f4xx_hal_gpio.h
+++ b/Inc/stm32f4xx_hal_gpio.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -324,4 +323,3 @@
#endif /* __STM32F4xx_HAL_GPIO_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_gpio_ex.h b/Inc/stm32f4xx_hal_gpio_ex.h
index 7db36cc..5e0b7cc 100644
--- a/Inc/stm32f4xx_hal_gpio_ex.h
+++ b/Inc/stm32f4xx_hal_gpio_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -1589,4 +1588,3 @@
#endif /* __STM32F4xx_HAL_GPIO_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_hash.h b/Inc/stm32f4xx_hal_hash.h
index 3b73282..9a93fbb 100644
--- a/Inc/stm32f4xx_hal_hash.h
+++ b/Inc/stm32f4xx_hal_hash.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -633,4 +632,3 @@
#endif /* STM32F4xx_HAL_HASH_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_hash_ex.h b/Inc/stm32f4xx_hal_hash_ex.h
index 0a9844c..91e65dc 100644
--- a/Inc/stm32f4xx_hal_hash_ex.h
+++ b/Inc/stm32f4xx_hal_hash_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -174,4 +173,3 @@
#endif /* STM32F4xx_HAL_HASH_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_hcd.h b/Inc/stm32f4xx_hal_hcd.h
index 6025e03..9cd1486 100644
--- a/Inc/stm32f4xx_hal_hcd.h
+++ b/Inc/stm32f4xx_hal_hcd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -315,5 +314,3 @@
#endif
#endif /* STM32F4xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_i2c.h b/Inc/stm32f4xx_hal_i2c.h
index 9a622b8..9a7a67e 100644
--- a/Inc/stm32f4xx_hal_i2c.h
+++ b/Inc/stm32f4xx_hal_i2c.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -740,4 +739,3 @@
#endif /* __STM32F4xx_HAL_I2C_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_i2c_ex.h b/Inc/stm32f4xx_hal_i2c_ex.h
index 6864d83..31ad99c 100644
--- a/Inc/stm32f4xx_hal_i2c_ex.h
+++ b/Inc/stm32f4xx_hal_i2c_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -114,4 +113,3 @@
#endif /* __STM32F4xx_HAL_I2C_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_i2s.h b/Inc/stm32f4xx_hal_i2s.h
index 1e9676f..66cee01 100644
--- a/Inc/stm32f4xx_hal_i2s.h
+++ b/Inc/stm32f4xx_hal_i2s.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -617,4 +616,3 @@
#endif /* STM32F4xx_HAL_I2S_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_i2s_ex.h b/Inc/stm32f4xx_hal_i2s_ex.h
index 10335f4..3aaa45b 100644
--- a/Inc/stm32f4xx_hal_i2s_ex.h
+++ b/Inc/stm32f4xx_hal_i2s_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -182,4 +181,3 @@
#endif /* STM32F4xx_HAL_I2S_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_irda.h b/Inc/stm32f4xx_hal_irda.h
index 4d83abc..0d1c5f1 100644
--- a/Inc/stm32f4xx_hal_irda.h
+++ b/Inc/stm32f4xx_hal_irda.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -145,7 +144,7 @@
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
- uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
+ const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
@@ -560,11 +559,11 @@
* @{
*/
/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
@@ -681,4 +680,3 @@
#endif /* __STM32F4xx_HAL_IRDA_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_iwdg.h b/Inc/stm32f4xx_hal_iwdg.h
index 32f5ff0..5273730 100644
--- a/Inc/stm32f4xx_hal_iwdg.h
+++ b/Inc/stm32f4xx_hal_iwdg.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -219,5 +218,3 @@
#endif
#endif /* STM32F4xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_lptim.h b/Inc/stm32f4xx_hal_lptim.h
index 80ea203..7a41ee9 100644
--- a/Inc/stm32f4xx_hal_lptim.h
+++ b/Inc/stm32f4xx_hal_lptim.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -819,11 +818,13 @@
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
+ ((__AUTORELOAD__) <= 0x0000FFFFUL))
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
-#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
+#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
+ ((__PERIOD__) <= 0x0000FFFFUL))
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
@@ -854,5 +855,3 @@
#endif
#endif /* STM32F4xx_HAL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_ltdc.h b/Inc/stm32f4xx_hal_ltdc.h
index 0cab844..ab951d3 100644
--- a/Inc/stm32f4xx_hal_ltdc.h
+++ b/Inc/stm32f4xx_hal_ltdc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -80,28 +79,36 @@
This parameter can be one of value of @ref LTDC_PC_POLARITY */
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
- This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
- This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
uint32_t TotalWidth; /*!< configures the total width.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
uint32_t TotalHeigh; /*!< configures the total height.
- This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
} LTDC_InitTypeDef;
@@ -112,25 +119,31 @@
typedef struct
{
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Alpha0; /*!< Configures the default alpha value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ This parameter must be a number between
+ Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
@@ -141,10 +154,12 @@
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+ This parameter must be a number between
+ Min_Data = 0x0000 and Max_Data = 0x1FFF. */
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+ This parameter must be a number between
+ Min_Data = 0x000 and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
} LTDC_LayerCfgTypeDef;
@@ -400,7 +415,7 @@
* @retval None
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
@@ -430,7 +445,8 @@
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
-#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+ |= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
@@ -439,7 +455,8 @@
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
-#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+ &= ~(uint32_t)LTDC_LxCR_LEN)
/**
* @brief Reload immediately all LTDC Layers.
@@ -545,7 +562,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+ pLTDC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
@@ -583,9 +601,12 @@
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+ uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+ uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
@@ -621,12 +642,18 @@
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
-#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
+#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\
+ ((uint32_t)((__HANDLE__)->Instance))\
+ + 0x84U + (0x80U*(__LAYER__)))))
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
-#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
-#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
-#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
-#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
+ || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
+ || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
+ || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
+ || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
@@ -642,10 +669,14 @@
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
-#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
- ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \
+ ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
@@ -655,7 +686,8 @@
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
-#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
+#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
+ ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
@@ -685,4 +717,3 @@
#endif /* STM32F4xx_HAL_LTDC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_ltdc_ex.h b/Inc/stm32f4xx_hal_ltdc_ex.h
index 37a5fdf..b9c39e4 100644
--- a/Inc/stm32f4xx_hal_ltdc_ex.h
+++ b/Inc/stm32f4xx_hal_ltdc_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -82,5 +81,3 @@
#endif
#endif /* STM32F4xx_HAL_LTDC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_mmc.h b/Inc/stm32f4xx_hal_mmc.h
index e65172a..30921aa 100644
--- a/Inc/stm32f4xx_hal_mmc.h
+++ b/Inc/stm32f4xx_hal_mmc.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -145,6 +144,8 @@
uint32_t CID[4U]; /*!< MMC card identification number table */
+ uint32_t Ext_CSD[128];
+
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc);
@@ -334,10 +335,12 @@
/**
* @brief
*/
-#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
-#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
+#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
+#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
+#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
+#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
+#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
+#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
@@ -636,6 +639,7 @@
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
/**
* @}
*/
@@ -649,7 +653,7 @@
* @}
*/
-/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
+/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
@@ -741,5 +745,3 @@
#endif /* SDIO */
#endif /* STM32F4xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_nand.h b/Inc/stm32f4xx_hal_nand.h
index e6aaabb..26f6502 100644
--- a/Inc/stm32f4xx_hal_nand.h
+++ b/Inc/stm32f4xx_hal_nand.h
@@ -6,35 +6,32 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_NAND_H
-#define __STM32F4xx_HAL_NAND_H
+#ifndef STM32F4xx_HAL_NAND_H
+#define STM32F4xx_HAL_NAND_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
- #include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
- #include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
- STM32F479xx */
+/* Includes ------------------------------------------------------------------*/
+#if defined(FSMC_Bank2_3)
+#include "stm32f4xx_ll_fsmc.h"
+#else
+#include "stm32f4xx_ll_fmc.h"
+#endif /* FSMC_Bank2_3 */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -42,11 +39,7 @@
/** @addtogroup NAND
* @{
- */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ */
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
@@ -54,7 +47,7 @@
* @{
*/
-/**
+/**
* @brief HAL NAND State structures definition
*/
typedef enum
@@ -63,65 +56,65 @@
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
-}HAL_NAND_StateTypeDef;
-
-/**
+} HAL_NAND_StateTypeDef;
+
+/**
* @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
/*<! NAND memory electronic signature maker and device IDs */
- uint8_t Maker_Id;
+ uint8_t Maker_Id;
uint8_t Device_Id;
uint8_t Third_Id;
uint8_t Fourth_Id;
-}NAND_IDTypeDef;
+} NAND_IDTypeDef;
-/**
+/**
* @brief NAND Memory address Structure definition
*/
-typedef struct
-{
- uint16_t Page; /*!< NAND memory Page address */
-
- uint16_t Plane; /*!< NAND memory Plane address */
-
- uint16_t Block; /*!< NAND memory Block address */
-
-}NAND_AddressTypeDef;
-
-/**
- * @brief NAND Memory info Structure definition
- */
typedef struct
{
- uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
+ uint16_t Page; /*!< NAND memory Page address */
- uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
-
+ uint16_t Plane; /*!< NAND memory Zone address */
+
+ uint16_t Block; /*!< NAND memory Block address */
+
+} NAND_AddressTypeDef;
+
+/**
+ * @brief NAND Memory info Structure definition
+ */
+typedef struct
+{
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
+ for 8 bits addressing or words for 16 bits addressing */
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
+ for 8 bits addressing or words for 16 bits addressing */
+
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
-
+
uint32_t PlaneNbr; /*!< NAND memory number of planes */
- uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
+ uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
- FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
- parameter is mandatory for some NAND parts after the read
- command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
+ FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
+ parameter is mandatory for some NAND parts after the read
+ command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
-}NAND_DeviceConfigTypeDef;
+} NAND_DeviceConfigTypeDef;
-/**
+/**
* @brief NAND handle Structure definition
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
@@ -131,7 +124,7 @@
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
{
FMC_NAND_TypeDef *Instance; /*!< Register base address */
-
+
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NAND locking object */
@@ -141,10 +134,10 @@
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
- void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
- void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
-#endif
+ void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
+ void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
+ void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
@@ -156,23 +149,23 @@
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
-}HAL_NAND_CallbackIDTypeDef;
+} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
@@ -186,7 +179,7 @@
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -196,14 +189,14 @@
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
@@ -218,40 +211,48 @@
/**
* @}
*/
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
-HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
@@ -263,12 +264,13 @@
/**
* @}
*/
-
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/**
* @}
*/
@@ -276,19 +278,23 @@
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
-#define NAND_DEVICE1 0x70000000U
-#define NAND_DEVICE2 0x80000000U
-#define NAND_WRITE_TIMEOUT 0x01000000U
+#if defined(FMC_Bank2_3)
+#define NAND_DEVICE1 0x70000000UL
+#define NAND_DEVICE2 0x80000000UL
+#else
+#define NAND_DEVICE 0x80000000UL
+#endif
+#define NAND_WRITE_TIMEOUT 0x01000000UL
-#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
+#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
+#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
@@ -305,12 +311,12 @@
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
-#define NAND_VALID_ADDRESS 0x00000100U
-#define NAND_INVALID_ADDRESS 0x00000200U
-#define NAND_TIMEOUT_ERROR 0x00000400U
-#define NAND_BUSY 0x00000000U
-#define NAND_ERROR 0x00000001U
-#define NAND_READY 0x00000040U
+#define NAND_VALID_ADDRESS 0x00000100UL
+#define NAND_INVALID_ADDRESS 0x00000200UL
+#define NAND_TIMEOUT_ERROR 0x00000400UL
+#define NAND_BUSY 0x00000000UL
+#define NAND_ERROR 0x00000001UL
+#define NAND_READY 0x00000040UL
/**
* @}
*/
@@ -323,11 +329,14 @@
/**
* @brief NAND memory address computation.
* @param __ADDRESS__ NAND memory address.
- * @param __HANDLE__ NAND handle.
+ * @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + \
+ (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize))) * \
+ ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
@@ -351,31 +360,29 @@
* @param __ADDRESS__ NAND memory address.
* @retval NAND Column address cycling value.
*/
-#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
+#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
- STM32F446xx || STM32F469xx || STM32F479xx */
-
-/**
- * @}
- */
-/**
- * @}
- */
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32F4xx_HAL_NAND_H */
diff --git a/Inc/stm32f4xx_hal_nor.h b/Inc/stm32f4xx_hal_nor.h
index dcd25c5..cc7f1b5 100644
--- a/Inc/stm32f4xx_hal_nor.h
+++ b/Inc/stm32f4xx_hal_nor.h
@@ -6,35 +6,32 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_NOR_H
-#define __STM32F4xx_HAL_NOR_H
+#ifndef STM32F4xx_HAL_NOR_H
+#define STM32F4xx_HAL_NOR_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
- #include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+#if defined(FMC_Bank1) || defined(FSMC_Bank1)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
- #include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/* Includes ------------------------------------------------------------------*/
+#if defined(FSMC_Bank1)
+#include "stm32f4xx_ll_fsmc.h"
+#else
+#include "stm32f4xx_ll_fmc.h"
+#endif /* FMC_Bank1 */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -42,29 +39,24 @@
/** @addtogroup NOR
* @{
- */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+ */
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup NOR_Exported_Types NOR Exported Types
* @{
*/
-/**
- * @brief HAL SRAM State structures definition
- */
+/**
+ * @brief HAL SRAM State structures definition
+ */
typedef enum
-{
+{
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
-}HAL_NOR_StateTypeDef;
+} HAL_NOR_StateTypeDef;
/**
* @brief FMC NOR Status typedef
@@ -75,7 +67,7 @@
HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT
-}HAL_NOR_StatusTypeDef;
+} HAL_NOR_StatusTypeDef;
/**
* @brief FMC NOR ID typedef
@@ -88,11 +80,11 @@
uint16_t Device_Code2;
- uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
- These codes can be accessed by performing read operations with specific
- control signals and addresses set.They can also be accessed by issuing
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
an Auto Select command */
-}NOR_IDTypeDef;
+} NOR_IDTypeDef;
/**
* @brief FMC NOR CFI typedef
@@ -100,7 +92,7 @@
typedef struct
{
/*!< Defines the information stored in the memory's Common flash interface
- which contains a description of various electrical and timing parameters,
+ which contains a description of various electrical and timing parameters,
density information and functions supported by the memory */
uint16_t CFI_1;
@@ -110,9 +102,9 @@
uint16_t CFI_3;
uint16_t CFI_4;
-}NOR_CFITypeDef;
+} NOR_CFITypeDef;
-/**
+/**
* @brief NOR handle Structure definition
*/
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
@@ -132,10 +124,12 @@
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+ uint32_t CommandSet; /*!< NOR algorithm command set and control */
+
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
- void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
-#endif
+ void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
+ void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
} NOR_HandleTypeDef;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
@@ -146,19 +140,19 @@
{
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
-}HAL_NOR_CallbackIDTypeDef;
+} HAL_NOR_CallbackIDTypeDef;
/**
* @brief HAL NOR Callback pointer definition
*/
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
-/* Exported macros ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
/** @defgroup NOR_Exported_Macros NOR Exported Macros
* @{
*/
@@ -174,21 +168,23 @@
} while(0)
#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions
- * @{
- */
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
-/** @addtogroup NOR_Exported_Functions_Group1
- * @{
- */
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
@@ -196,18 +192,21 @@
/**
* @}
*/
-
-/** @addtogroup NOR_Exported_Functions_Group2
- * @{
- */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
@@ -215,37 +214,40 @@
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/* NOR callback registering/unregistering */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
-
-/** @addtogroup NOR_Exported_Functions_Group3
- * @{
- */
+
+/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
+ * @{
+ */
+
/* NOR Control functions *****************************************************/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
/**
* @}
*/
-
-/** @addtogroup NOR_Exported_Functions_Group4
- * @{
- */
+
+/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
+ * @{
+ */
+
/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -266,16 +268,16 @@
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFF)
-
+
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x00)
#define NOR_MEMORY_16B ((uint8_t)0x01)
/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 0x60000000U
-#define NOR_MEMORY_ADRESS2 0x64000000U
-#define NOR_MEMORY_ADRESS3 0x68000000U
-#define NOR_MEMORY_ADRESS4 0x6C000000U
+#define NOR_MEMORY_ADRESS1 (0x60000000U)
+#define NOR_MEMORY_ADRESS2 (0x64000000U)
+#define NOR_MEMORY_ADRESS3 (0x68000000U)
+#define NOR_MEMORY_ADRESS4 (0x6C000000U)
/**
* @}
*/
@@ -286,41 +288,43 @@
*/
/**
* @brief NOR memory address shifting.
- * @param __NOR_ADDRESS__ NOR base address
- * @param NOR_MEMORY_WIDTH NOR memory width
- * @param ADDRESS NOR memory address
+ * @param __NOR_ADDRESS NOR base address
+ * @param __NOR_MEMORY_WIDTH_ NOR memory width
+ * @param __ADDRESS__ NOR memory address
* @retval NOR shifted address value
*/
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
- ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS))))
-
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
/**
* @brief NOR memory write data to specified address.
- * @param ADDRESS NOR memory address
- * @param DATA Data to write
+ * @param __ADDRESS__ NOR memory address
+ * @param __DATA__ Data to write
* @retval None
*/
-#define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
+#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
+ (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
+ __DSB(); \
+ } while(0)
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
- STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
- STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
-/**
- * @}
- */
/**
* @}
*/
+/**
+ * @}
+ */
+
+#endif /* FMC_Bank1 || FSMC_Bank1 */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32F4xx_HAL_NOR_H */
diff --git a/Inc/stm32f4xx_hal_pccard.h b/Inc/stm32f4xx_hal_pccard.h
index 41d7824..47fbb26 100644
--- a/Inc/stm32f4xx_hal_pccard.h
+++ b/Inc/stm32f4xx_hal_pccard.h
@@ -6,60 +6,56 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PCCARD_H
-#define __STM32F4xx_HAL_PCCARD_H
+#ifndef STM32F4xx_HAL_PCCARD_H
+#define STM32F4xx_HAL_PCCARD_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-/* Includes ------------------------------------------------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
- #include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+#if defined(FMC_Bank4) || defined(FSMC_Bank4)
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
- #include "stm32f4xx_ll_fmc.h"
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/* Includes ------------------------------------------------------------------*/
+#if defined(FSMC_Bank4)
+#include "stm32f4xx_ll_fsmc.h"
+#else
+#include "stm32f4xx_ll_fmc.h"
+#endif /* FSMC_Bank4 */
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-
/** @addtogroup PCCARD
* @{
- */
+ */
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
* @{
*/
-/**
- * @brief HAL PCCARD State structures definition
- */
+/**
+ * @brief HAL PCCARD State structures definition
+ */
typedef enum
{
HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
-}HAL_PCCARD_StateTypeDef;
+} HAL_PCCARD_StateTypeDef;
typedef enum
{
@@ -67,19 +63,19 @@
HAL_PCCARD_STATUS_ONGOING,
HAL_PCCARD_STATUS_ERROR,
HAL_PCCARD_STATUS_TIMEOUT
-}HAL_PCCARD_StatusTypeDef;
+} HAL_PCCARD_StatusTypeDef;
/**
* @brief FMC_PCCARD handle Structure definition
*/
-#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
+#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
typedef struct __PCCARD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
{
FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
-
+
FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
@@ -87,9 +83,9 @@
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */
- void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */
- void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */
+ void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
+ void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
+ void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
#endif
} PCCARD_HandleTypeDef;
@@ -102,7 +98,7 @@
HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
-}HAL_PCCARD_CallbackIDTypeDef;
+} HAL_PCCARD_CallbackIDTypeDef;
/**
* @brief HAL PCCARD Callback pointer definition
@@ -133,18 +129,19 @@
#endif
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCCARD_Exported_Functions
+/** @addtogroup PCCARD_Exported_Functions
* @{
*/
-/** @addtogroup PCCARD_Exported_Functions_Group1
+/** @addtogroup PCCARD_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
+HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
+ FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
@@ -157,8 +154,10 @@
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
+ uint8_t *pStatus);
+HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
+ uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
@@ -166,8 +165,10 @@
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/* PCCARD callback registering/unregistering */
-HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
+ pPCCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
+ HAL_PCCARD_CallbackIDTypeDef CallbackId);
#endif
/**
* @}
@@ -223,7 +224,7 @@
#define PCCARD_PROGR ((uint8_t)0x01)
#define PCCARD_READY ((uint8_t)0x40)
-#define PCCARD_SECTOR_SIZE 255U /* In half words */
+#define PCCARD_SECTOR_SIZE 255U /* In half words */
/**
* @}
@@ -254,14 +255,14 @@
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
-#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
-#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
-#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
+#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
+#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
+#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
-#define CF_BUSY PCCARD_BUSY
-#define CF_PROGR PCCARD_PROGR
-#define CF_READY PCCARD_READY
+#define CF_BUSY PCCARD_BUSY
+#define CF_PROGR PCCARD_PROGR
+#define CF_READY PCCARD_READY
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
@@ -270,18 +271,15 @@
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
- STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
/**
* @}
*/
-
+
+#endif /* FMC_Bank4 || FSMC_Bank4 */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_PCCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32F4xx_HAL_PCCARD_H */
diff --git a/Inc/stm32f4xx_hal_pcd.h b/Inc/stm32f4xx_hal_pcd.h
index e28285d..92488b2 100644
--- a/Inc/stm32f4xx_hal_pcd.h
+++ b/Inc/stm32f4xx_hal_pcd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -107,6 +106,7 @@
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
+ uint32_t FrameNumber; /*!< Store Current Frame number */
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
@@ -290,12 +290,10 @@
* @}
*/
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
- HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
@@ -317,14 +315,10 @@
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
- pPCD_BcdCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
- pPCD_LpmCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@@ -364,22 +358,17 @@
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint16_t ep_mps, uint8_t ep_type);
-
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
- uint8_t *pBuf, uint32_t len);
-
-
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
@@ -468,5 +457,3 @@
#endif
#endif /* STM32F4xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_pcd_ex.h b/Inc/stm32f4xx_hal_pcd_ex.h
index 71e9a2c..72ded2b 100644
--- a/Inc/stm32f4xx_hal_pcd_ex.h
+++ b/Inc/stm32f4xx_hal_pcd_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -23,7 +22,7 @@
#ifdef __cplusplus
extern "C" {
-#endif
+#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -83,9 +82,7 @@
#ifdef __cplusplus
}
-#endif
+#endif /* __cplusplus */
#endif /* STM32F4xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_pwr.h b/Inc/stm32f4xx_hal_pwr.h
index 6f3bf71..d97f255 100644
--- a/Inc/stm32f4xx_hal_pwr.h
+++ b/Inc/stm32f4xx_hal_pwr.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -427,5 +425,3 @@
#endif /* __STM32F4xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_pwr_ex.h b/Inc/stm32f4xx_hal_pwr_ex.h
index 10e017a..57fd4d9 100644
--- a/Inc/stm32f4xx_hal_pwr_ex.h
+++ b/Inc/stm32f4xx_hal_pwr_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -340,5 +338,3 @@
#endif /* __STM32F4xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_qspi.h b/Inc/stm32f4xx_hal_qspi.h
index 97e9324..56287af 100644
--- a/Inc/stm32f4xx_hal_qspi.h
+++ b/Inc/stm32f4xx_hal_qspi.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -457,7 +456,7 @@
* @{
*/
/** @brief Reset QSPI handle state.
- * @param __HANDLE__ : QSPI handle.
+ * @param __HANDLE__ QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@@ -471,20 +470,20 @@
#endif
/** @brief Enable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __HANDLE__ specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
- * @param __HANDLE__ : specifies the QSPI Handle.
+ * @param __HANDLE__ specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -497,8 +496,8 @@
/** @brief Disable the specified QSPI interrupt.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -510,8 +509,8 @@
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __INTERRUPT__ specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -524,8 +523,8 @@
/**
* @brief Check whether the selected QSPI flag is set or not.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI flag to check.
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
@@ -538,8 +537,8 @@
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
- * @param __HANDLE__ : specifies the QSPI Handle.
- * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
+ * @param __HANDLE__ specifies the QSPI Handle.
+ * @param __FLAG__ specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
@@ -742,12 +741,10 @@
* @}
*/
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
+#endif /* defined(QUADSPI) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F4xx_HAL_QSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_rcc.h b/Inc/stm32f4xx_hal_rcc.h
index 2eeff34..dcf5814 100644
--- a/Inc/stm32f4xx_hal_rcc.h
+++ b/Inc/stm32f4xx_hal_rcc.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -1459,4 +1457,3 @@
#endif /* __STM32F4xx_HAL_RCC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_rcc_ex.h b/Inc/stm32f4xx_hal_rcc_ex.h
index df6a66a..909a717 100644
--- a/Inc/stm32f4xx_hal_rcc_ex.h
+++ b/Inc/stm32f4xx_hal_rcc_ex.h
@@ -6,14 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
+ * This software is licensed under terms that can be found in the LICENSE file in
+ * the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
@@ -7111,4 +7109,3 @@
#endif /* __STM32F4xx_HAL_RCC_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_rng.h b/Inc/stm32f4xx_hal_rng.h
index cde4859..7d4dca1 100644
--- a/Inc/stm32f4xx_hal_rng.h
+++ b/Inc/stm32f4xx_hal_rng.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -360,4 +359,3 @@
#endif /* STM32F4xx_HAL_RNG_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_rtc.h b/Inc/stm32f4xx_hal_rtc.h
index 9afa8a1..24affc5 100644
--- a/Inc/stm32f4xx_hal_rtc.h
+++ b/Inc/stm32f4xx_hal_rtc.h
@@ -6,26 +6,26 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RTC_H
-#define __STM32F4xx_HAL_RTC_H
+#ifndef STM32F4xx_HAL_RTC_H
+#define STM32F4xx_HAL_RTC_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
+
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
@@ -37,6 +37,7 @@
*/
/* Exported types ------------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
@@ -51,7 +52,7 @@
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-}HAL_RTCStateTypeDef;
+} HAL_RTCStateTypeDef;
/**
* @brief RTC Configuration Structure definition
@@ -65,7 +66,7 @@
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTC_Output_selection_Definitions */
@@ -75,7 +76,7 @@
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-}RTC_InitTypeDef;
+} RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
@@ -83,8 +84,8 @@
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
@@ -95,22 +96,22 @@
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
- uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
+ uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
- corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+ corresponding to Synchronous prescaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
- uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
- please use HAL_RTC_DST_xxx functions */
+ uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight
+ Saving Time, please use HAL_RTC_DST_xxx functions */
- uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
- please use HAL_RTC_DST_xxx functions */
-}RTC_TimeTypeDef;
+ uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight
+ Saving Time, please use HAL_RTC_DST_xxx functions */
+} RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
@@ -129,7 +130,7 @@
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-}RTC_DateTypeDef;
+} RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
@@ -145,7 +146,7 @@
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+ This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
@@ -153,7 +154,7 @@
uint32_t Alarm; /*!< Specifies the alarm .
This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
+} RTC_AlarmTypeDef;
/**
* @brief RTC Handle Structure definition
@@ -162,7 +163,7 @@
typedef struct __RTC_HandleTypeDef
#else
typedef struct
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
{
RTC_TypeDef *Instance; /*!< Register base address */
@@ -173,25 +174,27 @@
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
- void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */
+ void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
- void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */
+ void (* AlarmBEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
- void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
+ void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */
- void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */
+ void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
- void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */
+ void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
- void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */
+#if defined(RTC_TAMPER2_SUPPORT)
+ void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
+#endif /* RTC_TAMPER2_SUPPORT */
- void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */
+ void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
- void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */
+ void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-}RTC_HandleTypeDef;
+} RTC_HandleTypeDef;
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
@@ -199,20 +202,22 @@
*/
typedef enum
{
- HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
- HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */
- HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
- HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */
- HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
- HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
- HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
- HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
-}HAL_RTC_CallbackIDTypeDef;
+ HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
+ HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
+ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */
+ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */
+ HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
+#if defined(RTC_TAMPER2_SUPPORT)
+ HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
+#endif /* RTC_TAMPER2_SUPPORT */
+ HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
+ HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
+} HAL_RTC_CallbackIDTypeDef;
/**
* @brief HAL RTC Callback pointer definition
*/
-typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
+typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
@@ -220,6 +225,7 @@
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
@@ -228,7 +234,7 @@
* @{
*/
#define RTC_HOURFORMAT_24 0x00000000U
-#define RTC_HOURFORMAT_12 0x00000040U
+#define RTC_HOURFORMAT_12 RTC_CR_FMT
/**
* @}
*/
@@ -237,9 +243,9 @@
* @{
*/
#define RTC_OUTPUT_DISABLE 0x00000000U
-#define RTC_OUTPUT_ALARMA 0x00200000U
-#define RTC_OUTPUT_ALARMB 0x00400000U
-#define RTC_OUTPUT_WAKEUP 0x00600000U
+#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
+#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
+#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
/**
* @}
*/
@@ -248,7 +254,7 @@
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
-#define RTC_OUTPUT_POLARITY_LOW 0x00100000U
+#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
/**
* @}
*/
@@ -257,7 +263,7 @@
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
-#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U
+#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
/**
* @}
*/
@@ -266,7 +272,7 @@
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
+#define RTC_HOURFORMAT12_PM ((uint8_t)0x01)
/**
* @}
*/
@@ -274,8 +280,8 @@
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
-#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U
-#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U
+#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
+#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
/**
* @}
@@ -285,7 +291,7 @@
* @{
*/
#define RTC_STOREOPERATION_RESET 0x00000000U
-#define RTC_STOREOPERATION_SET 0x00040000U
+#define RTC_STOREOPERATION_SET RTC_CR_BKP
/**
* @}
*/
@@ -293,16 +299,15 @@
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
-#define RTC_FORMAT_BIN 0x00000000U
-#define RTC_FORMAT_BCD 0x00000001U
+#define RTC_FORMAT_BIN 0x00000000U
+#define RTC_FORMAT_BCD 0x00000001U
/**
* @}
*/
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
* @{
*/
-/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
@@ -337,7 +342,7 @@
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
/**
* @}
*/
@@ -350,7 +355,10 @@
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL 0x80808080U
+#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \
+ RTC_ALARMMASK_HOURS | \
+ RTC_ALARMMASK_MINUTES | \
+ RTC_ALARMMASK_SECONDS)
/**
* @}
*/
@@ -367,39 +375,38 @@
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
-#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match
- to activate alarm. */
+/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */
+#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U
+/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0
+/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1
+/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)
+/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2
+/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)
+/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3
+/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */
+#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)
+/*!< SS[14:0] are compared and must match to activate alarm. */
+#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS
/**
* @}
*/
@@ -407,13 +414,10 @@
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
-#define RTC_IT_TS 0x00008000U
-#define RTC_IT_WUT 0x00004000U
-#define RTC_IT_ALRB 0x00002000U
-#define RTC_IT_ALRA 0x00001000U
-#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 0x00020000U
-#define RTC_IT_TAMP2 0x00040000U
+#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
+#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
+#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */
+#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
/**
* @}
*/
@@ -421,21 +425,23 @@
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
-#define RTC_FLAG_RECALPF 0x00010000U
-#define RTC_FLAG_TAMP2F 0x00004000U
-#define RTC_FLAG_TAMP1F 0x00002000U
-#define RTC_FLAG_TSOVF 0x00001000U
-#define RTC_FLAG_TSF 0x00000800U
-#define RTC_FLAG_WUTF 0x00000400U
-#define RTC_FLAG_ALRBF 0x00000200U
-#define RTC_FLAG_ALRAF 0x00000100U
-#define RTC_FLAG_INITF 0x00000040U
-#define RTC_FLAG_RSF 0x00000020U
-#define RTC_FLAG_INITS 0x00000010U
-#define RTC_FLAG_SHPF 0x00000008U
-#define RTC_FLAG_WUTWF 0x00000004U
-#define RTC_FLAG_ALRBWF 0x00000002U
-#define RTC_FLAG_ALRAWF 0x00000001U
+#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */
+#endif /* RTC_TAMPER2_SUPPORT */
+#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */
+#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */
+#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */
+#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */
+#define RTC_FLAG_ALRBF RTC_ISR_ALRBF /*!< Alarm B event flag */
+#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */
+#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */
+#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */
+#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */
+#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */
+#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */
+#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF /*!< ALRMBR register write allowance flag */
+#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */
/**
* @}
*/
@@ -444,7 +450,8 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
@@ -454,11 +461,11 @@
* @retval None
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
- (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
- (__HANDLE__)->MspInitCallback = NULL;\
- (__HANDLE__)->MspDeInitCallback = NULL;\
- }while(0u)
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \
+ (__HANDLE__)->State = HAL_RTC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0U)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
@@ -468,21 +475,20 @@
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xCAU; \
- (__HANDLE__)->Instance->WPR = 0x53U; \
- } while(0U)
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \
+ (__HANDLE__)->Instance->WPR = 0xCAU; \
+ (__HANDLE__)->Instance->WPR = 0x53U; \
+ } while(0U)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xFFU; \
- } while(0U)
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \
+ (__HANDLE__)->Instance->WPR = 0xFFU; \
+ } while(0U)
+
/**
* @brief Enable the RTC ALARMA peripheral.
@@ -527,9 +533,9 @@
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_ALRB: Alarm B interrupt
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_ALRA: Alarm A interrupt
+ * @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
@@ -543,25 +549,25 @@
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag to check.
* This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @arg RTC_FLAG_ALRBF
- * @arg RTC_FLAG_ALRAWF
- * @arg RTC_FLAG_ALRBWF
+ * @arg RTC_FLAG_ALRAF: Alarm A interrupt flag
+ * @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag
+ * @arg RTC_FLAG_ALRBF: Alarm B interrupt flag
+ * @arg RTC_FLAG_ALRBWF: Alarm B 'write allowed' flag
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
/**
* @brief Clear the RTC Alarm's pending flags.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __FLAG__ specifies the RTC Alarm flag to be cleared.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
@@ -569,7 +575,6 @@
*/
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
@@ -579,86 +584,88 @@
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Enable interrupt on the RTC Alarm associated Exti line.
+ * @brief Enable interrupt on the RTC Alarm associated EXTI line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable interrupt on the RTC Alarm associated Exti line.
+ * @brief Disable interrupt on the RTC Alarm associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable event on the RTC Alarm associated Exti line.
+ * @brief Enable event on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable event on the RTC Alarm associated Exti line.
+ * @brief Disable event on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
} while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\
- __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
} while(0U)
/**
- * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Clear the RTC Alarm associated Exti line flag.
+ * @brief Clear the RTC Alarm associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
/**
- * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+ * @brief Generate a Software interrupt on RTC Alarm associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
@@ -666,10 +673,11 @@
* @}
*/
-/* Include RTC HAL Extension module */
+/* Include RTC HAL Extended module */
#include "stm32f4xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
+
/** @addtogroup RTC_Exported_Functions
* @{
*/
@@ -680,8 +688,8 @@
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
@@ -700,11 +708,6 @@
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
@@ -717,9 +720,9 @@
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
@@ -728,7 +731,14 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
+
+/* RTC Daylight Saving Time functions *****************************************/
+void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
+void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
@@ -749,28 +759,38 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
-#define RTC_TR_RESERVED_MASK 0x007F7F7FU
-#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
+#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \
+ RTC_TR_MNT | RTC_TR_MNU | \
+ RTC_TR_ST | RTC_TR_SU | \
+ RTC_TR_PM))
+#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \
+ RTC_DR_MT | RTC_DR_MU | \
+ RTC_DR_DT | RTC_DR_DU | \
+ RTC_DR_WDU))
#define RTC_INIT_MASK 0xFFFFFFFFU
-#define RTC_RSF_MASK 0xFFFFFF5FU
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
- RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
- RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
- RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
+#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \
+ RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \
+ RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | \
+ RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \
+ RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \
+ RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
+ RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK))
-#define RTC_TIMEOUT_VALUE 1000
+#define RTC_TIMEOUT_VALUE 1000U
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
+
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
@@ -780,31 +800,42 @@
*/
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
+
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
((OUTPUT) == RTC_OUTPUT_WAKEUP))
+
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
+
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
+
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
+
+#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
-#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
+ ((PM) == RTC_HOURFORMAT12_PM))
+
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
+
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
+
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -812,7 +843,9 @@
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
+
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
@@ -820,27 +853,31 @@
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
-#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U)
+
+#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
- ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
/**
* @}
@@ -851,12 +888,14 @@
*/
/* Private functions ---------------------------------------------------------*/
+
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-uint8_t RTC_ByteToBcd2(uint8_t Value);
-uint8_t RTC_Bcd2ToByte(uint8_t Value);
+HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
+uint8_t RTC_ByteToBcd2(uint8_t number);
+uint8_t RTC_Bcd2ToByte(uint8_t number);
/**
* @}
*/
@@ -873,6 +912,4 @@
}
#endif
-#endif /* __STM32F4xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32F4xx_HAL_RTC_H */
diff --git a/Inc/stm32f4xx_hal_rtc_ex.h b/Inc/stm32f4xx_hal_rtc_ex.h
index 76859ee..ff5f14d 100644
--- a/Inc/stm32f4xx_hal_rtc_ex.h
+++ b/Inc/stm32f4xx_hal_rtc_ex.h
@@ -2,30 +2,30 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.h
* @author MCD Application Team
- * @brief Header file of RTC HAL Extension module.
+ * @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RTC_EX_H
-#define __STM32F4xx_HAL_RTC_EX_H
+#ifndef STM32F4xx_HAL_RTC_EX_H
+#define STM32F4xx_HAL_RTC_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
+
#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
@@ -34,26 +34,27 @@
/** @addtogroup RTCEx
* @{
- */
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
* @{
*/
-/**
- * @brief RTC Tamper structure definition
+/**
+ * @brief RTC Tamper structure definition
*/
-typedef struct
+typedef struct
{
uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Definitions */
uint32_t PinSelection; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Selection */
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
@@ -62,24 +63,25 @@
This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
- This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */
uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
- This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
-}RTC_TamperTypeDef;
+} RTC_TamperTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
- */
+ */
-/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions
+/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definitions
* @{
*/
#define RTC_BKP_DR0 0x00000000U
@@ -104,213 +106,226 @@
#define RTC_BKP_DR19 0x00000013U
/**
* @}
- */
+ */
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions
+/** @defgroup RTCEx_Timestamp_Edges_Definitions RTCEx Timestamp Edges Definitions
* @{
- */
+ */
#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
-#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U
+#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
/**
* @}
*/
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
+
+/** @defgroup RTCEx_Timestamp_Pin_Selection RTC Timestamp Pin Selection
+ * @{
+ */
+#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
+#if defined(RTC_AF2_SUPPORT)
+#define RTC_TIMESTAMPPIN_POS1 RTC_TAFCR_TSINSEL
+#endif /* RTC_AF2_SUPPORT */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_Pin_Definitions RTCEx Tamper Pins Definitions
* @{
*/
#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E
-
-#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
+#if defined(RTC_TAMPER2_SUPPORT)
#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E
-#endif
+#endif /* RTC_TAMPER2_SUPPORT */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection
+/** @defgroup RTCEx_Tamper_Pin_Selection RTC tamper Pins Selection
* @{
*/
-
#define RTC_TAMPERPIN_DEFAULT 0x00000000U
-
-#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
-#define RTC_TAMPERPIN_POS1 0x00010000U
-#endif
+#if defined(RTC_AF2_SUPPORT)
+#define RTC_TAMPERPIN_POS1 RTC_TAFCR_TAMP1INSEL
+#endif /* RTC_AF2_SUPPORT */
/**
* @}
- */
+ */
-/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection
+/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions
* @{
- */
-#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
-
-#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
-#define RTC_TIMESTAMPPIN_POS1 0x00020000U
-#endif
+ */
+#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /*!< Enable global Tamper Interrupt */
/**
* @}
- */
+ */
-/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions
* @{
- */
+ */
#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U
-#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U
+#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG
#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE
#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE
/**
* @}
- */
+ */
-/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
+/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions
* @{
- */
-#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+ */
+#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
-#define RTC_TAMPERFILTER_2SAMPLE 0x00000800U /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE 0x00001000U /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE 0x00001800U /*!< Tamper is activated after 8
- consecutive samples at the active level. */
+#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8
+ consecutive samples at the active level */
+#define RTC_TAMPERFILTER_MASK RTC_TAFCR_TAMPFLT /*!< Masking all bits except those of
+ field TAMPFLT */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
* @{
- */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 0x00000100U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 0x00000200U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 0x00000300U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 0x00000400U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 0x00000500U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 0x00000600U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 0x00000700U /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
+ */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 32768 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 16384 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 8192 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 4096 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 2048 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 1024 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 512 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAFCR_TAMPFREQ /*!< Masking all bits except those of
+ field TAMPFREQ */
/**
* @}
*/
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
* @{
- */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-/**
- * @}
*/
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
- * @{
- */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
- * @{
- */
-#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
+ sampling during 1 RTCCLK cycle */
+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
+ sampling during 2 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
+ sampling during 4 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before
+ sampling during 8 RTCCLK cycles */
+#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAFCR_TAMPPRCH /*!< Masking all bits except those of
+ field TAMPPRCH */
/**
* @}
*/
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions
+/** @defgroup RTCEx_Tamper_Pull_Up_Definitions RTCEx Tamper Pull Up Definitions
* @{
- */
+ */
+#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_DISABLE RTC_TAFCR_TAMPPUDIS /*!< Tamper pins are not pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_MASK RTC_TAFCR_TAMPPUDIS /*!< Masking all bits except bit TAMPPUDIS */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions
+ * @{
+ */
+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAFCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAFCR_TAMPTS /*!< Masking all bits except bit TAMPTS */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
+ * @{
+ */
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions
- * @{
- */
-#define RTC_CALIBSIGN_POSITIVE 0x00000000U
-#define RTC_CALIBSIGN_NEGATIVE 0x00000080U
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
/**
* @}
*/
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions
+/** @defgroup RTCEx_Coarse_Calibration_Definitions RTCEx Coarse Calib Definitions
* @{
- */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC 0x00002000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC 0x00004000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
- period is 8s, else 2exp18 RTCCLK seconds */
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions
- * @{
- */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET 0x00008000U /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0]
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0] */
+ */
+#define RTC_CALIBSIGN_POSITIVE 0x00000000U
+#define RTC_CALIBSIGN_NEGATIVE RTC_CALIBR_DCS
/**
* @}
*/
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions
+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions
* @{
- */
+ */
+#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 32s, otherwise 2^20 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 16s, otherwise 2^19 RTCCLK pulses */
+#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, smooth calibration
+ period is 8s, otherwise 2^18 RTCCLK pulses */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth Calib Plus Pulses Definitions
+ * @{
+ */
+#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
+ during a X -second window = Y - CALM[8:0]
+ with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
+ during a 32-second window = CALM[8:0] */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions
+ * @{
+ */
#define RTC_SHIFTADD1S_RESET 0x00000000U
-#define RTC_SHIFTADD1S_SET 0x80000000U
+#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
/**
* @}
- */
+ */
-
- /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions
+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions
* @{
- */
-#define RTC_CALIBOUTPUT_512HZ 0x00000000U
-#define RTC_CALIBOUTPUT_1HZ 0x00080000U
+ */
+#define RTC_CALIBOUTPUT_512HZ 0x00000000U
+#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
/**
* @}
- */
+ */
/**
* @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
+ */
+
+/* Exported macros -----------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
* @{
*/
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
+/* ---------------------------------WAKEUPTIMER-------------------------------*/
+
+/** @defgroup RTCEx_WakeUp_Timer RTCEx WakeUp Timer
* @{
*/
@@ -322,152 +337,154 @@
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
- * @brief Disable the RTC Wake-up Timer peripheral.
+ * @brief Disable the RTC Wakeup Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
/**
- * @brief Enable the RTC WakeUpTimer interrupt.
+ * @brief Enable the RTC Wakeup Timer interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC WakeUpTimer interrupt.
+ * @brief Disable the RTC Wakeup Timer interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
+ * @brief Check whether the specified RTC Wakeup Timer interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
+ * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt to check.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer A interrupt
+ * @arg RTC_IT_WUT: Wakeup Timer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
- * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
+ * @brief Check whether the specified RTC Wakeup timer interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
+ * @param __INTERRUPT__ specifies the RTC Wakeup timer interrupt sources to check.
* This parameter can be:
- * @arg RTC_IT_WUT: WakeUpTimer interrupt
+ * @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC WakeUpTimer's flag status.
+ * @brief Get the selected RTC Wakeup Timer's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC WakeUpTimer Flag to check.
+ * @param __FLAG__ specifies the RTC Wakeup Timer flag to check.
* This parameter can be:
- * @arg RTC_FLAG_WUTF
- * @arg RTC_FLAG_WUTWF
+ * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt flag
+ * @arg RTC_FLAG_WUTWF: Wakeup Timer 'write allowed' flag
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
- * @brief Clear the RTC Wake Up timer's pending flags.
+ * @brief Clear the RTC Wakeup timer's pending flags.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * @param __FLAG__ specifies the RTC Wakeup Timer Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_WUTF
+ * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt Flag
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
- * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @brief Enable interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable interrupt on the RTC Wake-up Timer associated Exti line.
+ * @brief Disable interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable event on the RTC Wake-up Timer associated Exti line.
+ * @brief Enable event on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable event on the RTC Wake-up Timer associated Exti line.
+ * @brief Disable event on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
- } while(0U)
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
- __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
- } while(0U)
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Wakeup Timer associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Clear the RTC Wake-up Timer associated Exti line flag.
+ * @brief Clear the RTC Wakeup Timer associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
- * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line.
+ * @brief Generate a Software interrupt on the RTC Wakeup Timer associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
@@ -477,28 +494,29 @@
*/
/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Timestamp
+
+/** @defgroup RTCEx_Timestamp RTCEx Timestamp
* @{
*/
/**
- * @brief Enable the RTC TimeStamp peripheral.
+ * @brief Enable the RTC Timestamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
/**
- * @brief Disable the RTC TimeStamp peripheral.
+ * @brief Disable the RTC Timestamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
- * @brief Enable the RTC TimeStamp interrupt.
+ * @brief Enable the RTC Timestamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -506,9 +524,9 @@
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
- * @brief Disable the RTC TimeStamp interrupt.
+ * @brief Disable the RTC Timestamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -516,42 +534,43 @@
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
- * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
+ * @brief Check whether the specified RTC Timestamp interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
- * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
+ * @brief Check whether the specified RTC Timestamp interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
+ * @param __INTERRUPT__ specifies the RTC Timestamp interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
- * @brief Get the selected RTC TimeStamp's flag status.
+ * @brief Get the selected RTC Timestamp's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC TimeStamp flag to check.
+ * @param __FLAG__ specifies the RTC Timestamp flag to check.
* This parameter can be:
- * @arg RTC_FLAG_TSF
- * @arg RTC_FLAG_TSOVF
+ * @arg RTC_FLAG_TSF: Timestamp interrupt flag
+ * @arg RTC_FLAG_TSOVF: Timestamp overflow flag
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
- * @brief Clear the RTC Time Stamp's pending flags.
+ * @brief Clear the RTC Timestamp's pending flags.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TSF
+ * @param __FLAG__ specifies the RTC Timestamp flag to clear.
+ * This parameter can be:
+ * @arg RTC_FLAG_TSF: Timestamp interrupt flag
+ * @arg RTC_FLAG_TSOVF: Timestamp overflow flag
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -561,7 +580,8 @@
*/
/* ---------------------------------TAMPER------------------------------------*/
-/** @defgroup RTCEx_Tamper RTC Tamper
+
+/** @defgroup RTCEx_Tamper RTCEx Tamper
* @{
*/
@@ -578,8 +598,8 @@
* @retval None
*/
#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
-
-#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
+
+#if defined(RTC_TAMPER2_SUPPORT)
/**
* @brief Enable the RTC Tamper2 input detection.
* @param __HANDLE__ specifies the RTC handle.
@@ -593,47 +613,70 @@
* @retval None
*/
#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
-#endif
-
+#endif /* RTC_TAMPER2_SUPPORT */
+
+/**
+ * @brief Enable the RTC Tamper interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper global interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the RTC Tamper interrupt.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
+ * This parameter can be any combination of the following values:
+ * @arg RTC_IT_TAMP: Tamper global interrupt
+ * @retval None
+ */
+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__))
+
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
- * @arg RTC_IT_TAMP1
- * @arg RTC_IT_TAMP2
+ * @arg RTC_IT_TAMP1: Tamper 1 interrupt
+ * @arg RTC_IT_TAMP2: Tamper 2 interrupt
+ * @note RTC_IT_TAMP2 is not applicable to all devices.
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U)
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be:
- * @arg RTC_IT_TAMP: Tamper interrupt
+ * @arg RTC_IT_TAMP: Tamper global interrupt
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
* @brief Get the selected RTC Tamper's flag status.
* @param __HANDLE__ specifies the RTC handle.
- * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * @param __FLAG__ specifies the RTC Tamper flag to be checked.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
+ * @note RTC_FLAG_TAMP2F is not applicable to all devices.
* @retval None
*/
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
* @brief Clear the RTC Tamper's pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @arg RTC_FLAG_TAMP2F
+ * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag
+ * @note RTC_FLAG_TAMP2F is not applicable to all devices.
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
@@ -647,84 +690,86 @@
*/
/**
- * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable interrupt on the RTC Tamper and Timestamp associated EXTI line.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable interrupt on the RTC Tamper and Timestamp associated EXTI line.
* @retval None
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable event on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable event on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
+ } while(0U)
/**
- * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
+ * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\
- } while(0U)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
- * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.
+ * @brief Check whether the RTC Tamper and Timestamp associated EXTI line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.
+ * @brief Clear the RTC Tamper and Timestamp associated EXTI line flag.
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
- * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
+ * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated EXTI line
* @retval None.
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
@@ -732,8 +777,9 @@
* @}
*/
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Calibration
+/* ------------------------------CALIBRATION----------------------------------*/
+
+/** @defgroup RTCEx_Calibration RTCEx Calibration
* @{
*/
@@ -784,10 +830,10 @@
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
* This parameter can be:
- * @arg RTC_FLAG_SHPF
+ * @arg RTC_FLAG_SHPF: Shift pending flag
* @retval None
*/
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
/**
* @}
*/
@@ -797,6 +843,7 @@
*/
/* Exported functions --------------------------------------------------------*/
+
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
@@ -804,23 +851,27 @@
/** @addtogroup RTCEx_Exported_Functions_Group1
* @{
*/
-/* RTC TimeStamp and Tamper functions *****************************************/
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
+/* RTC Timestamp and Tamper functions *****************************************/
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin);
+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
+#if defined(RTC_TAMPER2_SUPPORT)
+void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
+#endif /* RTC_TAMPER2_SUPPORT */
+void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#if defined(RTC_TAMPER2_SUPPORT)
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+#endif /* RTC_TAMPER2_SUPPORT */
/**
* @}
*/
@@ -828,13 +879,13 @@
/** @addtogroup RTCEx_Exported_Functions_Group2
* @{
*/
-/* RTC Wake-up functions ******************************************************/
+/* RTC Wakeup functions ******************************************************/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
+uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
+void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
@@ -843,13 +894,13 @@
/** @addtogroup RTCEx_Exported_Functions_Group3
* @{
*/
-/* Extension Control functions ************************************************/
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
+/* Extended Control functions ************************************************/
+void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
@@ -864,8 +915,8 @@
/** @addtogroup RTCEx_Exported_Functions_Group4
* @{
*/
-/* Extension RTC features functions *******************************************/
-void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
+/* Extended RTC features functions *******************************************/
+void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
@@ -878,73 +929,83 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
+
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */
+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR21 /*!< External interrupt line 21 Connected to the RTC Tamper and Timestamp event */
+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+/**
+ * @}
+ */
+
+/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
+ * @{
+ */
+/* Masks Definition */
+#if defined(RTC_TAMPER2_SUPPORT)
+#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \
+ RTC_TAMPER_2))
+
+#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \
+ RTC_FLAG_TAMP2F))
+#else /* RTC_TAMPER2_SUPPORT */
+#define RTC_TAMPER_ENABLE_BITS_MASK RTC_TAMPER_1
+
+#define RTC_TAMPER_FLAGS_MASK RTC_FLAG_TAMP1F
+#endif /* RTC_TAMPER2_SUPPORT */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
+
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
* @{
*/
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
* @{
- */
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4) || \
- ((BKP) == RTC_BKP_DR5) || \
- ((BKP) == RTC_BKP_DR6) || \
- ((BKP) == RTC_BKP_DR7) || \
- ((BKP) == RTC_BKP_DR8) || \
- ((BKP) == RTC_BKP_DR9) || \
- ((BKP) == RTC_BKP_DR10) || \
- ((BKP) == RTC_BKP_DR11) || \
- ((BKP) == RTC_BKP_DR12) || \
- ((BKP) == RTC_BKP_DR13) || \
- ((BKP) == RTC_BKP_DR14) || \
- ((BKP) == RTC_BKP_DR15) || \
- ((BKP) == RTC_BKP_DR16) || \
- ((BKP) == RTC_BKP_DR17) || \
- ((BKP) == RTC_BKP_DR18) || \
- ((BKP) == RTC_BKP_DR19))
+ */
+#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER)
+
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E ))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
-#else
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET))
-#endif
+#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~RTC_TAMPER_ENABLE_BITS_MASK)) == 0x00U) && ((TAMPER) != 0U))
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT)
-#else
+#if defined(RTC_AF2_SUPPORT)
#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \
((PIN) == RTC_TAMPERPIN_POS1))
-#endif
+#else /* RTC_AF2_SUPPORT */
+#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT)
+#endif /* RTC_AF2_SUPPORT */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT)
-#else
+#if defined(RTC_AF2_SUPPORT)
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \
((PIN) == RTC_TIMESTAMPPIN_POS1))
-#endif
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+#else /* RTC_AF2_SUPPORT */
+#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT)
+#endif /* RTC_AF2_SUPPORT */
+
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
+
+#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER) \
+ ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) \
+ && ( ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) \
+ || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \
+ || ( ((FILTER) == RTC_TAMPERFILTER_DISABLE) \
+ && ( ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) \
+ || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))))
+
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
@@ -953,14 +1014,18 @@
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
+
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
- ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
((STATE) == RTC_TAMPER_PULLUP_DISABLE))
+
+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
+ ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
+
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
@@ -968,7 +1033,8 @@
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU)
+#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
+
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
((SIGN) == RTC_CALIBSIGN_NEGATIVE))
@@ -976,14 +1042,18 @@
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
- ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
+
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU)
+#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
+
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
- ((SEL) == RTC_SHIFTADD1S_SET))
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU)
+ ((SEL) == RTC_SHIFTADD1S_SET))
+
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
+
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
@@ -996,16 +1066,14 @@
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F4xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32F4xx_HAL_RTC_EX_H */
diff --git a/Inc/stm32f4xx_hal_sai.h b/Inc/stm32f4xx_hal_sai.h
index 0307f92..6c23f93 100644
--- a/Inc/stm32f4xx_hal_sai.h
+++ b/Inc/stm32f4xx_hal_sai.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -118,7 +117,7 @@
uint32_t TriState; /*!< Specifies the companding mode type.
This parameter can be a value of @ref SAI_TRIState_Management */
- /* This part of the structure is automatically filled if your are using the high level intialisation
+ /* This part of the structure is automatically filled if your are using the high level initialisation
function HAL_SAI_InitProtocol */
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
@@ -894,4 +893,3 @@
#endif /* __STM32F4xx_HAL_SAI_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_sai_ex.h b/Inc/stm32f4xx_hal_sai_ex.h
index fbd4497..c6fdd56 100644
--- a/Inc/stm32f4xx_hal_sai_ex.h
+++ b/Inc/stm32f4xx_hal_sai_ex.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -113,4 +112,3 @@
#endif /* __STM32F4xx_HAL_SAI_EX_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_sd.h b/Inc/stm32f4xx_hal_sd.h
index e82e7e0..73fc7de 100644
--- a/Inc/stm32f4xx_hal_sd.h
+++ b/Inc/stm32f4xx_hal_sd.h
@@ -6,13 +6,12 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
@@ -757,5 +756,3 @@
#endif /* STM32F4xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f4xx_hal_sdram.h b/Inc/stm32f4xx_hal_sdram.h
index 3dd7802..3d450a0 100644
--- a/Inc/stm32f4xx_hal_sdram.h
+++ b/Inc/stm32f4xx_hal_sdram.h
@@ -6,27 +6,25 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_SDRAM_H
-#define __STM32F4xx_HAL_SDRAM_H
+#ifndef STM32F4xx_HAL_SDRAM_H
+#define STM32F4xx_HAL_SDRAM_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(FMC_Bank5_6)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_ll_fmc.h"
@@ -37,16 +35,17 @@
/** @addtogroup SDRAM
* @{
- */
+ */
-/* Exported typedef ----------------------------------------------------------*/
+/* Exported typedef ----------------------------------------------------------*/
+
/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
* @{
*/
-/**
- * @brief HAL SDRAM State structure definition
- */
+/**
+ * @brief HAL SDRAM State structure definition
+ */
typedef enum
{
HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
@@ -68,22 +67,22 @@
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
{
FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
-
+
FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
-
+
__IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
-
- HAL_LockTypeDef Lock; /*!< SDRAM locking object */
+
+ HAL_LockTypeDef Lock; /*!< SDRAM locking object */
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */
- void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */
- void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */
- void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Complete callback */
- void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Error callback */
-#endif
+ void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */
+ void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */
+ void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */
+ void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
} SDRAM_HandleTypeDef;
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
@@ -97,20 +96,21 @@
HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */
HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */
HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */
-}HAL_SDRAM_CallbackIDTypeDef;
+} HAL_SDRAM_CallbackIDTypeDef;
/**
* @brief HAL SDRAM Callback pointer definition
*/
typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);
typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
+
/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
* @{
*/
@@ -127,17 +127,18 @@
} while(0)
#else
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
-#endif
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
+
/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
* @{
*/
-/** @addtogroup SDRAM_Exported_Functions_Group1
+/** @addtogroup SDRAM_Exported_Functions_Group1
* @{
*/
@@ -151,50 +152,63 @@
void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
+
/**
* @}
*/
-/** @addtogroup SDRAM_Exported_Functions_Group2
+/** @addtogroup SDRAM_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
/* SDRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+ pSDRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback);
-#endif
+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
+ pSDRAM_DmaCallbackTypeDef pCallback);
+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
