Release v1.2.10
diff --git a/Inc/stm32f7xx_hal_nand.h b/Inc/stm32f7xx_hal_nand.h
index 1d225cf..57e358c 100644
--- a/Inc/stm32f7xx_hal_nand.h
+++ b/Inc/stm32f7xx_hal_nand.h
@@ -6,25 +6,25 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
+ * Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.
*
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_NAND_H
-#define __STM32F7xx_HAL_NAND_H
+#ifndef STM32F7xx_HAL_NAND_H
+#define STM32F7xx_HAL_NAND_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
+
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_fmc.h"
@@ -34,7 +34,7 @@
/** @addtogroup NAND
* @{
- */
+ */
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
@@ -42,7 +42,7 @@
* @{
*/
-/**
+/**
* @brief HAL NAND State structures definition
*/
typedef enum
@@ -51,28 +51,28 @@
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
-}HAL_NAND_StateTypeDef;
-
-/**
+} HAL_NAND_StateTypeDef;
+
+/**
* @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
/*<! NAND memory electronic signature maker and device IDs */
- uint8_t Maker_Id;
+ uint8_t Maker_Id;
uint8_t Device_Id;
uint8_t Third_Id;
uint8_t Fourth_Id;
-}NAND_IDTypeDef;
+} NAND_IDTypeDef;
-/**
+/**
* @brief NAND Memory address Structure definition
*/
-typedef struct
+typedef struct
{
uint16_t Page; /*!< NAND memory Page address */
@@ -80,36 +80,36 @@
uint16_t Block; /*!< NAND memory Block address */
-}NAND_AddressTypeDef;
+} NAND_AddressTypeDef;
-/**
+/**
* @brief NAND Memory info Structure definition
- */
+ */
typedef struct
{
- uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
- for 8 bits addressing or words for 16 bits addressing */
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
+ for 8 bits addressing or words for 16 bits addressing */
- uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
- for 8 bits addressing or words for 16 bits addressing */
-
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
+ for 8 bits addressing or words for 16 bits addressing */
+
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
-
+
uint32_t PlaneNbr; /*!< NAND memory number of planes */
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
- FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
- parameter is mandatory for some NAND parts after the read
- command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
+ FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
+ parameter is mandatory for some NAND parts after the read
+ command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
-}NAND_DeviceConfigTypeDef;
+} NAND_DeviceConfigTypeDef;
-/**
+/**
* @brief NAND handle Structure definition
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
@@ -119,7 +119,7 @@
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
{
FMC_NAND_TypeDef *Instance; /*!< Register base address */
-
+
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NAND locking object */
@@ -129,10 +129,10 @@
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
- void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
- void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
-#endif
+ void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
+ void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
+ void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
@@ -144,13 +144,13 @@
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
-}HAL_NAND_CallbackIDTypeDef;
+} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -159,8 +159,8 @@
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
@@ -174,7 +174,7 @@
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
@@ -184,13 +184,14 @@
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
@@ -205,24 +206,31 @@
/**
* @}
*/
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* IO operation functions ****************************************************/
-
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@@ -230,15 +238,16 @@
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
-HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
-#endif
+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
@@ -250,8 +259,8 @@
/**
* @}
*/
-
-/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* NAND State functions *******************************************************/
@@ -264,39 +273,40 @@
/**
* @}
*/
+
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
-#define NAND_DEVICE ((uint32_t)0x80000000U)
-#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
+#define NAND_DEVICE 0x80000000UL
+#define NAND_WRITE_TIMEOUT 0x01000000UL
-#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
+#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
+#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00U)
-#define NAND_CMD_AREA_B ((uint8_t)0x01U)
-#define NAND_CMD_AREA_C ((uint8_t)0x50U)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
-#define NAND_CMD_READID ((uint8_t)0x90U)
-#define NAND_CMD_STATUS ((uint8_t)0x70U)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
-#define NAND_CMD_RESET ((uint8_t)0xFFU)
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
-#define NAND_BUSY ((uint32_t)0x00000000U)
-#define NAND_ERROR ((uint32_t)0x00000001U)
-#define NAND_READY ((uint32_t)0x00000040U)
+#define NAND_VALID_ADDRESS 0x00000100UL
+#define NAND_INVALID_ADDRESS 0x00000200UL
+#define NAND_TIMEOUT_ERROR 0x00000400UL
+#define NAND_BUSY 0x00000000UL
+#define NAND_ERROR 0x00000001UL
+#define NAND_READY 0x00000040UL
/**
* @}
*/
@@ -313,8 +323,16 @@
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + \
+ (((__ADDRESS__)->Plane) * \
+ ((__HANDLE__)->Config.PlaneSize))) * \
+ ((__HANDLE__)->Config.BlockSize)))
+/**
+ * @brief NAND memory Column address computation.
+ * @param __HANDLE__ NAND handle.
+ * @retval NAND Raw address value
+ */
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
@@ -332,28 +350,28 @@
* @param __ADDRESS__ NAND memory address.
* @retval NAND Column address cycling value.
*/
-#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
+#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/**
* @}
*/
-
-/**
- * @}
- */
-/**
- * @}
- */
/**
* @}
- */
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
-#endif /* __STM32F7xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32F7xx_HAL_NAND_H */
