[HAL][SPI] Add assert on 16-bit aligned address
diff --git a/Inc/stm32g0xx_hal_spi.h b/Inc/stm32g0xx_hal_spi.h
index 4416e93..5788ac0 100644
--- a/Inc/stm32g0xx_hal_spi.h
+++ b/Inc/stm32g0xx_hal_spi.h
@@ -754,6 +754,12 @@
*/
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
+/** @brief Checks if a data address is 16bit aligned.
+ * @param __DATA__ specifies a data address.
+ * @retval None
+ */
+#define IS_SPI_16BIT_ALIGNED_ADDRESS(__DATA__) (((uint32_t)(__DATA__) % 2U) == 0U)
+
/**
* @}
*/
diff --git a/Src/stm32g0xx_hal_spi.c b/Src/stm32g0xx_hal_spi.c
index 6284e41..72f7b19 100644
--- a/Src/stm32g0xx_hal_spi.c
+++ b/Src/stm32g0xx_hal_spi.c
@@ -68,6 +68,14 @@
(##) HAL_SPI_DeInit()
(##) HAL_SPI_Init()
[..]
+ Data buffer address alignment restriction:
+ (#) There is no support for unaligned accesses on the Cortex-M0 processor.
+ If the user wants to transfer in 16Bit data mode, it shall ensure that 16-bit aligned address is used for:
+ (##) pData parameter in HAL_SPI_Transmit(), HAL_SPI_Transmit_IT(), HAL_SPI_Receive() and HAL_SPI_Receive_IT()
+ (##) pTxData and pRxData parameters in HAL_SPI_TransmitReceive() and HAL_SPI_TransmitReceive_IT()
+ (#) There is no such restriction when going through DMA by using HAL_SPI_Transmit_DMA(), HAL_SPI_Receive_DMA()
+ and HAL_SPI_TransmitReceive_DMA().
+ [..]
Callback registration:
(#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
@@ -823,6 +831,13 @@
uint32_t tickstart;
uint16_t initial_TxXferCount;
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* in this case, 16-bit access is performed on Data
+ So, check Data is 16-bit aligned address */
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+ }
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -993,6 +1008,13 @@
#endif /* USE_SPI_CRC */
uint32_t tickstart;
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* in this case, 16-bit access is performed on Data
+ So, check Data is 16-bit aligned address */
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+ }
+
if (hspi->State != HAL_SPI_STATE_READY)
{
return HAL_BUSY;
@@ -1245,6 +1267,14 @@
/* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U;
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* in this case, 16-bit access is performed on Data
+ So, check Data is 16-bit aligned address */
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
+ }
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
@@ -1543,6 +1573,13 @@
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* in this case, 16-bit access is performed on Data
+ So, check Data is 16-bit aligned address */
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+ }
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
@@ -1624,6 +1661,13 @@
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* in this case, 16-bit access is performed on Data
+ So, check Data is 16-bit aligned address */
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pData));
+ }
+
if (hspi->State != HAL_SPI_STATE_READY)
{
@@ -1731,6 +1775,14 @@
uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state;
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ /* in this case, 16-bit access is performed on Data
+ So, check Data is 16-bit aligned address */
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pTxData));
+ assert_param(IS_SPI_16BIT_ALIGNED_ADDRESS(pRxData));
+ }
+
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
