Release v1.2.4
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 4aba5af..0a68e90 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -103,7 +103,15 @@
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
/**
* @}
*/
@@ -207,6 +215,9 @@
#endif
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
/**
* @}
@@ -216,6 +227,11 @@
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
+#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
+#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
+#endif /* STM32U5 */
/**
* @}
*/
@@ -223,10 +239,13 @@
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
+#if defined(STM32H5) || defined(STM32C0)
+#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
inter STM32 series compatibility */
+#endif
/**
* @}
*/
@@ -256,12 +275,22 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
+#endif
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
defined(STM32F4) || defined(STM32G4)
@@ -408,6 +437,9 @@
#endif /* STM32H7 */
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
/**
* @}
*/
@@ -487,7 +519,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
@@ -504,6 +536,28 @@
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
+#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_USER_nBOOT1 OB_USER_NBOOT1
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U0 */
/**
* @}
@@ -547,6 +601,104 @@
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
/**
@@ -624,12 +776,13 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+ defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB */
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -646,6 +799,28 @@
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+
+#if defined(STM32WBA)
+#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
+#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
+#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
+#endif /* STM32WBA */
/**
* @}
*/
@@ -653,6 +828,27 @@
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
* @{
*/
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@@ -900,6 +1096,11 @@
* @}
*/
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL 0x00000000U
+#endif /* STM32U5 */
/**
* @}
*/
@@ -967,7 +1168,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -1063,8 +1264,25 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H5) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 || STM32H7RS */
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1248,6 +1466,10 @@
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
+#if defined(STM32U5)
+#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
+#endif
/**
* @}
*/
@@ -1398,7 +1620,7 @@
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
-#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */
+#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
/**
* @}
@@ -1448,7 +1670,9 @@
*/
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+ || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+ || defined(STM32H7) || defined(STM32U5)
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
@@ -1458,7 +1682,7 @@
* @}
*/
-#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
+#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@@ -1482,6 +1706,10 @@
* @{
*/
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
/**
* @}
@@ -1604,7 +1832,7 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
@@ -1692,6 +1920,92 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
+#endif
/**
* @}
@@ -1700,6 +2014,12 @@
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
/**
* @}
@@ -2014,8 +2334,8 @@
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2048,8 +2368,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2106,8 +2426,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2124,7 +2444,7 @@
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
+#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2426,6 +2746,12 @@
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#if defined(STM32C0)
+#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
+#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
+#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
+#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
+#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3349,8 +3675,12 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3452,8 +3782,10 @@
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3462,7 +3794,124 @@
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
/**
* @}
@@ -3480,7 +3929,9 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3540,6 +3991,10 @@
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
/**
* @}
diff --git a/Inc/stm32g4xx_hal.h b/Inc/stm32g4xx_hal.h
index 5786f8a..e67a203 100644
--- a/Inc/stm32g4xx_hal.h
+++ b/Inc/stm32g4xx_hal.h
@@ -601,7 +601,9 @@
void HAL_SYSCFG_EnableIOSwitchVDD(void);
void HAL_SYSCFG_DisableIOSwitchVDD(void);
+#if defined(CCMSRAM_BASE)
void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
+#endif /* CCMSRAM_BASE */
/**
* @}
diff --git a/Inc/stm32g4xx_hal_adc.h b/Inc/stm32g4xx_hal_adc.h
index 97bc1bb..81622aa 100644
--- a/Inc/stm32g4xx_hal_adc.h
+++ b/Inc/stm32g4xx_hal_adc.h
@@ -1305,7 +1305,7 @@
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
diff --git a/Inc/stm32g4xx_hal_adc_ex.h b/Inc/stm32g4xx_hal_adc_ex.h
index 7acf6e6..d893d33 100644
--- a/Inc/stm32g4xx_hal_adc_ex.h
+++ b/Inc/stm32g4xx_hal_adc_ex.h
@@ -631,7 +631,7 @@
: \
RESET \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
@@ -790,7 +790,7 @@
: \
((__HANDLE_SLAVE__)->Instance = NULL) \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
/**
* @brief Set handle instance of the ADC slave associated to the ADC master.
* @param __HANDLE_MASTER__ ADC master handle.
@@ -816,7 +816,7 @@
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
@@ -828,7 +828,7 @@
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
@@ -947,7 +947,7 @@
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \
((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
@@ -1069,7 +1069,7 @@
((__CHANNEL__) == ADC_CHANNEL_13))) || \
((((__HANDLE__)->Instance) == ADC3) && \
((__CHANNEL__) == ADC_CHANNEL_15))) )
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
@@ -1239,7 +1239,7 @@
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
diff --git a/Inc/stm32g4xx_hal_comp.h b/Inc/stm32g4xx_hal_comp.h
index f575d60..2aecfde 100644
--- a/Inc/stm32g4xx_hal_comp.h
+++ b/Inc/stm32g4xx_hal_comp.h
@@ -369,16 +369,16 @@
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
- LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+ LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
} while(0)
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
} while(0)
@@ -453,17 +453,17 @@
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\
- LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+ LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
} while(0)
/**
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
} while(0)
@@ -537,19 +537,19 @@
* @brief Enable the COMP3 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
- LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
- } while(0)
+#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
+ LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
+ } while(0)
/**
* @brief Disable the COMP3 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
- LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
- } while(0)
+#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
+ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3);\
+ } while(0)
/**
* @brief Enable the COMP3 EXTI line in interrupt mode.
@@ -621,19 +621,19 @@
* @brief Enable the COMP4 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
- LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
- } while(0)
+#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
+ LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
+ } while(0)
/**
* @brief Disable the COMP4 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
- LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
- } while(0)
+#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
+ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4);\
+ } while(0)
/**
* @brief Enable the COMP4 EXTI line in interrupt mode.
@@ -677,7 +677,7 @@
*/
#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP5 EXTI line rising edge trigger.
* @retval None
@@ -706,19 +706,19 @@
* @brief Enable the COMP5 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
- LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
- } while(0)
+#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
+ LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
+ } while(0)
/**
* @brief Disable the COMP5 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
- LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
- } while(0)
+#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
+ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5);\
+ } while(0)
/**
* @brief Enable the COMP5 EXTI line in interrupt mode.
@@ -762,8 +762,8 @@
*/
#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP5)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP6 EXTI line rising edge trigger.
* @retval None
@@ -792,19 +792,19 @@
* @brief Enable the COMP6 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
- LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
- } while(0)
+#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
+ LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
+ } while(0)
/**
* @brief Disable the COMP6 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
- LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
- } while(0)
+#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6);\
+ LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6);\
+ } while(0)
/**
* @brief Enable the COMP6 EXTI line in interrupt mode.
@@ -848,8 +848,8 @@
*/
#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP6)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP7 EXTI line rising edge trigger.
* @retval None
@@ -878,19 +878,19 @@
* @brief Enable the COMP7 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
- LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
- } while(0)
+#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
+ LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
+ } while(0)
/**
* @brief Disable the COMP7 EXTI line rising & falling edge trigger.
* @retval None
*/
-#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
- LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
- } while(0)
+#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+ LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7);\
+ LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7);\
+ } while(0)
/**
* @brief Enable the COMP7 EXTI line in interrupt mode.
@@ -934,7 +934,7 @@
*/
#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP7)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/**
* @}
*/
@@ -957,11 +957,11 @@
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30) /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP7 (LL_EXTI_LINE_33) /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/**
* @}
*/
@@ -994,7 +994,7 @@
* @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
@@ -1007,7 +1007,7 @@
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
: COMP_EXTI_LINE_COMP4)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/**
* @}
*/
@@ -1018,63 +1018,63 @@
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
-#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
(((__COMP_INSTANCE__) == COMP1) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP2) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP3) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP4) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP5) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP6) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP7) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
(((__COMP_INSTANCE__) == COMP1) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP2) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP3) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP4) && \
- (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\
- ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
+ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
+ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
))
#endif
@@ -1098,159 +1098,159 @@
/* Better use IS_COMP_BLANKINGSRC_INSTANCE instead */
/* Macro kept for compatibility with other STM32 series */
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
- ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
+ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((((__INSTANCE__) == COMP1) && \
+ ((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
- || \
- (((__INSTANCE__) == COMP2) && \
+ || \
+ (((__INSTANCE__) == COMP2) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
- || \
- (((__INSTANCE__) == COMP3) && \
+ || \
+ (((__INSTANCE__) == COMP3) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
- || \
- (((__INSTANCE__) == COMP4) && \
+ || \
+ (((__INSTANCE__) == COMP4) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
- || \
- (((__INSTANCE__) == COMP5) && \
+ || \
+ (((__INSTANCE__) == COMP5) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \
- || \
- (((__INSTANCE__) == COMP6) && \
+ || \
+ (((__INSTANCE__) == COMP6) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \
- || \
- (((__INSTANCE__) == COMP7) && \
+ || \
+ (((__INSTANCE__) == COMP7) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((((__INSTANCE__) == COMP1) && \
+ ((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
- || \
- (((__INSTANCE__) == COMP2) && \
+ || \
+ (((__INSTANCE__) == COMP2) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
- || \
- (((__INSTANCE__) == COMP3) && \
+ || \
+ (((__INSTANCE__) == COMP3) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
- || \
- (((__INSTANCE__) == COMP4) && \
+ || \
+ (((__INSTANCE__) == COMP4) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((((__INSTANCE__) == COMP1) && \
+ ((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
- || \
- (((__INSTANCE__) == COMP2) && \
+ || \
+ (((__INSTANCE__) == COMP2) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
- || \
- (((__INSTANCE__) == COMP3) && \
+ || \
+ (((__INSTANCE__) == COMP3) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
- || \
- (((__INSTANCE__) == COMP4) && \
+ || \
+ (((__INSTANCE__) == COMP4) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
diff --git a/Inc/stm32g4xx_hal_cordic.h b/Inc/stm32g4xx_hal_cordic.h
index 2f06845..ddb7a7b 100644
--- a/Inc/stm32g4xx_hal_cordic.h
+++ b/Inc/stm32g4xx_hal_cordic.h
@@ -149,7 +149,6 @@
* @}
*/
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
* @{
@@ -166,6 +165,7 @@
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -183,6 +183,7 @@
#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
+
/**
* @}
*/
@@ -212,6 +213,7 @@
#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
|CORDIC_CSR_PRECISION_0))
+
/**
* @}
*/
@@ -229,6 +231,7 @@
#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
+
/**
* @}
*/
@@ -237,6 +240,7 @@
* @{
*/
#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
+
/**
* @}
*/
@@ -245,6 +249,7 @@
* @{
*/
#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
+
/**
* @}
*/
@@ -253,6 +258,7 @@
* @{
*/
#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
+
/**
* @}
*/
@@ -288,6 +294,7 @@
*/
#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
+
/**
* @}
*/
@@ -297,6 +304,7 @@
*/
#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
+
/**
* @}
*/
@@ -305,6 +313,7 @@
* @{
*/
#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
+
/**
* @}
*/
@@ -316,6 +325,7 @@
#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
+
/**
* @}
*/
@@ -336,9 +346,9 @@
*/
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+ (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
@@ -416,7 +426,7 @@
* @}
*/
-/* Private macros --------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
* @{
*/
@@ -584,6 +594,7 @@
/* Peripheral State functions *************************************************/
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_dac.h b/Inc/stm32g4xx_hal_dac.h
index a331446..d196be0 100644
--- a/Inc/stm32g4xx_hal_dac.h
+++ b/Inc/stm32g4xx_hal_dac.h
@@ -499,7 +499,7 @@
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
(((DACX) == DAC2) ? \
((CHANNEL) == DAC_CHANNEL_1) \
@@ -510,7 +510,7 @@
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
(((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx */
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
diff --git a/Inc/stm32g4xx_hal_dac_ex.h b/Inc/stm32g4xx_hal_dac_ex.h
index d042af1..bbc7f57 100644
--- a/Inc/stm32g4xx_hal_dac_ex.h
+++ b/Inc/stm32g4xx_hal_dac_ex.h
@@ -103,7 +103,7 @@
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
-#if defined(STM32G474xx) || defined(STM32G484xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_DAC_TRIGGER(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
@@ -153,9 +153,9 @@
: ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
-#endif /* STM32G474xx || STM32G484xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
-#if defined(STM32G474xx) || defined(STM32G484xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
@@ -201,7 +201,7 @@
:((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
-#endif /* STM32G474xx || STM32G484xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \
diff --git a/Inc/stm32g4xx_hal_fmac.h b/Inc/stm32g4xx_hal_fmac.h
index ca89269..48a94b6 100644
--- a/Inc/stm32g4xx_hal_fmac.h
+++ b/Inc/stm32g4xx_hal_fmac.h
@@ -243,10 +243,7 @@
* @}
*/
-
/* Exported constants --------------------------------------------------------*/
-
-
/** @defgroup FMAC_Exported_Constants FMAC Exported Constants
* @{
*/
@@ -357,7 +354,6 @@
* @}
*/
-
/* Exported variables --------------------------------------------------------*/
/** @defgroup FMAC_Exported_variables FMAC Exported variables
* @{
@@ -499,7 +495,7 @@
* @}
*/
-/* Private Macros-----------------------------------------------------------*/
+/* Private Macros-------------------------------------------------------------*/
/** @addtogroup FMAC_Private_Macros FMAC Private Macros
* @{
*/
@@ -578,9 +574,9 @@
* @param __FUNCTION__ ID of the filter function.
* @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
*/
-#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
- (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
- (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
+#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
+ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))))
/**
* @brief Verify the FMAC filter parameter R.
diff --git a/Inc/stm32g4xx_hal_i2c_ex.h b/Inc/stm32g4xx_hal_i2c_ex.h
index 840beea..3042f9e 100644
--- a/Inc/stm32g4xx_hal_i2c_ex.h
+++ b/Inc/stm32g4xx_hal_i2c_ex.h
@@ -60,7 +60,11 @@
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
+#endif /* SYSCFG_CFGR1_I2C3_FMP */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
@@ -138,6 +142,7 @@
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+#if defined (I2C3)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
@@ -147,6 +152,16 @@
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
+#else
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
+ ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
+ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
+#endif /* I2C3 */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_irda_ex.h b/Inc/stm32g4xx_hal_irda_ex.h
index 24df2eb..c1f87f4 100644
--- a/Inc/stm32g4xx_hal_irda_ex.h
+++ b/Inc/stm32g4xx_hal_irda_ex.h
@@ -69,7 +69,99 @@
* @param __CLOCKSOURCE__ output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(UART5)
+#if defined(UART5) && !defined(USART3)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#elif defined(UART5) && defined(USART3)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -182,7 +274,78 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#elif defined(UART4)
+#elif defined(UART4) && !defined(USART3)
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#elif defined(UART4) && defined(USART3)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -274,7 +437,7 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#else
+#elif defined(USART3)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -345,7 +508,57 @@
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#endif /* UART5 */
+#else
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* UART5 && !USART3 */
/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
diff --git a/Inc/stm32g4xx_hal_lptim.h b/Inc/stm32g4xx_hal_lptim.h
index 6ceca1a..82176c3 100644
--- a/Inc/stm32g4xx_hal_lptim.h
+++ b/Inc/stm32g4xx_hal_lptim.h
@@ -766,7 +766,7 @@
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-#if defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx)
+#if defined(STM32G414xx) || defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
@@ -793,7 +793,7 @@
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
((__TRIG__) == LPTIM_TRIGSOURCE_9))
-#endif /* STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
+#endif /* STM32G414xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
diff --git a/Inc/stm32g4xx_hal_opamp.h b/Inc/stm32g4xx_hal_opamp.h
index a884905..e00b828 100644
--- a/Inc/stm32g4xx_hal_opamp.h
+++ b/Inc/stm32g4xx_hal_opamp.h
@@ -31,6 +31,8 @@
* @{
*/
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
+
/** @addtogroup OPAMP
* @{
*/
@@ -560,14 +562,14 @@
* @}
*/
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
+
/**
* @}
*/
-
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_OPAMP_H */
-
diff --git a/Inc/stm32g4xx_hal_opamp_ex.h b/Inc/stm32g4xx_hal_opamp_ex.h
index 4ec3601..72d48cf 100644
--- a/Inc/stm32g4xx_hal_opamp_ex.h
+++ b/Inc/stm32g4xx_hal_opamp_ex.h
@@ -31,6 +31,8 @@
* @{
*/
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
+
/** @addtogroup OPAMPEx OPAMPEx
* @{
*/
@@ -71,15 +73,15 @@
* @}
*/
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
+
/**
* @}
*/
-
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_OPAMP_EX_H */
-
diff --git a/Inc/stm32g4xx_hal_pcd.h b/Inc/stm32g4xx_hal_pcd.h
index 1aee820..52e06a9 100644
--- a/Inc/stm32g4xx_hal_pcd.h
+++ b/Inc/stm32g4xx_hal_pcd.h
@@ -806,20 +806,17 @@
\
*(pdwReg) &= 0x3FFU; \
\
- if ((wCount) > 62U) \
+ if ((wCount) == 0U) \
{ \
- PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
+ *(pdwReg) |= USB_CNTRX_BLSIZE; \
+ } \
+ else if ((wCount) <= 62U) \
+ { \
+ PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
- if ((wCount) == 0U) \
- { \
- *(pdwReg) |= USB_CNTRX_BLSIZE; \
- } \
- else \
- { \
- PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
- } \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
diff --git a/Inc/stm32g4xx_hal_pcd_ex.h b/Inc/stm32g4xx_hal_pcd_ex.h
index afb606d..3d85758 100644
--- a/Inc/stm32g4xx_hal_pcd_ex.h
+++ b/Inc/stm32g4xx_hal_pcd_ex.h
@@ -47,7 +47,6 @@
*/
-
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
diff --git a/Inc/stm32g4xx_hal_rcc_ex.h b/Inc/stm32g4xx_hal_rcc_ex.h
index 6cebf27..10206ee 100644
--- a/Inc/stm32g4xx_hal_rcc_ex.h
+++ b/Inc/stm32g4xx_hal_rcc_ex.h
@@ -53,9 +53,10 @@
uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
-
+#if defined(USART3)
uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
+#endif /* UART3 */
#if defined(UART4)
uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
@@ -353,6 +354,7 @@
* @}
*/
+#if defined(SPI_I2S_SUPPORT)
/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
* @{
*/
@@ -363,6 +365,8 @@
/**
* @}
*/
+#endif /* SPI_I2S_SUPPORT */
+
#if defined(FDCAN1)
/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
* @{
@@ -827,6 +831,8 @@
*
* @retval None
*/
+
+#if defined(SAI1)
#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
@@ -839,7 +845,9 @@
*
*/
#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
+#endif /* SAI1 */
+#if defined(SPI_I2S_SUPPORT)
/**
* @brief Macro to configure the I2S clock source.
* @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived
@@ -864,6 +872,7 @@
*
*/
#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
+#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/**
@@ -1404,7 +1413,6 @@
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32G431xx) || defined(STM32G441xx)
-
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
@@ -1423,6 +1431,22 @@
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+#elif defined(STM32G414xx)
+#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
+ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
+ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32GBK1CB)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
@@ -1514,11 +1538,13 @@
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
+#if defined(SAI1)
#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
+#endif /* SAI1 */
#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \
diff --git a/Inc/stm32g4xx_hal_sai.h b/Inc/stm32g4xx_hal_sai.h
index 771d4d6..d8311b2 100644
--- a/Inc/stm32g4xx_hal_sai.h
+++ b/Inc/stm32g4xx_hal_sai.h
@@ -31,6 +31,8 @@
* @{
*/
+#if defined(SAI1)
+
/** @addtogroup SAI
* @{
*/
@@ -943,6 +945,8 @@
* @}
*/
+#endif /* SAI1 */
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_sai_ex.h b/Inc/stm32g4xx_hal_sai_ex.h
index 05771be..86a9625 100644
--- a/Inc/stm32g4xx_hal_sai_ex.h
+++ b/Inc/stm32g4xx_hal_sai_ex.h
@@ -31,6 +31,8 @@
* @{
*/
+#if defined(SAI1)
+
/** @addtogroup SAIEx
* @{
*/
@@ -92,6 +94,8 @@
* @}
*/
+#endif /* SAI1 */
+
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_smartcard.h b/Inc/stm32g4xx_hal_smartcard.h
index a2f700d..d765c0f 100644
--- a/Inc/stm32g4xx_hal_smartcard.h
+++ b/Inc/stm32g4xx_hal_smartcard.h
@@ -859,6 +859,7 @@
* @param __CLOCKSOURCE__ output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
+#if defined(USART3)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -929,6 +930,57 @@
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
+#else
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* USART3 */
/** @brief Check the Baud rate range.
* @note The maximum Baud Rate is derived from the maximum clock on G4 (150 MHz)
diff --git a/Inc/stm32g4xx_hal_smbus_ex.h b/Inc/stm32g4xx_hal_smbus_ex.h
index 5043329..7ddf770 100644
--- a/Inc/stm32g4xx_hal_smbus_ex.h
+++ b/Inc/stm32g4xx_hal_smbus_ex.h
@@ -51,7 +51,11 @@
#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
+#if defined(SYSCFG_CFGR1_I2C3_FMP)
#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
+#else
+#define SMBUS_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
+#endif /* SYSCFG_CFGR1_I2C3_FMP */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
diff --git a/Inc/stm32g4xx_hal_uart.h b/Inc/stm32g4xx_hal_uart.h
index bb06ee8..2f308b3 100644
--- a/Inc/stm32g4xx_hal_uart.h
+++ b/Inc/stm32g4xx_hal_uart.h
@@ -1230,7 +1230,7 @@
/** @defgroup UART_Private_Macros UART Private Macros
* @{
*/
-/** @brief Get UART clok division factor from clock prescaler value.
+/** @brief Get UART clock division factor from clock prescaler value.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval UART clock division factor
*/
@@ -1245,8 +1245,7 @@
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \
- ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)
+ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U)
/** @brief BRR division operation to set BRR register with LPUART.
* @param __PCLK__ LPUART clock.
diff --git a/Inc/stm32g4xx_hal_uart_ex.h b/Inc/stm32g4xx_hal_uart_ex.h
index 34c1715..0c56e27 100644
--- a/Inc/stm32g4xx_hal_uart_ex.h
+++ b/Inc/stm32g4xx_hal_uart_ex.h
@@ -199,7 +199,7 @@
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
-#if defined(UART5)
+#if defined(UART5) && defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -333,7 +333,120 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#elif defined(UART4)
+#elif defined(UART5) && !defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART5) \
+ { \
+ switch(__HAL_RCC_GET_UART5_SOURCE()) \
+ { \
+ case RCC_UART5CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART5CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART5CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART5CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
+ { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#elif defined(UART4) && defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -446,7 +559,99 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#else
+#elif defined(UART4) && !defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == UART4) \
+ { \
+ switch(__HAL_RCC_GET_UART4_SOURCE()) \
+ { \
+ case RCC_UART4CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_UART4CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_UART4CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_UART4CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
+ { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#elif defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -538,7 +743,78 @@
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
-#endif /* UART5 */
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == LPUART1) \
+ { \
+ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
+ { \
+ case RCC_LPUART1CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_LPUART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0U)
+#endif /* UART5 && !USART3 */
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
diff --git a/Inc/stm32g4xx_hal_usart.h b/Inc/stm32g4xx_hal_usart.h
index 8e012b8..7c305b8 100644
--- a/Inc/stm32g4xx_hal_usart.h
+++ b/Inc/stm32g4xx_hal_usart.h
@@ -704,8 +704,7 @@
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \
- ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \
- ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
+ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U)
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
@@ -722,6 +721,7 @@
* @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
+#if defined(USART3)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
@@ -792,6 +792,57 @@
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
+ do { \
+ if((__HANDLE__)->Instance == USART1) \
+ { \
+ switch(__HAL_RCC_GET_USART1_SOURCE()) \
+ { \
+ case RCC_USART1CLKSOURCE_PCLK2: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
+ break; \
+ case RCC_USART1CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART1CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART1CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else if((__HANDLE__)->Instance == USART2) \
+ { \
+ switch(__HAL_RCC_GET_USART2_SOURCE()) \
+ { \
+ case RCC_USART2CLKSOURCE_PCLK1: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
+ break; \
+ case RCC_USART2CLKSOURCE_HSI: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
+ break; \
+ case RCC_USART2CLKSOURCE_SYSCLK: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
+ break; \
+ case RCC_USART2CLKSOURCE_LSE: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
+ break; \
+ default: \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ break; \
+ } \
+ } \
+ else \
+ { \
+ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
+ } \
+ } while(0)
+#endif /* USART3 */
/** @brief Check USART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
diff --git a/Inc/stm32g4xx_ll_adc.h b/Inc/stm32g4xx_ll_adc.h
index dc64ef1..5621f09 100644
--- a/Inc/stm32g4xx_ll_adc.h
+++ b/Inc/stm32g4xx_ll_adc.h
@@ -2873,7 +2873,7 @@
) \
) \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC1) \
&&( \
diff --git a/Inc/stm32g4xx_ll_cordic.h b/Inc/stm32g4xx_ll_cordic.h
index 8adb69b..5abc532 100644
--- a/Inc/stm32g4xx_ll_cordic.h
+++ b/Inc/stm32g4xx_ll_cordic.h
@@ -131,12 +131,12 @@
/** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE
* @{
*/
-#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
- 32-bit data input (Q1.31 format), or two
- 16-bit data input (Q1.15 format) packed
- in one 32 bits Data */
-#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
- (Q1.31 format) */
+#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
+ 32-bits data input (Q1.31 format), or two
+ 16-bits data input (Q1.15 format) packed
+ in one 32 bits Data */
+#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
+ (Q1.31 format) */
/**
* @}
*/
@@ -144,12 +144,12 @@
/** @defgroup CORDIC_LL_EC_NBREAD NBREAD
* @{
*/
-#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
- 32-bit data output (Q1.31 format), or two
- 16-bit data output (Q1.15 format) packed
- in one 32 bits Data */
-#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
- (Q1.31 format) */
+#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
+ 32-bits data output (Q1.31 format), or two
+ 16-bits data output (Q1.15 format) packed
+ in one 32 bits Data */
+#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
+ (Q1.31 format) */
/**
* @}
*/
@@ -218,9 +218,7 @@
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
-
/** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions
* @{
*/
@@ -749,8 +747,6 @@
* @}
*/
-
-
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions
* @{
diff --git a/Inc/stm32g4xx_ll_fmac.h b/Inc/stm32g4xx_ll_fmac.h
index 102cac0..63fac20 100644
--- a/Inc/stm32g4xx_ll_fmac.h
+++ b/Inc/stm32g4xx_ll_fmac.h
@@ -38,7 +38,6 @@
*/
/* Exported types ------------------------------------------------------------*/
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants
* @{
@@ -147,9 +146,7 @@
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
-
/** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions
* @{
*/
@@ -1033,8 +1030,6 @@
* @}
*/
-
-
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions
* @{
@@ -1042,7 +1037,6 @@
ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx);
-
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_lpuart.h b/Inc/stm32g4xx_ll_lpuart.h
index e3f996a..0c9a894 100644
--- a/Inc/stm32g4xx_ll_lpuart.h
+++ b/Inc/stm32g4xx_ll_lpuart.h
@@ -2606,6 +2606,21 @@
}
/**
+ * @brief Request a Transmit data FIFO flush
+ * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
+ * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * FIFO mode feature is supported by the USARTx instance.
+ * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_pwr.h b/Inc/stm32g4xx_ll_pwr.h
index e3c1bef..4a5a0c9 100644
--- a/Inc/stm32g4xx_ll_pwr.h
+++ b/Inc/stm32g4xx_ll_pwr.h
@@ -783,6 +783,7 @@
return ((temp == (PWR_CR3_APC))?1U:0U);
}
+#if defined(SRAM2_BASE)
/**
* @brief Enable SRAM2 content retention in Standby mode
* @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
@@ -816,6 +817,7 @@
return ((temp == (PWR_CR3_RRS))?1U:0U);
}
+#endif /* SRAM2_BASE */
/**
* @brief Enable the WakeUp PINx functionality
* @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
diff --git a/Inc/stm32g4xx_ll_rcc.h b/Inc/stm32g4xx_ll_rcc.h
index 9fef6c1..eb9d9f4 100644
--- a/Inc/stm32g4xx_ll_rcc.h
+++ b/Inc/stm32g4xx_ll_rcc.h
@@ -319,10 +319,12 @@
#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
+#if defined(RCC_CCIPR_USART3SEL)
#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
+#endif /* RCC_CCIPR_USART3SEL */
/**
* @}
*/
@@ -472,7 +474,9 @@
*/
#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
+#if defined(RCC_CCIPR_USART3SEL)
#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
+#endif /* RCC_CCIPR_USART3SEL */
/**
* @}
*/
@@ -503,7 +507,9 @@
*/
#define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
#define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
+#if defined(RCC_CCIPR_I2C3SEL)
#define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
+#endif /* RCC_CCIPR_I2C3SEL */
#if defined(RCC_CCIPR2_I2C4SEL)
#define LL_RCC_I2C4_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
#endif /* RCC_CCIPR2_I2C4SEL */
@@ -1602,6 +1608,7 @@
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
}
+#if defined(SAI1)
/**
* @brief Configure SAIx clock source
* @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
@@ -1618,7 +1625,9 @@
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
}
+#endif /* SAI1 */
+#if defined(SPI_I2S_SUPPORT)
/**
* @brief Configure I2S clock source
* @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource
@@ -1633,6 +1642,7 @@
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
}
+#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/**
diff --git a/Inc/stm32g4xx_ll_rng.h b/Inc/stm32g4xx_ll_rng.h
index dce1306..90d95e5 100644
--- a/Inc/stm32g4xx_ll_rng.h
+++ b/Inc/stm32g4xx_ll_rng.h
@@ -369,7 +369,7 @@
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
*/
-ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct);
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
diff --git a/Inc/stm32g4xx_ll_system.h b/Inc/stm32g4xx_ll_system.h
index e90aebb..58aedfc 100644
--- a/Inc/stm32g4xx_ll_system.h
+++ b/Inc/stm32g4xx_ll_system.h
@@ -187,6 +187,7 @@
/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
* @{
*/
+#if defined(CCMSRAM_BASE)
#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
@@ -197,6 +198,7 @@
#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
+#endif /* CCMSRAM_BASE */
#if defined(SYSCFG_SWPR_PAGE10)
#define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
@@ -261,7 +263,9 @@
#if defined(I2C2)
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
#endif /* I2C2 */
+#if defined(I2C3)
#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
+#endif /* I2C3 */
#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
/**
* @}
@@ -754,6 +758,7 @@
return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU));
}
+#if defined (CCMSRAM_BASE)
/**
* @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is
* automatically cleared at the end of the CCMSRAM erase operation.)
@@ -779,6 +784,7 @@
return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL);
}
+#endif /* CCMSRAM_BASE */
/**
* @brief Set connections to TIM1/8/15/16/17 Break inputs
* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
@@ -834,6 +840,7 @@
SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
}
+#if defined(CCMSRAM_BASE)
/**
* @brief Enable CCMSRAM page write protection
* @note Write protection is cleared only by a system reset
@@ -902,7 +909,7 @@
WRITE_REG(SYSCFG->SKR, 0xCA);
WRITE_REG(SYSCFG->SKR, 0x53);
}
-
+#endif /* CCMSRAM_BASE */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_ucpd.h b/Inc/stm32g4xx_ll_ucpd.h
index 2cafeaa..0e90d7e 100644
--- a/Inc/stm32g4xx_ll_ucpd.h
+++ b/Inc/stm32g4xx_ll_ucpd.h
@@ -847,7 +847,7 @@
}
/**
- * @brief Enable Rx hard resrt interrupt
+ * @brief Enable Rx hard reset interrupt
* @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval None
@@ -1012,7 +1012,7 @@
}
/**
- * @brief Disable Rx hard resrt interrupt
+ * @brief Disable Rx hard reset interrupt
* @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval None
@@ -1177,7 +1177,7 @@
}
/**
- * @brief Check if Rx hard resrt interrupt enabled
+ * @brief Check if Rx hard reset interrupt enabled
* @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
@@ -1350,7 +1350,7 @@
}
/**
- * @brief Clear Rx hard resrt interrupt
+ * @brief Clear Rx hard reset interrupt
* @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
* @param UCPDx UCPD Instance
* @retval None
@@ -1501,7 +1501,7 @@
}
/**
- * @brief Check if Rx hard resrt interrupt
+ * @brief Check if Rx hard reset interrupt
* @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
* @param UCPDx UCPD Instance
* @retval None
@@ -1833,7 +1833,7 @@
*/
ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
-ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct);
void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
/**
diff --git a/Inc/stm32g4xx_ll_utils.h b/Inc/stm32g4xx_ll_utils.h
index 60510db..e8c955f 100644
--- a/Inc/stm32g4xx_ll_utils.h
+++ b/Inc/stm32g4xx_ll_utils.h
@@ -160,14 +160,13 @@
*/
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */
-#if defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32G471xx) || \
- defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || \
- defined (STM32G484xx)
+#if defined (STM32G431xx) || defined (STM32G414xx) || defined (STM32G441xx) || defined (STM32G471xx) || \
+ defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || defined (STM32G484xx)
#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U /*!< LQFP100 \ LQFP80 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 /*!< For backward compatibility */
#else
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
-#endif /* STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */
+#endif /* STM32G431xx || STM32G414xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
#define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */
#define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U /*!< LQFP128 \ UFBGA121 package type */
#define LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 /*!< For backward compatibility */
diff --git a/Release_Notes.html b/Release_Notes.html
index c38e0b0..0799e96 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -5,13 +5,16 @@
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for STM32G4xx HAL Drivers</title>
- <style type="text/css">
- code{white-space: pre-wrap;}
- span.smallcaps{font-variant: small-caps;}
- span.underline{text-decoration: underline;}
- div.column{display: inline-block; vertical-align: top; width: 50%;}
+ <style>
+ code{white-space: pre-wrap;}
+ span.smallcaps{font-variant: small-caps;}
+ span.underline{text-decoration: underline;}
+ div.column{display: inline-block; vertical-align: top; width: 50%;}
+ div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
+ ul.task-list{list-style: none;}
+ .display.math{display: block; text-align: center; margin: 0.5rem auto;}
</style>
- <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
@@ -24,7 +27,7 @@
<h1 id="release-notes-for-stm32g4xx-hal-drivers"><small>Release Notes for</small> STM32G4xx HAL Drivers</h1>
<p>Copyright © 2019 STMicroelectronics<br />
</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
</center>
<h1 id="purpose">Purpose</h1>
<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
@@ -37,14 +40,103 @@
<li>Full features coverage of the all the supported peripherals.</li>
</ul>
</div>
-<div class="col-sm-12 col-lg-8">
-<h1 id="update-history">Update History</h1>
+<section id="update-history" class="col-sm-12 col-lg-8">
+<h1>Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section7" checked aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.2.3 / 15-December-2023</label>
+<input type="checkbox" id="collapse-section8" checked aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">V1.2.4 / 05-June-2024</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<h3 id="maintenance-release">Maintenance Release</h3>
<ul>
+<li><p>Add support of <strong>STM32G414xx</strong> devices.</p></li>
+<li><p>General updates to fix known defects and enhancements implementation.</p></li>
+<li><p><strong>HAL DAC</strong> update</p>
+<ul>
+<li>Update HAL_DACEx_SelfCalibrate() API to manage case of calibration factor equal to range maximum value.</li>
+</ul></li>
+<li><p><strong>HAL CORTEX</strong> update</p>
+<ul>
+<li>Update HAL_MPU_ConfigRegion() API to allow the configuration of the MPU registers independently of the value of Enable/Disable field.</li>
+<li>Add new HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion() APIs.</li>
+</ul></li>
+<li><p><strong>HAL QSPI</strong> update</p>
+<ul>
+<li>Clear AR register after CCR to avoid new transfer when address is not needed.</li>
+</ul></li>
+<li><p><strong>HAL I2C</strong> update</p>
+<ul>
+<li>Code quality enhancement MISRA-C 2012 Rule-13.5 within the HAL_I2C_Master_Abort_IT() API:
+<ul>
+<li>Add a temporary variable to get the value to check before comparison.</li>
+</ul></li>
+<li>Add abort memory management to HAL_I2C_Master_Abort_IT() API.</li>
+<li>Move the prefetch process in HAL_I2C_Slave_Transmit() API.</li>
+</ul></li>
+<li><p><strong>HAL SPI</strong> update</p>
+<ul>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers..</li>
+</ul></li>
+<li><p><strong>HAL/LL TIM</strong> update</p>
+<ul>
+<li>Fixed typo in PWM asymmetric mode related constants.</li>
+</ul></li>
+<li><p><strong>HAL UART</strong> update</p>
+<ul>
+<li>Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.</li>
+<li>Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.</li>
+<li>Correct wrong comment in HAL_UARTEx_DisableFifoMode() API.</li>
+<li>Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode.</li>
+</ul></li>
+<li><p><strong>HAL USART</strong> update</p>
+<ul>
+<li>Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.</li>
+<li>Correct wrong comment in HAL_USARTEx_DisableFifoMode() API.</li>
+<li>Improve the visibility of the SPI mode support in HAL USART description.</li>
+</ul></li>
+<li><p><strong>HAL CRYP</strong> update</p>
+<ul>
+<li>Code quality enhancement MISRA-C 2012 Rule-10.4 within HAL_CRYP_IRQHandler() API.</li>
+</ul></li>
+<li><p><strong>HAL FDCAN</strong> update</p>
+<ul>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li>
+</ul></li>
+<li><p><strong>LL BUS</strong> update</p>
+<ul>
+<li>Update macro definition LL_AHB2_GRP1_PERIPH_CCM.</li>
+</ul></li>
+<li><p><strong>LL LPUART</strong> update</p>
+<ul>
+<li>Add LL_LPUART_RequestTxDataFlush() API allowing TX FIFO flush request.</li>
+</ul></li>
+<li><p><strong>LL UCPD</strong> update</p>
+<ul>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li>
+<li>Fix typo in Doxygen sections.</li>
+</ul></li>
+</ul>
+<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.50.9</strong> + ST-LINKV2</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.38</strong> + ST-LINKV2</li>
+<li>STM32CubeIDE toolchain (gcc9_2020_q2_update) <strong>V1.14.0</strong></li>
+</ul>
+<h2 id="supported-devices">Supported Devices</h2>
+<ul>
+<li>STM32G431xx/41xx</li>
+<li>STM32G471xx</li>
+<li><strong>STM32G414</strong>/73/83xx</li>
+<li>STM32G474/84xx</li>
+<li>STM32G491/A1xx</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">V1.2.3 / 15-December-2023</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="maintenance-release-1">Maintenance Release</h3>
+<ul>
<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li>
<li><strong>HAL Generic</strong> update
<ul>
@@ -247,13 +339,13 @@
<li>Fix a note about Ticks parameter.</li>
</ul></li>
</ul>
-<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.50.9</strong> + ST-LINKV2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.38</strong> + ST-LINKV2</li>
<li>STM32CubeIDE toolchain (gcc9_2020_q2_update) <strong>V1.14.0</strong></li>
</ul>
-<h2 id="supported-devices">Supported Devices</h2>
+<h2 id="supported-devices-1">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -266,29 +358,29 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">V1.2.2 / 10-November-2021</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<h3 id="maintenance-release-1">Maintenance Release</h3>
+<h2 id="main-changes-2">Main Changes</h2>
+<h3 id="maintenance-release-2">Maintenance Release</h3>
<ul>
<li><p>General updates to fix known defects and enhancements implementation.</p></li>
-<li><strong>HAL/LL ADC</strong> update
+<li><p><strong>HAL/LL ADC</strong> update</p>
<ul>
<li>Update HAL_ADC_Start_DMA() API to avoid return error when using Independent instance with multimode activated.</li>
<li>Update of the TEMPSENSOR_CAL2_TEMP value in the ll_adc.h file.</li>
<li>Update LL_ADC_SetChannelSingleDiff() API to be compliant with ARM CLang compiler v6.16.</li>
</ul></li>
-<li><strong>HAL/LL RCC</strong> update
+<li><p><strong>HAL/LL RCC</strong> update</p>
<ul>
<li>Add missing API IsEnabled for PLL "domain" output.</li>
<li>Enhance RCC_MCOx in order to support both MCO number (PA8 and PG10) and AF mapping.</li>
</ul></li>
-<li><strong>HAL/LL USART</strong> update
+<li><p><strong>HAL/LL USART</strong> update</p>
<ul>
<li>Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)</li>
<li>Add const qualifier for read only pointers.</li>
<li>Improve header description of USART_WaitOnFlagUntilTimeout() function</li>
<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
</ul></li>
-<li><strong>HAL/LL UART</strong> update
+<li><p><strong>HAL/LL UART</strong> update</p>
<ul>
<li>Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA().</li>
<li>Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback</li>
@@ -298,51 +390,51 @@
<li>Add const qualifier for read only pointers.</li>
<li>Fix wrong cast when computing the USARTDIV value in UART_SetConfig().</li>
</ul></li>
-<li><strong>LL LPTIM</strong> update
+<li><p><strong>LL LPTIM</strong> update</p>
<ul>
<li>Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable().</li>
</ul></li>
-<li><strong>LL TIM</strong> update
+<li><p><strong>LL TIM</strong> update</p>
<ul>
<li>Update LL_TIM_OC_SetPulseWidth implementation to properly align the PulseWidth input value with the TIM_ECR register.</li>
<li>Fix wrong compile switch used in TIM_LL_EC_DMABURST_BASEADDR constant definitions.</li>
</ul></li>
-<li><strong>LL LPUART</strong> update
+<li><p><strong>LL LPUART</strong> update</p>
<ul>
<li>Remove useless TXFECF reference from LL LPUART driver.</li>
</ul></li>
-<li><strong>HAL IRDA</strong> update
+<li><p><strong>HAL IRDA</strong> update</p>
<ul>
<li>Improve header description of IRDA_WaitOnFlagUntilTimeout() function</li>
<li>Add a check on the IRDA parity before enabling the parity error interrupt.</li>
<li>Add const qualifier for read only pointers.</li>
<li>Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().</li>
</ul></li>
-<li><strong>HAL SMARTCARD</strong> update
+<li><p><strong>HAL SMARTCARD</strong> update</p>
<ul>
<li>Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function.</li>
<li>Add const qualifier for read only pointers.</li>
<li>Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().</li>
</ul></li>
-<li><strong>HAL/LL SPI</strong> update
+<li><p><strong>HAL/LL SPI</strong> update</p>
<ul>
<li>Updated to fix MISRA-C 2012 Rule-13.2.</li>
<li>Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.</li>
</ul></li>
-<li><strong>HAL RTC</strong> update
+<li><p><strong>HAL RTC</strong> update</p>
<ul>
<li>Update __HAL_RTC_…(<strong>HANDLE</strong>, …) macros to access registers through (<strong>HANDLE</strong>)->Instance pointer and avoid “unused variable” warnings.</li>
</ul></li>
-<li><strong>HAL CRYP</strong> update
+<li><p><strong>HAL CRYP</strong> update</p>
<ul>
<li>CRYP_AESCCM_Process_IT() update to manage header lengths in bytes or words when header length is less than 16 bytes.</li>
</ul></li>
-<li><strong>HAL HRTIM</strong> update
+<li><p><strong>HAL HRTIM</strong> update</p>
<ul>
<li>Fix compilation ARMCLANG -Wparenteses-equality warnings.</li>
<li>Fix missing initial update when Resynchronized update is used.</li>
</ul></li>
-<li><strong>HAL FLASH</strong> update
+<li><p><strong>HAL FLASH</strong> update</p>
<ul>
<li>Update to support STM32G4 part numbers with 256K flash</li>
<li>Disable ICache while Flash programming.
@@ -350,27 +442,27 @@
<li>Update HAL_FLASHEx_Erase() to remove __HAL_FLASH_INSTRUCTION_CACHE_DISABLE().</li>
</ul></li>
</ul></li>
-<li><strong>HAL USB</strong> update
+<li><p><strong>HAL USB</strong> update</p>
<ul>
<li>HAL PCD: add fix transfer complete for IN Interrupt transaction in single buffer mode</li>
</ul></li>
-<li><strong>HAL GPIO</strong> update
+<li><p><strong>HAL GPIO</strong> update</p>
<ul>
<li>Reorder EXTI configuration sequence in order to avoid unexpected level detection.</li>
<li>Optimize assertion control for GPIO Pull mode in HAL_GPIO_Init() API.</li>
<li>Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.</li>
</ul></li>
-<li><strong>HAL EXTI</strong> update
+<li><p><strong>HAL EXTI</strong> update</p>
<ul>
<li>Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.</li>
</ul></li>
-<li><strong>HAL USART</strong> update
+<li><p><strong>HAL USART</strong> update</p>
<ul>
<li>Improve header description of USART_WaitOnFlagUntilTimeout() function</li>
<li>Add a check on the USART parity before enabling the parity error interrupt.</li>
<li>Fix compilation warnings generated with ARMV6 compiler.</li>
</ul></li>
-<li><strong>HAL I2C</strong> update
+<li><p><strong>HAL I2C</strong> update</p>
<ul>
<li>Update I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.</li>
<li>Update to handle errors in polling mode.
@@ -380,7 +472,7 @@
<li>Update to fix issue detected due to low system frequency execution (HSI).</li>
<li>Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA.</li>
</ul></li>
-<li><strong>HAL SMBUS</strong> update
+<li><p><strong>HAL SMBUS</strong> update</p>
<ul>
<li>Add the support of wake up capability.
<ul>
@@ -395,26 +487,26 @@
<li>Add flush on TX register.</li>
</ul></li>
</ul></li>
-<li><strong>HAL IWDG</strong> update
+<li><p><strong>HAL IWDG</strong> update</p>
<ul>
<li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li>
</ul></li>
-<li><strong>HAL RNG</strong> update
+<li><p><strong>HAL RNG</strong> update</p>
<ul>
<li>Update timeout mechanism to avoid false timeout detection in case of preemption.</li>
</ul></li>
-<li><strong>HAL NAND</strong> update
+<li><p><strong>HAL NAND</strong> update</p>
<ul>
<li>Update implementation of “HAL_NAND_Write_Page_16b” and “HAL_NAND_Read_Page_16b” APIs implementation to fix an issue with the page calculation of 8 bits memories.</li>
</ul></li>
</ul>
-<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-LINKV2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-LINKV2</li>
<li>STM32CubeIDE toolchain (gcc9_2020_q2_update) <strong>V1.7.0</strong></li>
</ul>
-<h2 id="supported-devices-1">Supported Devices</h2>
+<h2 id="supported-devices-2">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -427,31 +519,31 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">V1.2.1 / 27-January-2021</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
-<h3 id="maintenance-release-2">Maintenance Release</h3>
+<h2 id="main-changes-3">Main Changes</h2>
+<h3 id="maintenance-release-3">Maintenance Release</h3>
<ul>
<li><p>General updates to fix known defects and enhancements implementation</p></li>
-<li><strong>HAL</strong></li>
-<li>General updates to fix known defects and enhancements implementation.</li>
-<li>Support for new ARM compiler Keil V6.</li>
-<li>Added new defines for ARM compiler V6:
+<li><p><strong>HAL</strong></p></li>
+<li><p>General updates to fix known defects and enhancements implementation.</p></li>
+<li><p>Support for new ARM compiler Keil V6.</p></li>
+<li><p>Added new defines for ARM compiler V6:</p>
<ul>
<li>__weak</li>
<li>__packed</li>
<li>__NOINLINE</li>
</ul></li>
-<li><strong>LL RCC</strong> update
+<li><p><strong>LL RCC</strong> update</p>
<ul>
<li>Private functions made static.</li>
</ul></li>
-<li><strong>HAL CRYP</strong> update
+<li><p><strong>HAL CRYP</strong> update</p>
<ul>
<li>Correction made for the Official NIST CCM test pattern ciphering failing when header length is null.</li>
<li>GCM/GMAC/CCM data header is now fed using DMA instead of polling.</li>
<li>Fixed CRYP HAL driver to manage GCM header lengths not multiple of 4 bytes in 8-bit, 16-bit and 32-bit data types.</li>
<li>Fixed handling of AUD with size not multiple of 4 bytes in CRYP_AESGCM_Process_IT for GCM.</li>
</ul></li>
-<li><strong>HAL RTC</strong> Update
+<li><p><strong>HAL RTC</strong> Update</p>
<ul>
<li>New APIs to subtract or add one hour to the calendar in one single operation without going through the initialization procedure (Daylight Saving):
<ul>
@@ -465,37 +557,37 @@
<li>Updated HAL_RTC_SetTimeStamp() API to call __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT before configuring the TimeStamp.</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL TIM</strong> update
+<li><p><strong>HAL/LL TIM</strong> update</p>
<ul>
<li>Updated HAL_TIMEx_OnePulseN_Start() and HAL_TIMEx_OnePulseN_Stop() APIs (pooling and IT mode) to take into consideration all OutputChannel parameters.</li>
<li>Corrected reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.</li>
<li>Updated LL_TIM_GetCounterMode() API to return the correct counter mode.</li>
</ul></li>
-<li><strong>HAL/LL LPTIM</strong> update
+<li><p><strong>HAL/LL LPTIM</strong> update</p>
<ul>
<li>Updated HAL_LPTIM_Init() API implementation to configure digital filter for external clock when LPTIM is configured with internal clock source.</li>
</ul></li>
-<li><strong>HAL/LL HRTIM</strong> update
+<li><p><strong>HAL/LL HRTIM</strong> update</p>
<ul>
<li>IRQ handlers optimized by reducing the multiple read-accesses to ISR and IER registers to one read-access per register.</li>
<li>LL_HRTIM_FLT_SetSrc() API updated to avoid overwriting the content of FLTINR2 register on successive calls.</li>
</ul></li>
-<li><strong>HAL EXTI</strong> update
+<li><p><strong>HAL EXTI</strong> update</p>
<ul>
<li>__EXTI__LINE is now used instead of <strong>LINE</strong> which is a standard C macro.</li>
</ul></li>
-<li><strong>HAL OPAMP</strong> update
+<li><p><strong>HAL OPAMP</strong> update</p>
<ul>
<li>Corrected OPAMPs outputs for the STM32G4 device table to be coherent with reference manual.</li>
</ul></li>
-<li><strong>HAL/LL ADC</strong> Update
+<li><p><strong>HAL/LL ADC</strong> Update</p>
<ul>
<li>Update HAL_ADC_DeInit() to avoid ADC hardware resource deinitialization when other ADC instances sharing the same common ADC instance are disable.</li>
<li>Update temperature sensor stabilization time management.</li>
<li>Update timeout mechanism to avoid false timeout detection in case of preemption.</li>
<li>Align the defined value of internal regulator stabilization time (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US) with product documentation (20us instead of 10us).</li>
</ul></li>
-<li><strong>HAL DAC</strong> update
+<li><p><strong>HAL DAC</strong> update</p>
<ul>
<li>Updated HAL_DAC_Stop_DMA() API to not return HAL_ERROR when DAC is already disabled.</li>
<li>Updated HAL_DAC_ConfigChannel to return the right timeout error for channel 2.</li>
@@ -505,7 +597,7 @@
<li>(DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)) instead of DAC_CR_TEN2</li>
</ul></li>
</ul></li>
-<li><strong>HAL NOR</strong> Update
+<li><p><strong>HAL NOR</strong> Update</p>
<ul>
<li>Corrected how p_endaddress is computed and how p_currentaddress is used in the HAL_NOR_ProgramBuffer() API.</li>
<li>NOR command sets can now be selected by manufacturer code, as specified in JEDEC JEP137B 2004-05, using NOR_HandleTypeDef field CommandSet. the following APIs have been updated:
@@ -534,27 +626,27 @@
</ul></li>
<li>Updated multiple APIs to treat separately the different memory types.</li>
</ul></li>
-<li><strong>LL FMC </strong> Update
+<li><p><strong>LL FMC </strong> Update</p>
<ul>
<li>Updated FMC_NORSRAM_Extended_Timing_Init() API to manage the “bus turn around duration” parameter availability.</li>
<li>Updated FMC_NORSRAM_Init() API to resolve compilation issue with Microsoft Visual Studio 2017.</li>
</ul></li>
-<li><strong>HAL NAND</strong> update
+<li><p><strong>HAL NAND</strong> update</p>
<ul>
<li>Updated HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b() APIs to fix the column address calculation.</li>
</ul></li>
-<li><strong>HAL/LL SMARTCARD</strong> update
+<li><p><strong>HAL/LL SMARTCARD</strong> update</p>
<ul>
<li>Fixed invalid initialization of SMARTCARD configuration by removing the FIFO mode configuration.</li>
<li>Fixed typos in SMARTCARD State definition description.</li>
<li>Optimized stack usage for multiple APIs.</li>
</ul></li>
-<li><strong>HAL/LL IRDA</strong> update
+<li><p><strong>HAL/LL IRDA</strong> update</p>
<ul>
<li>Fixed typos in IRDA State definition description.</li>
<li>Optimized stack usage for multiple APIs.</li>
</ul></li>
-<li><strong>HAL/LL UART</strong> update
+<li><p><strong>HAL/LL UART</strong> update</p>
<ul>
<li>Enhanced reception for idle services (ReceptionToIdle):
<ul>
@@ -572,7 +664,7 @@
<li>Fixed typos in UART State definition description.</li>
<li>Optimized stack usage for multiple APIs.</li>
</ul></li>
-<li><strong>HAL/LL USART</strong> update
+<li><p><strong>HAL/LL USART</strong> update</p>
<ul>
<li>Removed IS_USART_OVERSAMPLING() as it is unused.</li>
<li>LL_USART_ClockInit now supports clock phase and clock polarity configuration for SPI_Slave mode.</li>
@@ -580,35 +672,35 @@
<li>Optimized stack usage for multiple APIs.</li>
<li>Removed useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.</li>
</ul></li>
-<li><strong>HAL SMBUS</strong> update
+<li><p><strong>HAL SMBUS</strong> update</p>
<ul>
<li>Support for Fast Mode Plus to be SMBUS rev 3 compliant.
<ul>
<li>Added HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+.</li>
</ul></li>
</ul></li>
-<li><strong>LL SPI</strong> update
+<li><p><strong>LL SPI</strong> update</p>
<ul>
<li>Updated to set the FRXTH bit for 8bit data for LL_SPI_Init() API.</li>
</ul></li>
-<li><strong>HAL WWDG</strong> update
+<li><p><strong>HAL WWDG</strong> update</p>
<ul>
<li>Updated HAL driver description.</li>
</ul></li>
-<li><strong>HAL/LL USB</strong> update
+<li><p><strong>HAL/LL USB</strong> update</p>
<ul>
<li>Fixed USB ISO IN double buffer mode Transfer.</li>
<li>Fixed PMA rx count descriptor</li>
</ul></li>
<li><p>Added few instructions before reading the RX count register.</p></li>
</ul>
-<h2 id="development-toolchains-and-compilers-2">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain <strong>V8.50.4</strong> + ST-LINKV2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.31</strong> + ST-LINKV2</li>
<li>STM32CubeIDE toolchain <strong>V1.6.0</strong></li>
</ul>
-<h2 id="supported-devices-2">Supported Devices</h2>
+<h2 id="supported-devices-3">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -621,17 +713,17 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.2.0 / 26-June-2020</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
-<h3 id="maintenance-release-3">Maintenance Release</h3>
+<h2 id="main-changes-4">Main Changes</h2>
+<h3 id="maintenance-release-4">Maintenance Release</h3>
<ul>
-<li>Add support for STM32G491xx and STM32G4A1 part numbers</li>
+<li><p>Add support for STM32G491xx and STM32G4A1 part numbers</p></li>
<li><p>General updates to fix known defects and enhancements implementation</p></li>
-<li><strong>HAL/LL GPIO</strong> update
+<li><p><strong>HAL/LL GPIO</strong> update</p>
<ul>
<li>Enhancement GPIO_TogglePin API to allow the toggling of many pins</li>
<li>Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s</li>
</ul></li>
-<li><strong>HAL/LL HRTIM</strong> update
+<li><p><strong>HAL/LL HRTIM</strong> update</p>
<ul>
<li>Constants renaming:
<ul>
@@ -645,7 +737,7 @@
<li>Remove unused LL constant LL_HRTIM_RESETTRIG_OTHER5_CMP4 as the definition it corresponds to (HRTIM_RSTR_TIMFCMP4) exists neither in the CMSIS nor in the reference manual.</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL I2S</strong> update
+<li><p><strong>HAL/LL I2S</strong> update</p>
<ul>
<li>Update HAL_I2S_DMAStop() API to be more safe
<ul>
@@ -657,7 +749,7 @@
<li>Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL SPI</strong> update
+<li><p><strong>HAL/LL SPI</strong> update</p>
<ul>
<li>Update HAL_SPI_Init() API
<ul>
@@ -677,11 +769,11 @@
<li>Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled</li>
</ul></li>
</ul></li>
-<li><strong>HAL SAI</strong> update
+<li><p><strong>HAL SAI</strong> update</p>
<ul>
<li>Update HAL_SAI_Init() API to correct the formula in case of SPDIF is wrong</li>
</ul></li>
-<li><strong>HAL/LL ADC</strong> update
+<li><p><strong>HAL/LL ADC</strong> update</p>
<ul>
<li>Update Channel & external trigger to support <strong>STM32G491/STM32G4A1</strong> embedded with 3 ADC:
<ul>
@@ -690,23 +782,23 @@
</ul></li>
<li>Update note in ll_adc.h & hal_adc.h to highlight that the ADC with transfers DMA and ADC mode auto delay can work simultaneously.</li>
</ul></li>
-<li><strong>HAL COMP</strong> update
+<li><p><strong>HAL COMP</strong> update</p>
<ul>
<li>Update Blanking sources to support <strong>STM32G491/STM32G4A1</strong> embedded with 4 COMP:
<ul>
<li>IS_COMP_BLANKINGSRC_INSTANCE</li>
</ul></li>
</ul></li>
-<li><strong>HAL OPAMP</strong> update
+<li><p><strong>HAL OPAMP</strong> update</p>
<ul>
<li>Update hal_opamp_ex.c to support <strong>STM32G491/STM32G4A1</strong> embedded with 4 OPAMP (OPAMP1/OPAMP2/OPAMP3/OPAMP6):</li>
</ul></li>
-<li><strong>HAL FLASH</strong> update
+<li><p><strong>HAL FLASH</strong> update</p>
<ul>
<li>Update FLASH Latency comment param to list all supported flash latency values.</li>
<li>Update FLASH_PAGE_NB to return the right page number(256 pages for devices embedded with 512KB flash size and 64 for devices embedded with 128KB flash size)</li>
</ul></li>
-<li><strong>HAL/LL RCC</strong> update
+<li><p><strong>HAL/LL RCC</strong> update</p>
<ul>
<li>Update Table 1. HCLK clock frequency for STM32G4xx devices to be aligned with reference manual RM0440</li>
<li>Update peripheral clock to support <strong>STM32G491/STM32G4A1</strong> devices:
@@ -715,7 +807,7 @@
<li>IS_RCC_PERIPHCLOCK</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL TIM</strong> driver
+<li><p><strong>HAL/LL TIM</strong> driver</p>
<ul>
<li>Align HAL/LL TIM driver with latest updates and enhancements</li>
<li>Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay
@@ -731,7 +823,7 @@
<li>Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral</li>
<li>Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory</li>
</ul></li>
-<li><strong>HAL/LL UART</strong> driver
+<li><p><strong>HAL/LL UART</strong> driver</p>
<ul>
<li>Update UART polling processes to handle efficiently the Lock mechanism
<ul>
@@ -740,11 +832,11 @@
<li>Update UART BRR calculation for ROM size gain</li>
<li>Remove ‘register’ storage class specifier from LL UART driver.</li>
</ul></li>
-<li><strong>HAL/LL USART</strong> driver
+<li><p><strong>HAL/LL USART</strong> driver</p>
<ul>
<li>Remove ‘register’ storage class specifier from LL USART driver.</li>
</ul></li>
-<li><strong>HAL/LL USB</strong> driver
+<li><p><strong>HAL/LL USB</strong> driver</p>
<ul>
<li>Fix USB Bulk transfer double buffer mode</li>
<li>Remove register keyword from USB defined macros as no more supported by c++ compiler</li>
@@ -752,13 +844,13 @@
<li>Correct some word spelling issues</li>
</ul></li>
</ul>
-<h2 id="development-toolchains-and-compilers-3">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.1</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain <strong>V5.29</strong></li>
<li>STM32CubeIDE toolchain <strong>V1.4.0</strong></li>
</ul>
-<h2 id="supported-devices-3">Supported Devices</h2>
+<h2 id="supported-devices-4">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -771,11 +863,11 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.1.1 / 14-February-2020</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
-<h3 id="maintenance-release-4">Maintenance Release</h3>
+<h2 id="main-changes-5">Main Changes</h2>
+<h3 id="maintenance-release-5">Maintenance Release</h3>
<ul>
<li><p>General updates to fix known defects and enhancements implementation</p></li>
-<li><strong>HAL/LL CRYP</strong> update
+<li><p><strong>HAL/LL CRYP</strong> update</p>
<ul>
<li>Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.1_R6, 10.3, 10.4_a, 10.6, 12.1, 13.5 15.7</li>
<li>Perform a new check mechanism on the cryp buffer size in Encryption et Decryption API
@@ -809,11 +901,11 @@
<li>Update CRYP_GCMCCM_SetPayloadPhase_IT() API</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL FMAC</strong> update
+<li><p><strong>HAL/LL FMAC</strong> update</p>
<ul>
<li>General updates to comply to internal coding rules.</li>
</ul></li>
-<li><strong>HAL GPIO</strong> update
+<li><p><strong>HAL GPIO</strong> update</p>
<ul>
<li>Update the GPIO initialization sequence in HAL_GPIO_Init() API to avoid unwanted glitches on GPIO pins.</li>
<li>Add missing GPIO Alternate Function definitions:
@@ -821,7 +913,7 @@
<li>GPIO_AF2_TIM16, GPIO_AF9_TIM8, GPIO_AF11_TIM8, GPIO_AF12_TIM1.</li>
</ul></li>
</ul></li>
-<li><strong>HAL HRTIM</strong> update
+<li><p><strong>HAL HRTIM</strong> update</p>
<ul>
<li>Update HAL_HRTIM_WaveformCompareConfig() to clear HRTIM_TIMxCR.DELCMP bitfield when the auto-delayed protection mode is disabled.</li>
<li>Correct some “HRTIM_OUTPUTSET_TIMxx” constant names which are not compliant with Timer Events Mapping specified in the reference manual
@@ -836,7 +928,7 @@
<li>Remove UPDGAT bits reset from the HRTIM_TimingUnitWaveform_Control() API</li>
<li>Add a lock and unlock handle process in the HAL_HRTIM_SimpleOCChannelConfig() API</li>
</ul></li>
-<li><strong>HAL I2C</strong> update
+<li><p><strong>HAL I2C</strong> update</p>
<ul>
<li>Update I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).
<ul>
@@ -847,7 +939,7 @@
<li>Update I2C_Slave_ISR_IT() and I2C_Slave_ISR_DMA() APIs to check on STOP condition and handle it before clearing the ADDR flag</li>
</ul></li>
</ul></li>
-<li><strong>HAL LPTIM</strong> update
+<li><p><strong>HAL LPTIM</strong> update</p>
<ul>
<li>Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API
<ul>
@@ -866,16 +958,16 @@
</ul></li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL RTC</strong> update
+<li><p><strong>HAL/LL RTC</strong> update</p>
<ul>
<li>Update API HAL_RTC_SetAlarm_IT() to allow changing alarm time “on the fly” simply by calling the API again.</li>
<li>Update API LL_RTC_BKP_SetRegister() and API LL_RTC_BKP_GetRegister() to comply to rules 2.2 and 13.2 of MISRAC-2012.</li>
</ul></li>
-<li><strong>HAL SPI</strong> update
+<li><p><strong>HAL SPI</strong> update</p>
<ul>
<li>Update the “Rx DMA transfer complete callback” to disable the Tx DMA request only in case of full-duplex mode and not it in half-duplex mode.</li>
</ul></li>
-<li><strong>HAL TIM</strong> update
+<li><p><strong>HAL TIM</strong> update</p>
<ul>
<li>Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
<ul>
@@ -937,7 +1029,7 @@
<li>Add a new element in the TIM_HandleTypeDef structure : ChannelNState to manage TIM complementary channel operation state</li>
</ul></li>
</ul></li>
-<li><strong>HAL/LL USART</strong> update
+<li><p><strong>HAL/LL USART</strong> update</p>
<ul>
<li>Add support to the Receiver Timeout Interrupt in the HAL_USART_IRQHandler</li>
<li>Fix wrong value for SlaveMode field in USART handle after HAL_USARTEx_DisableSlaveMode() call
@@ -945,23 +1037,23 @@
<li>Set USART_SLAVEMODE_DISABLE instead of USART_SLAVEMODE_ENABLE</li>
</ul></li>
</ul></li>
-<li><strong>HAL USB</strong> update
+<li><p><strong>HAL USB</strong> update</p>
<ul>
<li>Improve USB endpoint out re-enabling with double-buffer mode.</li>
</ul></li>
-<li><strong>LL UTILS</strong> update
+<li><p><strong>LL UTILS</strong> update</p>
<ul>
<li>API UTILS_SetFlashLatency() renamed LL_SetFlashLatency() and set exportable.</li>
<li>API LL_PLL_ConfigSystemClock_HSI() and API LL_PLL_ConfigSystemClock_HSE() updated to set back the AHB prescaler to 1 after it has been temporarily set to 2 to avoid undershoot when configuring PLL at high frequencies.</li>
</ul></li>
</ul>
-<h2 id="development-toolchains-and-compilers-4">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1</li>
<li>STM32CubeIDE toolchain v1.3.0</li>
</ul>
-<h2 id="supported-devices-4">Supported Devices</h2>
+<h2 id="supported-devices-5">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -973,8 +1065,8 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 28-June-2019</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
-<h3 id="maintenance-release-5">Maintenance Release</h3>
+<h2 id="main-changes-6">Main Changes</h2>
+<h3 id="maintenance-release-6">Maintenance Release</h3>
<p>Maintenance release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
<h2 id="contents">Contents</h2>
<table>
@@ -1057,13 +1149,13 @@
</tr>
</tbody>
</table>
-<h2 id="development-toolchains-and-compilers-5">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-6">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-5">Supported Devices</h2>
+<h2 id="supported-devices-6">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -1075,16 +1167,16 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 12-April-2019</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
-<h2 id="development-toolchains-and-compilers-6">Development Toolchains and Compilers</h2>
+<h2 id="development-toolchains-and-compilers-7">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
</ul>
-<h2 id="supported-devices-6">Supported Devices</h2>
+<h2 id="supported-devices-7">Supported Devices</h2>
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
@@ -1093,7 +1185,7 @@
</ul>
</div>
</div>
-</div>
+</section>
</div>
<footer class="sticky">
<p>For complete documentation on STM32G4xx, visit: [<a href="http://www.st.com/stm32g4">www.st.com/stm32g4</a>]</p>
diff --git a/Src/stm32g4xx_hal.c b/Src/stm32g4xx_hal.c
index ebe1bdf..53d264a 100644
--- a/Src/stm32g4xx_hal.c
+++ b/Src/stm32g4xx_hal.c
@@ -48,11 +48,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32G4xx HAL Driver version number V1.2.3
+ * @brief STM32G4xx HAL Driver version number V1.2.4
*/
#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
-#define __STM32G4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
+#define __STM32G4xx_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */
#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\
@@ -594,7 +594,7 @@
@endverbatim
* @{
*/
-
+#if defined (CCMSRAM_BASE)
/**
* @brief Start a hardware CCMSRAM erase operation.
* @note As long as CCMSRAM is not erased the CCMER bit will be set.
@@ -609,6 +609,7 @@
/* Starts a hardware CCMSRAM erase operation*/
SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
}
+#endif /* CCMSRAM_BASE */
/**
* @brief Enable the Internal FLASH Bank Swapping.
@@ -767,7 +768,7 @@
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
}
-
+#if defined(CCMSRAM_BASE)
/** @brief CCMSRAM page write protection enable
* @param Page: This parameter is a long 32bit value and can be a value of @ref SYSCFG_CCMSRAMWRP
* @note write protection can only be disabled by a system reset
@@ -779,7 +780,7 @@
SET_BIT(SYSCFG->SWPR, (uint32_t)(Page));
}
-
+#endif /* CCMSRAM_BASE */
/**
* @}
diff --git a/Src/stm32g4xx_hal_comp.c b/Src/stm32g4xx_hal_comp.c
index 1dc7f91..796998d 100644
--- a/Src/stm32g4xx_hal_comp.c
+++ b/Src/stm32g4xx_hal_comp.c
@@ -900,7 +900,7 @@
if (tmp_comp_exti_flag_set != 0UL)
{
- /* Clear COMP EXTI line pending bit */
+ /* Clear COMP EXTI line pending bit */
#if defined(COMP7)
if (tmp_comp_exti_flag_set == 2UL)
{
diff --git a/Src/stm32g4xx_hal_cordic.c b/Src/stm32g4xx_hal_cordic.c
index b5cb44a..efb7a1c 100644
--- a/Src/stm32g4xx_hal_cordic.c
+++ b/Src/stm32g4xx_hal_cordic.c
@@ -164,12 +164,12 @@
static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
+
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-
/** @defgroup CORDIC_Exported_Functions CORDIC Exported Functions
* @{
*/
diff --git a/Src/stm32g4xx_hal_cryp.c b/Src/stm32g4xx_hal_cryp.c
index 695c0ed..870ff6a 100644
--- a/Src/stm32g4xx_hal_cryp.c
+++ b/Src/stm32g4xx_hal_cryp.c
@@ -928,8 +928,6 @@
hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
}
-
-
/**
* @brief CRYP processing suspension and peripheral internal parameters storage.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
@@ -1874,23 +1872,23 @@
uint32_t itflag = hcryp->Instance->SR;
/* Check if error occurred */
- if ((itsource & CRYP_IT_ERRIE) != RESET)
+ if ((itsource & CRYP_IT_ERRIE) == CRYP_IT_ERRIE)
{
/* If write Error occurred */
- if ((itflag & CRYP_IT_WRERR) != RESET)
+ if ((itflag & CRYP_IT_WRERR) == CRYP_IT_WRERR)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
}
/* If read Error occurred */
- if ((itflag & CRYP_IT_RDERR) != RESET)
+ if ((itflag & CRYP_IT_RDERR) == CRYP_IT_RDERR)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
}
}
- if ((itflag & CRYP_IT_CCF) != RESET)
+ if ((itflag & CRYP_IT_CCF) == CRYP_IT_CCF)
{
- if ((itsource & CRYP_IT_CCFIE) != RESET)
+ if ((itsource & CRYP_IT_CCFIE) == CRYP_IT_CCFIE)
{
/* Clear computation complete flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
diff --git a/Src/stm32g4xx_hal_dac_ex.c b/Src/stm32g4xx_hal_dac_ex.c
index 0d1327b..e1d1e39 100644
--- a/Src/stm32g4xx_hal_dac_ex.c
+++ b/Src/stm32g4xx_hal_dac_ex.c
@@ -914,8 +914,8 @@
/* Init trimming counter */
/* Medium value */
- trimmingvalue = 16UL;
- delta = 8UL;
+ trimmingvalue = 0x10UL;
+ delta = 0x08UL;
while (delta != 0UL)
{
/* Set candidate trimming */
@@ -1045,8 +1045,7 @@
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
- * @retval Trimming value : range: 0->31
- *
+ * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
*/
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
diff --git a/Src/stm32g4xx_hal_dma.c b/Src/stm32g4xx_hal_dma.c
index 4df270d..0362659 100644
--- a/Src/stm32g4xx_hal_dma.c
+++ b/Src/stm32g4xx_hal_dma.c
@@ -1057,7 +1057,7 @@
else
{
/* DMA2 */
-#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx)
+#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx)
DMAMUX1_ChannelBase = DMAMUX1_Channel8;
#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
DMAMUX1_ChannelBase = DMAMUX1_Channel6;
diff --git a/Src/stm32g4xx_hal_flash_ex.c b/Src/stm32g4xx_hal_flash_ex.c
index 073eb31..6e65fbe 100644
--- a/Src/stm32g4xx_hal_flash_ex.c
+++ b/Src/stm32g4xx_hal_flash_ex.c
@@ -920,7 +920,7 @@
optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_PE);
optr_reg_mask |= FLASH_OPTR_SRAM_PE;
}
-
+#if defined(CCMSRAM_BASE)
if ((UserType & OB_USER_CCMSRAM_RST) != 0U)
{
/* CCMSRAM_RST option byte should be modified */
@@ -930,7 +930,7 @@
optr_reg_val |= (UserConfig & FLASH_OPTR_CCMSRAM_RST);
optr_reg_mask |= FLASH_OPTR_CCMSRAM_RST;
}
-
+#endif /* CCMSRAM_BASE */
if ((UserType & OB_USER_nSWBOOT0) != 0U)
{
/* nSWBOOT0 option byte should be modified */
diff --git a/Src/stm32g4xx_hal_fmac.c b/Src/stm32g4xx_hal_fmac.c
index db8f261..8220719 100644
--- a/Src/stm32g4xx_hal_fmac.c
+++ b/Src/stm32g4xx_hal_fmac.c
@@ -204,7 +204,6 @@
not defined, the callback registration feature is not available
and weak callbacks are used.
-
@endverbatim
*
*/
@@ -229,7 +228,6 @@
/** @defgroup FMAC_Private_Constants FMAC Private Constants
* @{
*/
-
#define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
#define MAX_PRELOAD_INDEX 0xFFU
#define PRELOAD_ACCESS_DMA 0x00U
@@ -322,7 +320,6 @@
/* Private variables ---------------------------------------------------------*/
/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
@@ -348,7 +345,6 @@
static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
/* Functions Definition ------------------------------------------------------*/
-
/** @defgroup FMAC_Exported_Functions FMAC Exported Functions
* @{
*/
@@ -2410,7 +2406,6 @@
#else
HAL_FMAC_ErrorCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
-
}
/**
@@ -2516,11 +2511,11 @@
HAL_FMAC_ErrorCallback(hfmac);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
+
/**
* @}
*/
-
/**
* @}
*/
diff --git a/Src/stm32g4xx_hal_i2c.c b/Src/stm32g4xx_hal_i2c.c
index 59da55d..787f4ac 100644
--- a/Src/stm32g4xx_hal_i2c.c
+++ b/Src/stm32g4xx_hal_i2c.c
@@ -90,7 +90,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -156,7 +156,7 @@
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
@@ -214,7 +214,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
- (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@@ -1407,14 +1407,6 @@
/* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
- /* Wait until ADDR flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
- {
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
- }
-
/* Preload TX data if no stretch enable */
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{
@@ -1428,6 +1420,18 @@
hi2c->XferCount--;
}
+ /* Wait until ADDR flag is set */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
+ return HAL_ERROR;
+ }
+
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@@ -1439,6 +1443,10 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -1451,6 +1459,10 @@
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
+
return HAL_ERROR;
}
@@ -4552,7 +4564,7 @@
}
/**
- * @brief Abort a master I2C IT or DMA process communication with Interrupt.
+ * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
@@ -4561,7 +4573,9 @@
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
- if (hi2c->Mode == HAL_I2C_MODE_MASTER)
+ HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
+
+ if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
{
/* Process Locked */
__HAL_LOCK(hi2c);
diff --git a/Src/stm32g4xx_hal_opamp.c b/Src/stm32g4xx_hal_opamp.c
index 08beec6..5e9bab0 100644
--- a/Src/stm32g4xx_hal_opamp.c
+++ b/Src/stm32g4xx_hal_opamp.c
@@ -231,7 +231,7 @@
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
-
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
#ifdef HAL_OPAMP_MODULE_ENABLED
/** @defgroup OPAMP OPAMP
@@ -1194,9 +1194,8 @@
*/
#endif /* HAL_OPAMP_MODULE_ENABLED */
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
+
/**
* @}
*/
-
-
-
diff --git a/Src/stm32g4xx_hal_opamp_ex.c b/Src/stm32g4xx_hal_opamp_ex.c
index aff46af..d4bfb2f 100644
--- a/Src/stm32g4xx_hal_opamp_ex.c
+++ b/Src/stm32g4xx_hal_opamp_ex.c
@@ -30,6 +30,7 @@
* @{
*/
+#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
#ifdef HAL_OPAMP_MODULE_ENABLED
/** @defgroup OPAMPEx OPAMPEx
@@ -740,6 +741,7 @@
*/
#endif /* HAL_OPAMP_MODULE_ENABLED */
+#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
/**
* @}
diff --git a/Src/stm32g4xx_hal_pcd.c b/Src/stm32g4xx_hal_pcd.c
index 8e93289..606551c 100644
--- a/Src/stm32g4xx_hal_pcd.c
+++ b/Src/stm32g4xx_hal_pcd.c
@@ -1389,7 +1389,7 @@
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
- HAL_StatusTypeDef ret = HAL_OK;
+ HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
if ((ep_addr & 0x80U) == 0x80U)
@@ -1404,7 +1404,7 @@
}
ep->num = ep_addr & EP_ADDR_MSK;
- ep->maxpacket = ep_mps;
+ ep->maxpacket = (uint32_t)ep_mps & 0x7FFU;
ep->type = ep_type;
/* Set initial data PID. */
@@ -2227,13 +2227,11 @@
#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */
-
/**
* @}
*/
#endif /* defined (USB) */
#endif /* HAL_PCD_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/Src/stm32g4xx_hal_pcd_ex.c b/Src/stm32g4xx_hal_pcd_ex.c
index cb53de6..96064ae 100644
--- a/Src/stm32g4xx_hal_pcd_ex.c
+++ b/Src/stm32g4xx_hal_pcd_ex.c
@@ -242,7 +242,6 @@
}
}
-
/**
* @brief Activate LPM feature.
* @param hpcd PCD handle
@@ -279,7 +278,6 @@
}
-
/**
* @brief Send LPM message to user layer callback.
* @param hpcd PCD handle
diff --git a/Src/stm32g4xx_hal_pwr_ex.c b/Src/stm32g4xx_hal_pwr_ex.c
index 5ec00b2..aad0925 100644
--- a/Src/stm32g4xx_hal_pwr_ex.c
+++ b/Src/stm32g4xx_hal_pwr_ex.c
@@ -39,13 +39,13 @@
/* Private define ------------------------------------------------------------*/
-#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx)
+#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G414xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx)
#define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */
#define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */
#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB) || defined (STM32G491xx) || defined (STM32G4A1xx)
#define PWR_PORTF_AVAILABLE_PINS 0x00000607U /* PF0..PF2 and PF9 and PF10 */
#define PWR_PORTG_AVAILABLE_PINS 0x00000400U /* PG10 */
-#endif
+#endif /* STM32G471xx || STM32G473xx || STM32G414xx || STM32G474xx || STM32G483xx || STM32G484xx */
/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
* @{
@@ -550,7 +550,7 @@
}
-
+#if defined (SRAM2_BASE)
/**
* @brief Enable SRAM2 content retention in Standby mode.
* @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
@@ -573,7 +573,7 @@
{
CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
}
-
+#endif /* SRAM2_BASE */
diff --git a/Src/stm32g4xx_hal_rcc_ex.c b/Src/stm32g4xx_hal_rcc_ex.c
index d56836e..d47da48 100644
--- a/Src/stm32g4xx_hal_rcc_ex.c
+++ b/Src/stm32g4xx_hal_rcc_ex.c
@@ -237,6 +237,8 @@
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
}
+#if defined(USART3)
+
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
{
@@ -247,6 +249,8 @@
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
}
+#endif /* USART3 */
+
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
@@ -302,6 +306,7 @@
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
}
+#if defined(I2C3)
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
@@ -313,7 +318,8 @@
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
}
-#if defined(I2C4)
+#endif /* I2C3 */
+#if defined(I2C4)
/*-------------------------- I2C4 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
@@ -337,6 +343,7 @@
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
}
+#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
{
@@ -353,6 +360,9 @@
}
}
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
/*-------------------------- I2S clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
{
@@ -369,6 +379,8 @@
}
}
+#endif /* SPI_I2S_SUPPORT */
+
#if defined(FDCAN1)
/*-------------------------- FDCAN clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
@@ -496,6 +508,13 @@
RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC345 | \
RCC_PERIPHCLK_QSPI | \
RCC_PERIPHCLK_RTC;
+
+#elif defined(STM32G414xx)
+
+ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
+ RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_RNG | \
+ RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_RTC;
+
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
@@ -526,6 +545,7 @@
RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2S | \
RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \
RCC_PERIPHCLK_RTC;
+
#elif defined(STM32G431xx) || defined(STM32G441xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
@@ -541,15 +561,18 @@
RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC12 | \
RCC_PERIPHCLK_RTC;
-#endif /* STM32G431xx */
+#endif /* STM32G474xx || STM32G484xx */
/* Get the USART1 clock source ---------------------------------------------*/
PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
/* Get the USART2 clock source ---------------------------------------------*/
PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
+
+#if defined(USART3)
/* Get the USART3 clock source ---------------------------------------------*/
PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
+#endif /* USART3 */
#if defined(UART4)
/* Get the UART4 clock source ----------------------------------------------*/
@@ -570,8 +593,10 @@
/* Get the I2C2 clock source ----------------------------------------------*/
PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
+#if defined(I2C3)
/* Get the I2C3 clock source -----------------------------------------------*/
PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
+#endif /* I2C3 */
#if defined(I2C4)
/* Get the I2C4 clock source -----------------------------------------------*/
@@ -581,11 +606,15 @@
/* Get the LPTIM1 clock source ---------------------------------------------*/
PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+#if defined(SAI1)
/* Get the SAI1 clock source -----------------------------------------------*/
PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+#endif /* SAI1 */
+#if defined(SPI_I2S_SUPPORT)
/* Get the I2S clock source -----------------------------------------------*/
PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/* Get the FDCAN clock source -----------------------------------------------*/
@@ -772,6 +801,7 @@
}
break;
+#if defined(USART3)
case RCC_PERIPHCLK_USART3:
/* Get the current USART3 source */
srcclk = __HAL_RCC_GET_USART3_SOURCE();
@@ -798,7 +828,8 @@
/* nothing to do: frequency already initialized to 0 */
}
break;
-
+#endif /* USART3 */
+
#if defined(UART4)
case RCC_PERIPHCLK_UART4:
/* Get the current UART4 source */
@@ -930,6 +961,8 @@
}
break;
+#if defined(I2C3)
+
case RCC_PERIPHCLK_I2C3:
/* Get the current I2C3 source */
srcclk = __HAL_RCC_GET_I2C3_SOURCE();
@@ -953,6 +986,8 @@
}
break;
+#endif /* I2C3 */
+
#if defined(I2C4)
case RCC_PERIPHCLK_I2C4:
@@ -1007,6 +1042,8 @@
}
break;
+#if defined(SAI1)
+
case RCC_PERIPHCLK_SAI1:
/* Get the current SAI1 source */
srcclk = __HAL_RCC_GET_SAI1_SOURCE();
@@ -1040,6 +1077,9 @@
}
break;
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
case RCC_PERIPHCLK_I2S:
/* Get the current I2Sx source */
srcclk = __HAL_RCC_GET_I2S_SOURCE();
@@ -1072,6 +1112,7 @@
/* nothing to do: frequency already initialized to 0 */
}
break;
+#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
case RCC_PERIPHCLK_FDCAN:
diff --git a/Src/stm32g4xx_hal_sai.c b/Src/stm32g4xx_hal_sai.c
index befbd56..96e06fe 100644
--- a/Src/stm32g4xx_hal_sai.c
+++ b/Src/stm32g4xx_hal_sai.c
@@ -217,13 +217,14 @@
* @{
*/
+#if defined(SAI1)
+#ifdef HAL_SAI_MODULE_ENABLED
+
/** @defgroup SAI SAI
* @brief SAI HAL module driver
* @{
*/
-#ifdef HAL_SAI_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/** @defgroup SAI_Private_Typedefs SAI Private Typedefs
* @{
@@ -2731,12 +2732,13 @@
* @}
*/
+/**
+ * @}
+ */
+
#endif /* HAL_SAI_MODULE_ENABLED */
-/**
- * @}
- */
+#endif /* SAI1 */
/**
* @}
*/
-
diff --git a/Src/stm32g4xx_hal_sai_ex.c b/Src/stm32g4xx_hal_sai_ex.c
index 78e90b6..20bdb06 100644
--- a/Src/stm32g4xx_hal_sai_ex.c
+++ b/Src/stm32g4xx_hal_sai_ex.c
@@ -26,6 +26,8 @@
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
+
+#if defined(SAI1)
#ifdef HAL_SAI_MODULE_ENABLED
/** @defgroup SAIEx SAIEx
@@ -124,7 +126,8 @@
*/
#endif /* HAL_SAI_MODULE_ENABLED */
+#endif /* SAI1 */
+
/**
* @}
*/
-
diff --git a/Src/stm32g4xx_hal_smartcard.c b/Src/stm32g4xx_hal_smartcard.c
index 53aa442..a3a83b1 100644
--- a/Src/stm32g4xx_hal_smartcard.c
+++ b/Src/stm32g4xx_hal_smartcard.c
@@ -2406,7 +2406,7 @@
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue;
}
- MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg);
+ WRITE_REG(hsmartcard->Instance->RTOR, tmpreg);
/*-------------------------- USART BRR Configuration -----------------------*/
SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
diff --git a/Src/stm32g4xx_hal_smbus_ex.c b/Src/stm32g4xx_hal_smbus_ex.c
index b4404ab..b431d8f 100644
--- a/Src/stm32g4xx_hal_smbus_ex.c
+++ b/Src/stm32g4xx_hal_smbus_ex.c
@@ -6,6 +6,8 @@
* This file provides firmware functions to manage the following
* functionalities of SMBUS Extended peripheral:
* + Extended features functions
+ * + WakeUp Mode Functions
+ * + FastModePlus Functions
*
******************************************************************************
* @attention
diff --git a/Src/stm32g4xx_hal_uart.c b/Src/stm32g4xx_hal_uart.c
index 2ca90c8..ba9df1e 100644
--- a/Src/stm32g4xx_hal_uart.c
+++ b/Src/stm32g4xx_hal_uart.c
@@ -2425,6 +2425,28 @@
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
+ else
+ {
+ /* If DMA is in Circular mode, Idle event is to be reported to user
+ even if occurring after a Transfer Complete event from DMA */
+ if (nb_remaining_rx_data == huart->RxXferSize)
+ {
+ if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ {
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+ }
+ }
+ }
return;
}
else
@@ -4466,6 +4488,7 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+ break;
}
}
@@ -4630,6 +4653,7 @@
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
+ break;
}
}
diff --git a/Src/stm32g4xx_hal_uart_ex.c b/Src/stm32g4xx_hal_uart_ex.c
index 30fd990..cdb0c95 100644
--- a/Src/stm32g4xx_hal_uart_ex.c
+++ b/Src/stm32g4xx_hal_uart_ex.c
@@ -576,7 +576,7 @@
/* Disable UART */
__HAL_UART_DISABLE(huart);
- /* Enable FIFO mode */
+ /* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
huart->FifoMode = UART_FIFOMODE_DISABLE;
diff --git a/Src/stm32g4xx_hal_usart.c b/Src/stm32g4xx_hal_usart.c
index 96617bc..a56ec7c 100644
--- a/Src/stm32g4xx_hal_usart.c
+++ b/Src/stm32g4xx_hal_usart.c
@@ -144,7 +144,7 @@
*/
/** @defgroup USART USART
- * @brief HAL USART Synchronous module driver
+ * @brief HAL USART Synchronous SPI module driver
* @{
*/
@@ -225,8 +225,8 @@
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
+ in synchronous SPI master/slave mode.
+ (+) For the synchronous SPI mode only these parameters can be configured:
(++) Baud Rate
(++) Word Length
(++) Stop Bit
@@ -238,7 +238,7 @@
(++) Receiver/transmitter modes
[..]
- The HAL_USART_Init() function follows the USART synchronous configuration
+ The HAL_USART_Init() function follows the USART synchronous SPI configuration
procedure (details for the procedure are available in reference manual).
@endverbatim
@@ -316,7 +316,7 @@
return HAL_ERROR;
}
- /* In Synchronous mode, the following bits must be kept cleared:
+ /* In Synchronous SPI mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register.
*/
@@ -657,11 +657,10 @@
===============================================================================
##### IO operation functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART synchronous
+ [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI
data transfers.
- [..] The USART supports master mode only: it cannot receive or send data related to an input
- clock (SCLK is always an output).
+ [..] The USART Synchronous SPI supports master and slave modes (SCLK as output or input).
[..]
@@ -2908,7 +2907,7 @@
/* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits:
* set CPOL bit according to husart->Init.CLKPolarity value
* set CPHA bit according to husart->Init.CLKPhase value
- * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only)
+ * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only)
* set STOP[13:12] bits according to husart->Init.StopBits value */
tmpreg = (uint32_t)(USART_CLOCK_ENABLE);
tmpreg |= (uint32_t)husart->Init.CLKLastBit;
diff --git a/Src/stm32g4xx_hal_usart_ex.c b/Src/stm32g4xx_hal_usart_ex.c
index 2c0dabd..dce4686 100644
--- a/Src/stm32g4xx_hal_usart_ex.c
+++ b/Src/stm32g4xx_hal_usart_ex.c
@@ -364,7 +364,7 @@
/* Disable USART */
__HAL_USART_DISABLE(husart);
- /* Enable FIFO mode */
+ /* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
husart->FifoMode = USART_FIFOMODE_DISABLE;
diff --git a/Src/stm32g4xx_ll_adc.c b/Src/stm32g4xx_ll_adc.c
index d49741c..907fbb3 100644
--- a/Src/stm32g4xx_ll_adc.c
+++ b/Src/stm32g4xx_ll_adc.c
@@ -250,7 +250,7 @@
) \
) \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
(((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
@@ -490,7 +490,7 @@
) \
) \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
(((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
diff --git a/Src/stm32g4xx_ll_comp.c b/Src/stm32g4xx_ll_comp.c
index 103e753..3c840a0 100644
--- a/Src/stm32g4xx_ll_comp.c
+++ b/Src/stm32g4xx_ll_comp.c
@@ -52,47 +52,47 @@
/* Note: On this STM32 series, comparator input plus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
-/* compatibility with other STM32 families. */
+/* compatibility with other STM32 series. */
#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \
(((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
|| ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \
- (((__COMP_INSTANCE__) == COMP1) && \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) || \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) || \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) || \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \
+ (((__COMP_INSTANCE__) == COMP1) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
- ) || \
- (((__COMP_INSTANCE__) == COMP2) && \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
+ ) || \
+ (((__COMP_INSTANCE__) == COMP2) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
- ) || \
- (((__COMP_INSTANCE__) == COMP3) && \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
+ ) || \
+ (((__COMP_INSTANCE__) == COMP3) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
- ) || \
- (((__COMP_INSTANCE__) == COMP4) && \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
+ ) || \
+ (((__COMP_INSTANCE__) == COMP4) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
- ) || \
- (((__COMP_INSTANCE__) == COMP5) && \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
+ ) || \
+ (((__COMP_INSTANCE__) == COMP5) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \
- ) || \
- (((__COMP_INSTANCE__) == COMP6) && \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \
+ ) || \
+ (((__COMP_INSTANCE__) == COMP6) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH2)) \
- ) || \
- (((__COMP_INSTANCE__) == COMP7) && \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH2)) \
+ ) || \
+ (((__COMP_INSTANCE__) == COMP7) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC2_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \
- ))
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC4_CH1)) \
+ ))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \
@@ -103,19 +103,19 @@
((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO2) || \
(((__COMP_INSTANCE__) == COMP1) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP2) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH2) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP3) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP4) && \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC1_CH1) || \
- ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
+ ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_DAC3_CH2)) \
))
#endif
@@ -135,124 +135,124 @@
|| ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
-#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((((__INSTANCE__) == COMP1) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
- || \
- (((__INSTANCE__) == COMP2) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
- || \
- (((__INSTANCE__) == COMP3) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
- || \
- (((__INSTANCE__) == COMP4) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
- || \
- (((__INSTANCE__) == COMP5) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \
- || \
- (((__INSTANCE__) == COMP6) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \
- || \
- (((__INSTANCE__) == COMP7) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ ((((__INSTANCE__) == COMP1) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
+ || \
+ (((__INSTANCE__) == COMP2) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
+ || \
+ (((__INSTANCE__) == COMP3) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
+ || \
+ (((__INSTANCE__) == COMP4) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
+ || \
+ (((__INSTANCE__) == COMP5) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \
+ || \
+ (((__INSTANCE__) == COMP6) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \
+ || \
+ (((__INSTANCE__) == COMP7) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
-#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((((__INSTANCE__) == COMP1) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
- || \
- (((__INSTANCE__) == COMP2) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
- || \
- (((__INSTANCE__) == COMP3) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
- || \
- (((__INSTANCE__) == COMP4) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ ((((__INSTANCE__) == COMP1) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
+ || \
+ (((__INSTANCE__) == COMP2) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
+ || \
+ (((__INSTANCE__) == COMP3) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
+ || \
+ (((__INSTANCE__) == COMP4) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \
)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
-#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
- ((((__INSTANCE__) == COMP1) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
- || \
- (((__INSTANCE__) == COMP2) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
- || \
- (((__INSTANCE__) == COMP3) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
- || \
- (((__INSTANCE__) == COMP4) && \
- (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
- ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \
- || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \
+#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
+ ((((__INSTANCE__) == COMP1) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
+ || \
+ (((__INSTANCE__) == COMP2) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
+ || \
+ (((__INSTANCE__) == COMP3) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
+ || \
+ (((__INSTANCE__) == COMP4) && \
+ (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
+ ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM20_OC5) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM15_OC1) \
+ || ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \
)
#endif
/**
diff --git a/Src/stm32g4xx_ll_dac.c b/Src/stm32g4xx_ll_dac.c
index 0b21f61..f47938f 100644
--- a/Src/stm32g4xx_ll_dac.c
+++ b/Src/stm32g4xx_ll_dac.c
@@ -45,7 +45,7 @@
/** @addtogroup DAC_LL_Private_Macros
* @{
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
(((__DACX__) == DAC2) ? \
((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
@@ -58,9 +58,9 @@
(((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
|| ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
)
-#endif /* #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
-#if defined(STM32G474xx) || defined(STM32G484xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_LL_DAC_TRIGGER_SOURCE(__DACX__, __TRIGGER_SOURCE__) \
(((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
@@ -96,9 +96,9 @@
|| (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
: ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \
)
-#endif /* STM32G474xx || STM32G484xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
-#if defined(STM32G474xx) || defined(STM32G484xx)
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_LL_DAC_TRIGGER_SOURCE2(__DACX__, __TRIGGER_SOURCE__) \
(((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
@@ -130,7 +130,7 @@
|| (((__DACX__) == DAC3) ? ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
: ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO)) \
)
-#endif /* STM32G474xx || STM32G484xx */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
diff --git a/Src/stm32g4xx_ll_fmac.c b/Src/stm32g4xx_ll_fmac.c
index 4c523c0..f6c0f70 100644
--- a/Src/stm32g4xx_ll_fmac.c
+++ b/Src/stm32g4xx_ll_fmac.c
@@ -113,8 +113,6 @@
return (status);
}
-
-
/**
* @}
*/
diff --git a/Src/stm32g4xx_ll_i2c.c b/Src/stm32g4xx_ll_i2c.c
index 8c165f9..aff36ed 100644
--- a/Src/stm32g4xx_ll_i2c.c
+++ b/Src/stm32g4xx_ll_i2c.c
@@ -107,6 +107,7 @@
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
}
+#if defined(I2C3)
else if (I2Cx == I2C3)
{
/* Force reset of I2C clock */
@@ -115,6 +116,7 @@
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
}
+#endif /* I2C3 */
#if defined(I2C4)
else if (I2Cx == I2C4)
{
diff --git a/Src/stm32g4xx_ll_rcc.c b/Src/stm32g4xx_ll_rcc.c
index 61f08d5..d2b00db 100644
--- a/Src/stm32g4xx_ll_rcc.c
+++ b/Src/stm32g4xx_ll_rcc.c
@@ -38,9 +38,15 @@
/** @addtogroup RCC_LL_Private_Macros
* @{
*/
-#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
+#if defined(RCC_CCIPR_USART3SEL)
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
+ || (__VALUE__) == LL_RCC_USART3_CLKSOURCE)
+#else
+#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
+#endif /* RCC_CCIPR_USART3SEL*/
+
#if defined(RCC_CCIPR_UART5SEL)
#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
@@ -55,15 +61,20 @@
|| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
-
-#else
+#elif defined(RCC_CCIPR_I2C3SEL)
#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
+#else
+#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE))
+
#endif /* RCC_CCIPR2_I2C4SEL */
#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
+#if defined(SAI1)
#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
+#endif /* SAI1 */
#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
@@ -297,6 +308,7 @@
}
else
{
+#if defined(RCC_CCIPR_USART3SEL)
if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
{
/* USART3CLK clock frequency */
@@ -326,6 +338,7 @@
break;
}
}
+#endif /* RCC_CCIPR_USART3SEL */
}
return usart_frequency;
}
@@ -479,6 +492,7 @@
}
else
{
+#if defined(RCC_CCIPR_I2C3SEL)
if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
{
/* I2C3 CLK clock frequency */
@@ -501,6 +515,7 @@
break;
}
}
+#endif /* RCC_CCIPR_I2C3SEL */
#if defined(RCC_CCIPR2_I2C4SEL)
else
{
@@ -628,6 +643,7 @@
return lptim_frequency;
}
+#if defined(SAI1)
/**
* @brief Return SAIx clock frequency
* @param SAIxSource This parameter can be one of the following values:
@@ -680,6 +696,9 @@
return sai_frequency;
}
+#endif /* SAI1 */
+
+#if defined(SPI_I2S_SUPPORT)
/**
* @brief Return I2Sx clock frequency
* @param I2SxSource This parameter can be one of the following values:
@@ -729,6 +748,7 @@
return i2s_frequency;
}
+#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/**
diff --git a/Src/stm32g4xx_ll_rng.c b/Src/stm32g4xx_ll_rng.c
index 9fdfa6e..c43a232 100644
--- a/Src/stm32g4xx_ll_rng.c
+++ b/Src/stm32g4xx_ll_rng.c
@@ -99,7 +99,7 @@
* - SUCCESS: RNG registers are initialized according to RNG_InitStruct content
* - ERROR: not applicable
*/
-ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct)
+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct)
{
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
diff --git a/Src/stm32g4xx_ll_ucpd.c b/Src/stm32g4xx_ll_ucpd.c
index c6e5b20..1d3d841 100644
--- a/Src/stm32g4xx_ll_ucpd.c
+++ b/Src/stm32g4xx_ll_ucpd.c
@@ -112,7 +112,7 @@
* the configuration information for the UCPD peripheral.
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
*/
-ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct)
+ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct)
{
/* Check the ucpd Instance UCPDx*/
assert_param(IS_UCPD_ALL_INSTANCE(UCPDx));
diff --git a/Src/stm32g4xx_ll_usart.c b/Src/stm32g4xx_ll_usart.c
index a3d3964..a0de805 100644
--- a/Src/stm32g4xx_ll_usart.c
+++ b/Src/stm32g4xx_ll_usart.c
@@ -159,6 +159,7 @@
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
}
+#if defined(USART3)
else if (USARTx == USART3)
{
/* Force reset of USART clock */
@@ -167,6 +168,7 @@
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
}
+#endif /* USART3 */
#if defined(UART4)
else if (USARTx == UART4)
{
@@ -267,10 +269,12 @@
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
}
+#if defined(USART3)
else if (USARTx == USART3)
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
}
+#endif /* USART3 */
#if defined(UART4)
else if (USARTx == UART4)
{
diff --git a/_htmresc/favicon.png b/_htmresc/favicon.png
deleted file mode 100644
index 06713ee..0000000
--- a/_htmresc/favicon.png
+++ /dev/null
Binary files differ
diff --git a/_htmresc/mini-st_2020.css b/_htmresc/mini-st.css
similarity index 77%
rename from _htmresc/mini-st_2020.css
rename to _htmresc/mini-st.css
index 3d9e81a..71fbc14 100644
--- a/_htmresc/mini-st_2020.css
+++ b/_htmresc/mini-st.css
@@ -1,39 +1,39 @@
@charset "UTF-8";
/*
- Flavor name: Custom (mini-custom)
- Generated online - https://minicss.org/flavors
- mini.css version: v3.0.1
+ Flavor name: Default (mini-default)
+ Author: Angelos Chalaris (chalarangelo@gmail.com)
+ Maintainers: Angelos Chalaris
+ mini.css version: v3.0.0-alpha.3
*/
/*
Browsers resets and base typography.
*/
/* Core module CSS variable definitions */
:root {
- --fore-color: #03234b;
- --secondary-fore-color: #03234b;
- --back-color: #ffffff;
- --secondary-back-color: #ffffff;
- --blockquote-color: #e6007e;
- --pre-color: #e6007e;
- --border-color: #3cb4e6;
- --secondary-border-color: #3cb4e6;
- --heading-ratio: 1.2;
+ --fore-color: #111;
+ --secondary-fore-color: #444;
+ --back-color: #f8f8f8;
+ --secondary-back-color: #f0f0f0;
+ --blockquote-color: #f57c00;
+ --pre-color: #1565c0;
+ --border-color: #aaa;
+ --secondary-border-color: #ddd;
+ --heading-ratio: 1.19;
--universal-margin: 0.5rem;
- --universal-padding: 0.25rem;
- --universal-border-radius: 0.075rem;
- --background-margin: 1.5%;
- --a-link-color: #3cb4e6;
- --a-visited-color: #8c0078; }
+ --universal-padding: 0.125rem;
+ --universal-border-radius: 0.125rem;
+ --a-link-color: #0277bd;
+ --a-visited-color: #01579b; }
html {
- font-size: 13.5px; }
+ font-size: 14px; }
a, b, del, em, i, ins, q, span, strong, u {
font-size: 1em; }
html, * {
- font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
- line-height: 1.25;
+ font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
+ line-height: 1.4;
-webkit-text-size-adjust: 100%; }
* {
@@ -42,10 +42,7 @@
body {
margin: 0;
color: var(--fore-color);
- @background: var(--back-color);
- background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
- background-size: var(--background-margin);
- }
+ background: var(--back-color); }
details {
display: block; }
@@ -65,9 +62,9 @@
height: auto; }
h1, h2, h3, h4, h5, h6 {
- line-height: 1.25;
+ line-height: 1.2;
margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
- font-weight: 400; }
+ font-weight: 500; }
h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
color: var(--secondary-fore-color);
display: block;
@@ -77,15 +74,21 @@
font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
h2 {
- font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
- border-style: none none solid none ;
- border-width: thin;
- border-color: var(--border-color); }
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
+ background: var(--mark-back-color);
+ font-weight: 600;
+ padding: 0.1em 0.5em 0.2em 0.5em;
+ color: var(--mark-fore-color); }
+
h3 {
- font-size: calc(1rem * var(--heading-ratio) ); }
+ font-size: calc(1rem * var(--heading-ratio));
+ padding-left: calc(2 * var(--universal-margin));
+ /* background: var(--border-color); */
+ }
h4 {
- font-size: calc(1rem * var(--heading-ratio)); }
+ font-size: 1rem;);
+ padding-left: calc(4 * var(--universal-margin)); }
h5 {
font-size: 1rem; }
@@ -98,7 +101,7 @@
ol, ul {
margin: var(--universal-margin);
- padding-left: calc(3 * var(--universal-margin)); }
+ padding-left: calc(6 * var(--universal-margin)); }
b, strong {
font-weight: 700; }
@@ -108,7 +111,7 @@
border: 0;
line-height: 1.25em;
margin: var(--universal-margin);
- height: 0.0714285714rem;
+ height: 0.0625rem;
background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
blockquote {
@@ -118,16 +121,16 @@
color: var(--secondary-fore-color);
margin: var(--universal-margin);
padding: calc(3 * var(--universal-padding));
- border: 0.0714285714rem solid var(--secondary-border-color);
- border-left: 0.3rem solid var(--blockquote-color);
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.375rem solid var(--blockquote-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
blockquote:before {
position: absolute;
top: calc(0rem - var(--universal-padding));
left: 0;
font-family: sans-serif;
- font-size: 2rem;
- font-weight: 800;
+ font-size: 3rem;
+ font-weight: 700;
content: "\201c";
color: var(--blockquote-color); }
blockquote[cite]:after {
@@ -157,8 +160,8 @@
background: var(--secondary-back-color);
padding: calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
- border: 0.0714285714rem solid var(--secondary-border-color);
- border-left: 0.2857142857rem solid var(--pre-color);
+ border: 0.0625rem solid var(--secondary-border-color);
+ border-left: 0.25rem solid var(--pre-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
sup, sub, code, kbd {
@@ -201,8 +204,7 @@
box-sizing: border-box;
display: flex;
flex: 0 1 auto;
- flex-flow: row wrap;
- margin: 0 0 0 var(--background-margin); }
+ flex-flow: row wrap; }
.col-sm,
[class^='col-sm-'],
@@ -563,9 +565,9 @@
order: 999; } }
/* Card component CSS variable definitions */
:root {
- --card-back-color: #3cb4e6;
- --card-fore-color: #03234b;
- --card-border-color: #03234b; }
+ --card-back-color: #f8f8f8;
+ --card-fore-color: #111;
+ --card-border-color: #ddd; }
.card {
display: flex;
@@ -576,7 +578,7 @@
width: 100%;
background: var(--card-back-color);
color: var(--card-fore-color);
- border: 0.0714285714rem solid var(--card-border-color);
+ border: 0.0625rem solid var(--card-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
overflow: hidden; }
@@ -590,7 +592,7 @@
margin: 0;
border: 0;
border-radius: 0;
- border-bottom: 0.0714285714rem solid var(--card-border-color);
+ border-bottom: 0.0625rem solid var(--card-border-color);
padding: var(--universal-padding);
width: 100%; }
.card > .sectione.media {
@@ -615,18 +617,17 @@
width: auto; }
.card.warning {
+/* --card-back-color: #ffca28; */
--card-back-color: #e5b8b7;
- --card-fore-color: #3b234b;
- --card-border-color: #8c0078; }
+ --card-border-color: #e8b825; }
.card.error {
- --card-back-color: #464650;
- --card-fore-color: #ffffff;
- --card-border-color: #8c0078; }
+ --card-back-color: #b71c1c;
+ --card-fore-color: #f8f8f8;
+ --card-border-color: #a71a1a; }
.card > .sectione.dark {
- --card-back-color: #3b234b;
- --card-fore-color: #ffffff; }
+ --card-back-color: #e0e0e0; }
.card > .sectione.double-padded {
padding: calc(1.5 * var(--universal-padding)); }
@@ -636,12 +637,12 @@
*/
/* Input_control module CSS variable definitions */
:root {
- --form-back-color: #ffe97f;
- --form-fore-color: #03234b;
- --form-border-color: #3cb4e6;
- --input-back-color: #ffffff;
- --input-fore-color: #03234b;
- --input-border-color: #3cb4e6;
+ --form-back-color: #f0f0f0;
+ --form-fore-color: #111;
+ --form-border-color: #ddd;
+ --input-back-color: #f8f8f8;
+ --input-fore-color: #111;
+ --input-border-color: #ddd;
--input-focus-color: #0288d1;
--input-invalid-color: #d32f2f;
--button-back-color: #e2e2e2;
@@ -654,13 +655,13 @@
form {
background: var(--form-back-color);
color: var(--form-fore-color);
- border: 0.0714285714rem solid var(--form-border-color);
+ border: 0.0625rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
fieldset {
- border: 0.0714285714rem solid var(--form-border-color);
+ border: 0.0625rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 4);
padding: var(--universal-padding); }
@@ -670,7 +671,7 @@
display: table;
max-width: 100%;
white-space: normal;
- font-weight: 500;
+ font-weight: 700;
padding: calc(var(--universal-padding) / 2); }
label {
@@ -715,7 +716,7 @@
box-sizing: border-box;
background: var(--input-back-color);
color: var(--input-fore-color);
- border: 0.0714285714rem solid var(--input-border-color);
+ border: 0.0625rem solid var(--input-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 2);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
@@ -762,8 +763,8 @@
[type="radio"]:checked:before {
border-radius: 100%;
content: '';
- top: calc(0.0714285714rem + var(--universal-padding) / 2);
- left: calc(0.0714285714rem + var(--universal-padding) / 2);
+ top: calc(0.0625rem + var(--universal-padding) / 2);
+ left: calc(0.0625rem + var(--universal-padding) / 2);
background: var(--input-fore-color);
width: 0.5rem;
height: 0.5rem; }
@@ -792,7 +793,7 @@
display: inline-block;
background: var(--button-back-color);
color: var(--button-fore-color);
- border: 0.0714285714rem solid var(--button-border-color);
+ border: 0.0625rem solid var(--button-border-color);
border-radius: var(--universal-border-radius);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
@@ -813,7 +814,7 @@
.button-group {
display: flex;
- border: 0.0714285714rem solid var(--button-group-border-color);
+ border: 0.0625rem solid var(--button-group-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
.button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
@@ -825,13 +826,13 @@
border-radius: 0;
box-shadow: none; }
.button-group > :not(:first-child) {
- border-left: 0.0714285714rem solid var(--button-group-border-color); }
+ border-left: 0.0625rem solid var(--button-group-border-color); }
@media screen and (max-width: 499px) {
.button-group {
flex-direction: column; }
.button-group > :not(:first-child) {
border: 0;
- border-top: 0.0714285714rem solid var(--button-group-border-color); } }
+ border-top: 0.0625rem solid var(--button-group-border-color); } }
/*
Custom elements for forms and input elements.
@@ -873,29 +874,29 @@
*/
/* Navigation module CSS variable definitions */
:root {
- --header-back-color: #03234b;
- --header-hover-back-color: #ffd200;
- --header-fore-color: #ffffff;
- --header-border-color: #3cb4e6;
- --nav-back-color: #ffffff;
- --nav-hover-back-color: #ffe97f;
- --nav-fore-color: #e6007e;
- --nav-border-color: #3cb4e6;
- --nav-link-color: #3cb4e6;
- --footer-fore-color: #ffffff;
- --footer-back-color: #03234b;
- --footer-border-color: #3cb4e6;
- --footer-link-color: #3cb4e6;
- --drawer-back-color: #ffffff;
- --drawer-hover-back-color: #ffe97f;
- --drawer-border-color: #3cb4e6;
- --drawer-close-color: #e6007e; }
+ --header-back-color: #f8f8f8;
+ --header-hover-back-color: #f0f0f0;
+ --header-fore-color: #444;
+ --header-border-color: #ddd;
+ --nav-back-color: #f8f8f8;
+ --nav-hover-back-color: #f0f0f0;
+ --nav-fore-color: #444;
+ --nav-border-color: #ddd;
+ --nav-link-color: #0277bd;
+ --footer-fore-color: #444;
+ --footer-back-color: #f8f8f8;
+ --footer-border-color: #ddd;
+ --footer-link-color: #0277bd;
+ --drawer-back-color: #f8f8f8;
+ --drawer-hover-back-color: #f0f0f0;
+ --drawer-border-color: #ddd;
+ --drawer-close-color: #444; }
header {
- height: 2.75rem;
+ height: 3.1875rem;
background: var(--header-back-color);
color: var(--header-fore-color);
- border-bottom: 0.0714285714rem solid var(--header-border-color);
+ border-bottom: 0.0625rem solid var(--header-border-color);
padding: calc(var(--universal-padding) / 4) 0;
white-space: nowrap;
overflow-x: auto;
@@ -926,7 +927,7 @@
nav {
background: var(--nav-back-color);
color: var(--nav-fore-color);
- border: 0.0714285714rem solid var(--nav-border-color);
+ border: 0.0625rem solid var(--nav-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
nav * {
@@ -945,10 +946,10 @@
nav .sublink-1:before {
position: absolute;
left: calc(var(--universal-padding) - 1 * var(--universal-padding));
- top: -0.0714285714rem;
+ top: -0.0625rem;
content: '';
height: 100%;
- border: 0.0714285714rem solid var(--nav-border-color);
+ border: 0.0625rem solid var(--nav-border-color);
border-left: 0; }
nav .sublink-2 {
position: relative;
@@ -956,16 +957,16 @@
nav .sublink-2:before {
position: absolute;
left: calc(var(--universal-padding) - 3 * var(--universal-padding));
- top: -0.0714285714rem;
+ top: -0.0625rem;
content: '';
height: 100%;
- border: 0.0714285714rem solid var(--nav-border-color);
+ border: 0.0625rem solid var(--nav-border-color);
border-left: 0; }
footer {
background: var(--footer-back-color);
color: var(--footer-fore-color);
- border-top: 0.0714285714rem solid var(--footer-border-color);
+ border-top: 0.0625rem solid var(--footer-border-color);
padding: calc(2 * var(--universal-padding)) var(--universal-padding);
font-size: 0.875rem; }
footer a, footer a:visited {
@@ -1012,7 +1013,7 @@
height: 100vh;
overflow-y: auto;
background: var(--drawer-back-color);
- border: 0.0714285714rem solid var(--drawer-border-color);
+ border: 0.0625rem solid var(--drawer-border-color);
border-radius: 0;
margin: 0;
z-index: 1110;
@@ -1059,36 +1060,38 @@
*/
/* Table module CSS variable definitions. */
:root {
- --table-border-color: #03234b;
- --table-border-separator-color: #03234b;
- --table-head-back-color: #03234b;
- --table-head-fore-color: #ffffff;
- --table-body-back-color: #ffffff;
- --table-body-fore-color: #03234b;
- --table-body-alt-back-color: #f4f4f4; }
+ --table-border-color: #aaa;
+ --table-border-separator-color: #666;
+ --table-head-back-color: #e6e6e6;
+ --table-head-fore-color: #111;
+ --table-body-back-color: #f8f8f8;
+ --table-body-fore-color: #111;
+ --table-body-alt-back-color: #eee; }
table {
border-collapse: separate;
border-spacing: 0;
- margin: 0;
+ : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
display: flex;
flex: 0 1 auto;
flex-flow: row wrap;
padding: var(--universal-padding);
- padding-top: 0; }
+ padding-top: 0;
+ margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
table caption {
- font-size: 1rem;
+ font-size: 1.25 * rem;
margin: calc(2 * var(--universal-margin)) 0;
max-width: 100%;
- flex: 0 0 100%; }
+ flex: 0 0 100%;
+ text-align: left;}
table thead, table tbody {
display: flex;
flex-flow: row wrap;
- border: 0.0714285714rem solid var(--table-border-color); }
+ border: 0.0625rem solid var(--table-border-color); }
table thead {
z-index: 999;
border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
- border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
+ border-bottom: 0.0625rem solid var(--table-border-separator-color); }
table tbody {
border-top: 0;
margin-top: calc(0 - var(--universal-margin));
@@ -1106,11 +1109,11 @@
table td {
background: var(--table-body-back-color);
color: var(--table-body-fore-color);
- border-top: 0.0714285714rem solid var(--table-border-color); }
+ border-top: 0.0625rem solid var(--table-border-color); }
table:not(.horizontal) {
overflow: auto;
- max-height: 100%; }
+ max-height: 850px; }
table:not(.horizontal) thead, table:not(.horizontal) tbody {
max-width: 100%;
flex: 0 0 100%; }
@@ -1131,33 +1134,32 @@
border: 0; }
table.horizontal thead, table.horizontal tbody {
border: 0;
- flex: .2 0 0;
flex-flow: row nowrap; }
table.horizontal tbody {
overflow: auto;
justify-content: space-between;
- flex: .8 0 0;
- margin-left: 0;
+ flex: 1 0 0;
+ margin-left: calc( 4 * var(--universal-margin));
padding-bottom: calc(var(--universal-padding) / 4); }
table.horizontal tr {
flex-direction: column;
flex: 1 0 auto; }
table.horizontal th, table.horizontal td {
- width: auto;
+ width: 100%;
border: 0;
- border-bottom: 0.0714285714rem solid var(--table-border-color); }
+ border-bottom: 0.0625rem solid var(--table-border-color); }
table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
border-top: 0; }
table.horizontal th {
text-align: right;
- border-left: 0.0714285714rem solid var(--table-border-color);
- border-right: 0.0714285714rem solid var(--table-border-separator-color); }
+ border-left: 0.0625rem solid var(--table-border-color);
+ border-right: 0.0625rem solid var(--table-border-separator-color); }
table.horizontal thead tr:first-child {
padding-left: 0; }
table.horizontal th:first-child, table.horizontal td:first-child {
- border-top: 0.0714285714rem solid var(--table-border-color); }
+ border-top: 0.0625rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td {
- border-right: 0.0714285714rem solid var(--table-border-color); }
+ border-right: 0.0625rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td:first-child {
border-top-right-radius: 0.25rem; }
table.horizontal tbody tr:last-child td:last-child {
@@ -1189,12 +1191,12 @@
display: table-row-group; }
table tr, table.horizontal tr {
display: block;
- border: 0.0714285714rem solid var(--table-border-color);
+ border: 0.0625rem solid var(--table-border-color);
border-radius: var(--universal-border-radius);
- background: #ffffff;
+ background: #fafafa;
padding: var(--universal-padding);
margin: var(--universal-margin);
- margin-bottom: calc(1 * var(--universal-margin)); }
+ margin-bottom: calc(2 * var(--universal-margin)); }
table th, table td, table.horizontal th, table.horizontal td {
width: auto; }
table td, table.horizontal td {
@@ -1209,6 +1211,9 @@
border-top: 0; }
table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
border-right: 0; } }
+:root {
+ --table-body-alt-back-color: #eee; }
+
table tr:nth-of-type(2n) > td {
background: var(--table-body-alt-back-color); }
@@ -1229,8 +1234,8 @@
*/
/* Contextual module CSS variable definitions */
:root {
- --mark-back-color: #3cb4e6;
- --mark-fore-color: #ffffff; }
+ --mark-back-color: #0277bd;
+ --mark-fore-color: #fafafa; }
mark {
background: var(--mark-back-color);
@@ -1238,11 +1243,11 @@
font-size: 0.95em;
line-height: 1em;
border-radius: var(--universal-border-radius);
- padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
+ padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
mark.inline-block {
display: inline-block;
font-size: 1em;
- line-height: 1.4;
+ line-height: 1.5;
padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
:root {
@@ -1309,8 +1314,8 @@
:root {
--modal-overlay-color: rgba(0, 0, 0, 0.45);
- --modal-close-color: #e6007e;
- --modal-close-hover-color: #ffe97f; }
+ --modal-close-color: #444;
+ --modal-close-hover-color: #f0f0f0; }
[type="checkbox"].modal {
height: 1px;
@@ -1363,14 +1368,13 @@
z-index: 1211; }
:root {
- --collapse-label-back-color: #03234b;
- --collapse-label-fore-color: #ffffff;
- --collapse-label-hover-back-color: #3cb4e6;
- --collapse-selected-label-back-color: #3cb4e6;
- --collapse-border-color: var(--collapse-label-back-color);
- --collapse-selected-border-color: #ceecf8;
- --collapse-content-back-color: #ffffff;
- --collapse-selected-label-border-color: #3cb4e6; }
+ --collapse-label-back-color: #e8e8e8;
+ --collapse-label-fore-color: #212121;
+ --collapse-label-hover-back-color: #f0f0f0;
+ --collapse-selected-label-back-color: #ececec;
+ --collapse-border-color: #ddd;
+ --collapse-content-back-color: #fafafa;
+ --collapse-selected-label-border-color: #0277bd; }
.collapse {
width: calc(100% - 2 * var(--universal-margin));
@@ -1391,13 +1395,13 @@
.collapse > label {
flex-grow: 1;
display: inline-block;
- height: 1.25rem;
+ height: 1.5rem;
cursor: pointer;
- transition: background 0.2s;
+ transition: background 0.3s;
color: var(--collapse-label-fore-color);
background: var(--collapse-label-back-color);
- border: 0.0714285714rem solid var(--collapse-selected-border-color);
- padding: calc(1.25 * var(--universal-padding)); }
+ border: 0.0625rem solid var(--collapse-border-color);
+ padding: calc(1.5 * var(--universal-padding)); }
.collapse > label:hover, .collapse > label:focus {
background: var(--collapse-label-hover-back-color); }
.collapse > label + div {
@@ -1414,7 +1418,7 @@
max-height: 1px; }
.collapse > :checked + label {
background: var(--collapse-selected-label-back-color);
- border-color: var(--collapse-selected-label-border-color); }
+ border-bottom-color: var(--collapse-selected-label-border-color); }
.collapse > :checked + label + div {
box-sizing: border-box;
position: relative;
@@ -1423,13 +1427,13 @@
overflow: auto;
margin: 0;
background: var(--collapse-content-back-color);
- border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ border: 0.0625rem solid var(--collapse-border-color);
border-top: 0;
padding: var(--universal-padding);
clip: auto;
-webkit-clip-path: inset(0%);
clip-path: inset(0%);
- max-height: 100%; }
+ max-height: 850px; }
.collapse > label:not(:first-of-type) {
border-top: 0; }
.collapse > label:first-of-type {
@@ -1446,8 +1450,11 @@
/*
Custom elements for contextual background elements, toasts and tooltips.
*/
+mark.secondary {
+ --mark-back-color: #d32f2f; }
+
mark.tertiary {
- --mark-back-color: #3cb4e6; }
+ --mark-back-color: #308732; }
mark.tag {
padding: calc(var(--universal-padding)/2) var(--universal-padding);
@@ -1456,9 +1463,9 @@
/*
Definitions for progress elements and spinners.
*/
-/* Progress module CSS variable definitions */
+/* Progess module CSS variable definitions */
:root {
- --progress-back-color: #3cb4e6;
+ --progress-back-color: #ddd;
--progress-fore-color: #555; }
progress {
@@ -1551,45 +1558,45 @@
filter: invert(100%); }
span.icon-alert {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-bookmark {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-calendar {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-credit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-edit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
span.icon-link {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-help {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-home {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-info {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-lock {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-mail {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-location {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-phone {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-rss {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-search {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-settings {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-share {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-cart {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-upload {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-user {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
/*
Definitions for utilities and helper classes.
@@ -1597,7 +1604,7 @@
/* Utility module CSS variable definitions */
:root {
--generic-border-color: rgba(0, 0, 0, 0.3);
- --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
+ --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
.hidden {
display: none !important; }
@@ -1615,7 +1622,7 @@
overflow: hidden !important; }
.bordered {
- border: 0.0714285714rem solid var(--generic-border-color) !important; }
+ border: 0.0625rem solid var(--generic-border-color) !important; }
.rounded {
border-radius: var(--universal-border-radius) !important; }
@@ -1690,14 +1697,4 @@
clip-path: inset(100%) !important;
overflow: hidden !important; } }
-/*# sourceMappingURL=mini-custom.css.map */
-
-img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
-img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
-
-.figure {
- display: block;
- margin-left: auto;
- margin-right: auto;
- text-align: center;
-}
\ No newline at end of file
+/*# sourceMappingURL=mini-default.css.map */
diff --git a/_htmresc/st_logo.png b/_htmresc/st_logo.png
new file mode 100644
index 0000000..8b80057
--- /dev/null
+++ b/_htmresc/st_logo.png
Binary files differ
diff --git a/_htmresc/st_logo_2020.png b/_htmresc/st_logo_2020.png
deleted file mode 100644
index d6cebb5..0000000
--- a/_htmresc/st_logo_2020.png
+++ /dev/null
Binary files differ
