Release v1.1.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index f605e57..887d64b 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -623,6 +623,118 @@
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
/**
* @}
*/
@@ -1297,7 +1409,7 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
@@ -3130,7 +3242,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4)
+#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index 28cfc36..15c12f1 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -8,7 +8,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal.h b/Inc/stm32g4xx_hal.h
index 6ea144e..fcff709 100644
--- a/Inc/stm32g4xx_hal.h
+++ b/Inc/stm32g4xx_hal.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_adc.h b/Inc/stm32g4xx_hal_adc.h
index f301d01..d0e4817 100644
--- a/Inc/stm32g4xx_hal_adc.h
+++ b/Inc/stm32g4xx_hal_adc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1006,7 +1006,7 @@
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
-#elif defined(STM32G473xx)
+#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
@@ -1039,7 +1039,35 @@
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
+ ((((__HANDLE__)->Instance == ADC3)) && \
+ (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
+ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
+ ((__REGTRIG__) == ADC_SOFTWARE_START) )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
diff --git a/Inc/stm32g4xx_hal_adc_ex.h b/Inc/stm32g4xx_hal_adc_ex.h
index 8518b3e..68e31be 100644
--- a/Inc/stm32g4xx_hal_adc_ex.h
+++ b/Inc/stm32g4xx_hal_adc_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -464,7 +464,7 @@
* @note When multimode feature is not available, the macro always returns SET.
* @retval SET (ADC is independent) or RESET (ADC is not).
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC5) \
)? \
@@ -607,7 +607,7 @@
ADC_CCR_DUAL)
#endif /* ADC_MULTIMODE_SUPPORT */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Set handle instance of the ADC slave associated to the ADC master.
* @param __HANDLE_MASTER__ ADC master handle.
@@ -646,7 +646,7 @@
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
@@ -657,7 +657,7 @@
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
@@ -691,7 +691,7 @@
* @param __CHANNEL__ programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
@@ -743,7 +743,37 @@
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G471xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15)) || \
+ ((((__HANDLE__)->Instance) == ADC1) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
+ ((((__HANDLE__)->Instance) == ADC3) && \
+ (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
@@ -776,7 +806,7 @@
* @param __CHANNEL__ programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
@@ -815,7 +845,25 @@
(((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_15))) )
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G471xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ (((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14)) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13))) || \
+ ((((__HANDLE__)->Instance) == ADC3) && \
+ ((__CHANNEL__) == ADC_CHANNEL_15))) )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
@@ -918,7 +966,7 @@
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
-#elif defined(STM32G473xx)
+#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
@@ -950,7 +998,35 @@
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
+ ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
+ ((((__HANDLE__)->Instance == ADC3)) && \
+ (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
+ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
+ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
diff --git a/Inc/stm32g4xx_hal_comp.h b/Inc/stm32g4xx_hal_comp.h
index 762ff3d..70796bc 100644
--- a/Inc/stm32g4xx_hal_comp.h
+++ b/Inc/stm32g4xx_hal_comp.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -67,9 +67,6 @@
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
- uint32_t DeglitcherMode; /*!< Set comparator deglitcher mode.
- This parameter can be a value of @ref COMP_DeglitcherMode */
-
} COMP_InitTypeDef;
/**
@@ -272,15 +269,6 @@
* @}
*/
-/** @defgroup COMP_DeglitcherMode COMP deglitcher mode
- * @{
- */
-#define COMP_DEGLITCHER_DISABLED (0x00000000UL) /*!< Comparator deglitcher disabled */
-#define COMP_DEGLITCHER_ENABLED (COMP_CSR_DEGLITCHEN) /*!< Comparator deglitcher enabled */
-/**
- * @}
- */
-
/**
* @}
*/
@@ -691,7 +679,7 @@
*/
#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP5 EXTI line rising edge trigger.
* @retval None
@@ -776,8 +764,8 @@
*/
#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP5)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP6 EXTI line rising edge trigger.
* @retval None
@@ -862,8 +850,8 @@
*/
#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP6)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP7 EXTI line rising edge trigger.
* @retval None
@@ -948,7 +936,7 @@
*/
#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP7)
-#endif /* STM32G474xx || STM32G484xx || STM32G473xx */
+#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/**
* @}
*/
@@ -971,7 +959,7 @@
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30) /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP7 (LL_EXTI_LINE_33) /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */
@@ -1008,7 +996,7 @@
* @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
@@ -1032,7 +1020,7 @@
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
@@ -1145,7 +1133,7 @@
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
@@ -1244,8 +1232,6 @@
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
-#define IS_COMP_DEGLITCHER_MODE(__MODE__) (((__MODE__) == COMP_DEGLITCHER_DISABLED) || \
- ((__MODE__) == COMP_DEGLITCHER_ENABLED))
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_conf_template.h b/Inc/stm32g4xx_hal_conf_template.h
index c5c6841..e518391 100644
--- a/Inc/stm32g4xx_hal_conf_template.h
+++ b/Inc/stm32g4xx_hal_conf_template.h
@@ -8,7 +8,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_cortex.h b/Inc/stm32g4xx_hal_cortex.h
index a9f0278..186376c 100644
--- a/Inc/stm32g4xx_hal_cortex.h
+++ b/Inc/stm32g4xx_hal_cortex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_crc.h b/Inc/stm32g4xx_hal_crc.h
index b497f5b..dd95f38 100644
--- a/Inc/stm32g4xx_hal_crc.h
+++ b/Inc/stm32g4xx_hal_crc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_crc_ex.h b/Inc/stm32g4xx_hal_crc_ex.h
index 44725f7..3a9b83c 100644
--- a/Inc/stm32g4xx_hal_crc_ex.h
+++ b/Inc/stm32g4xx_hal_crc_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_dac.h b/Inc/stm32g4xx_hal_dac.h
index 16e2d6e..455714a 100644
--- a/Inc/stm32g4xx_hal_dac.h
+++ b/Inc/stm32g4xx_hal_dac.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -79,17 +79,17 @@
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -169,8 +169,8 @@
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
- HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
- HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
+ HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
+ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
} HAL_DAC_CallbackIDTypeDef;
@@ -236,6 +236,7 @@
#define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
#define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+
/**
* @}
*/
@@ -298,6 +299,7 @@
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
#define DAC_CHIPCONNECT_BOTH (1UL << 2)
+
/**
* @}
*/
@@ -305,7 +307,6 @@
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
-
#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */
#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */
@@ -322,7 +323,6 @@
/**
* @}
*/
-
/** @defgroup DAC_HighFrequency DAC high frequency interface mode
* @{
*/
@@ -352,8 +352,8 @@
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
diff --git a/Inc/stm32g4xx_hal_dac_ex.h b/Inc/stm32g4xx_hal_dac_ex.h
index 7282cca..03e1ab5 100644
--- a/Inc/stm32g4xx_hal_dac_ex.h
+++ b/Inc/stm32g4xx_hal_dac_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -202,7 +202,6 @@
) \
)
#endif
-
#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \
@@ -315,7 +314,6 @@
* @}
*/
-
/** @addtogroup DACEx_Private_Functions
* @{
*/
diff --git a/Inc/stm32g4xx_hal_def.h b/Inc/stm32g4xx_hal_def.h
index 99e6696..e30a615 100644
--- a/Inc/stm32g4xx_hal_def.h
+++ b/Inc/stm32g4xx_hal_def.h
@@ -7,7 +7,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_dma.h b/Inc/stm32g4xx_hal_dma.h
index f9addff..56b9a8c 100644
--- a/Inc/stm32g4xx_hal_dma.h
+++ b/Inc/stm32g4xx_hal_dma.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_dma_ex.h b/Inc/stm32g4xx_hal_dma_ex.h
index 9c51082..70f558c 100644
--- a/Inc/stm32g4xx_hal_dma_ex.h
+++ b/Inc/stm32g4xx_hal_dma_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_exti.h b/Inc/stm32g4xx_hal_exti.h
index 4c8bff8..0872e28 100644
--- a/Inc/stm32g4xx_hal_exti.h
+++ b/Inc/stm32g4xx_hal_exti.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_fdcan.h b/Inc/stm32g4xx_hal_fdcan.h
index 589c06d..4311f11 100644
--- a/Inc/stm32g4xx_hal_fdcan.h
+++ b/Inc/stm32g4xx_hal_fdcan.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_flash.h b/Inc/stm32g4xx_hal_flash.h
index aa6868f..6578358 100644
--- a/Inc/stm32g4xx_hal_flash.h
+++ b/Inc/stm32g4xx_hal_flash.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
diff --git a/Inc/stm32g4xx_hal_flash_ex.h b/Inc/stm32g4xx_hal_flash_ex.h
index 364b79e..ef015b3 100644
--- a/Inc/stm32g4xx_hal_flash_ex.h
+++ b/Inc/stm32g4xx_hal_flash_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
diff --git a/Inc/stm32g4xx_hal_flash_ramfunc.h b/Inc/stm32g4xx_hal_flash_ramfunc.h
index 482e911..33bc137 100644
--- a/Inc/stm32g4xx_hal_flash_ramfunc.h
+++ b/Inc/stm32g4xx_hal_flash_ramfunc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
diff --git a/Inc/stm32g4xx_hal_fmac.h b/Inc/stm32g4xx_hal_fmac.h
index 9c28b5a..b6e21d7 100644
--- a/Inc/stm32g4xx_hal_fmac.h
+++ b/Inc/stm32g4xx_hal_fmac.h
@@ -1,13 +1,13 @@
/**
******************************************************************************
- * @file stm32g4xx_fmac.h
+ * @file stm32g4xx_hal_fmac.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the FMAC firmware
* library.
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_gpio.h b/Inc/stm32g4xx_hal_gpio.h
index 39305b8..dcb1894 100644
--- a/Inc/stm32g4xx_hal_gpio.h
+++ b/Inc/stm32g4xx_hal_gpio.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -213,8 +213,8 @@
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
- (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+ (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
diff --git a/Inc/stm32g4xx_hal_gpio_ex.h b/Inc/stm32g4xx_hal_gpio_ex.h
index 7429c75..cda1636 100644
--- a/Inc/stm32g4xx_hal_gpio_ex.h
+++ b/Inc/stm32g4xx_hal_gpio_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_hrtim.h b/Inc/stm32g4xx_hal_hrtim.h
index 50d56cb..086ec4f 100644
--- a/Inc/stm32g4xx_hal_hrtim.h
+++ b/Inc/stm32g4xx_hal_hrtim.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -25,10 +25,10 @@
extern "C" {
#endif
-#if defined(HRTIM1)
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
+#if defined(HRTIM1)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
@@ -688,6 +688,10 @@
#define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */
#define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */
#define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */
+/**
+ * @}
+ */
+
/** @defgroup HRTIM_ADC_Ext_Trigger HRTIM ADC Extended Trigger
* @{
* @brief Constants defining ADC Extended triggers identifiers
@@ -1207,18 +1211,18 @@
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
-#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
-#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
+#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
/* Timer Events mapping for Timer A */
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
@@ -1279,18 +1283,17 @@
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
-
-#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
-#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
+#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
/**
* @}
*/
@@ -1300,18 +1303,18 @@
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
-#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
-#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
+#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
/* Timer Events mapping for Timer A */
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
@@ -1372,18 +1375,17 @@
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
-
-#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
/**
* @}
*/
@@ -1618,8 +1620,12 @@
* @brief Constants enabling the External Event Counter A or B Reset Mode
*/
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL (0x00000000U) /*!< External Event Counter is reset on each reset / roll-over event */
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL (0x00000001U) /*!< External Event Counter is reset on each reset / roll-over event only if no event occurs during last
- counting period */
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL (0x00000001U) /*!< External Event Counter is reset on each reset / roll-over event only
+ if no event occurs during last counting period */
+/**
+ * @}
+ */
+
/** @defgroup HRTIM_Timer_ReSyncUpdate HRTIM Timer Re-Synchronized update
* @{
* @brief Constants defining the update coming condition
@@ -1989,7 +1995,8 @@
* @brief Constants defining the blanking source of a fault event
*/
#define HRTIM_FAULTBLANKINGMODE_RSTALIGNED (0x00000000U) /*!< Fault blanking source is Reset-aligned window */
-#define HRTIM_FAULTBLANKINGMODE_MOVING (0x00000001U) /*!< Fault blanking source is Moving window *//**
+#define HRTIM_FAULTBLANKINGMODE_MOVING (0x00000001U) /*!< Fault blanking source is Moving window */
+/**
* @}
*/
@@ -2958,71 +2965,71 @@
#define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
- (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
- ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
+ (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
+ ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
- (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
- ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
+ (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
+ ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
diff --git a/Inc/stm32g4xx_hal_i2c.h b/Inc/stm32g4xx_hal_i2c.h
index 8ad273f..158d2d0 100644
--- a/Inc/stm32g4xx_hal_i2c.h
+++ b/Inc/stm32g4xx_hal_i2c.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_i2c_ex.h b/Inc/stm32g4xx_hal_i2c_ex.h
index fdee1fd..68a443d 100644
--- a/Inc/stm32g4xx_hal_i2c_ex.h
+++ b/Inc/stm32g4xx_hal_i2c_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_i2s.h b/Inc/stm32g4xx_hal_i2s.h
index b7957f9..8cf3be7 100644
--- a/Inc/stm32g4xx_hal_i2s.h
+++ b/Inc/stm32g4xx_hal_i2s.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -25,10 +25,10 @@
extern "C" {
#endif
-#if defined(SPI_I2S_SUPPORT)
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
+#if defined(SPI_I2S_SUPPORT)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
@@ -456,14 +456,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
diff --git a/Inc/stm32g4xx_hal_irda.h b/Inc/stm32g4xx_hal_irda.h
index cd6ef72..edf22f5 100644
--- a/Inc/stm32g4xx_hal_irda.h
+++ b/Inc/stm32g4xx_hal_irda.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -303,7 +303,7 @@
* @}
*/
-/** @defgroup IRDA_ClockPrescaler Clock Prescaler
+/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
* @{
*/
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
diff --git a/Inc/stm32g4xx_hal_irda_ex.h b/Inc/stm32g4xx_hal_irda_ex.h
index f569486..603f78e 100644
--- a/Inc/stm32g4xx_hal_irda_ex.h
+++ b/Inc/stm32g4xx_hal_irda_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -32,7 +32,8 @@
* @{
*/
-/** @addtogroup IRDAEx
+/** @defgroup IRDAEx IRDAEx
+ * @brief IRDA Extended HAL module driver
* @{
*/
diff --git a/Inc/stm32g4xx_hal_iwdg.h b/Inc/stm32g4xx_hal_iwdg.h
index f563ec2..da0c946 100644
--- a/Inc/stm32g4xx_hal_iwdg.h
+++ b/Inc/stm32g4xx_hal_iwdg.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_lptim.h b/Inc/stm32g4xx_hal_lptim.h
index bfdcd77..e3bfd55 100644
--- a/Inc/stm32g4xx_hal_lptim.h
+++ b/Inc/stm32g4xx_hal_lptim.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -718,7 +718,7 @@
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G484xx)
+#if defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
@@ -745,7 +745,7 @@
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
((__TRIG__) == LPTIM_TRIGSOURCE_9))
-#endif /* STM32G473xx || STM32G474xx || STM32G484xx */
+#endif /* STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
diff --git a/Inc/stm32g4xx_hal_nand.h b/Inc/stm32g4xx_hal_nand.h
index fd142c2..7f7e36a 100644
--- a/Inc/stm32g4xx_hal_nand.h
+++ b/Inc/stm32g4xx_hal_nand.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_nor.h b/Inc/stm32g4xx_hal_nor.h
index 2aaa363..cf6d5cf 100644
--- a/Inc/stm32g4xx_hal_nor.h
+++ b/Inc/stm32g4xx_hal_nor.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_opamp.h b/Inc/stm32g4xx_hal_opamp.h
index 439fc09..8f185c0 100644
--- a/Inc/stm32g4xx_hal_opamp.h
+++ b/Inc/stm32g4xx_hal_opamp.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_opamp_ex.h b/Inc/stm32g4xx_hal_opamp_ex.h
index e62ada6..a89c2ca 100644
--- a/Inc/stm32g4xx_hal_opamp_ex.h
+++ b/Inc/stm32g4xx_hal_opamp_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -49,7 +49,7 @@
/* I/O operation functions *****************************************************/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6);
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
diff --git a/Inc/stm32g4xx_hal_pcd.h b/Inc/stm32g4xx_hal_pcd.h
index 852dc80..ce60a8a 100644
--- a/Inc/stm32g4xx_hal_pcd.h
+++ b/Inc/stm32g4xx_hal_pcd.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -155,7 +155,7 @@
/** @defgroup PCD_Speed PCD Speed
* @{
*/
-#define PCD_SPEED_FULL 2U
+#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
@@ -200,15 +200,6 @@
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR1 & (USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR1 = USB_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do { \
- EXTI->FTSR1 &= ~(USB_WAKEUP_EXTI_LINE); \
- EXTI->RTSR1 |= USB_WAKEUP_EXTI_LINE; \
- } while(0U)
-
/**
@@ -723,20 +714,20 @@
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
- register uint16_t *_wRegVal; \
+ register __IO uint16_t *_wRegVal; \
register uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
- register uint16_t *_wRegVal; \
+ register __IO uint16_t *_wRegVal; \
register uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
@@ -758,6 +749,10 @@
*/
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
(wNBlocks) = (wCount) >> 5; \
+ if (((wCount) & 0x1fU) == 0U) \
+ { \
+ (wNBlocks)--; \
+ } \
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
@@ -777,22 +772,22 @@
*(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
- else if((wCount) < 62U) \
+ else if((wCount) <= 62U) \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
- PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \
+ PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
- uint16_t *pdwReg; \
+ register __IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
- pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+ pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
} while(0)
@@ -805,19 +800,19 @@
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
- uint16_t *_wRegVal; \
+ register __IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
register uint32_t _wRegBase = (uint32_t)(USBx); \
- uint16_t *_wRegVal; \
+ register __IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
- _wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
+ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
} while(0)
@@ -893,7 +888,7 @@
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
register uint32_t _wBase = (uint32_t)(USBx); \
- uint16_t *_wEPRegVal; \
+ __IO uint16_t *_wEPRegVal; \
\
if ((bDir) == 0U) \
{ \
@@ -906,7 +901,7 @@
{ \
/* IN endpoint */ \
_wBase += (uint32_t)(USBx)->BTABLE; \
- _wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
+ _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
*_wEPRegVal = (uint16_t)(wCount); \
} \
} \
diff --git a/Inc/stm32g4xx_hal_pcd_ex.h b/Inc/stm32g4xx_hal_pcd_ex.h
index f706739..e8c1b2e 100644
--- a/Inc/stm32g4xx_hal_pcd_ex.h
+++ b/Inc/stm32g4xx_hal_pcd_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_pwr.h b/Inc/stm32g4xx_hal_pwr.h
index 782caed..7634556 100644
--- a/Inc/stm32g4xx_hal_pwr.h
+++ b/Inc/stm32g4xx_hal_pwr.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_pwr_ex.h b/Inc/stm32g4xx_hal_pwr_ex.h
index 5aaa548..6e0ac9e 100644
--- a/Inc/stm32g4xx_hal_pwr_ex.h
+++ b/Inc/stm32g4xx_hal_pwr_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_qspi.h b/Inc/stm32g4xx_hal_qspi.h
index feb50b0..4382ac3 100644
--- a/Inc/stm32g4xx_hal_qspi.h
+++ b/Inc/stm32g4xx_hal_qspi.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_rcc.h b/Inc/stm32g4xx_hal_rcc.h
index 07b307e..23263b2 100644
--- a/Inc/stm32g4xx_hal_rcc.h
+++ b/Inc/stm32g4xx_hal_rcc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_rcc_ex.h b/Inc/stm32g4xx_hal_rcc_ex.h
index 739c25c..899dbf7 100644
--- a/Inc/stm32g4xx_hal_rcc_ex.h
+++ b/Inc/stm32g4xx_hal_rcc_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1339,7 +1339,7 @@
(((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
-#elif defined(STM32G473xx)
+#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
diff --git a/Inc/stm32g4xx_hal_rng.h b/Inc/stm32g4xx_hal_rng.h
index 0868a06..f1a1fe6 100644
--- a/Inc/stm32g4xx_hal_rng.h
+++ b/Inc/stm32g4xx_hal_rng.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -176,7 +176,9 @@
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
-
+#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
+#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
+#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_hal_rtc.h b/Inc/stm32g4xx_hal_rtc.h
index 27a2b3c..5e66443 100644
--- a/Inc/stm32g4xx_hal_rtc.h
+++ b/Inc/stm32g4xx_hal_rtc.h
@@ -469,10 +469,10 @@
* @}
*/
-/** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask
+/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
* @{
*/
-#define RTC_IT_MASK 0x001FU /*!< RTC interruptions flags mask */
+#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask (5bits) */
/**
* @}
*/
@@ -482,24 +482,24 @@
* - YYYYY : Interrupt flag position in the XX register (5bits)
* - XX : Interrupt status register (2bits)
* - 01: ICSR register
- * - 10: SR register
+ * - 10: SR or SCR or MISR registers
* @{
*/
-#define RTC_FLAG_RECALPF 0x00000110U /*!< Recalibration pending Flag */
-#define RTC_FLAG_INITF 0x00000106U /*!< Initialization flag */
-#define RTC_FLAG_RSF 0x00000105U /*!< Registers synchronization flag */
-#define RTC_FLAG_INITS 0x00000104U /*!< Initialization status flag */
-#define RTC_FLAG_SHPF 0x00000103U /*!< Shift operation pending flag */
-#define RTC_FLAG_WUTWF 0x00000102U /*!< Wakeup timer write flag */
-#define RTC_FLAG_ALRBWF 0x00000101U /*!< Alarm B write flag */
-#define RTC_FLAG_ALRAWF 0x00000100U /*!< Alarm A write flag */
-#define RTC_FLAG_ITSF 0x00000205U /*!< Clear Internal Time-stamp flag */
-#define RTC_FLAG_TSOVF 0x00000204U /*!< Clear Time-stamp overflow flag */
-#define RTC_FLAG_TSF 0x00000203U /*!< Clear Time-stamp flag */
-#define RTC_FLAG_WUTF 0x00000202U /*!< Clear Wakeup timer flag */
-#define RTC_FLAG_ALRBF 0x00000201U /*!< Clear Alarm B flag */
-#define RTC_FLAG_ALRAF 0x00000200U /*!< Clear Alarm A flag */
-/**
+#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
+#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
+#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
+#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
+#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
+#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
+#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos) /*!< Alarm B write flag */
+#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos) /*!< Alarm A write flag */
+#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */
+#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */
+#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */
+#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */
+#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */
+#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */
+ /**
* @}
*/
@@ -982,6 +982,7 @@
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
diff --git a/Inc/stm32g4xx_hal_rtc_ex.h b/Inc/stm32g4xx_hal_rtc_ex.h
index 494c3ad..0fefc8f 100644
--- a/Inc/stm32g4xx_hal_rtc_ex.h
+++ b/Inc/stm32g4xx_hal_rtc_ex.h
@@ -575,8 +575,8 @@
* @arg @ref RTC_FLAG_ALRAF Alarm A flag
* @retval None
*/
-#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) : \
- (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))))
+#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
+ ((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
/* ---------------------------------WAKEUPTIMER---------------------------------*/
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
@@ -792,8 +792,7 @@
* @arg @ref RTC_FLAG_TSOVF
* @retval None
*/
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \
- (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF)))
+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
/* TIMESTAMP TIMER EXTI */
/* -------------------- */
diff --git a/Inc/stm32g4xx_hal_sai.h b/Inc/stm32g4xx_hal_sai.h
index f233579..36d9b18 100644
--- a/Inc/stm32g4xx_hal_sai.h
+++ b/Inc/stm32g4xx_hal_sai.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_sai_ex.h b/Inc/stm32g4xx_hal_sai_ex.h
index c25c456..2e0829d 100644
--- a/Inc/stm32g4xx_hal_sai_ex.h
+++ b/Inc/stm32g4xx_hal_sai_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_smartcard.h b/Inc/stm32g4xx_hal_smartcard.h
index 25b7818..40028b9 100644
--- a/Inc/stm32g4xx_hal_smartcard.h
+++ b/Inc/stm32g4xx_hal_smartcard.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -440,7 +440,7 @@
* @}
*/
-/** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler
+/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler
* @{
*/
#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
diff --git a/Inc/stm32g4xx_hal_smartcard_ex.h b/Inc/stm32g4xx_hal_smartcard_ex.h
index 4179c22..9fdd71e 100644
--- a/Inc/stm32g4xx_hal_smartcard_ex.h
+++ b/Inc/stm32g4xx_hal_smartcard_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -68,7 +68,7 @@
* @}
*/
-/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode
+/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
* @brief SMARTCARD FIFO mode
* @{
*/
@@ -78,7 +78,7 @@
* @}
*/
-/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level
+/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
* @brief SMARTCARD TXFIFO level
* @{
*/
@@ -92,7 +92,7 @@
* @}
*/
-/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level
+/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
* @brief SMARTCARD RXFIFO level
* @{
*/
diff --git a/Inc/stm32g4xx_hal_smbus.h b/Inc/stm32g4xx_hal_smbus.h
index db01a0a..c3abdb6 100644
--- a/Inc/stm32g4xx_hal_smbus.h
+++ b/Inc/stm32g4xx_hal_smbus.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_spi.h b/Inc/stm32g4xx_hal_spi.h
index 7e2f61e..6c5940a 100644
--- a/Inc/stm32g4xx_hal_spi.h
+++ b/Inc/stm32g4xx_hal_spi.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_spi_ex.h b/Inc/stm32g4xx_hal_spi_ex.h
index 143a4b1..8351238 100644
--- a/Inc/stm32g4xx_hal_spi_ex.h
+++ b/Inc/stm32g4xx_hal_spi_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_sram.h b/Inc/stm32g4xx_hal_sram.h
index 58cafd3..90c674d 100644
--- a/Inc/stm32g4xx_hal_sram.h
+++ b/Inc/stm32g4xx_hal_sram.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_tim.h b/Inc/stm32g4xx_hal_tim.h
index f01cdaa..fcf0950 100644
--- a/Inc/stm32g4xx_hal_tim.h
+++ b/Inc/stm32g4xx_hal_tim.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -242,7 +242,12 @@
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
+ This parameter can be a value of @ref TIM_Master_Slave_Mode
+ @note When the Master/slave mode is enabled, the effect of
+ an event on the trigger input (TRGI) is delayed to allow a
+ perfect synchronization between the current timer and its
+ slaves (through TRGO). It is not mandatory in case of timer
+ synchronization mode. */
} TIM_MasterConfigTypeDef;
/**
@@ -1621,12 +1626,62 @@
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
- ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+ * @brief Enable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is enabled an active edge on the trigger input acts
+ * like a compare match on CCx output. Delay to sample the trigger
+ * input and to activate CCx output is reduced to 3 clock cycles.
+ * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+ * @brief Disable fast mode for a given channel.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @arg TIM_CHANNEL_5: TIM Channel 5 selected
+ * @arg TIM_CHANNEL_6: TIM Channel 6 selected
+ * @note When fast mode is disabled CCx output behaves normally depending
+ * on counter and CCRx values even when the trigger is ON. The minimum
+ * delay to activate CCx output when an active edge occurs on the
+ * trigger input is 5 clock cycles.
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+ ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -2143,10 +2198,10 @@
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
@@ -2155,10 +2210,10 @@
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/**
* @}
diff --git a/Inc/stm32g4xx_hal_tim_ex.h b/Inc/stm32g4xx_hal_tim_ex.h
index a8dabda..2db8481 100644
--- a/Inc/stm32g4xx_hal_tim_ex.h
+++ b/Inc/stm32g4xx_hal_tim_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -80,9 +80,9 @@
typedef struct
{
uint32_t Polarity; /*!< TIM Encoder index polarity.
- This parameter can be a value of @ref TIM_Encoder_Index_Polarity */
+ This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */
uint32_t Prescaler; /*!< TIM Encoder index prescaler.
- This parameter can be a value of @ref TIM_Encoder_Index_Prescaler */
+ This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */
uint32_t Filter; /*!< TIM Encoder index filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.
diff --git a/Inc/stm32g4xx_hal_uart.h b/Inc/stm32g4xx_hal_uart.h
index f667c7a..002d35a 100644
--- a/Inc/stm32g4xx_hal_uart.h
+++ b/Inc/stm32g4xx_hal_uart.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_uart_ex.h b/Inc/stm32g4xx_hal_uart_ex.h
index 31fc30d..f3582bd 100644
--- a/Inc/stm32g4xx_hal_uart_ex.h
+++ b/Inc/stm32g4xx_hal_uart_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_usart.h b/Inc/stm32g4xx_hal_usart.h
index c140f78..4e94aa4 100644
--- a/Inc/stm32g4xx_hal_usart.h
+++ b/Inc/stm32g4xx_hal_usart.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_usart_ex.h b/Inc/stm32g4xx_hal_usart_ex.h
index e04ca0e..be45e60 100644
--- a/Inc/stm32g4xx_hal_usart_ex.h
+++ b/Inc/stm32g4xx_hal_usart_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_hal_wwdg.h b/Inc/stm32g4xx_hal_wwdg.h
index cad2953..0299d7f 100644
--- a/Inc/stm32g4xx_hal_wwdg.h
+++ b/Inc/stm32g4xx_hal_wwdg.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -22,7 +22,7 @@
#define STM32G4xx_HAL_WWDG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -89,12 +89,12 @@
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
-}HAL_WWDG_CallbackIDTypeDef;
+} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
-typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef * hppp); /*!< pointer to a WWDG common callback functions */
+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif
/**
@@ -247,7 +247,8 @@
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
+ & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
diff --git a/Inc/stm32g4xx_ll_adc.h b/Inc/stm32g4xx_ll_adc.h
index 0103ea4..f6870c9 100644
--- a/Inc/stm32g4xx_ll_adc.h
+++ b/Inc/stm32g4xx_ll_adc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1894,7 +1894,7 @@
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
* Value "1" if the internal channel selected is available on the ADC instance selected.
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC1) \
&&( \
@@ -1937,7 +1937,33 @@
) \
) \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G471xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ ((((__ADC_INSTANCE__) == ADC1) \
+ &&( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
+ ) \
+ ) \
+ || \
+ (((__ADC_INSTANCE__) == ADC2) \
+ &&( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
+ ) \
+ ) \
+ || \
+ (((__ADC_INSTANCE__) == ADC3) \
+ &&( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
+ ) \
+ ) \
+ )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC1) \
&&( \
@@ -2304,6 +2330,7 @@
* is enabled.
*/
#if defined(ADC345_COMMON)
+#if defined(ADC4) && defined(ADC5)
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(((__ADCXY_COMMON__) == ADC12_COMMON) \
? ( \
@@ -2319,6 +2346,17 @@
)
#else
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) \
+ ? ( \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) ) \
+ ) \
+ : \
+ (LL_ADC_IsEnabled(ADC3)) \
+ )
+#endif /* ADC4 && ADC5 */
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
#endif
@@ -5070,7 +5108,7 @@
ADC_JSQR_JSQ2 |
ADC_JSQR_JSQ1 |
ADC_JSQR_JL,
- TriggerSource |
+ (TriggerSource & ADC_JSQR_JEXTSEL) |
(ExternalTriggerEdge * (is_trigger_not_sw)) |
(((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
@@ -6944,7 +6982,7 @@
}
/**
- * @brief Get ADC group regular conversion data, range fit for
+ * @brief Get ADC group injected conversion data, range fit for
* all ADC configurations: all ADC resolutions and
* all oversampling increased data width (for devices
* with feature oversampling).
diff --git a/Inc/stm32g4xx_ll_bus.h b/Inc/stm32g4xx_ll_bus.h
index 3e02519..74c928d 100644
--- a/Inc/stm32g4xx_ll_bus.h
+++ b/Inc/stm32g4xx_ll_bus.h
@@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_comp.h b/Inc/stm32g4xx_ll_comp.h
index a32d58d..2a078a8 100644
--- a/Inc/stm32g4xx_ll_comp.h
+++ b/Inc/stm32g4xx_ll_comp.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -79,11 +79,6 @@
This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
- uint32_t DeglitcherMode; /*!< Configure the comparator deglitcher mode.
- This parameter can be a value of @ref COMP_LL_EC_DEGLITCHER_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_COMP_SetDeglitcherMode(). */
-
} LL_COMP_InitTypeDef;
/**
@@ -202,15 +197,6 @@
* @}
*/
-/** @defgroup COMP_LL_EC_DEGLITCHER_MODE Comparator Deglitcher Mode
- * @{
- */
-#define LL_COMP_DEGLITCHER_DISABLED (0x00000000UL) /*!< Comparator deglitcher disabled */
-#define LL_COMP_DEGLITCHER_ENABLED (COMP_CSR_DEGLITCHEN) /*!< Comparator deglitcher enabled */
-/**
- * @}
- */
-
/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
* @note Only COMP peripheral HW delays are defined in COMP LL driver driver,
* not timeout values.
@@ -630,32 +616,6 @@
}
/**
- * @brief Configure comparator instance deglitcher mode.
- * @rmtoll CSR DEGLITCHEN LL_COMP_SetDeglitcherMode
- * @param COMPx Comparator instance
- * @param DeglitcherMode This parameter can be one of the following values:
- * @arg @ref LL_COMP_DEGLITCHER_DISABLED
- * @arg @ref LL_COMP_DEGLITCHER_ENABLED
- * @retval None
- */
-__STATIC_INLINE void LL_COMP_SetDeglitcherMode(COMP_TypeDef *COMPx, uint32_t DeglitcherMode)
-{
- MODIFY_REG(COMPx->CSR, COMP_CSR_DEGLITCHEN, DeglitcherMode);
-}
-
-/**
- * @brief Get comparator instance deglitcher mode.
- * @rmtoll CSR DEGLITCHEN LL_COMP_GetDeglitcherMode
- * @param COMPx Comparator instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_COMP_DEGLITCHER_DISABLED
- * @arg @ref LL_COMP_DEGLITCHER_ENABLED
- */
-__STATIC_INLINE uint32_t LL_COMP_GetDeglitcherMode(COMP_TypeDef *COMPx)
-{
- return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_DEGLITCHEN));
-}
-/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_cortex.h b/Inc/stm32g4xx_ll_cortex.h
index d7a4997..4282fae 100644
--- a/Inc/stm32g4xx_ll_cortex.h
+++ b/Inc/stm32g4xx_ll_cortex.h
@@ -21,7 +21,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_crc.h b/Inc/stm32g4xx_ll_crc.h
index 7d2bd60..e6fa0e8 100644
--- a/Inc/stm32g4xx_ll_crc.h
+++ b/Inc/stm32g4xx_ll_crc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_dac.h b/Inc/stm32g4xx_ll_dac.h
index 4d8f544..cfa8055 100644
--- a/Inc/stm32g4xx_ll_dac.h
+++ b/Inc/stm32g4xx_ll_dac.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -55,7 +55,6 @@
/* - channel register offset of data output register DORx */
/* - channel register offset of sample-and-hold sample time register SHSRx */
/* - channel register offset of sawtooth register STRx */
-
#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
@@ -82,7 +81,6 @@
#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-
#define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */
#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
@@ -148,13 +146,13 @@
*/
typedef struct
{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource().
@note If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth RESET trigger */
- uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource2().
@@ -180,6 +178,7 @@
This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+
uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
@@ -189,7 +188,6 @@
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
-
} LL_DAC_InitTypeDef;
/**
@@ -266,31 +264,31 @@
* @{
*/
#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC (all) channel conversion trigger internal (SW start) */
-#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external IP: TIM1 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external IP: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: TIM15 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
-#define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC (all) channel conversion trigger from external IP: TIM3 TRGO. */
-#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external IP: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
-#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external IP: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
-#define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external IP: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM15 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
+#define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
+#define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
/**
* @}
*/
@@ -412,7 +410,7 @@
*/
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
- * @note Only DAC IP HW delays are defined in DAC LL driver driver,
+ * @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
@@ -433,7 +431,6 @@
/* Unit: us */
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
-
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
@@ -536,7 +533,7 @@
) \
: \
( \
- 0 \
+ 0U \
) \
) \
)
@@ -1065,7 +1062,7 @@
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_STR1_STDIR1,
@@ -1089,7 +1086,7 @@
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_STR1_STDIR1);
}
@@ -1116,7 +1113,7 @@
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_STR1_STRSTDATA1,
@@ -1139,7 +1136,7 @@
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t)(READ_BIT(*preg, DAC_STR1_STRSTDATA1) >> DAC_STR1_STRSTDATA1_Pos);
}
@@ -1168,7 +1165,7 @@
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_STR1_STINCDATA1,
@@ -1193,7 +1190,7 @@
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t)(READ_BIT(*preg, DAC_STR1_STINCDATA1) >> DAC_STR1_STINCDATA1_Pos);
}
@@ -1636,7 +1633,7 @@
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_SHSR1_TSAMPLE1,
@@ -1659,7 +1656,7 @@
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
}
@@ -2214,7 +2211,7 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_DHR12R1_DACC1DHR,
@@ -2239,7 +2236,7 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_DHR12L1_DACC1DHR,
@@ -2264,7 +2261,7 @@
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_DHR8R1_DACC1DHR,
@@ -2352,7 +2349,7 @@
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
- register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+ __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
diff --git a/Inc/stm32g4xx_ll_dma.h b/Inc/stm32g4xx_ll_dma.h
index b6095b7..c294bf9 100644
--- a/Inc/stm32g4xx_ll_dma.h
+++ b/Inc/stm32g4xx_ll_dma.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -272,17 +272,17 @@
/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
* @{
*/
-#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
-#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
#if defined (DMA1_Channel7)
-#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
+#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
-#define LL_DMA_CHANNEL_8 0x00000008U /*!< DMA Channel 8 */
+#define LL_DMA_CHANNEL_8 0x00000007U /*!< DMA Channel 8 */
#endif /* DMA1_Channel8 */
#if defined(USE_FULL_LL_DRIVER)
#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
@@ -517,9 +517,8 @@
*/
__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
}
/**
@@ -540,9 +539,8 @@
*/
__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
}
/**
@@ -563,9 +561,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
}
@@ -602,9 +599,8 @@
*/
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
Configuration);
}
@@ -632,9 +628,8 @@
*/
__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
}
@@ -660,9 +655,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
}
@@ -689,9 +683,8 @@
*/
__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC,
Mode);
}
@@ -715,9 +708,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_CIRC));
}
@@ -742,9 +734,8 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC,
PeriphOrM2MSrcIncMode);
}
@@ -768,9 +759,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_PINC));
}
@@ -795,9 +785,8 @@
*/
__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MINC,
MemoryOrM2MDstIncMode);
}
@@ -821,9 +810,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_MINC));
}
@@ -849,9 +837,8 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PSIZE,
PeriphOrM2MSrcDataSize);
}
@@ -876,9 +863,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_PSIZE));
}
@@ -904,9 +890,8 @@
*/
__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MSIZE,
MemoryOrM2MDstDataSize);
}
@@ -931,9 +916,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_MSIZE));
}
@@ -960,9 +944,8 @@
*/
__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PL,
Priority);
}
@@ -988,9 +971,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_PL));
}
@@ -1015,9 +997,8 @@
*/
__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
DMA_CNDTR_NDT, NbData);
}
@@ -1041,9 +1022,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
DMA_CNDTR_NDT));
}
@@ -1075,19 +1055,19 @@
__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
uint32_t DstAddress, uint32_t Direction)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
+ uint32_t dma_base_addr = (uint32_t)DMAx;
/* Direction Memory to Periph */
if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, DstAddress);
}
/* Direction Periph to Memory and Memory to Memory */
else
{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, DstAddress);
}
}
@@ -1112,9 +1092,8 @@
*/
__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
}
/**
@@ -1138,9 +1117,8 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, PeriphAddress);
}
/**
@@ -1162,9 +1140,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
}
/**
@@ -1186,9 +1163,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
}
/**
@@ -1212,9 +1188,8 @@
*/
__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, MemoryAddress);
}
/**
@@ -1238,9 +1213,8 @@
*/
__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
}
/**
@@ -1262,9 +1236,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
}
/**
@@ -1286,9 +1259,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
}
/**
@@ -1313,6 +1285,7 @@
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param PeriphRequest This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
@@ -1433,9 +1406,8 @@
*/
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
{
- UNUSED(DMAx);
- MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Channel - 1U))))->CCR,
- DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
+ uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
}
/**
@@ -1459,6 +1431,7 @@
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
@@ -1578,9 +1551,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
{
- UNUSED(DMAx);
- return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE *
- (Channel - 1U)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
+ uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
+ return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
}
/**
@@ -2352,9 +2324,8 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
}
/**
@@ -2375,9 +2346,8 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
}
/**
@@ -2398,9 +2368,8 @@
*/
__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
}
/**
@@ -2421,9 +2390,8 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
}
/**
@@ -2444,9 +2412,8 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
}
/**
@@ -2467,9 +2434,8 @@
*/
__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
}
/**
@@ -2490,9 +2456,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
}
@@ -2514,9 +2479,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
}
@@ -2538,9 +2502,8 @@
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAx;
-
- return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ uint32_t dma_base_addr = (uint32_t)DMAx;
+ return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
}
diff --git a/Inc/stm32g4xx_ll_dmamux.h b/Inc/stm32g4xx_ll_dmamux.h
index 8542f5b..9cc4548 100644
--- a/Inc/stm32g4xx_ll_dmamux.h
+++ b/Inc/stm32g4xx_ll_dmamux.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -274,8 +274,8 @@
#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 4 */
#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 5 */
#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 6 */
-#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX Channel 13 connected to DMA2 Channel 7 */
-#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX Channel 13 connected to DMA2 Channel 8 */
+#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX Channel 14 connected to DMA2 Channel 7 */
+#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX Channel 15 connected to DMA2 Channel 8 */
/**
* @}
*/
@@ -436,6 +436,7 @@
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @param Request This parameter can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
@@ -556,15 +557,13 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_DMAREQ_ID, Request);
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
}
/**
* @brief Get DMAMUX request ID for DMAMUX Channel x.
- * @note DMAMUX channel 1 to 7 are mapped to DMA1 channel 1 to 8.
+ * @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
* DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
* @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
* @param DMAMUXx DMAMUXx Instance
@@ -587,6 +586,8 @@
* @arg @ref LL_DMAMUX_CHANNEL_15
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMAMUX_REQ_MEM2MEM
+ * @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
@@ -706,10 +707,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel - 1U)))))->CCR,
- DMAMUX_CxCR_DMAREQ_ID));
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
}
/**
@@ -738,10 +737,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_NBREQ, RequestNb - 1U);
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
}
/**
@@ -769,10 +766,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_NBREQ) + 1U);
+ (void)(DMAMUXx);
+ return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
}
/**
@@ -805,10 +800,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_SPOL, Polarity);
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
}
/**
@@ -840,10 +833,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_SPOL));
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
}
/**
@@ -871,9 +862,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_EGE);
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
}
/**
@@ -901,10 +891,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_EGE);
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
}
/**
@@ -932,10 +920,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
+ (void)(DMAMUXx);
+ return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL);
}
/**
@@ -963,9 +949,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE);
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
}
/**
@@ -993,9 +978,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SE);
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
}
/**
@@ -1023,10 +1007,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- return ((READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
+ (void)(DMAMUXx);
+ return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL);
}
/**
@@ -1076,10 +1058,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- MODIFY_REG(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_SYNC_ID, SyncID);
+ (void)(DMAMUXx);
+ MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
}
/**
@@ -1128,10 +1108,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_SYNC_ID));
+ (void)(DMAMUXx);
+ return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
}
/**
@@ -1147,9 +1125,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- UNUSED(DMAMUXx);
- SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
- (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
+ (void)(DMAMUXx);
+ SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
}
/**
@@ -1165,9 +1142,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- UNUSED(DMAMUXx);
- CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
- (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
+ (void)(DMAMUXx);
+ CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
}
/**
@@ -1183,9 +1159,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
- UNUSED(DMAMUXx);
- return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
- (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
+ (void)(DMAMUXx);
+ return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL);
}
/**
@@ -1890,9 +1865,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
+ (void)(DMAMUXx);
+ SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
}
/**
@@ -1920,10 +1894,8 @@
*/
__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_SOIE);
+ (void)(DMAMUXx);
+ CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
}
/**
@@ -1951,10 +1923,8 @@
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
- register uint32_t dma_base_addr = (uint32_t)DMAMUXx;
-
- return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dma_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR,
- DMAMUX_CxCR_SOIE));
+ (void)(DMAMUXx);
+ return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL);
}
/**
diff --git a/Inc/stm32g4xx_ll_exti.h b/Inc/stm32g4xx_ll_exti.h
index 65fb810..4a9b27d 100644
--- a/Inc/stm32g4xx_ll_exti.h
+++ b/Inc/stm32g4xx_ll_exti.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_fmac.h b/Inc/stm32g4xx_ll_fmac.h
index 993f7c1..b3f3371 100644
--- a/Inc/stm32g4xx_ll_fmac.h
+++ b/Inc/stm32g4xx_ll_fmac.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_fmc.h b/Inc/stm32g4xx_ll_fmc.h
index 6fb8007..8d97426 100644
--- a/Inc/stm32g4xx_ll_fmc.h
+++ b/Inc/stm32g4xx_ll_fmc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_gpio.h b/Inc/stm32g4xx_ll_gpio.h
index 32e7a8f..e241e32 100644
--- a/Inc/stm32g4xx_ll_gpio.h
+++ b/Inc/stm32g4xx_ll_gpio.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_hrtim.h b/Inc/stm32g4xx_ll_hrtim.h
index cbd291d..9865f1e 100644
--- a/Inc/stm32g4xx_ll_hrtim.h
+++ b/Inc/stm32g4xx_ll_hrtim.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -470,16 +470,6 @@
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
- * @{
- */
-/* TO BE COMPLETED */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
* @{
diff --git a/Inc/stm32g4xx_ll_i2c.h b/Inc/stm32g4xx_ll_i2c.h
index 7a67eb4..8000eb6 100644
--- a/Inc/stm32g4xx_ll_i2c.h
+++ b/Inc/stm32g4xx_ll_i2c.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_iwdg.h b/Inc/stm32g4xx_ll_iwdg.h
index 853f4b3..40f4ab8 100644
--- a/Inc/stm32g4xx_ll_iwdg.h
+++ b/Inc/stm32g4xx_ll_iwdg.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_lptim.h b/Inc/stm32g4xx_ll_lptim.h
index b49a6ca..7874903 100644
--- a/Inc/stm32g4xx_ll_lptim.h
+++ b/Inc/stm32g4xx_ll_lptim.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_lpuart.h b/Inc/stm32g4xx_ll_lpuart.h
index e1e12f4..54d496f 100644
--- a/Inc/stm32g4xx_ll_lpuart.h
+++ b/Inc/stm32g4xx_ll_lpuart.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_opamp.h b/Inc/stm32g4xx_ll_opamp.h
index f36e1c9..c938df4 100644
--- a/Inc/stm32g4xx_ll_opamp.h
+++ b/Inc/stm32g4xx_ll_opamp.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -73,7 +73,7 @@
* @retval Register address
*/
#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2))))
+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2))))
diff --git a/Inc/stm32g4xx_ll_pwr.h b/Inc/stm32g4xx_ll_pwr.h
index 4224b5c..5133b0c 100644
--- a/Inc/stm32g4xx_ll_pwr.h
+++ b/Inc/stm32g4xx_ll_pwr.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1087,7 +1087,7 @@
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
- SET_BIT(*((uint32_t *)GPIO), GPIONumber);
+ SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
@@ -1130,7 +1130,7 @@
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
- CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber);
+ CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
@@ -1173,10 +1173,7 @@
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
- uint32_t temp;
- temp = READ_BIT(*((uint32_t *)(GPIO)), GPIONumber);
-
- return ((temp == (GPIONumber))?1U:0U);
+ return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
/**
@@ -1219,8 +1216,7 @@
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
- register uint32_t temp = (uint32_t)(GPIO) + 4U;
- SET_BIT(*((uint32_t *)(temp)), GPIONumber);
+ SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
}
/**
@@ -1263,8 +1259,7 @@
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
- register uint32_t temp = (uint32_t)(GPIO) + 4U;
- CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber);
+ CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
}
/**
@@ -1307,12 +1302,7 @@
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
- register uint32_t temp_reg = (uint32_t)(GPIO) + 4U;
- uint32_t temp;
- temp = READ_BIT(*((uint32_t *)(temp_reg)), GPIONumber);
-
- return ((temp == (GPIONumber))?1U:0U);
-
+ return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
/**
diff --git a/Inc/stm32g4xx_ll_rcc.h b/Inc/stm32g4xx_ll_rcc.h
index ce741d8..4b1c86e 100644
--- a/Inc/stm32g4xx_ll_rcc.h
+++ b/Inc/stm32g4xx_ll_rcc.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_rng.h b/Inc/stm32g4xx_ll_rng.h
index 0a5f636..5880af5 100644
--- a/Inc/stm32g4xx_ll_rng.h
+++ b/Inc/stm32g4xx_ll_rng.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_rtc.h b/Inc/stm32g4xx_ll_rtc.h
index 2a0e728..3a52e9b 100644
--- a/Inc/stm32g4xx_ll_rtc.h
+++ b/Inc/stm32g4xx_ll_rtc.h
@@ -325,8 +325,8 @@
/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
* @{
*/
-#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM is open-drain output */
-#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is push-pull output */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */
/**
* @}
*/
@@ -1475,8 +1475,7 @@
*/
__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
{
- register uint32_t tmp = (ShiftSecond | Fraction);
- WRITE_REG(RTCx->SHIFTR, tmp);
+ WRITE_REG(RTCx->SHIFTR, (ShiftSecond | Fraction));
}
/**
@@ -3181,7 +3180,7 @@
*/
__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
- register uint32_t tmp;
+ register uint32_t tmp = 0U;
UNUSED(RTCx);
@@ -3206,7 +3205,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
- register uint32_t tmp;
+ register uint32_t tmp = 0U;
UNUSED(RTCx);
diff --git a/Inc/stm32g4xx_ll_spi.h b/Inc/stm32g4xx_ll_spi.h
index 42f8d96..159aba1 100644
--- a/Inc/stm32g4xx_ll_spi.h
+++ b/Inc/stm32g4xx_ll_spi.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_system.h b/Inc/stm32g4xx_ll_system.h
index 09223a3..2f3202c 100644
--- a/Inc/stm32g4xx_ll_system.h
+++ b/Inc/stm32g4xx_ll_system.h
@@ -19,7 +19,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_tim.h b/Inc/stm32g4xx_ll_tim.h
index 1d06434..89b84cd 100644
--- a/Inc/stm32g4xx_ll_tim.h
+++ b/Inc/stm32g4xx_ll_tim.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -2101,7 +2101,7 @@
/**
* @brief Set the timer counter counting mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
@@ -2125,7 +2125,7 @@
/**
* @brief Get actual counter mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
@@ -2178,7 +2178,7 @@
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
@@ -2196,7 +2196,7 @@
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
@@ -2213,7 +2213,7 @@
/**
* @brief Set the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the Counter value interpretation
* @rmtoll CNT CNT LL_TIM_SetCounter
@@ -2228,7 +2228,7 @@
/**
* @brief Get the counter value.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the Counter value interpretation
* @rmtoll CNT CNT LL_TIM_GetCounter
@@ -2283,7 +2283,7 @@
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload parameter.
@@ -2300,7 +2300,7 @@
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the returned value interpretation
* @param TIMx Timer instance
@@ -2314,7 +2314,7 @@
/**
* @brief Set the repetition counter value.
* @note For advanced timer instances RepetitionCounter can be up to 65535.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
@@ -2328,7 +2328,7 @@
/**
* @brief Get the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
@@ -2390,7 +2390,7 @@
/**
* @brief Indicates whether dithering is activated.
- * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
* @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
* @param TIMx Timer instance
@@ -2413,7 +2413,7 @@
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
@@ -2426,7 +2426,7 @@
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
@@ -2439,7 +2439,7 @@
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
@@ -2483,7 +2483,7 @@
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
@@ -2799,7 +2799,7 @@
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
- * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
@@ -3027,7 +3027,7 @@
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
@@ -3054,7 +3054,7 @@
/**
* @brief Disable clearing the output channel on an external event.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
@@ -3083,7 +3083,7 @@
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
@@ -3111,7 +3111,7 @@
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
@@ -3127,9 +3127,9 @@
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
@@ -3145,9 +3145,9 @@
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
@@ -3163,9 +3163,9 @@
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
@@ -3181,9 +3181,9 @@
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
@@ -3198,7 +3198,7 @@
/**
* @brief Set compare value for output channel 5 (TIMx_CCR5).
- * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
@@ -3213,7 +3213,7 @@
/**
* @brief Set compare value for output channel 6 (TIMx_CCR6).
- * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
@@ -3229,9 +3229,9 @@
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
@@ -3246,9 +3246,9 @@
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
@@ -3263,9 +3263,9 @@
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
@@ -3280,9 +3280,9 @@
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
@@ -3296,7 +3296,7 @@
/**
* @brief Get compare value (TIMx_CCR5) set for output channel 5.
- * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
@@ -3310,7 +3310,7 @@
/**
* @brief Get compare value (TIMx_CCR6) set for output channel 6.
- * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
@@ -3324,7 +3324,7 @@
/**
* @brief Select on which reference signal the OC5REF is combined to.
- * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the combined 3-phase PWM mode.
* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
@@ -3344,7 +3344,7 @@
/**
* @brief Set the pulse on compare pulse width prescaler.
- * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
@@ -3367,7 +3367,7 @@
/**
* @brief Get the pulse on compare pulse width prescaler.
- * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
@@ -3389,7 +3389,7 @@
/**
* @brief Set the pulse on compare pulse width duration.
- * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
@@ -3404,7 +3404,7 @@
/**
* @brief Get the pulse on compare pulse width duration.
- * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
@@ -3702,7 +3702,7 @@
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
@@ -3715,7 +3715,7 @@
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
@@ -3728,7 +3728,7 @@
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
@@ -3742,9 +3742,9 @@
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
@@ -3759,9 +3759,9 @@
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
@@ -3776,9 +3776,9 @@
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
@@ -3793,9 +3793,9 @@
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
- * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
@@ -3817,7 +3817,7 @@
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
@@ -3830,7 +3830,7 @@
/**
* @brief Disable external clock mode 2.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
@@ -3843,7 +3843,7 @@
/**
* @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
@@ -3860,9 +3860,9 @@
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
@@ -3880,7 +3880,7 @@
/**
* @brief Set the encoder interface mode.
- * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
@@ -3910,7 +3910,7 @@
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
@@ -3933,7 +3933,7 @@
/**
* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
- * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can be used for ADC synchronization.
* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
* @param TIMx Timer Instance
@@ -3963,7 +3963,7 @@
/**
* @brief Set the synchronization mode of a slave timer.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
@@ -3983,7 +3983,7 @@
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
@@ -4013,7 +4013,7 @@
/**
* @brief Enable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
@@ -4026,7 +4026,7 @@
/**
* @brief Disable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
@@ -4039,7 +4039,7 @@
/**
* @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
@@ -4052,7 +4052,7 @@
/**
* @brief Configure the external trigger (ETR) input.
- * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
@@ -4093,7 +4093,7 @@
/**
* @brief Select the external trigger (ETR) input source.
- * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+ * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports ETR source selection.
* @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
* @param TIMx Timer instance
@@ -4221,7 +4221,7 @@
/**
* @brief Enable SMS preload.
- * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
* @param TIMx Timer instance
@@ -4234,7 +4234,7 @@
/**
* @brief Disable SMS preload.
- * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
* @param TIMx Timer instance
@@ -4247,7 +4247,7 @@
/**
* @brief Indicate whether SMS preload is enabled.
- * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
* @param TIMx Timer instance
@@ -4260,7 +4260,7 @@
/**
* @brief Set the preload source of SMS.
- * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
* @param TIMx Timer instance
@@ -4276,7 +4276,7 @@
/**
* @brief Get the preload source of SMS.
- * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+ * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
* @param TIMx Timer instance
@@ -4298,7 +4298,7 @@
*/
/**
* @brief Enable the break function.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
@@ -4313,7 +4313,7 @@
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
@@ -4324,10 +4324,10 @@
/**
* @brief Configure the break input.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @note Bidirectional mode is only supported by advanced timer instances.
- * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
* a timer instance is an advanced-control timer.
* @note In bidirectional mode (BKBID bit set), the Break input is configured both
* in input mode and in open drain output mode. Any active Break event will
@@ -4399,7 +4399,7 @@
/**
* @brief Enable the break 2 function.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
* @param TIMx Timer instance
@@ -4412,7 +4412,7 @@
/**
* @brief Disable the break 2 function.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
* @param TIMx Timer instance
@@ -4425,10 +4425,10 @@
/**
* @brief Configure the break 2 input.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @note Bidirectional mode is only supported by advanced timer instances.
- * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+ * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
* a timer instance is an advanced-control timer.
* @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
* in input mode and in open drain output mode. Any active Break event will
@@ -4500,7 +4500,7 @@
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
@@ -4520,7 +4520,7 @@
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
@@ -4533,7 +4533,7 @@
/**
* @brief Disable automatic output (MOE can be set only by software).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
@@ -4546,7 +4546,7 @@
/**
* @brief Indicate whether automatic output is enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
@@ -4561,7 +4561,7 @@
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
@@ -4576,7 +4576,7 @@
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
@@ -4589,7 +4589,7 @@
/**
* @brief Indicates whether outputs are enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
@@ -4602,7 +4602,7 @@
/**
* @brief Enable the signals connected to the designated timer break input.
- * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
@@ -4645,7 +4645,7 @@
/**
* @brief Disable the signals connected to the designated timer break input.
- * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
@@ -4688,7 +4688,7 @@
/**
* @brief Set the polarity of the break signal for the timer break input.
- * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
@@ -4749,7 +4749,7 @@
/**
* @brief Indicates whether asymmetrical deadtime is activated.
- * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides asymmetrical deadtime.
* @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
* @param TIMx Timer instance
@@ -4762,7 +4762,7 @@
/**
* @brief Set the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
- * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* asymmetrical dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
@@ -4779,7 +4779,7 @@
/**
* @brief Get the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
- * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* asymmetrical dead-time insertion feature is supported by a timer instance.
* @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
* (LOCK bits in TIMx_BDTR register).
@@ -4820,7 +4820,7 @@
/**
* @brief Indicates whether deadtime preload is activated.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides deadtime preload.
* @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
* @param TIMx Timer instance
@@ -4840,7 +4840,7 @@
*/
/**
* @brief Configures the timer DMA burst feature.
- * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
@@ -4917,7 +4917,7 @@
/**
* @brief Enable encoder index.
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_EnableEncoderIndex
* @param TIMx Timer instance
@@ -4930,7 +4930,7 @@
/**
* @brief Disable encoder index.
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_DisableEncoderIndex
* @param TIMx Timer instance
@@ -4943,7 +4943,7 @@
/**
* @brief Indicate whether encoder index is enabled.
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
* @param TIMx Timer instance
@@ -4956,7 +4956,7 @@
/**
* @brief Set index direction
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_SetIndexDirection
* @param TIMx Timer instance
@@ -4973,7 +4973,7 @@
/**
* @brief Get actual index direction
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_GetIndexDirection
* @param TIMx Timer instance
@@ -4989,7 +4989,7 @@
/**
* @brief Enable first index.
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
* @param TIMx Timer instance
@@ -5002,7 +5002,7 @@
/**
* @brief Disable first index.
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
* @param TIMx Timer instance
@@ -5015,7 +5015,7 @@
/**
* @brief Indicates whether first index is enabled.
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
* @param TIMx Timer instance
@@ -5028,7 +5028,7 @@
/**
* @brief Set index positionning
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
* @param TIMx Timer instance
@@ -5048,7 +5048,7 @@
/**
* @brief Get actual index positionning
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
* @param TIMx Timer instance
@@ -5067,7 +5067,7 @@
/**
* @brief Configure encoder index.
- * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
* ECR FIDX LL_TIM_ConfigIDX\n
@@ -5093,7 +5093,7 @@
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
- * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
@@ -5352,7 +5352,7 @@
* @brief Set the OCREF clear input source
* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
* @note This function can only be used in Output compare and PWM modes.
- * @note Macro @ref IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
+ * @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can configure OCREF clear input source.
* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
* @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
@@ -5737,7 +5737,7 @@
/**
* @brief Clear the transition error interrupt flag (TERRF).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
* @param TIMx Timer instance
@@ -5750,7 +5750,7 @@
/**
* @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
* @param TIMx Timer instance
@@ -5763,7 +5763,7 @@
/**
* @brief Clear the index error interrupt flag (IERRF).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
* @param TIMx Timer instance
@@ -5776,7 +5776,7 @@
/**
* @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
* @param TIMx Timer instance
@@ -6111,7 +6111,7 @@
/**
* @brief Enable transition error interrupt (TERRIE).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
* @param TIMx Timer instance
@@ -6124,7 +6124,7 @@
/**
* @brief Disable transition error interrupt (TERRIE).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
* @param TIMx Timer instance
@@ -6137,7 +6137,7 @@
/**
* @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
* @param TIMx Timer instance
@@ -6150,7 +6150,7 @@
/**
* @brief Enable index error interrupt (IERRIE).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
* @param TIMx Timer instance
@@ -6163,7 +6163,7 @@
/**
* @brief Disable index error interrupt (IERRIE).
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
* @param TIMx Timer instance
@@ -6176,7 +6176,7 @@
/**
* @brief Indicates whether the index error interrupt (IERRIE) is enabled.
- * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
* @param TIMx Timer instance
diff --git a/Inc/stm32g4xx_ll_ucpd.h b/Inc/stm32g4xx_ll_ucpd.h
index 7c5eecc..dfeddc2 100644
--- a/Inc/stm32g4xx_ll_ucpd.h
+++ b/Inc/stm32g4xx_ll_ucpd.h
@@ -53,24 +53,24 @@
*/
typedef struct
{
- uint32_t psc_ucpdclk; /*!< Specifies the prescaler for the ucpd clock.
+ uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock.
This parameter can be a value of @ref UCPD_LL_EC_PSC.
- This feature can be modified afterwards using unitary function @ref LL_UCPD_SetPSCClk().*/
+ This feature can be modified afterwards using unitary function @ref LL_UCPD_SetPSCClk(). */
- uint32_t transwin; /*!< Specifies the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal
- tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us).
+ uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal
+ tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us)
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
- This value can be modified afterwards using unitary function @ref LL_UCPD_SetTransWin().*/
+ This value can be modified afterwards using unitary function @ref LL_UCPD_SetTransWin(). */
- uint32_t IfrGap; /*!< Specifies the definition of the clock divider (minus 1) in order to generate tInterframeGap
+ uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate tInterframeGap
from the peripheral clock.
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
- This feature can be modified afterwards using unitary function @ref LL_UCPD_SetIfrGap().*/
+ This feature can be modified afterwards using unitary function @ref LL_UCPD_SetIfrGap(). */
- uint32_t HbitClockDiv; /*!< Specifies the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3
+ uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3
for a bit clock that takes 8 cycles of the peripheral clock "UCPD1_CLK"..
This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
- This feature can be modified afterwards using unitary function @ref LL_UCPD_SetHbitClockDiv().*/
+ This feature can be modified afterwards using unitary function @ref LL_UCPD_SetHbitClockDiv(). */
} LL_UCPD_InitTypeDef;
@@ -88,24 +88,24 @@
* @brief Flags defines which can be used with LL_ucpd_ReadReg function
* @{
*/
-#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
-#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
-#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
-#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
-#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
-#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
-#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
-#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
-#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
-#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
-#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
-#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
-#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
-#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
-#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
-#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!<Status of DC level on CC1 pin */
-#define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 /*!<Status of DC level on CC2 pin */
-#define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT /*!<Fast Role Swap detection event */
+#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
+#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
+#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
+#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
+#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
+#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
+#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
+#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
+#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
+#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
+#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
+#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
+#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
+#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
+#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
+#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!<Status of DC level on CC1 pin */
+#define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 /*!<Status of DC level on CC2 pin */
+#define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT /*!<Fast Role Swap detection event */
/**
* @}
@@ -115,44 +115,44 @@
* @brief IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions
* @{
*/
-#define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE /*!< Enable transmit interrupt status */
-#define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE /*!< Enable transmit message discarded interrupt */
-#define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE /*!< Enable transmit message sent interrupt */
-#define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE /*!< Enable transmit message abort interrupt */
-#define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE /*!< Enable HRST discarded interrupt */
-#define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE /*!< Enable HRST sent interrupt */
-#define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE /*!< Enable tx data underrun condition interrupt */
-#define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE /*!< Enable Receive data register not empty interrupt */
-#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
-#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
-#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
-#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGEND /*!< Enable Rx message received */
-#define LL_UCPD_IMR_RXERR UCPD_IMR_RXMSGENDIE /*!< Enable Rx error */
-#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
-#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
-#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
+#define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE /*!< Enable transmit interrupt status */
+#define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE /*!< Enable transmit message discarded interrupt */
+#define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE /*!< Enable transmit message sent interrupt */
+#define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE /*!< Enable transmit message abort interrupt */
+#define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE /*!< Enable HRST discarded interrupt */
+#define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE /*!< Enable HRST sent interrupt */
+#define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE /*!< Enable tx data underrun condition interrupt */
+#define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE /*!< Enable Receive data register not empty interrupt */
+#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
+#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
+#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
+#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGEND /*!< Enable Rx message received */
+#define LL_UCPD_IMR_RXERR UCPD_IMR_RXMSGENDIE /*!< Enable Rx error */
+#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
+#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
+#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_ORDERSET orderset value
- * @brief definition of the usual orderset
+/** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
+ * @brief definition of the usual Ordered sets
* @{
*/
-#define LL_UCPD_SYNC1 0x18u
-#define LL_UCPD_SYNC2 0x11u
-#define LL_UCPD_SYNC3 0x06u
-#define LL_UCPD_RST1 0x07u
-#define LL_UCPD_RST2 0x19u
-#define LL_UCPD_EOP 0x0Du
+#define LL_UCPD_SYNC1 0x18u /*!< K-code for Startsynch #1 */
+#define LL_UCPD_SYNC2 0x11u /*!< K-code for Startsynch #2 */
+#define LL_UCPD_SYNC3 0x06u /*!< K-code for Startsynch #3 */
+#define LL_UCPD_RST1 0x07u /*!< K-code for Hard Reset #1 */
+#define LL_UCPD_RST2 0x19u /*!< K-code for Hard Reset #2 */
+#define LL_UCPD_EOP 0x0Du /*!< K-code for EOP End of Packet */
-#define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))
-#define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))
-#define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))
-#define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))
-#define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))
-#define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))
-#define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))
+#define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding */
+#define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding */
+#define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding */
+#define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding */
+#define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
+#define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding */
+#define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
/**
* @}
*/
@@ -160,59 +160,59 @@
/** @defgroup UCPD_LL_EC_MODE Role Mode
* @{
*/
-#define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE /*!< Mode SNK Rd */
-#define LL_UCPD_ROLE_SRC 0x0U
+#define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE /*!< Mode SNK Rd */
+#define LL_UCPD_ROLE_SRC 0x0U /*!< Mode SRC Rp */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_RESISTOR resistor value
+/** @defgroup UCPD_LL_EC_RESISTOR Resistor value
* @{
*/
-#define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 /*!< Rp default */
-#define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 /*!< Rp 1.5 A */
-#define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE /*!< Rp 3.0 A */
-#define LL_UCPD_RESISTOR_NONE 0x0U /*!< No resistor */
+#define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 /*!< Rp default */
+#define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 /*!< Rp 1.5 A */
+#define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE /*!< Rp 3.0 A */
+#define LL_UCPD_RESISTOR_NONE 0x0U /*!< No resistor */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_CFG1_ORDERSET orderset configuration
+/** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
* @{
*/
-#define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0
-#define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1
-#define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2
-#define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3
-#define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4
-#define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5
-#define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6
-#define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7
-#define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8
+#define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0 /*!< SOP Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1 /*!< SOP' Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2 /*!< SOP'' Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3 /*!< Hard Reset Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4 /*!< Cable Reset Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5 /*!< SOP' Debug Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6 /*!< SOP'' Debug Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7 /*!< SOP extension#1 Ordered set detection enabled */
+#define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8 /*!< SOP extension#2 Ordered set detection enabled */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_CCxEVT ccxevt
+/** @defgroup UCPD_LL_EC_CCxEVT CCx event
* @{
*/
-#define LL_UCPD_SNK_CC1_VOPEN 0x00u
-#define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0
-#define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1
-#define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)
+#define LL_UCPD_SNK_CC1_VOPEN 0x00u /*!< CC1 Sink Open state */
+#define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Sink vRP default state */
+#define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Sink vRP 1.5A state */
+#define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1) /*!< CC1 Sink vRP 3.0A state */
-#define LL_UCPD_SNK_CC2_VOPEN 0x00u
-#define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0
-#define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1
-#define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)
+#define LL_UCPD_SNK_CC2_VOPEN 0x00u /*!< CC2 Sink Open state */
+#define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Sink vRP default state */
+#define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Sink vRP 1.5A state */
+#define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1) /*!< CC2 Sink vRP 3.0A state */
-#define LL_UCPD_SRC_CC1_VRA 0x0U
-#define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0
-#define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1
+#define LL_UCPD_SRC_CC1_VRA 0x0U /*!< CC1 Source vRA state */
+#define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Source vRD state */
+#define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Source Open state */
-#define LL_UCPD_SRC_CC2_VRA 0x0U
-#define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0
-#define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1
+#define LL_UCPD_SRC_CC2_VRA 0x0U /*!< CC2 Source vRA state */
+#define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Source vRD state */
+#define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Source Open state */
/**
* @}
*/
@@ -220,65 +220,65 @@
/** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
* @{
*/
-#define LL_UCPD_PSC_DIV1 0x0u
-#define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0
-#define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1
-#define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)
-#define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2
+#define LL_UCPD_PSC_DIV1 0x0u /*!< Bypass pre-scaling / divide by 1 */
+#define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0 /*!< Pre-scale clock by dividing by 2 */
+#define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1 /*!< Pre-scale clock by dividing by 4 */
+#define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0) /*!< Pre-scale clock by dividing by 8 */
+#define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2 /*!< Pre-scale clock by dividing by 16 */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_CCENABLE cc pin enable
+/** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
* @{
*/
-#define LL_UCPD_CCENABLE_NONE 0x0U
-#define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0
-#define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1
-#define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)
+#define LL_UCPD_CCENABLE_NONE 0x0U /*!< Neither PHY is activated (e.g. disabled state of source) */
+#define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0 /*!< Controls apply to only CC1 */
+#define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1 /*!< Controls apply to only CC1 */
+#define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1) /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_CCPIN cc pin selection
+/** @defgroup UCPD_LL_EC_CCPIN CC pin selection
* @{
*/
-#define LL_UCPD_CCPIN_CC1 0x0U
-#define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL
+#define LL_UCPD_CCPIN_CC1 0x0U /*!< Use CC1 IO for power delivery communication */
+#define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL /*!< Use CC2 IO for power delivery communication */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_RXMODE rx mode
+/** @defgroup UCPD_LL_EC_RXMODE Receiver mode
* @{
*/
-#define LL_UCPD_RXMODE_NORMAL 0x0U
-#define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE
+#define LL_UCPD_RXMODE_NORMAL 0x0U /*!< Normal receive mode */
+#define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE /*!< BIST receive mode (BIST Test Data Mode) */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_TXMODE tx mode
+/** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
* @{
*/
-#define LL_UCPD_TXMODE_NORMAL 0x0U
-#define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0
-#define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1
+#define LL_UCPD_TXMODE_NORMAL 0x0U /*!< Initiate the transfer of a Tx message */
+#define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0 /*!< Trigger a the transfer of a Cable Reset sequence */
+#define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1 /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2) */
/**
* @}
*/
-/** @defgroup UCPD_LL_EC_RXORDSET rx orderset
+/** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
* @{
*/
-#define LL_UCPD_RXORDSET_SOP 0x0U
-#define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0
-#define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1
-#define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)
-#define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2
-#define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)
-#define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)
-#define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)
+#define LL_UCPD_RXORDSET_SOP 0x0U /*!< SOP code detected in receiver */
+#define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0 /*!< SOP' code detected in receiver */
+#define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1 /*!< SOP'' code detected in receiver */
+#define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP' Debug code detected in receiver */
+#define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2 /*!< SOP'' Debug code detected in receiver */
+#define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0) /*!< Cable Reset code detected in receiver */
+#define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP extension#1 code detected in receiver */
+#define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0) /*!< SOP extension#2 code detected in receiver */
/**
* @}
*/
diff --git a/Inc/stm32g4xx_ll_usart.h b/Inc/stm32g4xx_ll_usart.h
index 5abcb74..4f1af73 100644
--- a/Inc/stm32g4xx_ll_usart.h
+++ b/Inc/stm32g4xx_ll_usart.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -64,13 +64,6 @@
*/
/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
- * @{
- */
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
diff --git a/Inc/stm32g4xx_ll_usb.h b/Inc/stm32g4xx_ll_usb.h
index be08dd8..2539da8 100644
--- a/Inc/stm32g4xx_ll_usb.h
+++ b/Inc/stm32g4xx_ll_usb.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -151,6 +151,14 @@
* @}
*/
+/** @defgroup USB_LL Device Speed
+ * @{
+ */
+#define USBD_FS_SPEED 2U
+/**
+ * @}
+ */
+
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
diff --git a/Inc/stm32g4xx_ll_utils.h b/Inc/stm32g4xx_ll_utils.h
index 8b22ab6..f8cd1b9 100644
--- a/Inc/stm32g4xx_ll_utils.h
+++ b/Inc/stm32g4xx_ll_utils.h
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Inc/stm32g4xx_ll_wwdg.h b/Inc/stm32g4xx_ll_wwdg.h
index b97d393..11966b8 100644
--- a/Inc/stm32g4xx_ll_wwdg.h
+++ b/Inc/stm32g4xx_ll_wwdg.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -58,8 +58,8 @@
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
+ * @{
+ */
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
@@ -183,7 +183,7 @@
* @arg @ref LL_WWDG_PRESCALER_32
* @arg @ref LL_WWDG_PRESCALER_64
* @arg @ref LL_WWDG_PRESCALER_128
-* @retval None
+ * @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
diff --git a/README.md b/README.md
index 64423d8..f21006a 100644
--- a/README.md
+++ b/README.md
@@ -35,6 +35,7 @@
HAL Driver G4 | CMSIS Device G4 | CMSIS Core | Was delivered in the full MCU package
------------- | --------------- | ---------- | -------------------------------------
Tag v1.0.0 | Tag v1.0.0 | Tag v5.4.0_cm4 | Tag v1.0.0 (and following, if any, till next new tag)
+Tag v1.1.0 | Tag v1.1.0 | Tag v5.4.0_cm4 | Tag v1.1.0 (and following, if any, till next new tag)
The full **STM32CubeG4** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeG4).
diff --git a/Release_Notes.html b/Release_Notes.html
index 402e392..ca18495 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -11,7 +11,7 @@
span.underline{text-decoration: underline;}
div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
- <link rel="stylesheet" href="../../_htmresc/mini-st.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
@@ -46,11 +46,92 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">V1.0.0 / 12-April-2019</label>
+<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.1.0 / 28-June-2019</label>
<div>
<h2 id="main-changes">Main Changes</h2>
-<h3 id="first-release">First release</h3>
-<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
+<h3 id="maintenance-release">Maintenance Release</h3>
+<p>Maintenance release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
+<h2 id="contents">Contents</h2>
+<table>
+<caption>Additional features and changes :</caption>
+<thead>
+<tr class="header">
+<th style="text-align: left;">Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td style="text-align: left;">General: Support of device STM32G483xx in HAL and LL drivers</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">COMP: Suppress Deglitcher mode - Not supported on STM32G4 series</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">HAL: Change naming of the IRQn 2 to RTC_TAMP_LSECSS_IRQn</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">HRTIM: HRTIM_OUTPUTRESET_TIMAEVx renamed to HRTIM_OUTPUTRESET_TIMEVx</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">TIM: Add new macro to configure fast mode</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">TIM: Master Slave Mode (MSM) is now configurable</td>
+</tr>
+</tbody>
+</table>
+<table>
+<caption>Bugs fix :</caption>
+<thead>
+<tr class="header">
+<th style="text-align: left;">Headline</th>
+</tr>
+</thead>
+<tbody>
+<tr class="odd">
+<td style="text-align: left;">General : redefinition of registers with adjusted address MUST be volatile</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">DMA : DMA2 instance cannot be configured in LL drivers</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">GPIO: HAL_GPIO_DeInit() bug on EXTI management</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">GPIO: Compilation warning with IAR v8.30</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">HAL: Correct potential issue within HAL_SetTickFreq() function</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">HRTIM: HRTIM_TIMxCR.DELCMP isn’t systematically programmed</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">HRTIM: Fault source programming isn’t wrong in HAL_HRTIM_FaultConfig</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">HRTIM : Useless Assignment at function HAL_HRTIM_SimpleOCChannelConfig</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">RCC: Should not overwrite Tick priority</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">RTC: HAL_RTCEx_SetWakeUpTimer WUTWF management reworked to be aligned with Reference Manual</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">RTC: INITF can rise too early when entering init mode just after exiting</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">RTC : fix issue in define with STM32L4 LL RTC month macros</td>
+</tr>
+<tr class="odd">
+<td style="text-align: left;">RTC : Remove ALRBWF and ALRAWF bits</td>
+</tr>
+<tr class="even">
+<td style="text-align: left;">TIM: CodeSonar warnings about useless assignment in HAL_TIMEx_ConfigBreakInput()</td>
+</tr>
+</tbody>
+</table>
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
<ul>
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
@@ -61,6 +142,27 @@
<ul>
<li>STM32G431/41xx</li>
<li>STM32G471xx</li>
+<li>STM32G473/<strong>83xx</strong></li>
+<li>STM32G474/84xx</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 12-April-2019</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<h3 id="first-release">First release</h3>
+<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.</p>
+<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
+<ul>
+<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
+<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
+<li>System Workbench STM32 (SW4STM32) toolchain V2.7.2</li>
+</ul>
+<h2 id="supported-devices-1">Supported Devices</h2>
+<ul>
+<li>STM32G431/41xx</li>
+<li>STM32G471xx</li>
<li>STM32G473xx</li>
<li>STM32G474/84xx</li>
</ul>
diff --git a/Src/stm32g4xx_hal.c b/Src/stm32g4xx_hal.c
index 19beb14..e8a8b2a 100644
--- a/Src/stm32g4xx_hal.c
+++ b/Src/stm32g4xx_hal.c
@@ -21,7 +21,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -52,7 +52,7 @@
* @brief STM32G4xx HAL Driver version number $VERSION$
*/
#define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32G4xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
+#define __STM32G4xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
#define __STM32G4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\
@@ -347,7 +347,7 @@
/**
* @brief Set new tick Freq.
- * @retval Status
+ * @retval status
*/
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
{
@@ -356,10 +356,12 @@
if (uwTickFreq != Freq)
{
- uwTickFreq = Freq;
-
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
+ if (status == HAL_OK)
+ {
+ uwTickFreq = Freq;
+ }
}
return status;
diff --git a/Src/stm32g4xx_hal_adc.c b/Src/stm32g4xx_hal_adc.c
index 1034b5e..191cfc8 100644
--- a/Src/stm32g4xx_hal_adc.c
+++ b/Src/stm32g4xx_hal_adc.c
@@ -290,7 +290,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_adc_ex.c b/Src/stm32g4xx_hal_adc_ex.c
index ec0857b..d2eb690 100644
--- a/Src/stm32g4xx_hal_adc_ex.c
+++ b/Src/stm32g4xx_hal_adc_ex.c
@@ -28,7 +28,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_comp.c b/Src/stm32g4xx_hal_comp.c
index 3700779..b31c0db 100644
--- a/Src/stm32g4xx_hal_comp.c
+++ b/Src/stm32g4xx_hal_comp.c
@@ -57,7 +57,6 @@
(++) Select the hysteresis
(++) Select the blanking source
(++) Select the output polarity
- (++) Select the deglitcher mode
-@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
to enable internal control clock of the comparators.
@@ -144,7 +143,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -253,7 +252,6 @@
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
- assert_param(IS_COMP_DEGLITCHER_MODE(hcomp->Init.DeglitcherMode));
if(hcomp->State == HAL_COMP_STATE_RESET)
{
@@ -296,13 +294,12 @@
| hcomp->Init.BlankingSrce
| hcomp->Init.Hysteresis
| hcomp->Init.OutputPol
- | hcomp->Init.DeglitcherMode
);
/* Set parameters in COMP register */
/* Note: Update all bits except read-only, lock and enable bits */
MODIFY_REG(hcomp->Instance->CSR,
- COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_DEGLITCHEN |
+ COMP_CSR_INMSEL | COMP_CSR_INPSEL |
COMP_CSR_POLARITY | COMP_CSR_HYST |
COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN,
tmp_csr
@@ -333,7 +330,7 @@
/* Configure EXTI rising edge */
if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_EnableRisingTrig_32_63(exti_line);
@@ -348,7 +345,7 @@
}
else
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_DisableRisingTrig_32_63(exti_line);
@@ -365,7 +362,7 @@
/* Configure EXTI falling edge */
if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_EnableFallingTrig_32_63(exti_line);
@@ -380,7 +377,7 @@
}
else
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_DisableFallingTrig_32_63(exti_line);
@@ -395,7 +392,7 @@
}
/* Clear COMP EXTI pending bit (if any) */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_ClearFlag_32_63(exti_line);
@@ -411,7 +408,7 @@
/* Configure EXTI event mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_EnableEvent_32_63(exti_line);
@@ -426,7 +423,7 @@
}
else
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_DisableEvent_32_63(exti_line);
@@ -443,7 +440,7 @@
/* Configure EXTI interrupt mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_EnableIT_32_63(exti_line);
@@ -458,7 +455,7 @@
}
else
{
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_DisableIT_32_63(exti_line);
@@ -475,7 +472,7 @@
else
{
/* Disable EXTI event mode */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_DisableEvent_32_63(exti_line);
@@ -489,7 +486,7 @@
#endif
/* Disable EXTI interrupt mode */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
LL_EXTI_DisableIT_32_63(exti_line);
@@ -883,7 +880,7 @@
uint32_t tmp_comp_exti_flag_set = 0UL;
/* Check COMP EXTI flag */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
{
if(LL_EXTI_IsActiveFlag_32_63(exti_line) != 0UL)
@@ -908,7 +905,7 @@
if(tmp_comp_exti_flag_set != 0UL)
{
/* Clear COMP EXTI line pending bit */
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
if(tmp_comp_exti_flag_set == 2UL)
{
LL_EXTI_ClearFlag_32_63(exti_line);
diff --git a/Src/stm32g4xx_hal_cortex.c b/Src/stm32g4xx_hal_cortex.c
index a80ba5d..00e6108 100644
--- a/Src/stm32g4xx_hal_cortex.c
+++ b/Src/stm32g4xx_hal_cortex.c
@@ -90,7 +90,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_crc.c b/Src/stm32g4xx_hal_crc.c
index e7536a2..f1b1fef 100644
--- a/Src/stm32g4xx_hal_crc.c
+++ b/Src/stm32g4xx_hal_crc.c
@@ -31,7 +31,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_crc_ex.c b/Src/stm32g4xx_hal_crc_ex.c
index 30dfcd9..652e78f 100644
--- a/Src/stm32g4xx_hal_crc_ex.c
+++ b/Src/stm32g4xx_hal_crc_ex.c
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_cryp.c b/Src/stm32g4xx_hal_cryp.c
index eb2ac5b..9eced79 100644
--- a/Src/stm32g4xx_hal_cryp.c
+++ b/Src/stm32g4xx_hal_cryp.c
@@ -248,13 +248,15 @@
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
*** Callback registration ***
- =============================================
+ =============================
+ [..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback.
+ [..]
Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback.
@@ -264,6 +266,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@@ -275,6 +278,7 @@
(+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit.
+ [..]
By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions :
examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
@@ -284,6 +288,7 @@
if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
@@ -292,14 +297,16 @@
using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
or @ref HAL_CRYP_Init() function.
+ [..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
*** Suspend/Resume feature ***
- =============================================
+ ==============================
+ [..]
The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
allows the user to resort to the suspend/resume feature.
A low priority block processing can be suspended to process a high priority block
diff --git a/Src/stm32g4xx_hal_dac.c b/Src/stm32g4xx_hal_dac.c
index f2b5731..377d0b8 100644
--- a/Src/stm32g4xx_hal_dac.c
+++ b/Src/stm32g4xx_hal_dac.c
@@ -134,8 +134,6 @@
& DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
DAC_HoldTime & DAC_RefreshTime;
-
-
*** DAC calibration feature ***
===================================
[..]
@@ -316,8 +314,6 @@
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
-
-
*** DAC HAL driver macros list ***
=============================================
[..]
@@ -335,7 +331,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -376,7 +372,6 @@
*/
/* Private macro -------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions -------------------------------------------------------*/
@@ -593,7 +588,7 @@
if (Channel == DAC_CHANNEL_1)
{
/* Check if software trigger enabled */
- if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1)
+ if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
{
/* Enable the selected DAC software conversion */
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
@@ -602,7 +597,7 @@
else
{
/* Check if software trigger enabled */
- if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2)
+ if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
{
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
@@ -1279,7 +1274,6 @@
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
-
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
@@ -1373,8 +1367,8 @@
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
- * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
- * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
*
* @param pCallback pointer to the Callback function
* @retval status
@@ -1422,10 +1416,10 @@
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = pCallback;
break;
- case HAL_DAC_MSP_INIT_CB_ID :
+ case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
- case HAL_DAC_MSP_DEINIT_CB_ID :
+ case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
@@ -1440,10 +1434,10 @@
{
switch (CallbackID)
{
- case HAL_DAC_MSP_INIT_CB_ID :
+ case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = pCallback;
break;
- case HAL_DAC_MSP_DEINIT_CB_ID :
+ case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = pCallback;
break;
default :
@@ -1481,8 +1475,8 @@
* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
* @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
* @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
- * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID
- * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID
+ * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
+ * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
* @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
* @retval status
*/
@@ -1521,10 +1515,10 @@
case HAL_DAC_CH2_UNDERRUN_CB_ID :
hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
break;
- case HAL_DAC_MSP_INIT_CB_ID :
+ case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
- case HAL_DAC_MSP_DEINIT_CB_ID :
+ case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
case HAL_DAC_ALL_CB_ID :
@@ -1551,10 +1545,10 @@
{
switch (CallbackID)
{
- case HAL_DAC_MSP_INIT_CB_ID :
+ case HAL_DAC_MSPINIT_CB_ID :
hdac->MspInitCallback = HAL_DAC_MspInit;
break;
- case HAL_DAC_MSP_DEINIT_CB_ID :
+ case HAL_DAC_MSPDEINIT_CB_ID :
hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
break;
default :
diff --git a/Src/stm32g4xx_hal_dac_ex.c b/Src/stm32g4xx_hal_dac_ex.c
index 46d1827..b767265 100644
--- a/Src/stm32g4xx_hal_dac_ex.c
+++ b/Src/stm32g4xx_hal_dac_ex.c
@@ -37,6 +37,7 @@
===================================
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
(+) Use HAL_DACEx_SawtoothWaveGenerate() to generate sawtooth signal.
(+) Use HAL_DACEx_SawtoothWaveDataReset() to reset sawtooth wave.
(+) Use HAL_DACEx_SawtoothWaveDataStep() to step sawtooth wave.
@@ -51,7 +52,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_dma.c b/Src/stm32g4xx_hal_dma.c
index 5bdbad4..94937e6 100644
--- a/Src/stm32g4xx_hal_dma.c
+++ b/Src/stm32g4xx_hal_dma.c
@@ -75,7 +75,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1057,7 +1057,7 @@
else
{
/* DMA2 */
-#if defined (STM32G474xx) || defined (STM32G473xx) || defined (STM32G471xx) || defined (STM32G484xx)
+#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx)
DMAMUX1_ChannelBase = DMAMUX1_Channel8;
#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
DMAMUX1_ChannelBase = DMAMUX1_Channel6;
diff --git a/Src/stm32g4xx_hal_dma_ex.c b/Src/stm32g4xx_hal_dma_ex.c
index 4a9f149..7a7ea70 100644
--- a/Src/stm32g4xx_hal_dma_ex.c
+++ b/Src/stm32g4xx_hal_dma_ex.c
@@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_exti.c b/Src/stm32g4xx_hal_exti.c
index 0ef77dc..74fa603 100644
--- a/Src/stm32g4xx_hal_exti.c
+++ b/Src/stm32g4xx_hal_exti.c
@@ -73,7 +73,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_fdcan.c b/Src/stm32g4xx_hal_fdcan.c
index 30ace9e..d4350b4 100644
--- a/Src/stm32g4xx_hal_fdcan.c
+++ b/Src/stm32g4xx_hal_fdcan.c
@@ -154,7 +154,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_flash.c b/Src/stm32g4xx_hal_flash.c
index eb088c0..9b797ca 100644
--- a/Src/stm32g4xx_hal_flash.c
+++ b/Src/stm32g4xx_hal_flash.c
@@ -75,7 +75,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
diff --git a/Src/stm32g4xx_hal_flash_ex.c b/Src/stm32g4xx_hal_flash_ex.c
index 90dbcde..651da1c 100644
--- a/Src/stm32g4xx_hal_flash_ex.c
+++ b/Src/stm32g4xx_hal_flash_ex.c
@@ -58,7 +58,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
diff --git a/Src/stm32g4xx_hal_flash_ramfunc.c b/Src/stm32g4xx_hal_flash_ramfunc.c
index fe221ad..2e177aa 100644
--- a/Src/stm32g4xx_hal_flash_ramfunc.c
+++ b/Src/stm32g4xx_hal_flash_ramfunc.c
@@ -36,7 +36,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
diff --git a/Src/stm32g4xx_hal_fmac.c b/Src/stm32g4xx_hal_fmac.c
index 9367ce1..f5816bb 100644
--- a/Src/stm32g4xx_hal_fmac.c
+++ b/Src/stm32g4xx_hal_fmac.c
@@ -1,6 +1,6 @@
/**
******************************************************************************
- * @file stm32g4xx_fmac.c
+ * @file stm32g4xx_hal_fmac.c
* @author MCD Application Team
* @brief FMAC HAL module driver.
* This file provides firmware functions to manage the following
@@ -187,7 +187,7 @@
or @ref HAL_FMAC_Init() function.
[..]
- When The compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
+ When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
and weak (surcharged) callbacks are used.
@@ -197,7 +197,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_gpio.c b/Src/stm32g4xx_hal_gpio.c
index 0317f70..3a8dfd3 100644
--- a/Src/stm32g4xx_hal_gpio.c
+++ b/Src/stm32g4xx_hal_gpio.c
@@ -91,7 +91,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -317,9 +317,6 @@
tmp &= (0x0FUL << (4U * (position & 0x03U)));
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
- tmp = 0x0FUL << (4U * (position & 0x03U));
- SYSCFG->EXTICR[position >> 2U] &= ~tmp;
-
/* Clear EXTI line configuration */
EXTI->IMR1 &= ~(iocurrent);
EXTI->EMR1 &= ~(iocurrent);
@@ -327,6 +324,9 @@
/* Clear Rising Falling edge configuration */
EXTI->RTSR1 &= ~(iocurrent);
EXTI->FTSR1 &= ~(iocurrent);
+
+ tmp = 0x0FUL << (4U * (position & 0x03U));
+ SYSCFG->EXTICR[position >> 2U] &= ~tmp;
}
/*------------------------- GPIO Mode Configuration --------------------*/
diff --git a/Src/stm32g4xx_hal_hrtim.c b/Src/stm32g4xx_hal_hrtim.c
index b8eb527..7aa48e8 100644
--- a/Src/stm32g4xx_hal_hrtim.c
+++ b/Src/stm32g4xx_hal_hrtim.c
@@ -290,6 +290,7 @@
Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
to register an interrupt callback.
+ [..]
Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
(+) Fault1Callback : Fault 1 interrupt callback function
(+) Fault2Callback : Fault 2 interrupt callback function
@@ -305,6 +306,7 @@
(+) MspInitCallback : HRTIM MspInit callback function
(+) MspDeInitCallback : HRTIM MspInit callback function
+ [..]
Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
(+) RegistersUpdateCallback : Timer x Update interrupt callback function
(+) RepetitionEventCallback : Timer x Repetition interrupt callback function
@@ -322,13 +324,16 @@
(+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
(+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
+ [..]
Both functions take as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
to reset a callback to the default weak function. Both functions take as parameters
the HAL peripheral handle and the Callback ID.
+ [..]
By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
Exception done for MspInit and MspDeInit functions that are reset to the legacy
@@ -337,14 +342,16 @@
not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
(user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
- or @ref HAL_HRTIM_Init() function.
+ or HAL_HRTIM_Init() function.
+ [..]
When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all
callbacks are set to the corresponding weak functions.
@@ -354,7 +361,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -5879,9 +5886,14 @@
}
else
{
- /* nothing to do */
+ /* nothing to do */
}
}
+ else
+ {
+ /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
+ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
+ }
break;
}
@@ -5919,9 +5931,14 @@
}
else
{
- /* nothing to do */
+ /* nothing to do */
}
}
+ else
+ {
+ /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
+ MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
+ }
break;
}
diff --git a/Src/stm32g4xx_hal_i2c.c b/Src/stm32g4xx_hal_i2c.c
index 5b4375f..bd3eac9 100644
--- a/Src/stm32g4xx_hal_i2c.c
+++ b/Src/stm32g4xx_hal_i2c.c
@@ -293,7 +293,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_i2c_ex.c b/Src/stm32g4xx_hal_i2c_ex.c
index 0c6d04b..ca37d84 100644
--- a/Src/stm32g4xx_hal_i2c_ex.c
+++ b/Src/stm32g4xx_hal_i2c_ex.c
@@ -35,7 +35,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_i2s.c b/Src/stm32g4xx_hal_i2s.c
index e6c1340..8d497e3 100644
--- a/Src/stm32g4xx_hal_i2s.c
+++ b/Src/stm32g4xx_hal_i2s.c
@@ -115,13 +115,13 @@
Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
Function HAL_I2S_RegisterCallback() allows to register following callbacks:
- (+) TxCpltCallback : I2S Tx Completed callback
- (+) RxCpltCallback : I2S Rx Completed callback
- (+) TxHalfCpltCallback : I2S Tx Half Completed callback
- (+) RxHalfCpltCallback : I2S Rx Half Completed callback
- (+) ErrorCallback : I2S Error callback
- (+) MspInitCallback : I2S Msp Init callback
- (+) MspDeInitCallback : I2S Msp DeInit callback
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
@@ -131,14 +131,15 @@
HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
- (+) TxCpltCallback : I2S Tx Completed callback
- (+) RxCpltCallback : I2S Rx Completed callback
- (+) TxHalfCpltCallback : I2S Tx Half Completed callback
- (+) RxHalfCpltCallback : I2S Rx Half Completed callback
- (+) ErrorCallback : I2S Error callback
- (+) MspInitCallback : I2S Msp Init callback
- (+) MspDeInitCallback : I2S Msp DeInit callback
+ (++) TxCpltCallback : I2S Tx Completed callback
+ (++) RxCpltCallback : I2S Rx Completed callback
+ (++) TxHalfCpltCallback : I2S Tx Half Completed callback
+ (++) RxHalfCpltCallback : I2S Rx Half Completed callback
+ (++) ErrorCallback : I2S Error callback
+ (++) MspInitCallback : I2S Msp Init callback
+ (++) MspDeInitCallback : I2S Msp DeInit callback
+ [..]
By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
@@ -148,6 +149,7 @@
If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
@@ -156,7 +158,8 @@
using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
or HAL_I2S_Init() function.
- When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
+ [..]
+ When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -164,7 +167,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_irda.c b/Src/stm32g4xx_hal_irda.c
index d744795..d1cdaa5 100644
--- a/Src/stm32g4xx_hal_irda.c
+++ b/Src/stm32g4xx_hal_irda.c
@@ -173,7 +173,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -718,6 +718,7 @@
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
+ [..]
(#) There are two modes of transfer:
(++) Blocking mode: the communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
@@ -755,28 +756,28 @@
(++) HAL_IRDA_ErrorCallback()
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_IRDA_Abort()
- (+) HAL_IRDA_AbortTransmit()
- (+) HAL_IRDA_AbortReceive()
- (+) HAL_IRDA_Abort_IT()
- (+) HAL_IRDA_AbortTransmit_IT()
- (+) HAL_IRDA_AbortReceive_IT()
+ (++) HAL_IRDA_Abort()
+ (++) HAL_IRDA_AbortTransmit()
+ (++) HAL_IRDA_AbortReceive()
+ (++) HAL_IRDA_Abort_IT()
+ (++) HAL_IRDA_AbortTransmit_IT()
+ (++) HAL_IRDA_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_IRDA_AbortCpltCallback()
- (+) HAL_IRDA_AbortTransmitCpltCallback()
- (+) HAL_IRDA_AbortReceiveCpltCallback()
+ (++) HAL_IRDA_AbortCpltCallback()
+ (++) HAL_IRDA_AbortTransmitCpltCallback()
+ (++) HAL_IRDA_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -784,10 +785,13 @@
/**
* @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@@ -870,10 +874,13 @@
/**
* @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value.
* @retval HAL status
*/
@@ -958,10 +965,13 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1000,10 +1010,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1049,10 +1062,13 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pData pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -1124,12 +1140,15 @@
/**
* @brief Receive an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must reflect the number
+ * of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -2218,6 +2237,7 @@
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ uint32_t pclk;
/* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@@ -2246,7 +2266,7 @@
MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
/*-------------------------- USART GTPR Configuration ----------------------*/
- MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler);
+ MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource);
@@ -2254,16 +2274,19 @@
switch (clocksource)
{
case IRDA_CLOCKSOURCE_PCLK1:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_PCLK2:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_SYSCLK:
- tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break;
case IRDA_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
diff --git a/Src/stm32g4xx_hal_iwdg.c b/Src/stm32g4xx_hal_iwdg.c
index 76d71a3..38fe72d 100644
--- a/Src/stm32g4xx_hal_iwdg.c
+++ b/Src/stm32g4xx_hal_iwdg.c
@@ -48,19 +48,19 @@
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
- (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
- (+) Enable write access to configuration registers:
+ (++) Enable write access to configuration registers:
IWDG_PR, IWDG_RLR and IWDG_WINR.
- (+) Configure the IWDG prescaler and counter reload value. This reload
+ (++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
- (+) Wait for status flags to be reset.
- (+) Depending on window parameter:
- (++) If Window Init parameter is same as Window register value,
+ (++) Wait for status flags to be reset.
+ (++) Depending on window parameter:
+ (+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
- (++) Else modify Window register. This will automatically reload
+ (+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
@@ -79,7 +79,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -126,8 +126,8 @@
*/
/** @addtogroup IWDG_Exported_Functions_Group1
- * @brief Initialization and Start functions.
- *
+ * @brief Initialization and Start functions.
+ *
@verbatim
===============================================================================
##### Initialization and Start functions #####
@@ -215,8 +215,8 @@
/** @addtogroup IWDG_Exported_Functions_Group2
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
diff --git a/Src/stm32g4xx_hal_lptim.c b/Src/stm32g4xx_hal_lptim.c
index b608529..d51539d 100644
--- a/Src/stm32g4xx_hal_lptim.c
+++ b/Src/stm32g4xx_hal_lptim.c
@@ -92,19 +92,19 @@
*** Callback registration ***
=============================================
-
+ [..]
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
-
+ [..]
Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
@ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
-
+ [..]
Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function.
@ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
-
+ [..]
These functions allow to register/unregister following callbacks:
(+) MspInitCallback : LPTIM Base Msp Init Callback.
@@ -117,15 +117,18 @@
(+) DirectionUpCallback : Up-counting direction change Callback.
(+) DirectionDownCallback : Down-counting direction change Callback.
+ [..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+ [..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init/DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
@@ -133,6 +136,7 @@
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+ [..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -141,7 +145,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_msp_template.c b/Src/stm32g4xx_hal_msp_template.c
index 6361431..73668bf 100644
--- a/Src/stm32g4xx_hal_msp_template.c
+++ b/Src/stm32g4xx_hal_msp_template.c
@@ -8,7 +8,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_nand.c b/Src/stm32g4xx_hal_nand.c
index 41f78fe..6cf1e21 100644
--- a/Src/stm32g4xx_hal_nand.c
+++ b/Src/stm32g4xx_hal_nand.c
@@ -95,7 +95,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_nor.c b/Src/stm32g4xx_hal_nor.c
index f1a0875..bcf7df0 100644
--- a/Src/stm32g4xx_hal_nor.c
+++ b/Src/stm32g4xx_hal_nor.c
@@ -92,7 +92,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_opamp.c b/Src/stm32g4xx_hal_opamp.c
index 9d12de5..d77d4a0 100644
--- a/Src/stm32g4xx_hal_opamp.c
+++ b/Src/stm32g4xx_hal_opamp.c
@@ -169,7 +169,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_opamp_ex.c b/Src/stm32g4xx_hal_opamp_ex.c
index 5948219..02c3984 100644
--- a/Src/stm32g4xx_hal_opamp_ex.c
+++ b/Src/stm32g4xx_hal_opamp_ex.c
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -82,7 +82,7 @@
* @note Calibration runs about 25 ms.
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
@@ -96,7 +96,7 @@
uint32_t trimmingvaluep2;
uint32_t trimmingvaluen3;
uint32_t trimmingvaluep3;
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
uint32_t trimmingvaluen4;
uint32_t trimmingvaluep4;
uint32_t trimmingvaluen5;
@@ -108,7 +108,7 @@
uint32_t delta;
if ((hopamp1 == NULL) || (hopamp2 == NULL) || (hopamp3 == NULL)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
|| (hopamp4 == NULL) || (hopamp5 == NULL) || (hopamp6 == NULL)
#endif
)
@@ -127,7 +127,7 @@
{
return HAL_ERROR;
}
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
else if (hopamp4->State != HAL_OPAMP_STATE_READY)
{
return HAL_ERROR;
@@ -148,7 +148,7 @@
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp4->Instance));
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp5->Instance));
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp6->Instance));
@@ -159,7 +159,7 @@
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP);
SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP);
@@ -169,7 +169,7 @@
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_USERTRIM);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_USERTRIM);
SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_USERTRIM);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_USERTRIM);
SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_USERTRIM);
SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_USERTRIM);
@@ -179,7 +179,7 @@
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_CALON);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON);
SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON);
SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON);
@@ -190,7 +190,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_90VDDA);
@@ -200,7 +200,7 @@
SET_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
SET_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
SET_BIT(hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
SET_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
SET_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN);
SET_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN);
@@ -211,7 +211,7 @@
trimmingvaluen1 = 16UL;
trimmingvaluen2 = 16UL;
trimmingvaluen3 = 16UL;
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
trimmingvaluen4 = 16UL;
trimmingvaluen5 = 16UL;
trimmingvaluen6 = 16UL;
@@ -224,7 +224,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
@@ -268,7 +268,7 @@
trimmingvaluen3 -= delta;
}
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
{
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
@@ -311,7 +311,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
@@ -346,7 +346,7 @@
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
}
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
{
/* OPAMP_CSR_OUTCAL is actually one value more */
@@ -377,7 +377,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
@@ -388,7 +388,7 @@
trimmingvaluep1 = 16UL;
trimmingvaluep2 = 16UL;
trimmingvaluep3 = 16UL;
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
trimmingvaluep4 = 16UL;
trimmingvaluep5 = 16UL;
trimmingvaluep6 = 16UL;
@@ -402,7 +402,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
@@ -443,7 +443,7 @@
trimmingvaluep3 -= delta;
}
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
{
/* OPAMP_CSR_OUTCAL is HIGH try higher trimming */
@@ -484,7 +484,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep5 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep6 << OPAMP_INPUT_NONINVERTING);
@@ -519,7 +519,7 @@
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
}
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
if ((hopamp4->Instance->CSR & OPAMP_CSR_OUTCAL) != 0UL)
{
/* Trimming value is actually one value more */
@@ -549,7 +549,7 @@
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_CALON);
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_CALON);
CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_CALON);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_CALON);
CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_CALON);
CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_CALON);
@@ -559,7 +559,7 @@
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_OPAMPxEN);
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_OPAMPxEN);
CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_OPAMPxEN);
CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_OPAMPxEN);
CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_OPAMPxEN);
@@ -569,7 +569,7 @@
CLEAR_BIT(hopamp1->Instance->CSR, OPAMP_CSR_FORCEVP);
CLEAR_BIT(hopamp2->Instance->CSR, OPAMP_CSR_FORCEVP);
CLEAR_BIT(hopamp3->Instance->CSR, OPAMP_CSR_FORCEVP);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
CLEAR_BIT(hopamp4->Instance->CSR, OPAMP_CSR_FORCEVP);
CLEAR_BIT(hopamp5->Instance->CSR, OPAMP_CSR_FORCEVP);
CLEAR_BIT(hopamp6->Instance->CSR, OPAMP_CSR_FORCEVP);
@@ -583,7 +583,7 @@
hopamp1->Init.TrimmingValueN = trimmingvaluen1;
hopamp2->Init.TrimmingValueN = trimmingvaluen2;
hopamp3->Init.TrimmingValueN = trimmingvaluen3;
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
hopamp4->Init.TrimmingValueN = trimmingvaluen4;
hopamp5->Init.TrimmingValueN = trimmingvaluen5;
hopamp6->Init.TrimmingValueN = trimmingvaluen6;
@@ -593,7 +593,7 @@
hopamp1->Init.TrimmingValueP = trimmingvaluep1;
hopamp2->Init.TrimmingValueP = trimmingvaluep2;
hopamp3->Init.TrimmingValueP = trimmingvaluep3;
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
hopamp4->Init.TrimmingValueP = trimmingvaluep4;
hopamp5->Init.TrimmingValueP = trimmingvaluep5;
hopamp6->Init.TrimmingValueP = trimmingvaluep6;
@@ -604,7 +604,7 @@
hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
hopamp4->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp5->Init.UserTrimming = OPAMP_TRIMMING_USER;
hopamp6->Init.UserTrimming = OPAMP_TRIMMING_USER;
@@ -613,7 +613,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen1 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen2 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen3 << OPAMP_INPUT_INVERTING);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen4 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen5 << OPAMP_INPUT_INVERTING);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETN, trimmingvaluen6 << OPAMP_INPUT_INVERTING);
@@ -622,7 +622,7 @@
MODIFY_REG(hopamp1->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep1 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp2->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep2 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp3->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G483xx)
MODIFY_REG(hopamp4->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp5->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep3 << OPAMP_INPUT_NONINVERTING);
MODIFY_REG(hopamp6->Instance->CSR, OPAMP_CSR_TRIMOFFSETP, trimmingvaluep4 << OPAMP_INPUT_NONINVERTING);
diff --git a/Src/stm32g4xx_hal_pcd.c b/Src/stm32g4xx_hal_pcd.c
index d4e3d2d..c435ac6 100644
--- a/Src/stm32g4xx_hal_pcd.c
+++ b/Src/stm32g4xx_hal_pcd.c
@@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1714,7 +1714,10 @@
{
/* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count);
+
+ USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
+ ep->pmaadress, (uint16_t)ep->xfer_count);
+
/* SETUP bit kept frozen while CTR_RX = 1*/
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
@@ -1729,21 +1732,24 @@
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
+
/* Get Control Data OUT Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0U)
+ if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
{
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, (uint16_t)ep->xfer_count);
- ep->xfer_buff += ep->xfer_count;
- }
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
+ ep->pmaadress, (uint16_t)ep->xfer_count);
- /* Process Control Data OUT Packet*/
+ ep->xfer_buff += ep->xfer_count;
+
+ /* Process Control Data OUT Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataOutStageCallback(hpcd, 0U);
+ hpcd->DataOutStageCallback(hpcd, 0U);
#else
- HAL_PCD_DataOutStageCallback(hpcd, 0U);
+ HAL_PCD_DataOutStageCallback(hpcd, 0U);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
diff --git a/Src/stm32g4xx_hal_pcd_ex.c b/Src/stm32g4xx_hal_pcd_ex.c
index 26765f0..74d50c0 100644
--- a/Src/stm32g4xx_hal_pcd_ex.c
+++ b/Src/stm32g4xx_hal_pcd_ex.c
@@ -10,7 +10,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -125,6 +125,9 @@
USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 1U;
+ /* Enable BCD feature */
+ USBx->BCDR |= USB_BCDR_BCDEN;
+
/* Enable DCD : Data Contact Detect */
USBx->BCDR &= ~(USB_BCDR_PDEN);
USBx->BCDR &= ~(USB_BCDR_SDEN);
@@ -143,6 +146,7 @@
USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 0U;
+ /* Disable BCD feature */
USBx->BCDR &= ~(USB_BCDR_BCDEN);
return HAL_OK;
diff --git a/Src/stm32g4xx_hal_pwr.c b/Src/stm32g4xx_hal_pwr.c
index fdab794..49b5190 100644
--- a/Src/stm32g4xx_hal_pwr.c
+++ b/Src/stm32g4xx_hal_pwr.c
@@ -11,7 +11,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_pwr_ex.c b/Src/stm32g4xx_hal_pwr_ex.c
index 8811a5b..fddf7fb 100644
--- a/Src/stm32g4xx_hal_pwr_ex.c
+++ b/Src/stm32g4xx_hal_pwr_ex.c
@@ -11,7 +11,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -40,7 +40,7 @@
/* Private define ------------------------------------------------------------*/
-#if defined (STM32G474xx) || defined (STM32G473xx) || defined (STM32G471xx) || defined (STM32G484xx)
+#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G483xx) || defined (STM32G484xx)
#define PWR_PORTF_AVAILABLE_PINS 0x0000FFFFU /* PF0..PF15 */
#define PWR_PORTG_AVAILABLE_PINS 0x000007FFU /* PG0..PG10 */
#elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
diff --git a/Src/stm32g4xx_hal_qspi.c b/Src/stm32g4xx_hal_qspi.c
index e3b705f..59dc1d9 100644
--- a/Src/stm32g4xx_hal_qspi.c
+++ b/Src/stm32g4xx_hal_qspi.c
@@ -196,7 +196,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_rcc.c b/Src/stm32g4xx_hal_rcc.c
index 22171e8..a515fec 100644
--- a/Src/stm32g4xx_hal_rcc.c
+++ b/Src/stm32g4xx_hal_rcc.c
@@ -39,7 +39,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -263,7 +263,7 @@
SystemCoreClock = HSI_VALUE;
/* Adapt Systick interrupt period */
- if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@@ -407,7 +407,7 @@
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
/* Adapt Systick interrupt period */
- if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
@@ -943,7 +943,7 @@
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
/* Configure the source of time base considering new system clocks settings*/
- return HAL_InitTick(TICK_INT_PRIORITY);
+ return HAL_InitTick(uwTickPrio);
}
/**
diff --git a/Src/stm32g4xx_hal_rcc_ex.c b/Src/stm32g4xx_hal_rcc_ex.c
index b61d912..56f5704 100644
--- a/Src/stm32g4xx_hal_rcc_ex.c
+++ b/Src/stm32g4xx_hal_rcc_ex.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -499,7 +499,7 @@
RCC_PERIPHCLK_QSPI | \
RCC_PERIPHCLK_RTC;
-#elif defined(STM32G473xx)
+#elif defined(STM32G473xx) || defined(STM32G483xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
RCC_PERIPHCLK_UART5 | \
diff --git a/Src/stm32g4xx_hal_rng.c b/Src/stm32g4xx_hal_rng.c
index ac87abb..569b167 100644
--- a/Src/stm32g4xx_hal_rng.c
+++ b/Src/stm32g4xx_hal_rng.c
@@ -81,7 +81,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -308,7 +308,7 @@
if (pCallback == NULL)
{
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
@@ -332,7 +332,7 @@
default :
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
@@ -352,7 +352,7 @@
default :
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
@@ -361,7 +361,7 @@
else
{
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
@@ -407,7 +407,7 @@
default :
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
@@ -427,7 +427,7 @@
default :
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
@@ -436,7 +436,7 @@
else
{
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
@@ -460,7 +460,7 @@
if (pCallback == NULL)
{
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
/* Process locked */
@@ -473,7 +473,7 @@
else
{
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
@@ -503,7 +503,7 @@
else
{
/* Update the error code */
- hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
@@ -537,8 +537,16 @@
/**
* @brief Generates a 32-bit random number.
- * @note Each time the random number data is read the RNG_FLAG_DRDY flag
- * is automatically cleared.
+ * @note This function checks value of RNG_FLAG_DRDY flag to know if valid
+ * random number is available in the DR register (RNG_FLAG_DRDY flag set
+ * whenever a random number is available through the RNG_DR register).
+ * After transitioning from 0 to 1 (random number available),
+ * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
+ * four words from the RNG_DR register, i.e. further function calls
+ * will immediately return a new u32 random number (additional words are
+ * available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
+ * @note When no more random number data is available in DR register, RNG_FLAG_DRDY
+ * flag is automatically cleared.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit pointer to generated random number variable if successful.
@@ -568,7 +576,7 @@
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
return HAL_ERROR;
@@ -583,6 +591,7 @@
}
else
{
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
@@ -619,6 +628,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hrng);
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR;
}
@@ -653,10 +663,14 @@
/* RNG clock error interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
{
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
rngclockerror = 1U;
}
else
@@ -721,6 +735,11 @@
/**
* @brief Data Ready callback in non-blocking mode.
+ * @note When RNG_FLAG_DRDY flag value is set, first random number has been read
+ * from DR register in IRQ Handler and is provided as callback parameter.
+ * Depending on valid data available in the conditioning output buffer,
+ * additional words can be read by the application from DR register till
+ * DRDY bit remains high.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit generated random number.
diff --git a/Src/stm32g4xx_hal_rtc.c b/Src/stm32g4xx_hal_rtc.c
index d16a7c6..b9a295c 100644
--- a/Src/stm32g4xx_hal_rtc.c
+++ b/Src/stm32g4xx_hal_rtc.c
@@ -96,10 +96,12 @@
are set to the corresponding weak functions. This is the recommended configuration
in order to optimize memory/code consumption footprint/performances.
+ [..]
The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+ [..]
Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback.
@@ -139,9 +141,11 @@
#endif
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+ [..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
+ [..]
Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@@ -190,6 +194,7 @@
(+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback.
+ [..]
By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions :
examples @ref AlarmAEventCallback(), @ref TimeStampEventCallback().
@@ -199,6 +204,7 @@
If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
@@ -207,6 +213,7 @@
using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
or @ref HAL_RTC_Init() function.
+ [..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@@ -297,7 +304,6 @@
/* Check the RTC peripheral state */
if (hrtc != NULL)
{
- status = HAL_OK;
/* Check the parameters */
assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
@@ -368,18 +374,10 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- status = HAL_ERROR;
- }
- else
+ if (status == HAL_OK)
{
/* Clear RTC_CR FMT, OSEL and POL Bits */
CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE));
@@ -390,35 +388,25 @@
WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos)));
/* Exit Initialization mode */
- CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
- status = HAL_ERROR;
- }
- }
+ status = RTC_ExitInitMode(hrtc);
if (status == HAL_OK)
{
MODIFY_REG(RTC->CR, \
RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \
hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
}
}
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
}
+
return status;
}
@@ -868,6 +856,7 @@
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
uint32_t tmpreg;
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -882,21 +871,9 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
if (Format == RTC_FORMAT_BIN)
{
@@ -948,34 +925,18 @@
SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation));
/* Exit Initialization mode */
- CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+ status = RTC_ExitInitMode(hrtc);
+ }
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_READY;
-
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
__HAL_UNLOCK(hrtc);
- return HAL_OK;
- }
+ return status;
}
/**
@@ -1048,6 +1009,7 @@
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
uint32_t datetmpreg;
+ HAL_StatusTypeDef status;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1090,55 +1052,29 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
/* Set the RTC_DR register */
WRITE_REG(RTC->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK));
/* Exit Initialization mode */
- CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ status = RTC_ExitInitMode(hrtc);
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ if (status == HAL_OK)
+ {
hrtc->State = HAL_RTC_STATE_READY ;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_OK;
}
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return status;
}
/**
@@ -1923,6 +1859,7 @@
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
uint32_t tickstart;
+ HAL_StatusTypeDef status = HAL_OK;
UNUSED(hrtc);
@@ -1934,20 +1871,60 @@
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
- while (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+ while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
- return HAL_TIMEOUT;
+ status = HAL_TIMEOUT;
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
}
}
}
- return HAL_OK;
+ return status;
}
/**
+ * @brief Exit the RTC Initialization mode.
+ * @param hrtc RTC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Exit Initialization mode */
+ CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro */
+ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ }
+ else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry */
+ {
+ /* Clear BYPSHAD bit */
+ CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+ status = HAL_TIMEOUT;
+ }
+ /* Restore BYPSHAD bit */
+ SET_BIT(RTC->CR, RTC_CR_BYPSHAD);
+ }
+
+ return status;
+}
+
+
+
+/**
* @brief Convert a 2 digit decimal to BCD format.
* @param Value Byte to be converted
* @retval Converted byte
diff --git a/Src/stm32g4xx_hal_rtc_ex.c b/Src/stm32g4xx_hal_rtc_ex.c
index 6f8285e..fc3adce 100644
--- a/Src/stm32g4xx_hal_rtc_ex.c
+++ b/Src/stm32g4xx_hal_rtc_ex.c
@@ -542,13 +542,18 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Check RTC WUTWF flag is reset only when wake up timer enabled*/
- if (READ_BIT(RTC->CR, RTC_CR_WUTE) != 0U)
+ /* Clear WUTE in RTC_CR to disable the wakeup timer */
+ CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE);
+
+ /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
+ counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+ calendar initialization mode. */
+ if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U)
{
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) != 0U)
+ while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -565,42 +570,14 @@
}
}
- /* Disable Wake Up timer */
- CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
-
- /* Clear flag Wake-Up */
- WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
+ /* Configure the clock source */
+ MODIFY_REG(hrtc->Instance->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
/* Configure the Wakeup Timer counter */
- WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter);
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- CLEAR_BIT(RTC->CR, RTC_CR_WUCKSEL);
-
- /* Configure the clock source */
- MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
+ WRITE_REG(hrtc->Instance->WUTR, (uint32_t)WakeUpCounter);
/* Enable the Wakeup Timer */
- SET_BIT(RTC->CR, RTC_CR_WUTE);
+ SET_BIT(hrtc->Instance->CR, RTC_CR_WUTE);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -636,13 +613,21 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Check RTC WUTWF flag is reset only when wake up timer enabled */
- if (READ_BIT(RTC->CR, RTC_CR_WUTE) != 0U)
+ /* Clear WUTE in RTC_CR to disable the wakeup timer */
+ CLEAR_BIT(hrtc->Instance->CR, RTC_CR_WUTE);
+
+ /* Clear flag Wake-Up */
+ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
+
+ /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
+ counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
+ calendar initialization mode. */
+ if (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_INITF) == 0U)
{
tickstart = HAL_GetTick();
/* Wait till RTC WUTWF flag is reset and if Time out is reached exit */
- while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) != 0U)
+ while (READ_BIT(hrtc->Instance->ICSR, RTC_ICSR_WUTWF) == 0U)
{
if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
{
@@ -658,38 +643,9 @@
}
}
}
- /* Disable the Wake-Up timer */
- CLEAR_BIT(RTC->CR, RTC_CR_WUTE);
-
- /* Clear flag Wake-Up */
- WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
- __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT();
-
- tickstart = HAL_GetTick();
-
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U)
- {
- if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_TIMEOUT;
- }
- }
-
/* Configure the Wakeup Timer counter */
WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter);
- /* Clear the Wakeup Timer clock source bits in CR register */
- CLEAR_BIT(RTC->CR, RTC_CR_WUCKSEL);
-
/* Configure the clock source */
MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock);
@@ -697,7 +653,7 @@
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT();
- /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/
+ /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer */
SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE));
/* Enable the write protection for RTC registers */
@@ -1134,6 +1090,8 @@
*/
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc)
{
+ HAL_StatusTypeDef status;
+
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1142,39 +1100,29 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
/* Enable clockref detection */
SET_BIT(RTC->CR, RTC_CR_REFCKON);
/* Exit Initialization mode */
- CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+ status = RTC_ExitInitMode(hrtc);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
/**
@@ -1184,6 +1132,8 @@
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc)
{
+ HAL_StatusTypeDef status;
+
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1192,39 +1142,29 @@
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state*/
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- else
+ /* Enter Initialization mode */
+ status = RTC_EnterInitMode(hrtc);
+ if (status == HAL_OK)
{
/* Disable clockref detection */
CLEAR_BIT(RTC->CR, RTC_CR_REFCKON);
/* Exit Initialization mode */
- CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+ status = RTC_ExitInitMode(hrtc);
}
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- /* Change RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
+ if (status == HAL_OK)
+ {
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
/* Process Unlocked */
__HAL_UNLOCK(hrtc);
- return HAL_OK;
+ return status;
}
/**
diff --git a/Src/stm32g4xx_hal_sai.c b/Src/stm32g4xx_hal_sai.c
index 2d719aa..d703676 100644
--- a/Src/stm32g4xx_hal_sai.c
+++ b/Src/stm32g4xx_hal_sai.c
@@ -139,12 +139,13 @@
*** Callback registration ***
=============================
-
+ [..]
The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
- Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
+ Use functions HAL_SAI_RegisterCallback() to register a user callback.
- Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
+ [..]
+ Function HAL_SAI_RegisterCallback() allows to register following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
(+) TxCpltCallback : SAI transmit complete.
@@ -152,13 +153,16 @@
(+) ErrorCallback : SAI error.
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
+ [..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
- Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
+ [..]
+ Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
+ [..]
This function allows to reset following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
@@ -168,23 +172,26 @@
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
- By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
+ [..]
+ By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
- examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
+ examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
- and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
+ reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+ [..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
- or @ref HAL_SAI_Init function.
+ using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
+ or HAL_SAI_Init function.
+ [..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -193,7 +200,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_sai_ex.c b/Src/stm32g4xx_hal_sai_ex.c
index 27374a0..faf0d74 100644
--- a/Src/stm32g4xx_hal_sai_ex.c
+++ b/Src/stm32g4xx_hal_sai_ex.c
@@ -10,7 +10,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_smartcard.c b/Src/stm32g4xx_hal_smartcard.c
index 0039055..77277cd 100644
--- a/Src/stm32g4xx_hal_smartcard.c
+++ b/Src/stm32g4xx_hal_smartcard.c
@@ -168,7 +168,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -757,29 +757,30 @@
(++) HAL_SMARTCARD_RxCpltCallback()
(++) HAL_SMARTCARD_ErrorCallback()
+ [..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (+) HAL_SMARTCARD_Abort()
- (+) HAL_SMARTCARD_AbortTransmit()
- (+) HAL_SMARTCARD_AbortReceive()
- (+) HAL_SMARTCARD_Abort_IT()
- (+) HAL_SMARTCARD_AbortTransmit_IT()
- (+) HAL_SMARTCARD_AbortReceive_IT()
+ (++) HAL_SMARTCARD_Abort()
+ (++) HAL_SMARTCARD_AbortTransmit()
+ (++) HAL_SMARTCARD_AbortReceive()
+ (++) HAL_SMARTCARD_Abort_IT()
+ (++) HAL_SMARTCARD_AbortTransmit_IT()
+ (++) HAL_SMARTCARD_AbortReceive_IT()
(#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (+) HAL_SMARTCARD_AbortCpltCallback()
- (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+ (++) HAL_SMARTCARD_AbortCpltCallback()
+ (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -2292,6 +2293,7 @@
SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
@@ -2363,16 +2365,19 @@
switch (clocksource)
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
- tmpreg = (uint16_t)(((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK1Freq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
- tmpreg = (uint16_t)(((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetPCLK2Freq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
- tmpreg = (uint16_t)(((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ pclk = HAL_RCC_GetSysClockFreq();
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
diff --git a/Src/stm32g4xx_hal_smartcard_ex.c b/Src/stm32g4xx_hal_smartcard_ex.c
index c3f9c95..8c731c6 100644
--- a/Src/stm32g4xx_hal_smartcard_ex.c
+++ b/Src/stm32g4xx_hal_smartcard_ex.c
@@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -55,11 +55,17 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants
+ * @{
+ */
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -188,8 +194,8 @@
This subsection provides a set of FIFO mode related callback functions.
(#) TX/RX Fifos Callbacks:
- (+) HAL_SMARTCARDEx_RxFifoFullCallback()
- (+) HAL_SMARTCARDEx_TxFifoEmptyCallback()
+ (++) HAL_SMARTCARDEx_RxFifoFullCallback()
+ (++) HAL_SMARTCARDEx_TxFifoEmptyCallback()
@endverbatim
* @{
@@ -231,15 +237,16 @@
* @}
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions
+/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions
* @brief SMARTCARD control functions
*
@verbatim
===============================================================================
- ##### Peripheral Control functions #####
+ ##### Peripheral FIFO Control functions #####
===============================================================================
[..]
- This subsection provides a set of functions allowing to control the SMARTCARD.
+ This subsection provides a set of functions allowing to control the SMARTCARD
+ FIFO feature.
(+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode
(+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode
(+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold
@@ -433,7 +440,7 @@
* @}
*/
-/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions
+/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions
* @{
*/
diff --git a/Src/stm32g4xx_hal_smbus.c b/Src/stm32g4xx_hal_smbus.c
index af699a2..829b12b 100644
--- a/Src/stm32g4xx_hal_smbus.c
+++ b/Src/stm32g4xx_hal_smbus.c
@@ -153,7 +153,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_spi.c b/Src/stm32g4xx_hal_spi.c
index b6e5ed0..fa5e3ea 100644
--- a/Src/stm32g4xx_hal_spi.c
+++ b/Src/stm32g4xx_hal_spi.c
@@ -65,16 +65,16 @@
Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
Function HAL_SPI_RegisterCallback() allows to register following callbacks:
- (+) TxCpltCallback : SPI Tx Completed callback
- (+) RxCpltCallback : SPI Rx Completed callback
- (+) TxRxCpltCallback : SPI TxRx Completed callback
- (+) TxHalfCpltCallback : SPI Tx Half Completed callback
- (+) RxHalfCpltCallback : SPI Rx Half Completed callback
- (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (+) ErrorCallback : SPI Error callback
- (+) AbortCpltCallback : SPI Abort callback
- (+) MspInitCallback : SPI Msp Init callback
- (+) MspDeInitCallback : SPI Msp DeInit callback
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
@@ -84,17 +84,18 @@
HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
- (+) TxCpltCallback : SPI Tx Completed callback
- (+) RxCpltCallback : SPI Rx Completed callback
- (+) TxRxCpltCallback : SPI TxRx Completed callback
- (+) TxHalfCpltCallback : SPI Tx Half Completed callback
- (+) RxHalfCpltCallback : SPI Rx Half Completed callback
- (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
- (+) ErrorCallback : SPI Error callback
- (+) AbortCpltCallback : SPI Abort callback
- (+) MspInitCallback : SPI Msp Init callback
- (+) MspDeInitCallback : SPI Msp DeInit callback
+ (++) TxCpltCallback : SPI Tx Completed callback
+ (++) RxCpltCallback : SPI Rx Completed callback
+ (++) TxRxCpltCallback : SPI TxRx Completed callback
+ (++) TxHalfCpltCallback : SPI Tx Half Completed callback
+ (++) RxHalfCpltCallback : SPI Rx Half Completed callback
+ (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
+ (++) ErrorCallback : SPI Error callback
+ (++) AbortCpltCallback : SPI Abort callback
+ (++) MspInitCallback : SPI Msp Init callback
+ (++) MspDeInitCallback : SPI Msp DeInit callback
+ [..]
By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
@@ -104,6 +105,7 @@
If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+ [..]
Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
@@ -112,7 +114,8 @@
using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
or HAL_SPI_Init() function.
- When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
+ [..]
+ When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@@ -184,7 +187,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_spi_ex.c b/Src/stm32g4xx_hal_spi_ex.c
index de4a14f..18de06b 100644
--- a/Src/stm32g4xx_hal_spi_ex.c
+++ b/Src/stm32g4xx_hal_spi_ex.c
@@ -10,7 +10,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_sram.c b/Src/stm32g4xx_hal_sram.c
index ac18dae..249d904 100644
--- a/Src/stm32g4xx_hal_sram.c
+++ b/Src/stm32g4xx_hal_sram.c
@@ -101,7 +101,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_tim.c b/Src/stm32g4xx_hal_tim.c
index 7b40269..58aa3e6 100644
--- a/Src/stm32g4xx_hal_tim.c
+++ b/Src/stm32g4xx_hal_tim.c
@@ -176,7 +176,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -496,11 +496,11 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -948,11 +948,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -1527,11 +1527,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2075,11 +2075,11 @@
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((pData == NULL) && (Length > 0U))
{
@@ -2986,11 +2986,11 @@
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
{
@@ -3805,6 +3805,10 @@
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @note To output a waveform with a minimum delay user can enable the fast
+ * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
+ * output is forced in response to the edge detection on TIx input,
+ * without taking in account the comparison.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
@@ -4021,11 +4025,11 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4353,11 +4357,11 @@
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
diff --git a/Src/stm32g4xx_hal_tim_ex.c b/Src/stm32g4xx_hal_tim_ex.c
index 0311adc..a6a5057 100644
--- a/Src/stm32g4xx_hal_tim_ex.c
+++ b/Src/stm32g4xx_hal_tim_ex.c
@@ -71,7 +71,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -415,11 +415,11 @@
/* Check the parameters */
assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -746,11 +746,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -1201,11 +1201,11 @@
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
- if ((htim->State == HAL_TIM_STATE_BUSY))
+ if (htim->State == HAL_TIM_STATE_BUSY)
{
return HAL_BUSY;
}
- else if ((htim->State == HAL_TIM_STATE_READY))
+ else if (htim->State == HAL_TIM_STATE_READY)
{
if (((uint32_t)pData == 0U) && (Length > 0U))
{
@@ -1898,6 +1898,9 @@
* @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
+ * @note Interrupts can be generated when an active level is detected on the
+ * break input, the break 2 input or the system break input. Break
+ * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@@ -1988,10 +1991,10 @@
{
uint32_t tmporx;
- uint32_t bkin_enable_mask = 0U;
- uint32_t bkin_polarity_mask = 0U;
- uint32_t bkin_enable_bitpos = 0U;
- uint32_t bkin_polarity_bitpos = 0U;
+ uint32_t bkin_enable_mask;
+ uint32_t bkin_polarity_mask;
+ uint32_t bkin_enable_bitpos;
+ uint32_t bkin_polarity_bitpos;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
@@ -2051,6 +2054,8 @@
bkin_enable_mask = TIM1_AF1_BKCMP5E;
bkin_enable_bitpos = TIM1_AF1_BKCMP5E_Pos;
/* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
break;
}
#endif /* COMP5 */
@@ -2060,6 +2065,8 @@
bkin_enable_mask = TIM1_AF1_BKCMP6E;
bkin_enable_bitpos = TIM1_AF1_BKCMP6E_Pos;
/* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
break;
}
#endif /* COMP7 */
@@ -2069,12 +2076,20 @@
bkin_enable_mask = TIM1_AF1_BKCMP7E;
bkin_enable_bitpos = TIM1_AF1_BKCMP7E_Pos;
/* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */
+ bkin_polarity_mask = 0U;
+ bkin_polarity_bitpos = 0U;
break;
}
#endif /* COMP7 */
default:
+ {
+ bkin_enable_mask = 0U;
+ bkin_polarity_mask = 0U;
+ bkin_enable_bitpos = 0U;
+ bkin_polarity_bitpos = 0U;
break;
+ }
}
switch (BreakInput)
diff --git a/Src/stm32g4xx_hal_timebase_tim_template.c b/Src/stm32g4xx_hal_timebase_tim_template.c
index 7cd6df0..8ee6ddc 100644
--- a/Src/stm32g4xx_hal_timebase_tim_template.c
+++ b/Src/stm32g4xx_hal_timebase_tim_template.c
@@ -27,7 +27,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_uart.c b/Src/stm32g4xx_hal_uart.c
index c280974..9bb0ed6 100644
--- a/Src/stm32g4xx_hal_uart.c
+++ b/Src/stm32g4xx_hal_uart.c
@@ -142,7 +142,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -1015,13 +1015,16 @@
/**
* @brief Send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @note When FIFO mode is enabled, writing a data in the TDR register adds one
* data to the TXFIFO. Write operations to the TDR register are performed
* when TXFNF flag is set. From hardware perspective, TXFNF flag and
* TXE are mapped on the same bit-field.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -1101,13 +1104,16 @@
/**
* @brief Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
* is not empty. Read operations from the RDR register are performed when
* RXFNE flag is set. From hardware perspective, RXFNE flag and
* RXNE are mapped on the same bit-field.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -1188,9 +1194,12 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1259,9 +1268,12 @@
/**
* @brief Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1337,9 +1349,12 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -1410,9 +1425,12 @@
* @brief Receive an amount of data in DMA mode.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pData.
* @param huart UART handle.
- * @param pData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -2735,6 +2753,7 @@
uint32_t usartdiv = 0x00000000U;
HAL_StatusTypeDef ret = HAL_OK;
uint32_t lpuart_ker_ck_pres = 0x00000000U;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
@@ -2811,7 +2830,6 @@
case UART_CLOCKSOURCE_LSE:
lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@@ -2831,18 +2849,19 @@
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@@ -2866,21 +2885,23 @@
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
@@ -2903,21 +2924,23 @@
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_HSI:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_LSE:
usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
- case UART_CLOCKSOURCE_UNDEFINED:
default:
ret = HAL_ERROR;
break;
diff --git a/Src/stm32g4xx_hal_uart_ex.c b/Src/stm32g4xx_hal_uart_ex.c
index 49d1981..8182039 100644
--- a/Src/stm32g4xx_hal_uart_ex.c
+++ b/Src/stm32g4xx_hal_uart_ex.c
@@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_hal_usart.c b/Src/stm32g4xx_hal_usart.c
index 2db6cd7..c9449d8 100644
--- a/Src/stm32g4xx_hal_usart.c
+++ b/Src/stm32g4xx_hal_usart.c
@@ -124,7 +124,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -734,9 +734,12 @@
/**
* @brief Simplex send an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData Pointer to data buffer.
- * @param Size Amount of data to be sent.
+ * @param pTxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -827,10 +830,13 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData Pointer to data buffer.
- * @param Size Amount of data to be received.
+ * @param pRxData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -936,10 +942,13 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @param Timeout Timeout duration.
* @retval HAL status
*/
@@ -1082,9 +1091,12 @@
/**
* @brief Send an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1161,10 +1173,13 @@
/**
* @brief Receive an amount of data in interrupt mode.
- * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note To receive synchronous data, dummy data are simultaneously transmitted.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1262,10 +1277,13 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be sent (same amount to be received).
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
@@ -1358,9 +1376,12 @@
/**
* @brief Send an amount of data in DMA mode.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 provided through pTxData.
* @param husart USART handle.
- * @param pTxData pointer to data buffer.
- * @param Size amount of data to be sent.
+ * @param pTxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -1439,10 +1460,13 @@
* @brief Receive an amount of data in DMA mode.
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
- * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of u16. In this case, Size must indicate the number
+ * of u16 available through pRxData.
* @param husart USART handle.
- * @param pRxData pointer to data buffer.
- * @param Size amount of data to be received.
+ * @param pRxData pointer to data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -1553,10 +1577,13 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
+ * of u16 available through pTxData and through pRxData.
* @param husart USART handle.
- * @param pTxData pointer to TX data buffer.
- * @param pRxData pointer to RX data buffer.
- * @param Size amount of data to be received/sent.
+ * @param pTxData pointer to TX data buffer (u8 or u16 data elements).
+ * @param pRxData pointer to RX data buffer (u8 or u16 data elements).
+ * @param Size amount of data elements (u8 or u16) to be received/sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
@@ -2812,6 +2839,7 @@
HAL_StatusTypeDef ret = HAL_OK;
uint16_t brrtemp;
uint32_t usartdiv = 0x00000000;
+ uint32_t pclk;
/* Check the parameters */
assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
@@ -2858,16 +2886,19 @@
switch (clocksource)
{
case USART_CLOCKSOURCE_PCLK1:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK1Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_PCLK2:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK2Freq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_HSI:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_SYSCLK:
- usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), husart->Init.BaudRate, husart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetSysClockFreq();
+ usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler));
break;
case USART_CLOCKSOURCE_LSE:
usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler));
diff --git a/Src/stm32g4xx_hal_usart_ex.c b/Src/stm32g4xx_hal_usart_ex.c
index d1a2b92..6da75be 100644
--- a/Src/stm32g4xx_hal_usart_ex.c
+++ b/Src/stm32g4xx_hal_usart_ex.c
@@ -28,7 +28,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -54,11 +54,17 @@
#ifdef HAL_USART_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
+/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
+ * @{
+ */
/* UART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
+/**
+ * @}
+ */
/* Private define ------------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
diff --git a/Src/stm32g4xx_hal_wwdg.c b/Src/stm32g4xx_hal_wwdg.c
index 7807ff0..92f8ec5 100644
--- a/Src/stm32g4xx_hal_wwdg.c
+++ b/Src/stm32g4xx_hal_wwdg.c
@@ -32,17 +32,19 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @56 MHz(PCLK1) with zero prescaler:
- max timeout before reset: ~73.14 µs
- (++) Counter max (T[5;0] = 0x3F) @56 MHz(PCLK1) with prescaler dividing by 128:
- max timeout before reset: ~599.18 ms
+ (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
+ max timeout before reset: ~73.14µs
+ (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: ~599.18ms
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
+
*** Common driver usage ***
===========================
+
+ [..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
@@ -59,9 +61,10 @@
HAL_WWDG_Refresh() function. This operation must occur only when
the counter is lower than the refresh window value already programmed.
- [..]
*** Callback registration ***
=============================
+
+ [..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
@ref HAL_WWDG_RegisterCallback() to register a user callback.
@@ -80,13 +83,15 @@
(++) EwiCallback : callback for Early WakeUp Interrupt.
(++) MspInitCallback : WWDG MspInit.
+ [..]
When calling @ref HAL_WWDG_Init function, callbacks are reset to the
- corresponding legacy weak (surcharged) functions:
+ corresponding legacy weak (surcharged) functions:
@ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have
not been registered before.
+ [..]
When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
+ not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
*** WWDG HAL driver macros list ***
@@ -102,7 +107,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -138,8 +143,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions.
- *
+ * @brief Initialization and Configuration functions.
+ *
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
@@ -178,12 +183,12 @@
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/* Reset Callback pointers */
- if(hwwdg->EwiCallback == NULL)
+ if (hwwdg->EwiCallback == NULL)
{
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
}
- if(hwwdg->MspInitCallback == NULL)
+ if (hwwdg->MspInitCallback == NULL)
{
hwwdg->MspInitCallback = HAL_WWDG_MspInit;
}
@@ -242,13 +247,13 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
status = HAL_ERROR;
}
else
{
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = pCallback;
@@ -270,7 +275,7 @@
/**
* @brief Unregister a WWDG Callback
- * WWDG Callback is redirected to the weak (surcharged) predefined callback
+ * WWDG Callback is redirected to the weak (surcharged) predefined callback
* @param hwwdg WWDG handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -282,7 +287,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- switch(CallbackID)
+ switch (CallbackID)
{
case HAL_WWDG_EWI_CB_ID:
hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback;
@@ -306,8 +311,8 @@
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
+ * @brief IO operation functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
diff --git a/Src/stm32g4xx_ll_adc.c b/Src/stm32g4xx_ll_adc.c
index 0dc7b51..531b7d8 100644
--- a/Src/stm32g4xx_ll_adc.c
+++ b/Src/stm32g4xx_ll_adc.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -172,13 +172,14 @@
) \
) \
)
-#elif defined(STM32G473xx)
+#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
@@ -213,7 +214,44 @@
) \
) \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
+ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ && ( \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ ) \
+ ) \
+ || (((__ADC_INSTANCE__) == ADC3) \
+ && ( \
+ ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \
+ ) \
+ ) \
+ )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
@@ -336,7 +374,7 @@
) \
) \
)
-#elif defined(STM32G473xx)
+#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
@@ -376,7 +414,43 @@
) \
) \
)
-#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
+ || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ && ( \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ ) \
+ ) \
+ || ((((__ADC_INSTANCE__) == ADC3)) \
+ && ( \
+ ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \
+ ) \
+ ) \
+ )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
diff --git a/Src/stm32g4xx_ll_comp.c b/Src/stm32g4xx_ll_comp.c
index 80d1439..9dc0ecc 100644
--- a/Src/stm32g4xx_ll_comp.c
+++ b/Src/stm32g4xx_ll_comp.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -57,7 +57,7 @@
( ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \
|| ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2) \
)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \
(((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) || \
@@ -135,7 +135,7 @@
|| ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \
)
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \
@@ -222,11 +222,6 @@
|| ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM4_OC3) \
)
#endif
-#define IS_LL_COMP_DEGLITCHER_MODE(__INSTANCE__, __DEGLITCHER__) \
- ( ((__DEGLITCHER__) == LL_COMP_DEGLITCHER_DISABLED) \
- || ((__DEGLITCHER__) == LL_COMP_DEGLITCHER_ENABLED) \
- )
-
/**
* @}
*/
@@ -302,7 +297,6 @@
assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis));
assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity));
assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource));
- assert_param(IS_LL_COMP_DEGLITCHER_MODE(COMPx, COMP_InitStruct->DeglitcherMode));
/* Note: Hardware constraint (refer to description of this function) */
/* COMP instance must not be locked. */
@@ -314,7 +308,6 @@
/* - InputHysteresis */
/* - OutputPolarity */
/* - OutputBlankingSource */
- /* - DeglitcherMode */
MODIFY_REG(COMPx->CSR,
COMP_CSR_INPSEL
| COMP_CSR_SCALEN
@@ -323,14 +316,12 @@
| COMP_CSR_HYST
| COMP_CSR_POLARITY
| COMP_CSR_BLANKING
- | COMP_CSR_DEGLITCHEN
,
COMP_InitStruct->InputPlus
| COMP_InitStruct->InputMinus
| COMP_InitStruct->InputHysteresis
| COMP_InitStruct->OutputPolarity
| COMP_InitStruct->OutputBlankingSource
- | COMP_InitStruct->DeglitcherMode
);
}
@@ -357,7 +348,6 @@
COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE;
COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED;
COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE;
- COMP_InitStruct->DeglitcherMode = LL_COMP_DEGLITCHER_DISABLED;
}
/**
diff --git a/Src/stm32g4xx_ll_crc.c b/Src/stm32g4xx_ll_crc.c
index 7e68754..1fa05bd 100644
--- a/Src/stm32g4xx_ll_crc.c
+++ b/Src/stm32g4xx_ll_crc.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_dac.c b/Src/stm32g4xx_ll_dac.c
index 6997841..698a693 100644
--- a/Src/stm32g4xx_ll_dac.c
+++ b/Src/stm32g4xx_ll_dac.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -46,7 +46,7 @@
/** @addtogroup DAC_LL_Private_Macros
* @{
*/
-#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
(((__DACX__) == DAC2) ? \
((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
@@ -365,7 +365,6 @@
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
-
MODIFY_REG(DACx->MCR,
(DAC_MCR_MODE1_1
| DAC_MCR_MODE1_0
diff --git a/Src/stm32g4xx_ll_dma.c b/Src/stm32g4xx_ll_dma.c
index 78a3405..08fab49 100644
--- a/Src/stm32g4xx_ll_dma.c
+++ b/Src/stm32g4xx_ll_dma.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_exti.c b/Src/stm32g4xx_ll_exti.c
index 69e97bb..a777e65 100644
--- a/Src/stm32g4xx_ll_exti.c
+++ b/Src/stm32g4xx_ll_exti.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_fmac.c b/Src/stm32g4xx_ll_fmac.c
index 455e9bd..2ad6787 100644
--- a/Src/stm32g4xx_ll_fmac.c
+++ b/Src/stm32g4xx_ll_fmac.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_fmc.c b/Src/stm32g4xx_ll_fmc.c
index 39ec52b..12439fe 100644
--- a/Src/stm32g4xx_ll_fmc.c
+++ b/Src/stm32g4xx_ll_fmc.c
@@ -41,7 +41,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_gpio.c b/Src/stm32g4xx_ll_gpio.c
index 6f520a7..2d46dcc 100644
--- a/Src/stm32g4xx_ll_gpio.c
+++ b/Src/stm32g4xx_ll_gpio.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_hrtim.c b/Src/stm32g4xx_ll_hrtim.c
index a76af59..374e878 100644
--- a/Src/stm32g4xx_ll_hrtim.c
+++ b/Src/stm32g4xx_ll_hrtim.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_i2c.c b/Src/stm32g4xx_ll_i2c.c
index 0c48cd5..60c3c85 100644
--- a/Src/stm32g4xx_ll_i2c.c
+++ b/Src/stm32g4xx_ll_i2c.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_lptim.c b/Src/stm32g4xx_ll_lptim.c
index e77f508..a04a458 100644
--- a/Src/stm32g4xx_ll_lptim.c
+++ b/Src/stm32g4xx_ll_lptim.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_lpuart.c b/Src/stm32g4xx_ll_lpuart.c
index a063b0d..7b1564a 100644
--- a/Src/stm32g4xx_ll_lpuart.c
+++ b/Src/stm32g4xx_ll_lpuart.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_opamp.c b/Src/stm32g4xx_ll_opamp.c
index 76392dd..750fe9b 100644
--- a/Src/stm32g4xx_ll_opamp.c
+++ b/Src/stm32g4xx_ll_opamp.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_pwr.c b/Src/stm32g4xx_ll_pwr.c
index e920ee1..0e02bb8 100644
--- a/Src/stm32g4xx_ll_pwr.c
+++ b/Src/stm32g4xx_ll_pwr.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_rcc.c b/Src/stm32g4xx_ll_rcc.c
index 4950dc4..57f442d 100644
--- a/Src/stm32g4xx_ll_rcc.c
+++ b/Src/stm32g4xx_ll_rcc.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_rng.c b/Src/stm32g4xx_ll_rng.c
index 8016a79..3ab1687 100644
--- a/Src/stm32g4xx_ll_rng.c
+++ b/Src/stm32g4xx_ll_rng.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_rtc.c b/Src/stm32g4xx_ll_rtc.c
index a4d5838..f0316eb 100644
--- a/Src/stm32g4xx_ll_rtc.c
+++ b/Src/stm32g4xx_ll_rtc.c
@@ -85,18 +85,7 @@
#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
-#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
- || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
- || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
- || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
- || ((__VALUE__) == LL_RTC_MONTH_MAY) \
- || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
- || ((__VALUE__) == LL_RTC_MONTH_JULY) \
- || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
- || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
- || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
- || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
- || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
@@ -394,7 +383,7 @@
if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
{
- RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
+ RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU;
}
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
diff --git a/Src/stm32g4xx_ll_spi.c b/Src/stm32g4xx_ll_spi.c
index 551bbe9..68e63c2 100644
--- a/Src/stm32g4xx_ll_spi.c
+++ b/Src/stm32g4xx_ll_spi.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
diff --git a/Src/stm32g4xx_ll_tim.c b/Src/stm32g4xx_ll_tim.c
index 0fcf6d8..e3e5f49 100644
--- a/Src/stm32g4xx_ll_tim.c
+++ b/Src/stm32g4xx_ll_tim.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -714,9 +714,9 @@
* and DTG[7:0] can be write-locked depending on the LOCK configuration, it
* can be necessary to configure all of them during the first write access to
* the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
- * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+ * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @param TIMx Timer Instance
* @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
diff --git a/Src/stm32g4xx_ll_usart.c b/Src/stm32g4xx_ll_usart.c
index 5a8d6ec..911654d 100644
--- a/Src/stm32g4xx_ll_usart.c
+++ b/Src/stm32g4xx_ll_usart.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -41,14 +41,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup USART_LL_Private_Constants
- * @{
- */
-
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
diff --git a/Src/stm32g4xx_ll_usb.c b/Src/stm32g4xx_ll_usb.c
index 76b4e1f..f2cef5a 100644
--- a/Src/stm32g4xx_ll_usb.c
+++ b/Src/stm32g4xx_ll_usb.c
@@ -26,7 +26,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -800,16 +800,16 @@
uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
uint32_t i, temp1, temp2;
- uint16_t *pdwVal;
+ __IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
- pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+ pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
for (i = n; i != 0U; i--)
{
- temp1 = (uint16_t) * pBuf;
+ temp1 = *pBuf;
pBuf++;
- temp2 = temp1 | ((uint16_t)((uint16_t) * pBuf << 8));
+ temp2 = temp1 | ((uint16_t)((uint16_t) *pBuf << 8));
*pdwVal = (uint16_t)temp2;
pdwVal++;
@@ -834,14 +834,14 @@
uint32_t n = (uint32_t)wNBytes >> 1;
uint32_t BaseAddr = (uint32_t)USBx;
uint32_t i, temp;
- uint16_t *pdwVal;
+ __IO uint16_t *pdwVal;
uint8_t *pBuf = pbUsrBuf;
- pdwVal = (uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
+ pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
for (i = n; i != 0U; i--)
{
- temp = *pdwVal;
+ temp = *(__IO uint16_t *)pdwVal;
pdwVal++;
*pBuf = (uint8_t)((temp >> 0) & 0xFFU);
pBuf++;
diff --git a/Src/stm32g4xx_ll_utils.c b/Src/stm32g4xx_ll_utils.c
index 0f29ff6..ea78949 100644
--- a/Src/stm32g4xx_ll_utils.c
+++ b/Src/stm32g4xx_ll_utils.c
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2017 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
