commit 2bfa1cae79926af47ff79a48757d29a38c9c8978
author Ali Labbene <ali.labbene@st.com> Thu Jan 20 19:21:11 2022 +0100
committer Ali Labbene <ali.labbene@st.com> Thu Jan 20 19:21:11 2022 +0100
tree 8f70bf284ac0f670214b41e9e33366413f909866
parent f5a36d64391c40c12cc649de0a027b5bffe856a6

[HAL][OSPI] Update HAL_OSPI_Init() to fix DelayBlockBypass parameter configuration issue

Inc/stm32h7xx_hal_ospi.h

diff --git a/Inc/stm32h7xx_hal_ospi.h b/Inc/stm32h7xx_hal_ospi.h
index 1bcce97..894154b 100644
--- a/Inc/stm32h7xx_hal_ospi.h
+++ b/Inc/stm32h7xx_hal_ospi.h
@@ -1029,6 +1029,9 @@
 
 #define IS_OSPI_CKCSHT(CLK_NB)             ((CLK_NB) <= 7U)
 
+#define IS_OSPI_DLYBYP(MODE)               (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
+                                            ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
+
 #define IS_OSPI_MAXTRAN(NB_BYTES)          ((NB_BYTES) <= 255U)
 
 #define IS_OSPIM_PORT(NUMBER)              (((NUMBER) >= 1U) && ((NUMBER) <= 8U))

Src/stm32h7xx_hal_ospi.c

diff --git a/Src/stm32h7xx_hal_ospi.c b/Src/stm32h7xx_hal_ospi.c
index 62cfcbb..76302fe 100644
--- a/Src/stm32h7xx_hal_ospi.c
+++ b/Src/stm32h7xx_hal_ospi.c
@@ -366,6 +366,7 @@
     assert_param(IS_OSPI_DHQC           (hospi->Init.DelayHoldQuarterCycle));
     assert_param(IS_OSPI_CS_BOUNDARY    (hospi->Init.ChipSelectBoundary));
     assert_param(IS_OSPI_CKCSHT         (hospi->Init.ClkChipSelectHighTime));
+    assert_param(IS_OSPI_DLYBYP         (hospi->Init.DelayBlockBypass));
     assert_param(IS_OSPI_MAXTRAN        (hospi->Init.MaxTran));
 
     /* Initialize error code */
@@ -402,13 +403,14 @@
       /* Configure the default timeout for the OSPI memory access */
       (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
 
-      /* Configure memory type, device size, chip select high time, clocked chip select high time, free running clock, clock mode */
+      /* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
       MODIFY_REG(hospi->Instance->DCR1,
-                 (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
-                  OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
+                 (OCTOSPI_DCR1_MTYP   | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
+                  OCTOSPI_DCR1_DLYBYP | OCTOSPI_DCR1_FRCK    | OCTOSPI_DCR1_CKMODE),
                  (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
                   ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
-                  (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) | hospi->Init.ClockMode));
+                  (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) |
+                  hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
 
       /* Configure wrap size */
       MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize);