commit 7a9b4eff63551204638c15f6b9faa0e1cfea219e
author karim <karim.rabhi-ext@st.com> Mon Mar 11 14:46:25 2024 +0100
committer karim <karim.rabhi-ext@st.com> Mon Mar 11 14:49:51 2024 +0100
tree 1271786490c0bfc3d0f571d4b0382ccd3401bf1f
parent f21bf293ff81c3e41ecbe2e9dd8cba26a335de47

[HAL][ETH] Move the section of disable MMC interrupts from HAL_ETH_Start_IT() to HAL_ETH_Init()

Src/stm32h7xx_hal_eth.c

diff --git a/Src/stm32h7xx_hal_eth.c b/Src/stm32h7xx_hal_eth.c
index ba55178..acee70e 100644
--- a/Src/stm32h7xx_hal_eth.c
+++ b/Src/stm32h7xx_hal_eth.c
@@ -410,6 +410,14 @@
   heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
                              ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
 
+    /* Disable Rx MMC Interrupts */
+    SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
+            ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
+
+    /* Disable Tx MMC Interrupts */
+    SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
+            ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
+
   heth->ErrorCode = HAL_ETH_ERROR_NONE;
   heth->gState = HAL_ETH_STATE_READY;
 
@@ -760,13 +768,6 @@
 
     /* save IT mode to ETH Handle */
     heth->RxDescList.ItMode = 1U;
-    /* Disable Rx MMC Interrupts */
-    SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
-            ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
-
-    /* Disable Tx MMC Interrupts */
-    SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
-            ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
 
     /* Set nombre of descriptors to build */
     heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;