Release v1.11.3
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 730762f..6e2d2d2 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -37,16 +37,12 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
+#if defined(STM32H7) || defined(STM32MP1)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
-#if defined(STM32U5)
-#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-#endif /* STM32U5 || STM32H7 || STM32MP1 */
+#endif /* STM32H7 || STM32MP1 */
/**
* @}
*/
@@ -113,6 +109,9 @@
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
#endif /* STM32U5 */
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
/**
* @}
*/
@@ -140,7 +139,8 @@
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
+ input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
@@ -239,10 +239,12 @@
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
-#if defined(STM32C0)
+#if defined(STM32H5) || defined(STM32C0)
#else
-#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
-#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
+ inter STM32 series compatibility */
+#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
+ inter STM32 series compatibility */
#endif
/**
* @}
@@ -273,7 +275,7 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
@@ -285,7 +287,13 @@
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+ defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
@@ -350,7 +358,8 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+ defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
@@ -539,6 +548,16 @@
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_USER_nBOOT1 OB_USER_NBOOT1
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U0 */
/**
* @}
@@ -582,6 +601,106 @@
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII SBS_ETH_MII
+#define SYSCFG_ETH_RMII SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU SBS_SAU
+#define SYSCFG_MPU_SEC SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK SBS_CLK
+#define SYSCFG_CLASSB SBS_CLASSB
+#define SYSCFG_FPU SBS_FPU
+#define SYSCFG_ALL SBS_ALL
+
+#define SYSCFG_SEC SBS_SEC
+#define SYSCFG_NSEC SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
/**
* @}
*/
@@ -649,14 +768,16 @@
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+ STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+ defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
@@ -678,8 +799,10 @@
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-#if defined(STM32U5)
+#if defined(STM32U5) || defined(STM32H5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
@@ -694,7 +817,23 @@
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */
-
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
/**
* @}
*/
@@ -875,7 +1014,8 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+ defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
@@ -1109,6 +1249,26 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
+#if defined(STM32H5) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 || STM32H7RS */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
@@ -1119,12 +1279,12 @@
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#endif /* STM32H7 */
-#if defined(STM32F7) || defined(STM32H7)
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
-#endif /* STM32F7 || STM32H7 */
+#endif /* STM32F7 || STM32H7 || STM32L0 */
/**
* @}
@@ -1404,30 +1564,40 @@
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
+ the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
+ MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
+ or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
+ of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
+ transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
+ frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
+ de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
+ activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
+ (or time-stamp) */
#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
+ status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
@@ -1435,6 +1605,8 @@
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
+
/**
* @}
*/
@@ -1598,7 +1770,8 @@
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
- )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+ )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+ HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@@ -1607,8 +1780,10 @@
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+ )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
+ HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+ defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
@@ -1642,16 +1817,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
- )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+ defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+ defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+ STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+ defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1776,6 +1956,17 @@
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
+#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
+
+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
@@ -1784,6 +1975,8 @@
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
@@ -1794,6 +1987,7 @@
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
#endif
@@ -1802,6 +1996,20 @@
* @}
*/
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
+/**
+ * @}
+ */
+
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1827,7 +2035,8 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+ defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@@ -2084,7 +2293,8 @@
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+ defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@@ -2109,8 +2319,8 @@
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2143,8 +2353,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2201,8 +2411,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2219,7 +2429,7 @@
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
+#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2256,8 +2466,10 @@
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
+ done into HAL_COMP_Init() */
/**
* @}
*/
@@ -2416,7 +2628,9 @@
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -2425,8 +2639,12 @@
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+ HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+ } while(0)
+#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+ HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+ } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
@@ -2462,8 +2680,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
- )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+ HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@@ -3436,7 +3654,12 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3538,8 +3761,10 @@
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3581,6 +3806,92 @@
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
#endif /* STM32U5 */
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3597,9 +3908,9 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
- defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- defined (STM32C0)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3634,6 +3945,13 @@
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+ defined (STM32H7) || \
+ defined (STM32L0) || defined (STM32L1) || \
+ defined (STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
@@ -3652,6 +3970,11 @@
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
+#endif /* STM32H5 */
+
/**
* @}
*/
@@ -3910,6 +4233,9 @@
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_conf_template.h b/Inc/stm32h7xx_hal_conf_template.h
index a44dfcc..7099c72 100644
--- a/Inc/stm32h7xx_hal_conf_template.h
+++ b/Inc/stm32h7xx_hal_conf_template.h
@@ -166,8 +166,9 @@
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (0x0FUL) /*!< tick interrupt priority */
#define USE_RTOS 0
-#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
-#define USE_SPI_CRC 1U /*!< use CRC in SPI */
+#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
+#define USE_SPI_CRC 1U /*!< use CRC in SPI */
+#define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
diff --git a/Inc/stm32h7xx_hal_cortex.h b/Inc/stm32h7xx_hal_cortex.h
index 2645c28..134fc48 100644
--- a/Inc/stm32h7xx_hal_cortex.h
+++ b/Inc/stm32h7xx_hal_cortex.h
@@ -307,6 +307,8 @@
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
diff --git a/Inc/stm32h7xx_hal_crc.h b/Inc/stm32h7xx_hal_crc.h
index f41b123..cd0c2b7 100644
--- a/Inc/stm32h7xx_hal_crc.h
+++ b/Inc/stm32h7xx_hal_crc.h
@@ -318,7 +318,7 @@
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_dac.h b/Inc/stm32h7xx_hal_dac.h
index 1c48323..65e5fd9 100644
--- a/Inc/stm32h7xx_hal_dac.h
+++ b/Inc/stm32h7xx_hal_dac.h
@@ -78,19 +78,19 @@
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
- void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
- void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
- void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
+ void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+ void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
- void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
- void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
+ void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+ void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
@@ -127,7 +127,7 @@
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
- uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+ uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
@@ -209,19 +209,19 @@
#if defined(HRTIM1)
#define DAC_TRIGGER_HR1_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HR1_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
-#endif
+#endif /* HRTIM12 */
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#if defined(TIM23)
#define DAC_TRIGGER_T23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */
-#endif
+#endif /* TIM23 */
#if defined(TIM24)
#define DAC_TRIGGER_T24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */
-#endif
+#endif /* TIM24 */
#if defined(DAC2)
#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
-#endif
+#endif /* DAC2 */
/**
* @}
@@ -478,7 +478,7 @@
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
@@ -504,8 +504,9 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+ const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
@@ -514,8 +515,8 @@
* @{
*/
/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
/**
* @}
@@ -551,4 +552,3 @@
#endif /* STM32H7xx_HAL_DAC_H */
-
diff --git a/Inc/stm32h7xx_hal_dac_ex.h b/Inc/stm32h7xx_hal_dac_ex.h
index 8fcd75a..43060ee 100644
--- a/Inc/stm32h7xx_hal_dac_ex.h
+++ b/Inc/stm32h7xx_hal_dac_ex.h
@@ -81,6 +81,7 @@
* @}
*/
+
/**
* @}
*/
@@ -140,7 +141,7 @@
((TRIGGER) == DAC_TRIGGER_T23_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T24_TRGO) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif
+#endif /* HRTIM1 */
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
@@ -205,11 +206,11 @@
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
- uint32_t Alignment);
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+ const uint32_t *pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
@@ -229,7 +230,7 @@
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
* @}
@@ -268,4 +269,3 @@
#endif
#endif /* STM32H7xx_HAL_DAC_EX_H */
-
diff --git a/Inc/stm32h7xx_hal_dsi.h b/Inc/stm32h7xx_hal_dsi.h
index ec36c46..2aaaeb3 100644
--- a/Inc/stm32h7xx_hal_dsi.h
+++ b/Inc/stm32h7xx_hal_dsi.h
@@ -976,7 +976,7 @@
#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
__IO uint32_t tmpreg = 0x00U; \
SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper enabling */ \
+ /* Delay after an DSI wrapper enabling */ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
UNUSED(tmpreg); \
} while(0U)
@@ -989,7 +989,7 @@
#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
__IO uint32_t tmpreg = 0x00U; \
CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
- /* Delay after an DSI warpper disabling*/ \
+ /* Delay after an DSI wrapper disabling*/ \
tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
UNUSED(tmpreg); \
} while(0U)
@@ -1184,7 +1184,7 @@
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
- uint8_t *ParametersTable);
+ const uint8_t *ParametersTable);
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
uint32_t ChannelNbr,
uint8_t *Array,
@@ -1222,8 +1222,8 @@
* @brief Peripheral State and Errors functions
* @{
*/
-uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
-HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);
+HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);
/**
* @}
@@ -1271,10 +1271,10 @@
|| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
|| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
-#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\
- || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
-#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\
- || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\
+ || ((Vsync) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\
+ || ((Hsync) == DSI_HSYNC_ACTIVE_LOW))
#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
((VideoModeType) == DSI_VID_MODE_BURST))
diff --git a/Inc/stm32h7xx_hal_eth.h b/Inc/stm32h7xx_hal_eth.h
index 0a14686..726127e 100644
--- a/Inc/stm32h7xx_hal_eth.h
+++ b/Inc/stm32h7xx_hal_eth.h
@@ -24,7 +24,6 @@
extern "C" {
#endif
-
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
@@ -160,7 +159,7 @@
void *pData; /*!< Specifies Application packet pointer to save */
-} ETH_TxPacketConfig;
+} ETH_TxPacketConfigTypeDef;
/**
*
*/
@@ -359,7 +358,6 @@
uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
This parameter can be a value of @ref ETH_Burst_Mode */
-
FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
of any initiated burst transfer with INCRx and SINGLE transfers. */
@@ -385,6 +383,7 @@
uint32_t
MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
This parameter can be a value from 0x40 to 0x3FFF */
+
} ETH_DMAConfigTypeDef;
/**
*
@@ -421,7 +420,6 @@
*/
typedef struct
{
-
uint8_t
*MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
@@ -540,7 +538,7 @@
__IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
and also related to Tx operations. This parameter can
- be a value of @ref HAL_ETH_StateTypeDef */
+ be a value of @ref ETH_State_Codes */
__IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
This parameter can be a value of @ref ETH_Error_Code.*/
@@ -598,7 +596,6 @@
{
HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
-
HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
HAL_ETH_ERROR_CB_ID = 0x04U, /*!< ETH Error Callback ID */
@@ -606,7 +603,6 @@
HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */
HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
-
} HAL_ETH_CallbackIDTypeDef;
/**
@@ -738,11 +734,11 @@
#define ETH_DMATXNDESCRF_CIC_DISABLE 0x00000000U /*!< Do Nothing: Checksum Engine is disabled */
#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 0x00010000U /*!< Only IP header checksum calculation and insertion are enabled. */
#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 0x00020000U /*!< IP header checksum and payload checksum calculation and insertion are
- enabled, but pseudo header
+ enabled, but pseudo header
checksum is not
calculated in hardware */
#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 0x00030000U /*!< IP Header checksum and payload checksum calculation and insertion are
- enabled, and pseudo header
+ enabled, and pseudo header
checksum is
calculated in hardware. */
#define ETH_DMATXNDESCRF_TPL 0x0003FFFFU /*!< TCP Payload Length */
@@ -795,7 +791,6 @@
#define ETH_DMATXNDESCWBF_DB 0x00000002U /*!< Deferred Bit */
#define ETH_DMATXNDESCWBF_IHE 0x00000004U /*!< IP Header Error */
-
/*
DMA Tx Context Descriptor
-----------------------------------------------------------------------------------------------
@@ -846,7 +841,6 @@
* @}
*/
-
/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
* @{
*/
@@ -945,7 +939,6 @@
#define ETH_DMARXNDESCWBF_VF 0x00008000U /*!< VLAN Filter Status */
#define ETH_DMARXNDESCWBF_ARPNR 0x00000400U /*!< ARP Reply Not Generated */
-
/**
* @brief Bit definition of Rx normal descriptor register 3 write back format
*/
@@ -1475,7 +1468,7 @@
* @}
*/
-/** @defgroup HAL_ETH_StateTypeDef ETH States
+/** @defgroup ETH_State_Codes ETH States
* @{
*/
#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */
@@ -1490,11 +1483,12 @@
/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
* @{
*/
-#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */
-#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */
+#define HAL_ETH_PTP_NOT_CONFIGURED 0x00000000U /*!< ETH PTP Configuration not done */
+#define HAL_ETH_PTP_CONFIGURED 0x00000001U /*!< ETH PTP Configuration done */
/**
* @}
*/
+
/**
* @}
*/
@@ -1587,6 +1581,7 @@
* enabled @ref ETH_MAC_Interrupts
* @retval None
*/
+
#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
/**
@@ -1604,8 +1599,8 @@
* @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
* @retval The state of ETH MAC IT (SET or RESET).
*/
-#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &\
+ ( __INTERRUPT__)) == ( __INTERRUPT__))
/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
#define ETH_WAKEUP_EXTI_LINE 0x00400000U /* !< 86 - 64 = 22 */
@@ -1694,11 +1689,10 @@
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
-
#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
+
/**
* @}
*/
@@ -1747,7 +1741,7 @@
HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
@@ -1766,10 +1760,10 @@
HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
#endif /* HAL_ETH_USE_PTP */
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
uint32_t RegValue);
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
uint32_t *pRegValue);
@@ -1794,8 +1788,8 @@
*/
/* Peripheral Control functions **********************************************/
/* MAC & DMA Configuration APIs **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
@@ -1805,13 +1799,15 @@
uint32_t VLANIdentifier);
/* MAC L2 Packet Filtering APIs **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
+ const uint8_t *pMACAddr);
/* MAC Power Down APIs *****************************************************/
-void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
+ const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
@@ -1823,11 +1819,11 @@
* @{
*/
/* Peripheral State functions **************************************************/
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
+HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
+uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
/**
* @}
*/
@@ -1851,5 +1847,3 @@
#endif
#endif /* STM32H7xx_HAL_ETH_H */
-
-
diff --git a/Inc/stm32h7xx_hal_eth_ex.h b/Inc/stm32h7xx_hal_eth_ex.h
index b9580fa..4e229bc 100644
--- a/Inc/stm32h7xx_hal_eth_ex.h
+++ b/Inc/stm32h7xx_hal_eth_ex.h
@@ -314,32 +314,32 @@
/* MAC L3 L4 Filtering APIs ***************************************************/
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L3FilterConfigTypeDef *pL3FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L4FilterConfigTypeDef *pL4FilterConfig);
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
- ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+ const ETH_L3FilterConfigTypeDef *pL3FilterConfig);
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
- ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+ const ETH_L4FilterConfigTypeDef *pL4FilterConfig);
/* MAC VLAN Processing APIs ************************************************/
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
ETH_TxVLANConfigTypeDef *pVlanConfig);
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
- ETH_TxVLANConfigTypeDef *pVlanConfig);
+ const ETH_TxVLANConfigTypeDef *pVlanConfig);
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
/* Energy Efficient Ethernet APIs *********************************************/
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
FunctionalState TxClockStop);
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
-uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
+uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
/**
* @}
@@ -364,5 +364,3 @@
#endif
#endif /* STM32H7xx_HAL_ETH_EX_H */
-
-
diff --git a/Inc/stm32h7xx_hal_fdcan.h b/Inc/stm32h7xx_hal_fdcan.h
index 86bbc90..2d72d69 100644
--- a/Inc/stm32h7xx_hal_fdcan.h
+++ b/Inc/stm32h7xx_hal_fdcan.h
@@ -427,10 +427,10 @@
- 0 : Last received CAN FD message did not have its BRS flag set
- 1 : Last received CAN FD message had its BRS flag set */
- uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last
- protocol status.
+ uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
+ since last protocol status.
This parameter can be:
- - 0 : no CAN FD message received
+ - 0 : No CAN FD message received
- 1 : CAN FD message received */
uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
@@ -765,15 +765,15 @@
*/
typedef enum
{
- HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
- HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
- HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */
- HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */
- HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */
- HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */
+ HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
+ HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
+ HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */
+ HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */
+ HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */
+ HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */
- HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */
- HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */
+ HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */
+ HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */
} HAL_FDCAN_CallbackIDTypeDef;
@@ -874,21 +874,21 @@
* @{
*/
#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
-#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */
-#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */
-#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */
-#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */
-#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
-#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
-#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
-#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
-#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
-#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
-#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
-#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
-#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
-#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
-#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
+#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
+#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
+#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
/**
* @}
*/
@@ -968,21 +968,21 @@
* @{
*/
#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
-#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
-#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
-#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
-#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
-#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
-#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
-#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
-#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
-#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
-#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
-#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
-#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
-#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
-#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
-#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */
+#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */
+#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */
+#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */
+#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */
+#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */
+#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */
+#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
/**
* @}
*/
@@ -1221,7 +1221,7 @@
* @{
*/
#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
-#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
/**
* @}
*/
@@ -1666,9 +1666,9 @@
/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
* @{
*/
-#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
-#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
-#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
+#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
/**
* @}
*/
@@ -2234,8 +2234,8 @@
#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
-#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
-#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
+#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
((SIZE) == FDCAN_DATA_BYTES_12) || \
((SIZE) == FDCAN_DATA_BYTES_16) || \
diff --git a/Inc/stm32h7xx_hal_flash_ex.h b/Inc/stm32h7xx_hal_flash_ex.h
index 28bb380..1ca4e72 100644
--- a/Inc/stm32h7xx_hal_flash_ex.h
+++ b/Inc/stm32h7xx_hal_flash_ex.h
@@ -176,6 +176,20 @@
} FLASH_CRCInitTypeDef;
+#if (USE_FLASH_ECC == 1U)
+/**
+ * @brief ECC Info Structure definition
+ */
+typedef struct
+{
+ uint32_t Area; /*!< Area from which an ECC was detected.
+ This parameter can be a value of @ref FLASHEx_ECC_Area */
+
+ uint32_t Address; /*!< ECC error address */
+
+} FLASH_EccInfoTypeDef;
+#endif /* USE_FLASH_ECC */
+
/**
* @}
*/
@@ -216,6 +230,18 @@
* @}
*/
+#if (USE_FLASH_ECC == 1U)
+/** @defgroup FLASH_ECC_Area FLASH ECC Area
+ * @brief FLASH ECC Area
+ * @{
+ */
+#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
+#define FLASH_ECC_AREA_USER_BANK2 0x00000001U /*!< FLASH bank 2 area */
+/**
+ * @}
+ */
+#endif /* USE_FLASH_ECC */
+
/** @defgroup FLASHEx_Option_Type FLASH Option Type
* @{
*/
@@ -837,6 +863,38 @@
* @}
*/
+#if (USE_FLASH_ECC == 1U)
+/** @addtogroup FLASHEx_Exported_Functions_Group3
+ * @{
+ */
+void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
+void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
+void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void);
+void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void);
+#if defined (DUAL_BANK)
+void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void);
+void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void);
+#endif /* DUAL_BANK */
+
+void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
+void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
+void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void);
+void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void);
+#if defined (DUAL_BANK)
+void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void);
+void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void);
+#endif /* DUAL_BANK */
+
+void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
+void HAL_FLASHEx_BusFault_IRQHandler(void);
+
+__weak void HAL_FLASHEx_EccDetectionCallback(void);
+__weak void HAL_FLASHEx_EccCorrectionCallback(void);
+/**
+ * @}
+ */
+#endif /* USE_FLASH_ECC */
+
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_fmac.h b/Inc/stm32h7xx_hal_fmac.h
index 073bad9..bd37972 100644
--- a/Inc/stm32h7xx_hal_fmac.h
+++ b/Inc/stm32h7xx_hal_fmac.h
@@ -483,6 +483,22 @@
* @}
*/
+/* Private defines -----------------------------------------------------------*/
+/** @addtogroup FMAC_Private_Constants
+ * @{
+ */
+
+#define FMAC_PARAM_P_MAX_IIR 64U /*!< Maximum value of P parameter with IIR */
+#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */
+#define FMAC_PARAM_P_MIN 2U /*!< Minimum value of P parameter */
+#define FMAC_PARAM_Q_MAX 63U /*!< Maximum value of Q parameter */
+#define FMAC_PARAM_Q_MIN 1U /*!< Minimum value of Q parameter */
+#define FMAC_PARAM_R_MAX 7U /*!< Maximum value of R parameter */
+
+/**
+ * @}
+ */
+
/* Private Macros-----------------------------------------------------------*/
/** @addtogroup FMAC_Private_Macros FMAC Private Macros
* @{
@@ -549,10 +565,12 @@
* @param __FUNCTION__ ID of the filter function.
* @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
*/
-#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
- (((__P__) >= 2U) && ((__P__) <= 127U))) || \
- (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
- (((__P__) >= 2U) && ((__P__) <= 64U))) )
+#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
+ (((__P__) >= FMAC_PARAM_P_MIN) && \
+ ((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
+ (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+ (((__P__) >= FMAC_PARAM_P_MIN) && \
+ ((__P__) <= FMAC_PARAM_P_MAX_IIR))))
/**
* @brief Verify the FMAC filter parameter Q.
@@ -562,7 +580,7 @@
*/
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
- (((__Q__) >= 1U) && ((__Q__) <= 63U))) )
+ (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
/**
* @brief Verify the FMAC filter parameter R.
@@ -572,7 +590,7 @@
*/
#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
- ((__R__) <= 7U))
+ ((__R__) <= FMAC_PARAM_R_MAX))
/**
* @brief Verify the FMAC buffer access.
@@ -682,8 +700,8 @@
* @{
*/
/* Peripheral State functions *************************************************/
-HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
-uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
+uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_gpio_ex.h b/Inc/stm32h7xx_hal_gpio_ex.h
index 7a8edd3..9d6cb56 100644
--- a/Inc/stm32h7xx_hal_gpio_ex.h
+++ b/Inc/stm32h7xx_hal_gpio_ex.h
@@ -54,7 +54,12 @@
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
-#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
+#if defined(PWR_CPUCR_RETDS_CD) /* CPU domain power down Deepsleep */
+#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
+#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
+#define GPIO_AF0_NDSTOP2 ((uint8_t)0x00) /* NDSTOP2 Alternate Function mapping */
+#endif /* PWR_CPUCR_RETDS_CD */
+#if defined(PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
diff --git a/Inc/stm32h7xx_hal_hcd.h b/Inc/stm32h7xx_hal_hcd.h
index 7c853ca..b19622b 100644
--- a/Inc/stm32h7xx_hal_hcd.h
+++ b/Inc/stm32h7xx_hal_hcd.h
@@ -171,6 +171,9 @@
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT)
+#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT)
+#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN)
/**
* @}
*/
@@ -252,6 +255,11 @@
uint8_t token, uint8_t *pbuff,
uint16_t length, uint8_t do_ping);
+HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t addr, uint8_t PortNbr);
+
+HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+
/* Non-Blocking mode: Interrupt */
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
@@ -280,10 +288,10 @@
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
diff --git a/Inc/stm32h7xx_hal_i2c.h b/Inc/stm32h7xx_hal_i2c.h
index f2649b5..c524cbc 100644
--- a/Inc/stm32h7xx_hal_i2c.h
+++ b/Inc/stm32h7xx_hal_i2c.h
@@ -118,8 +118,6 @@
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
@@ -207,6 +205,7 @@
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
@@ -804,8 +803,8 @@
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
- (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
- (~I2C_CR2_RD_WRN)))
+ (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+ (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
diff --git a/Inc/stm32h7xx_hal_jpeg.h b/Inc/stm32h7xx_hal_jpeg.h
index d2ecdf8..0e3ccf8 100644
--- a/Inc/stm32h7xx_hal_jpeg.h
+++ b/Inc/stm32h7xx_hal_jpeg.h
@@ -289,7 +289,7 @@
* @brief JPEG Flags definition
* @{
*/
-#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is below its threshold flag */
#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */
#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */
#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */
@@ -357,7 +357,7 @@
* @param __HANDLE__ specifies the JPEG handle.
* @param __FLAG__ specifies the flag to check
* This parameter can be one of the following values:
- * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
+ * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is below its threshold flag
* @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
* @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
* @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
diff --git a/Inc/stm32h7xx_hal_lptim.h b/Inc/stm32h7xx_hal_lptim.h
index 4a97f27..59517aa 100644
--- a/Inc/stm32h7xx_hal_lptim.h
+++ b/Inc/stm32h7xx_hal_lptim.h
@@ -436,6 +436,7 @@
* @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
+ * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
* @retval None
* @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
@@ -657,7 +658,7 @@
* @{
*/
/* Peripheral State functions ************************************************/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
@@ -750,9 +751,6 @@
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\
- ((__AUTORELOAD__) <= 0x0000FFFFUL))
-
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\
diff --git a/Inc/stm32h7xx_hal_ltdc.h b/Inc/stm32h7xx_hal_ltdc.h
index 0eaa415..d5b4a66 100644
--- a/Inc/stm32h7xx_hal_ltdc.h
+++ b/Inc/stm32h7xx_hal_ltdc.h
@@ -338,14 +338,14 @@
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
-#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
+#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_nand.h b/Inc/stm32h7xx_hal_nand.h
index fdf845a..7290893 100644
--- a/Inc/stm32h7xx_hal_nand.h
+++ b/Inc/stm32h7xx_hal_nand.h
@@ -104,9 +104,8 @@
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
- Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
- Please check the Read Mode sequnece in the NAND device datasheet */
+ Please check the Read Mode sequence in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
@@ -126,7 +125,7 @@
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
- NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
+ NAND_DeviceConfigTypeDef Config; /*!< NAND physical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
@@ -214,27 +213,27 @@
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
@@ -264,8 +263,8 @@
* @{
*/
/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_nor.h b/Inc/stm32h7xx_hal_nor.h
index 1ef78f4..de0494b 100644
--- a/Inc/stm32h7xx_hal_nor.h
+++ b/Inc/stm32h7xx_hal_nor.h
@@ -233,7 +233,7 @@
*/
/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
diff --git a/Inc/stm32h7xx_hal_ospi.h b/Inc/stm32h7xx_hal_ospi.h
index 78e991a..6f96b60 100644
--- a/Inc/stm32h7xx_hal_ospi.h
+++ b/Inc/stm32h7xx_hal_ospi.h
@@ -21,7 +21,7 @@
#define STM32H7xx_HAL_OSPI_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -90,7 +90,7 @@
uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
Refresh+1 clock cycles.
This parameter can be a value between 0 and 0xFFFFFFFF */
-}OSPI_InitTypeDef;
+} OSPI_InitTypeDef;
/**
* @brief HAL OSPI Handle Structure definition
@@ -111,21 +111,21 @@
__IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
uint32_t Timeout; /*!< Timeout used for the OSPI external device access */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
- void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
+ void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
- void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi);
+ void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi);
- void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi);
- void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi);
+ void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi);
+ void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
-}OSPI_HandleTypeDef;
+} OSPI_HandleTypeDef;
/**
* @brief HAL OSPI Regular Command Structure definition
@@ -176,7 +176,7 @@
This parameter can be a value of @ref OSPI_DQSMode */
uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
This parameter can be a value of @ref OSPI_SIOOMode */
-}OSPI_RegularCmdTypeDef;
+} OSPI_RegularCmdTypeDef;
/**
* @brief HAL OSPI Hyperbus Configuration Structure definition
@@ -191,7 +191,7 @@
This parameter can be a value of @ref OSPI_WriteZeroLatency */
uint32_t LatencyMode; /*!< It configures the latency mode.
This parameter can be a value of @ref OSPI_LatencyMode */
-}OSPI_HyperbusCfgTypeDef;
+} OSPI_HyperbusCfgTypeDef;
/**
* @brief HAL OSPI Hyperbus Command Structure definition
@@ -210,7 +210,7 @@
In case of autopolling mode, this parameter can be any value between 1 and 4 */
uint32_t DQSMode; /*!< It enables or not the data strobe management.
This parameter can be a value of @ref OSPI_DQSMode */
-}OSPI_HyperbusCmdTypeDef;
+} OSPI_HyperbusCmdTypeDef;
/**
* @brief HAL OSPI Auto Polling mode configuration structure definition
@@ -227,7 +227,7 @@
This parameter can be a value of @ref OSPI_AutomaticStop */
uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases.
This parameter can be any value between 0 and 0xFFFF */
-}OSPI_AutoPollingTypeDef;
+} OSPI_AutoPollingTypeDef;
/**
* @brief HAL OSPI Memory Mapped mode configuration structure definition
@@ -238,7 +238,7 @@
This parameter can be a value of @ref OSPI_TimeOutActivation */
uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
-}OSPI_MemoryMappedTypeDef;
+} OSPI_MemoryMappedTypeDef;
/**
* @brief HAL OSPI IO Manager Configuration structure definition
@@ -258,7 +258,7 @@
uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected
if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
This parameter can be a value between 1 and 256 */
-}OSPIM_CfgTypeDef;
+} OSPIM_CfgTypeDef;
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/**
@@ -279,7 +279,7 @@
HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */
HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */
-}HAL_OSPI_CallbackIDTypeDef;
+} HAL_OSPI_CallbackIDTypeDef;
/**
* @brief HAL OSPI Callback pointer definition
@@ -790,10 +790,10 @@
/** @addtogroup OSPI_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi);
/**
* @}
@@ -804,7 +804,7 @@
* @{
*/
/* OSPI IRQ handler function */
-void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi);
/* OSPI command configuration functions */
HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
@@ -825,25 +825,25 @@
HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
/* OSPI memory-mapped mode functions */
-HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
+HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
/* Callback functions in non-blocking modes ***********************************/
-void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi);
void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
/* OSPI indirect mode functions */
-void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
-void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
/* OSPI status flag polling mode functions */
-void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi);
/* OSPI memory-mapped mode functions */
-void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi);
+void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi);
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/* OSPI callback registering/unregistering */
@@ -859,13 +859,13 @@
/** @addtogroup OSPI_Exported_Functions_Group3
* @{
*/
-HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
-uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
-uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi);
-uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
+uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
+uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi);
+uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi);
/**
* @}
diff --git a/Inc/stm32h7xx_hal_pcd.h b/Inc/stm32h7xx_hal_pcd.h
index c622c97..f1fe87f 100644
--- a/Inc/stm32h7xx_hal_pcd.h
+++ b/Inc/stm32h7xx_hal_pcd.h
@@ -352,10 +352,10 @@
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
-HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode);
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
/**
* @}
*/
@@ -364,7 +364,7 @@
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_pssi.h b/Inc/stm32h7xx_hal_pssi.h
index 69840ad..0fde68c 100644
--- a/Inc/stm32h7xx_hal_pssi.h
+++ b/Inc/stm32h7xx_hal_pssi.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2017 STMicroelectronics.
+ * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -31,6 +31,12 @@
* @{
*/
#if defined(PSSI)
+
+#ifndef USE_HAL_PSSI_REGISTER_CALLBACKS
+/* For backward compatibility, if USE_HAL_PSSI_REGISTER_CALLBACKS not defined, define it to 1*/
+#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
/** @addtogroup PSSI PSSI
* @brief PSSI HAL module driver
* @{
@@ -47,12 +53,18 @@
*/
typedef struct
{
- uint32_t DataWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
- uint32_t BusWidth; /* !< Configures the parallel bus width 8 lines or 16 lines */
- uint32_t ControlSignal; /* !< Configures Data enable and Data ready */
- uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity */
- uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */
- uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity */
+ uint32_t DataWidth; /* !< Configures the data width.
+ This parameter can be a value of @ref PSSI_DATA_WIDTH. */
+ uint32_t BusWidth; /* !< Configures the parallel bus width.
+ This parameter can be a value of @ref PSSI_BUS_WIDTH. */
+ uint32_t ControlSignal; /* !< Configures Data enable and Data ready.
+ This parameter can be a value of @ref ControlSignal_Configuration. */
+ uint32_t ClockPolarity; /* !< Configures the PSSI Input Clock polarity.
+ This parameter can be a value of @ref Clock_Polarity. */
+ uint32_t DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity.
+ This parameter can be a value of @ref Data_Enable_Polarity. */
+ uint32_t ReadyPolarity; /* !< Configures the PSSI Ready polarity.
+ This parameter can be a value of @ref Ready_Polarity. */
} PSSI_InitTypeDef;
@@ -76,16 +88,23 @@
/**
* @brief PSSI handle Structure definition
*/
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
typedef struct __PSSI_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
{
PSSI_TypeDef *Instance; /*!< PSSI register base address. */
PSSI_InitTypeDef Init; /*!< PSSI Initialization Structure. */
uint32_t *pBuffPtr; /*!< PSSI Data buffer. */
uint32_t XferCount; /*!< PSSI transfer count */
uint32_t XferSize; /*!< PSSI transfer size */
+#if defined(HAL_DMA_MODULE_ENABLED)
DMA_HandleTypeDef *hdmatx; /*!< PSSI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< PSSI Rx DMA Handle parameters */
+#endif /*HAL_DMA_MODULE_ENABLED*/
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer complete callback. */
@@ -93,6 +112,7 @@
void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp Init callback. */
void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback. */
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
HAL_LockTypeDef Lock; /*!< PSSI lock. */
__IO HAL_PSSI_StateTypeDef State; /*!< PSSI transfer state. */
@@ -100,7 +120,7 @@
} PSSI_HandleTypeDef;
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/**
* @brief HAL PSSI Callback pointer definition
*/
@@ -120,7 +140,7 @@
HAL_PSSI_MSPDEINIT_CB_ID = 0x06U /*!< PSSI Msp DeInit callback ID */
} HAL_PSSI_CallbackIDTypeDef;
-
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
/**
* @}
@@ -140,8 +160,9 @@
#define HAL_PSSI_ERROR_OVER_RUN 0x00000004U /*!< FIFO Over-run error */
#define HAL_PSSI_ERROR_DMA 0x00000008U /*!< Dma error */
#define HAL_PSSI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error */
-
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
/**
* @}
@@ -201,7 +222,7 @@
/**
* @}
*/
-/** @defgroup Reday_Polarity Reday Polarity
+/** @defgroup Ready_Polarity Ready Polarity
* @{
*/
#define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */
@@ -215,8 +236,6 @@
*/
#define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */
#define HAL_PSSI_RISING_EDGE 0x1U /*!< Rising Edge */
-
-
/**
* @}
*/
@@ -238,7 +257,7 @@
#define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */
#define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */
-#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag*/
+#define PSSI_FLAG_RTT1B PSSI_SR_RTT1B /*!< 1 Byte Fifo Flag */
#define PSSI_FLAG_RTT4B PSSI_SR_RTT4B /*!< 4 Bytes Fifo Flag*/
@@ -272,12 +291,15 @@
* @param __HANDLE__ specifies the PSSI handle.
* @retval None
*/
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
}while(0)
+#else
+#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PSSI_STATE_RESET)
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
/**
@@ -414,6 +436,7 @@
#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \
((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH ))
+
/**
* @}
*/
@@ -434,11 +457,11 @@
void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
/* Callbacks Register/UnRegister functions ***********************************/
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
pPSSI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
-
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
/**
* @}
@@ -452,9 +475,11 @@
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @}
@@ -465,8 +490,8 @@
*/
/* Peripheral State functions ***************************************************/
-HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
-uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi);
+uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi);
/**
* @}
@@ -482,7 +507,6 @@
void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
-
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_qspi.h b/Inc/stm32h7xx_hal_qspi.h
index 39eb5fa..98b2c5c 100644
--- a/Inc/stm32h7xx_hal_qspi.h
+++ b/Inc/stm32h7xx_hal_qspi.h
@@ -617,13 +617,13 @@
* @{
*/
/* Peripheral Control and State functions ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
-uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi);
+uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
/**
* @}
diff --git a/Inc/stm32h7xx_hal_ramecc.h b/Inc/stm32h7xx_hal_ramecc.h
index 37a90de..f9444eb 100644
--- a/Inc/stm32h7xx_hal_ramecc.h
+++ b/Inc/stm32h7xx_hal_ramecc.h
@@ -57,13 +57,19 @@
/**
* @brief RAMECC handle Structure definition
*/
-
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
typedef struct __RAMECC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
{
- RAMECC_MonitorTypeDef *Instance; /*!< Register base address */
- __IO HAL_RAMECC_StateTypeDef State; /*!< RAMECC state */
- __IO uint32_t ErrorCode; /*!< RAMECC Error Code */
- void (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC error detect callback */
+ RAMECC_MonitorTypeDef *Instance; /*!< Register base address */
+ __IO HAL_RAMECC_StateTypeDef State; /*!< RAMECC state */
+ __IO uint32_t ErrorCode; /*!< RAMECC Error Code */
+ __IO uint32_t RAMECCErrorCode; /*!< RAMECC Detected Error Code */
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
+ void (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc); /*!< RAMECC Error Detect callback */
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
}RAMECC_HandleTypeDef;
/**
@@ -81,7 +87,20 @@
#define HAL_RAMECC_ERROR_NONE 0x00000000U /*!< RAMECC No Error */
#define HAL_RAMECC_ERROR_TIMEOUT 0x00000001U /*!< RAMECC Timeout Error */
#define HAL_RAMECC_ERROR_BUSY 0x00000002U /*!< RAMECC Busy Error */
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
#define HAL_RAMECC_ERROR_INVALID_CALLBACK 0x00000003U /*!< Invalid Callback error */
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
+
+/**
+ * @}
+ */
+
+/** @defgroup RAMECC_Error_Codes RAMECC Error Detected Codes
+ * @{
+ */
+#define HAL_RAMECC_NO_ERROR 0x00000000U /*!< RAMECC No Error Detected */
+#define HAL_RAMECC_SINGLEERROR_DETECTED 0x00000001U /*!< RAMECC Single Error Detected */
+#define HAL_RAMECC_DOUBLEERROR_DETECTED 0x00000002U /*!< RAMECC Double Error Detected */
/**
* @}
*/
@@ -135,15 +154,15 @@
* @param __HANDLE__ : RAMECC handle.
* @param __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
- * @arg RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
- * @arg RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
- * @arg RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
- * @arg RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
- * @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
- * @arg RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
- * @arg RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
- * @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
- * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
+ * @arg RAMECC_IT_GLOBAL_ENABLE : Global interrupt enable mask.
+ * @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
+ * @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable.
+ * @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable.
+ * @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable.
+ * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
* @retval None
*/
#define __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( \
@@ -159,15 +178,15 @@
* @param __HANDLE__ : RAMECC handle.
* @param __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
- * @arg RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
- * @arg RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
- * @arg RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
- * @arg RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
- * @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
- * @arg RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
- * @arg RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
- * @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
- * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
+ * @arg RAMECC_IT_GLOBAL_ENABLE : Global interrupt enable mask.
+ * @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
+ * @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable.
+ * @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable.
+ * @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable.
+ * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
* @retval None
*/
#define __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ( \
@@ -183,15 +202,15 @@
* @param __HANDLE__ : Specifies the RAMECC Handle.
* @param __INTERRUPT__ : Specifies the RAMECC interrupt source to check.
* This parameter can be one of the following values:
- * @arg RAMECC_IT_GLOBAL_E : Global interrupt enable mask.
- * @arg RAMECC_IT_GLOBAL_SEE : Global ECC single error interrupt enable.
- * @arg RAMECC_IT_GLOBAL_DEE : Global ECC double error interrupt enable.
- * @arg RAMECC_IT_GLOBAL_DEBWE : Global ECC double error on byte write (BW) interrupt enable.
- * @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
- * @arg RAMECC_IT_MONITOR_SEE : Monitor ECC single error interrupt enable.
- * @arg RAMECC_IT_MONITOR_DEE : Monitor ECC double error interrupt enable.
- * @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
- * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
+ * @arg RAMECC_IT_GLOBAL_ENABLE : Global interrupt enable mask.
+ * @arg RAMECC_IT_GLOBAL_SINGLEERR_R : Global ECC single error interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_DOUBLEERR_R : Global ECC double error interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_DOUBLEERR_W : Global ECC double error on byte write (BW) interrupt enable.
+ * @arg RAMECC_IT_GLOBAL_ALL : All Global ECC interrupts enable mask.
+ * @arg RAMECC_IT_MONITOR_SINGLEERR_R : Monitor ECC single error interrupt enable.
+ * @arg RAMECC_IT_MONITOR_DOUBLEERR_R : Monitor ECC double error interrupt enable.
+ * @arg RAMECC_IT_MONITOR_DOUBLEERR_W : Monitor ECC double error on byte write (BW) interrupt enable.
+ * @arg RAMECC_IT_MONITOR_ALL : All Monitor ECC interrupts enable mask.
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ( \
@@ -204,10 +223,10 @@
* @param __HANDLE__ : RAMECC handle.
* @param __FLAG__ : specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg RAMECC_FLAG_SEDCF : RAMECC instance ECC single error detected and corrected flag.
- * @arg RAMECC_FLAG_DEDF : RAMECC instance ECC double error detected flag.
- * @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
- * @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
+ * @arg RAMECC_FLAG_SINGLEERR_R : RAMECC instance ECC single error detected and corrected flag.
+ * @arg RAMECC_FLAG_DOUBLEERR_R : RAMECC instance ECC double error detected flag.
+ * @arg RAMECC_FLAG_DOUBLEERR_W : RAMECC instance ECC double error on byte write (BW) detected flag.
+ * @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
* @retval The state of __FLAG__ (SET or RESET).
*/
#define __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))
@@ -218,10 +237,10 @@
* @param __HANDLE__ : RAMECC handle.
* @param __FLAG__ : specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg RAMECC_FLAG_SEDCF : RAMECC instance ECC single error detected and corrected flag.
- * @arg RAMECC_FLAG_DEDF : RAMECC instance ECC double error detected flag.
- * @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
- * @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
+ * @arg RAMECC_FLAG_SINGLEERR_R : RAMECC instance ECC single error detected and corrected flag.
+ * @arg RAMECC_FLAG_DOUBLEERR_R : RAMECC instance ECC double error detected flag.
+ * @arg RAMECC_FLAG_DOUBLEERR_W : RAMECC instance ECC double error on byte write (BW) detected flag.
+ * @arg RAMECC_FLAGS_ALL : RAMECC instance all flag.
* @retval None.
*/
#define __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
@@ -247,8 +266,8 @@
* @brief Initialization and de-initialization functions
* @{
*/
-HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc);
/**
* @}
*/
@@ -257,37 +276,50 @@
* @brief monitoring operation functions
* @{
*/
-HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
-HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
-void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
-HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
+HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
+
/**
* @}
*/
-/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions
+/** @defgroup RAMECC_Exported_Functions_Group3 handle Interrupt and Callbacks Functions
+ * @brief handle Interrupt and Callbacks Functions
+ * @{
+ */
+void HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc);
+void HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc);
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RAMECC_RegisterCallback(RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
+HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc);
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
+/**
+ * @}
+ */
+
+/** @defgroup RAMECC_Exported_Functions_Group4 Error information functions
* @brief Error information functions
* @{
*/
-uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc);
/**
* @}
*/
-/** @defgroup RAMECC_Exported_Functions_Group4 State and Error Functions
+/** @defgroup RAMECC_Exported_Functions_Group5 State and Error Functions
* @brief State and Error Functions
* @{
*/
-HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
+HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc);
/**
* @}
*/
@@ -350,4 +382,3 @@
#endif
#endif /* STM32H7xx_HAL_RAMECC_H */
-
diff --git a/Inc/stm32h7xx_hal_rng.h b/Inc/stm32h7xx_hal_rng.h
index ed7fe5e..e7dd55a 100644
--- a/Inc/stm32h7xx_hal_rng.h
+++ b/Inc/stm32h7xx_hal_rng.h
@@ -319,7 +319,7 @@
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
@@ -332,8 +332,8 @@
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
* @{
*/
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_rng_ex.h b/Inc/stm32h7xx_hal_rng_ex.h
index 028f71e..ee43ec1 100644
--- a/Inc/stm32h7xx_hal_rng_ex.h
+++ b/Inc/stm32h7xx_hal_rng_ex.h
@@ -196,14 +196,14 @@
*/
/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
+/** @addtogroup RNG_Ex_Exported_Functions
* @{
*/
/** @addtogroup RNG_Ex_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
diff --git a/Inc/stm32h7xx_hal_rtc_ex.h b/Inc/stm32h7xx_hal_rtc_ex.h
index 23ed81a..bb29abe 100644
--- a/Inc/stm32h7xx_hal_rtc_ex.h
+++ b/Inc/stm32h7xx_hal_rtc_ex.h
@@ -936,22 +936,6 @@
#endif /* TAMP */
/**
- * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__ specifies the RTC handle.
- * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F: Tamper1 interrupt flag
- * @arg RTC_FLAG_TAMP2F: Tamper2 interrupt flag
- * @arg RTC_FLAG_TAMP3F: Tamper3 interrupt flag
- * @retval Flag status
- */
-#if defined(TAMP)
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#else
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* TAMP */
-
-/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
diff --git a/Inc/stm32h7xx_hal_smbus.h b/Inc/stm32h7xx_hal_smbus.h
index dcdbc8a..a36f58c 100644
--- a/Inc/stm32h7xx_hal_smbus.h
+++ b/Inc/stm32h7xx_hal_smbus.h
@@ -100,8 +100,6 @@
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
diff --git a/Inc/stm32h7xx_hal_spdifrx.h b/Inc/stm32h7xx_hal_spdifrx.h
index 99d17c4..7c58960 100644
--- a/Inc/stm32h7xx_hal_spdifrx.h
+++ b/Inc/stm32h7xx_hal_spdifrx.h
@@ -56,7 +56,8 @@
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
- uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
+ uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status
+ from channel A or B.
This parameter can be a value of @ref SPDIFRX_Channel_Selection */
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
@@ -65,22 +66,25 @@
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
- uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PT_Mask */
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
+ into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
- uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
+ into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_V_Mask */
- uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
+ into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
FunctionalState SymbolClockGen; /*!< Enable/Disable the SPDIFRX Symbol Clock generation.
- This parameter can be set to Enable or Disable */
+ This parameter can be set to Enable or Disable */
FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.
- This parameter can be set to Enable or Disable */
+ This parameter can be set to Enable or Disable */
} SPDIFRX_InitTypeDef;
/**
@@ -94,17 +98,20 @@
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
- uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PT_Mask */
+ uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not
+ into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PT_Mask */
- uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+ uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not
+ into the received frame.
+ This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_V_Mask */
+ This parameter can be a value of @ref SPDIFRX_V_Mask */
- uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
- This parameter can be a value of @ref SPDIFRX_PE_Mask */
+ uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not
+ into the received frame.
+ This parameter can be a value of @ref SPDIFRX_PE_Mask */
} SPDIFRX_SetDataFormatTypeDef;
@@ -156,7 +163,8 @@
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
- DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
+ DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information
+ DMA handle parameters */
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
@@ -167,9 +175,11 @@
__IO uint32_t ErrorCode; /* SPDIFRX Error code */
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
- void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed callback */
+ void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed
+ callback */
void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */
- void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */
+ void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed
+ callback */
void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */
void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */
void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */
@@ -177,9 +187,6 @@
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
} SPDIFRX_HandleTypeDef;
-/**
- * @}
- */
#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
/**
@@ -199,9 +206,12 @@
/**
* @brief HAL SPDIFRX Callback pointer definition
*/
-typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */
+typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback
+ function */
#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
-
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
* @{
@@ -265,8 +275,10 @@
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
* @{
*/
-#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
-#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
+#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied
+ into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied
+ into the SPDIF_DR, zeros are written instead*/
/**
* @}
*/
diff --git a/Inc/stm32h7xx_hal_spi.h b/Inc/stm32h7xx_hal_spi.h
index 77578d1..71a7b1d 100644
--- a/Inc/stm32h7xx_hal_spi.h
+++ b/Inc/stm32h7xx_hal_spi.h
@@ -1091,8 +1091,11 @@
((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
((LENGTH) == SPI_CRC_LENGTH_4BIT))
+
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL)
+#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL)
+
#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
diff --git a/Inc/stm32h7xx_hal_sram.h b/Inc/stm32h7xx_hal_sram.h
index 4c17a6a..b50dc29 100644
--- a/Inc/stm32h7xx_hal_sram.h
+++ b/Inc/stm32h7xx_hal_sram.h
@@ -204,7 +204,7 @@
*/
/* SRAM State functions ******************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
/**
* @}
diff --git a/Inc/stm32h7xx_hal_tim.h b/Inc/stm32h7xx_hal_tim.h
index 6daa529..8f49df2 100644
--- a/Inc/stm32h7xx_hal_tim.h
+++ b/Inc/stm32h7xx_hal_tim.h
@@ -406,29 +406,28 @@
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@@ -1037,8 +1036,8 @@
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
-#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
-#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
+#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
+#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
/**
* @}
*/
@@ -1864,6 +1863,10 @@
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8))
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
+ ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
+ ((__CHANNEL__) != (TIM_CHANNEL_6)))
+
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE))
@@ -1884,8 +1887,9 @@
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
-#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
- ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+ (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
+ ((__PERIOD__) > 0U))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
@@ -1938,7 +1942,6 @@
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
@@ -2009,8 +2012,8 @@
((__MODE__) == TIM_OCMODE_PWM2) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
- ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
+ ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
((__MODE__) == TIM_OCMODE_ACTIVE) || \
@@ -2304,7 +2307,7 @@
* @{
*/
/* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
@@ -2353,7 +2356,8 @@
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
diff --git a/Inc/stm32h7xx_hal_tim_ex.h b/Inc/stm32h7xx_hal_tim_ex.h
index ebad016..0943858 100644
--- a/Inc/stm32h7xx_hal_tim_ex.h
+++ b/Inc/stm32h7xx_hal_tim_ex.h
@@ -471,7 +471,7 @@
#if defined(TIM_BDTR_BKBID)
HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
-HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
#endif /* TIM_BDTR_BKBID */
/**
* @}
diff --git a/Inc/stm32h7xx_hal_uart_ex.h b/Inc/stm32h7xx_hal_uart_ex.h
index a9415bc..5344695 100644
--- a/Inc/stm32h7xx_hal_uart_ex.h
+++ b/Inc/stm32h7xx_hal_uart_ex.h
@@ -178,7 +178,7 @@
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/**
diff --git a/Inc/stm32h7xx_hal_usart.h b/Inc/stm32h7xx_hal_usart.h
index ffb8f7b..518c0aa 100644
--- a/Inc/stm32h7xx_hal_usart.h
+++ b/Inc/stm32h7xx_hal_usart.h
@@ -144,7 +144,7 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
- uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
+ uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
of @ref USARTEx_Slave_Mode */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
diff --git a/Inc/stm32h7xx_hal_usart_ex.h b/Inc/stm32h7xx_hal_usart_ex.h
index 4cf7061..4db6566 100644
--- a/Inc/stm32h7xx_hal_usart_ex.h
+++ b/Inc/stm32h7xx_hal_usart_ex.h
@@ -45,7 +45,7 @@
* @{
*/
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
diff --git a/Inc/stm32h7xx_ll_adc.h b/Inc/stm32h7xx_ll_adc.h
index fc1f852..ac75a15 100644
--- a/Inc/stm32h7xx_ll_adc.h
+++ b/Inc/stm32h7xx_ll_adc.h
@@ -386,7 +386,14 @@
#endif /* ADC_VER_V5_3 */
#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx)
+#define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor ,
+ temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
+ 110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */
+#else
+#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been
+ calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */
#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
diff --git a/Inc/stm32h7xx_ll_bdma.h b/Inc/stm32h7xx_ll_bdma.h
index fd48624..8db1b7c 100644
--- a/Inc/stm32h7xx_ll_bdma.h
+++ b/Inc/stm32h7xx_ll_bdma.h
@@ -77,70 +77,79 @@
*/
typedef struct
{
- uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer
- or as Source base address in case of memory to memory transfer direction.
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer
+ or as Source base address in case of memory to memory transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
- uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
- or as Destination base address in case of memory to memory transfer direction.
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
- uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- This parameter can be a value of @ref BDMA_LL_EC_MODE
- @note: The circular buffer mode cannot be used if the memory to memory
- data transfer direction is configured on the selected Channel
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref BDMA_LL_EC_MODE
+ @note: The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Channel
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
- uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref BDMA_LL_EC_PERIPH
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref BDMA_LL_EC_PERIPH
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
- uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref BDMA_LL_EC_MEMORY
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref BDMA_LL_EC_MEMORY
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
- uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
- uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
- uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
- The data unit is equal to the source buffer configuration set in PeripheralSize
- or MemorySize parameters depending in the transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
- uint32_t PeriphRequest; /*!< Specifies the peripheral request.
- This parameter can be a value of @ref DMAMUX2_Request_selection
+ uint32_t PeriphRequest; /*!< Specifies the peripheral request.
+ This parameter can be a value of @ref DMAMUX2_Request_selection
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
- uint32_t Priority; /*!< Specifies the channel priority level.
- This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
- This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
+ uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
+ This parameter can be a value of @ref BDMA_LL_EC_DOUBLEBUFFER_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_EnableDoubleBufferMode() & LL_BDMA_DisableDoubleBufferMode(). */
+
+ uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
+ This parameter can be a value of @ref BDMA_LL_EC_CURRENTTARGETMEM
+
+ This feature can be modified afterwards using unitary function @ref LL_BDMA_SetCurrentTargetMem(). */
} LL_BDMA_InitTypeDef;
/**
* @}
@@ -275,7 +284,7 @@
* @}
*/
-/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+/** @defgroup BDMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
* @{
*/
#define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
@@ -284,6 +293,15 @@
* @}
*/
+/** @defgroup BDMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+ * @{
+ */
+#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
+#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
+/**
+ * @}
+ */
+
/** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode
* @{
*/
@@ -333,14 +351,6 @@
* @}
*/
-/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
- * @{
- */
-#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
-#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
-/**
- * @}
- */
/**
* @}
@@ -549,7 +559,9 @@
* CCR MINC LL_BDMA_ConfigTransfer\n
* CCR PSIZE LL_BDMA_ConfigTransfer\n
* CCR MSIZE LL_BDMA_ConfigTransfer\n
- * CCR PL LL_BDMA_ConfigTransfer
+ * CCR PL LL_BDMA_ConfigTransfer\n
+ * CCR DBM LL_BDMA_ConfigTransfer\n
+ * CCR CT LL_BDMA_ConfigTransfer
* @param BDMAx BDMA Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_BDMA_CHANNEL_0
@@ -568,6 +580,8 @@
* @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD
* @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD
* @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH
+ * @arg @ref LL_BDMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_BDMA_DOUBLEBUFFER_MODE_ENABLE
+ * @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1
* @retval None
*/
__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
@@ -575,8 +589,8 @@
uint32_t bdma_base_addr = (uint32_t)BDMAx;
MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
- BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
- Configuration);
+ BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL | \
+ BDMA_CCR_DBM | BDMA_CCR_CT, Configuration);
}
/**
@@ -1095,6 +1109,28 @@
}
/**
+ * @brief Check if double buffer mode is enabled or not.
+ * @rmtoll CCR DBM LL_BDMA_IsEnabledDoubleBufferMode
+ * @param BDMAx BDMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_BDMA_CHANNEL_0
+ * @arg @ref LL_BDMA_CHANNEL_1
+ * @arg @ref LL_BDMA_CHANNEL_2
+ * @arg @ref LL_BDMA_CHANNEL_3
+ * @arg @ref LL_BDMA_CHANNEL_4
+ * @arg @ref LL_BDMA_CHANNEL_5
+ * @arg @ref LL_BDMA_CHANNEL_6
+ * @arg @ref LL_BDMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
+{
+ register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+
+ return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM) == (BDMA_CCR_DBM)) ? 1UL : 0UL);
+}
+
+/**
* @brief Configure the Source and Destination addresses.
* @note This API must not be called when the BDMA channel is enabled.
* @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr).
diff --git a/Inc/stm32h7xx_ll_comp.h b/Inc/stm32h7xx_ll_comp.h
index 0598966..0d342c5 100644
--- a/Inc/stm32h7xx_ll_comp.h
+++ b/Inc/stm32h7xx_ll_comp.h
@@ -819,6 +819,91 @@
* @}
*/
+/** @defgroup COMP_LL_EF_FLAG_Management Comparator flag Management
+ * @{
+ */
+
+/**
+ * @brief Get comparator output trigger flag (latched)
+ * @rmtoll SR C1IF LL_COMP_IsActiveFlag_OutputTrig
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx)
+{
+ if (COMPx == COMP1)
+ {
+ return ((READ_BIT(COMP12->SR, COMP_SR_C1IF) == (COMP_SR_C1IF)) ? 1UL : 0UL);
+ }
+ else
+ {
+ return ((READ_BIT(COMP12->SR, COMP_SR_C2IF) == (COMP_SR_C2IF)) ? 1UL : 0UL);
+ }
+}
+
+/**
+ * @brief Clear comparator comparator output trigger flag (latched)
+ * @rmtoll ICFR CC1IF LL_COMP_ClearFlag_OutputTrig
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx)
+{
+ if (COMPx == COMP1)
+ {
+ SET_BIT(COMP12->ICFR, COMP_ICFR_C1IF);
+ }
+ else
+ {
+ SET_BIT(COMP12->ICFR, COMP_ICFR_C2IF);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup COMP_LL_EF_IT_Management Comparartor IT management
+ * @{
+ */
+
+/**
+ * @brief Enable comparator output trigger interrupt
+ * @rmtoll ICFR ITEN LL_COMP_EnableIT_OutputTrig
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_EnableIT_OutputTrig(COMP_TypeDef *COMPx)
+{
+ SET_BIT(COMPx->CFGR, COMP_CFGRx_ITEN);
+}
+
+/**
+ * @brief Disable comparator output trigger interrupt
+ * @rmtoll ICFR ITEN LL_COMP_DisableIT_OutputTrig
+ * @param COMPx Comparator instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx)
+{
+ CLEAR_BIT(COMPx->CFGR, COMP_CFGRx_ITEN);
+}
+
+/**
+ * @brief Get comparator output trigger interrupt state
+ * @rmtoll ICFR ITEN LL_COMP_IsEnabledIT_OutputTrig
+ * @param COMPx Comparator instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(COMP_TypeDef *COMPx)
+{
+ return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_ITEN) == (COMP_CFGRx_ITEN)) ? 1UL : 0UL);
+}
+
+/**
+ * @}
+ */
+
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
* @{
diff --git a/Inc/stm32h7xx_ll_crc.h b/Inc/stm32h7xx_ll_crc.h
index 6c6de8f..7c5aa20 100644
--- a/Inc/stm32h7xx_ll_crc.h
+++ b/Inc/stm32h7xx_ll_crc.h
@@ -184,7 +184,7 @@
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
@@ -215,7 +215,7 @@
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
-__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
@@ -242,7 +242,7 @@
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
-__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
@@ -270,7 +270,7 @@
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
-__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
@@ -301,7 +301,7 @@
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
@@ -359,7 +359,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
@@ -371,7 +371,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
-__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
@@ -383,7 +383,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
-__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
@@ -395,7 +395,7 @@
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
-__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
@@ -407,7 +407,7 @@
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
*/
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
@@ -433,7 +433,7 @@
* @{
*/
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
/**
* @}
diff --git a/Inc/stm32h7xx_ll_dac.h b/Inc/stm32h7xx_ll_dac.h
index f4a2efd..0059a34 100644
--- a/Inc/stm32h7xx_ll_dac.h
+++ b/Inc/stm32h7xx_ll_dac.h
@@ -282,19 +282,19 @@
#if defined (HRTIM1)
#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */
#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */
-#endif
+#endif /* HRTIM1 */
#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
#if defined(TIM23)
#define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */
-#endif
+#endif /* TIM23 */
#if defined(TIM24)
#define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */
-#endif
+#endif /* TIM24 */
#if defined (DAC2)
#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
-#endif
+#endif /* DAC2 */
/**
* @}
*/
@@ -557,12 +557,10 @@
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval DAC conversion data (unit: digital value)
*/
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
- __DAC_VOLTAGE__,\
- __DAC_RESOLUTION__) \
-((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
-)
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
+ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+ )
/**
* @}
@@ -577,6 +575,7 @@
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
+
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
* @{
*/
@@ -615,7 +614,7 @@
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
* @arg @ref LL_DAC_MODE_CALIBRATION
*/
-__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -654,7 +653,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
*/
-__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -749,7 +748,7 @@
* (4) On this STM32 series, parameter not available on all devices.
* Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
*/
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -792,7 +791,7 @@
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -858,7 +857,7 @@
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -925,7 +924,7 @@
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
*/
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1023,7 +1022,7 @@
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1066,7 +1065,7 @@
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1125,7 +1124,7 @@
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
*/
-__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1167,7 +1166,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
@@ -1205,7 +1204,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1242,7 +1241,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1304,7 +1303,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1343,7 +1342,7 @@
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
* @retval DAC register address
*/
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
@@ -1404,7 +1403,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1462,7 +1461,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1635,7 +1634,7 @@
* @arg @ref LL_DAC_CHANNEL_2
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
@@ -1657,7 +1656,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
}
@@ -1669,7 +1668,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
}
@@ -1681,7 +1680,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
}
@@ -1692,7 +1691,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
}
@@ -1704,7 +1703,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
@@ -1716,7 +1715,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
}
@@ -1808,7 +1807,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
@@ -1820,7 +1819,7 @@
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
}
@@ -1835,8 +1834,8 @@
* @{
*/
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
+ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
@@ -1863,4 +1862,3 @@
#endif
#endif /* STM32H7xx_LL_DAC_H */
-
diff --git a/Inc/stm32h7xx_ll_dma.h b/Inc/stm32h7xx_ll_dma.h
index 100a2c5..c05815a 100644
--- a/Inc/stm32h7xx_ll_dma.h
+++ b/Inc/stm32h7xx_ll_dma.h
@@ -85,98 +85,107 @@
*/
typedef struct
{
- uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
- or as Source base address in case of memory to memory transfer direction.
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
+ or as Source base address in case of memory to memory transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
- uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
- or as Destination base address in case of memory to memory transfer direction.
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_LL_EC_DIRECTION
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
- uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- This parameter can be a value of @ref DMA_LL_EC_MODE
- @note The circular buffer mode cannot be used if the memory to memory
- data transfer direction is configured on the selected Stream
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Stream
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
- uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_PERIPH
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_PERIPH
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
- uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_MEMORY
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_MEMORY
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
- uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
- uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
- uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
- The data unit is equal to the source buffer configuration set in PeripheralSize
- or MemorySize parameters depending in the transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
- uint32_t PeriphRequest; /*!< Specifies the peripheral request.
- This parameter can be a value of @ref DMAMUX1_Request_selection
+ uint32_t PeriphRequest; /*!< Specifies the peripheral request.
+ This parameter can be a value of @ref DMAMUX1_Request_selection
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
- uint32_t Priority; /*!< Specifies the channel priority level.
- This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
- uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
- This parameter can be a value of @ref DMA_LL_FIFOMODE
- @note The Direct mode (FIFO mode disabled) cannot be used if the
- memory-to-memory data transfer is configured on the selected stream
+ uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+ This parameter can be a value of @ref DMA_LL_FIFOMODE
+ @note The Direct mode (FIFO mode disabled) cannot be used if the
+ memory-to-memory data transfer is configured on the selected stream
- This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+ This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
- uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
- This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
+ This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
- uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_LL_EC_MBURST
- @note The burst mode is possible only if the address Increment mode is enabled.
+ uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_LL_EC_MBURST
+ @note The burst mode is possible only if the address Increment mode is enabled.
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
- uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
- It specifies the amount of data to be transferred in a single non interruptible
- transaction.
- This parameter can be a value of @ref DMA_LL_EC_PBURST
- @note The burst mode is possible only if the address Increment mode is enabled.
+ uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+ It specifies the amount of data to be transferred in a single non interruptible
+ transaction.
+ This parameter can be a value of @ref DMA_LL_EC_PBURST
+ @note The burst mode is possible only if the address Increment mode is enabled.
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+ uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
+ This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */
+
+ uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
+ This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */
} LL_DMA_InitTypeDef;
/**
* @}
@@ -233,6 +242,15 @@
* @}
*/
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+ * @{
+ */
+#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
+#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
+/**
+ * @}
+ */
+
/** @defgroup DMA_LL_EC_PERIPH PERIPH
* @{
*/
@@ -347,15 +365,6 @@
* @}
*/
-/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
- * @{
- */
-#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
-#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
-/**
- * @}
- */
-
/**
* @}
*/
@@ -537,7 +546,9 @@
* CR PSIZE LL_DMA_ConfigTransfer\n
* CR MSIZE LL_DMA_ConfigTransfer\n
* CR PL LL_DMA_ConfigTransfer\n
- * CR PFCTRL LL_DMA_ConfigTransfer
+ * CR PFCTRL LL_DMA_ConfigTransfer\n
+ * CR DBM LL_DMA_ConfigTransfer\n
+ * CR CT LL_DMA_ConfigTransfer
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
@@ -556,6 +567,8 @@
* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ * @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_DMA_DOUBLEBUFFER_MODE_ENABLE
+ * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1
*@retval None
*/
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
@@ -563,8 +576,8 @@
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
- DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
- Configuration);
+ DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | \
+ DMA_SxCR_PFCTRL | DMA_SxCR_DBM | DMA_SxCR_CT, Configuration);
}
/**
@@ -1588,6 +1601,28 @@
}
/**
+ * @brief Check if double buffer mode is enabled or not.
+ * @rmtoll CR DBM LL_DMA_IsEnabledDoubleBufferMode
+ * @param DMAx DMAx Instance
+ * @param Stream This parameter can be one of the following values:
+ * @arg @ref LL_DMA_STREAM_0
+ * @arg @ref LL_DMA_STREAM_1
+ * @arg @ref LL_DMA_STREAM_2
+ * @arg @ref LL_DMA_STREAM_3
+ * @arg @ref LL_DMA_STREAM_4
+ * @arg @ref LL_DMA_STREAM_5
+ * @arg @ref LL_DMA_STREAM_6
+ * @arg @ref LL_DMA_STREAM_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+ register uint32_t dma_base_addr = (uint32_t)DMAx;
+
+ return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL);
+}
+
+/**
* @brief Get FIFO status.
* @rmtoll FCR FS LL_DMA_GetFIFOStatus
* @param DMAx DMAx Instance
diff --git a/Inc/stm32h7xx_ll_fmac.h b/Inc/stm32h7xx_ll_fmac.h
index 63253ae..8e92c3d 100644
--- a/Inc/stm32h7xx_ll_fmac.h
+++ b/Inc/stm32h7xx_ll_fmac.h
@@ -184,7 +184,7 @@
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
*/
-__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(const FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
}
@@ -209,7 +209,7 @@
* @retval uint8_t Number of 16-bit words allocated to the input buffer
* (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
}
@@ -234,7 +234,7 @@
* @retval uint8_t Base address of the input buffer (X1) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
}
@@ -259,7 +259,7 @@
* @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
* (value between Min_Data=0x01 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
}
@@ -284,7 +284,7 @@
* @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
}
@@ -315,7 +315,7 @@
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
*/
-__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(const FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
}
@@ -340,7 +340,7 @@
* @retval uint8_t Number of 16-bit words allocated to the output buffer
* (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
}
@@ -365,7 +365,7 @@
* @retval uint8_t Base address of the output buffer (Y) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetYBase(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
}
@@ -398,7 +398,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
}
@@ -431,7 +431,7 @@
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
*/
-__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_GetFunction(const FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
}
@@ -455,7 +455,7 @@
* @param FMACx FMAC instance
* @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetParamR(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
}
@@ -479,7 +479,7 @@
* @param FMACx FMAC instance
* @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
}
@@ -504,7 +504,7 @@
* @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
-__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetParamP(const FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
}
@@ -534,7 +534,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
}
@@ -575,7 +575,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
}
@@ -616,7 +616,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
}
@@ -649,7 +649,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
}
@@ -690,7 +690,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
}
@@ -723,7 +723,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
}
@@ -756,7 +756,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
}
@@ -789,7 +789,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
}
@@ -822,7 +822,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
}
@@ -841,7 +841,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
}
@@ -852,7 +852,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
}
@@ -863,7 +863,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
}
@@ -874,7 +874,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
}
@@ -885,7 +885,7 @@
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(const FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
}
@@ -917,7 +917,7 @@
* @param FMACx FMAC instance
* @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
*/
-__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint16_t LL_FMAC_ReadData(const FMAC_TypeDef *FMACx)
{
return (uint16_t)(READ_REG(FMACx->RDATA));
}
@@ -1040,7 +1040,7 @@
* @{
*/
ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
-ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
+ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx);
/**
diff --git a/Inc/stm32h7xx_ll_fmc.h b/Inc/stm32h7xx_ll_fmc.h
index 5e8a401..3d34898 100644
--- a/Inc/stm32h7xx_ll_fmc.h
+++ b/Inc/stm32h7xx_ll_fmc.h
@@ -1135,7 +1135,7 @@
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
uint32_t AutoRefreshNumber);
-uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
diff --git a/Inc/stm32h7xx_ll_i2c.h b/Inc/stm32h7xx_ll_i2c.h
index a739d70..6400400 100644
--- a/Inc/stm32h7xx_ll_i2c.h
+++ b/Inc/stm32h7xx_ll_i2c.h
@@ -2248,8 +2248,8 @@
* @{
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
diff --git a/Inc/stm32h7xx_ll_lptim.h b/Inc/stm32h7xx_ll_lptim.h
index fd120b6..033e7b2 100644
--- a/Inc/stm32h7xx_ll_lptim.h
+++ b/Inc/stm32h7xx_ll_lptim.h
@@ -357,7 +357,7 @@
* @{
*/
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
diff --git a/Inc/stm32h7xx_ll_rng.h b/Inc/stm32h7xx_ll_rng.h
index 760a127..62039d0 100644
--- a/Inc/stm32h7xx_ll_rng.h
+++ b/Inc/stm32h7xx_ll_rng.h
@@ -219,7 +219,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
}
@@ -232,7 +232,12 @@
*/
__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
{
+#if defined(RNG_CR_CONDRST)
+ MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+#else
CLEAR_BIT(RNGx->CR, RNG_CR_CED);
+#endif /* RNG_CR_CONDRST*/
}
/**
@@ -243,7 +248,12 @@
*/
__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
{
+#if defined(RNG_CR_CONDRST)
+ MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+#else
SET_BIT(RNGx->CR, RNG_CR_CED);
+#endif /* RNG_CR_CONDRST*/
}
/**
@@ -252,7 +262,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
}
@@ -286,7 +296,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
}
@@ -308,7 +318,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
}
@@ -321,7 +331,8 @@
*/
__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
{
- CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
+ MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -332,7 +343,8 @@
*/
__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
{
- SET_BIT(RNGx->CR, RNG_CR_NISTC);
+ MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -341,7 +353,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
}
@@ -355,7 +367,8 @@
*/
__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
{
- MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -364,7 +377,7 @@
* @param RNGx RNG Instance
* @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
*/
-__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
}
@@ -378,7 +391,8 @@
*/
__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
{
- MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -387,7 +401,7 @@
* @param RNGx RNG Instance
* @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
*/
-__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
}
@@ -401,7 +415,8 @@
*/
__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
{
- MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -410,7 +425,7 @@
* @param RNGx RNG Instance
* @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
*/
-__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
}
@@ -440,7 +455,8 @@
*/
__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
{
- MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
+ MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
+ CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -465,7 +481,7 @@
* @arg @ref LL_RNG_CLKDIV_BY_16384
* @arg @ref LL_RNG_CLKDIV_BY_32768
*/
-__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
{
return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
}
@@ -484,7 +500,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
}
@@ -495,7 +511,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
}
@@ -506,7 +522,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
}
@@ -517,7 +533,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
}
@@ -528,7 +544,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
}
@@ -594,7 +610,7 @@
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
}
@@ -613,7 +629,7 @@
* @param RNGx RNG Instance
* @retval Generated 32-bit random value
*/
-__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_REG(RNGx->DR));
}
@@ -666,7 +682,7 @@
*/
ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
/**
* @}
diff --git a/Inc/stm32h7xx_ll_spi.h b/Inc/stm32h7xx_ll_spi.h
index e8bdc1f..e382453 100644
--- a/Inc/stm32h7xx_ll_spi.h
+++ b/Inc/stm32h7xx_ll_spi.h
@@ -575,7 +575,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
@@ -610,7 +610,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
}
@@ -645,7 +645,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
}
@@ -673,7 +673,7 @@
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
}
@@ -728,7 +728,7 @@
* @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
* @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
}
@@ -783,7 +783,7 @@
* @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
* @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
}
@@ -808,7 +808,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
}
@@ -833,7 +833,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
}
@@ -857,7 +857,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
}
@@ -884,7 +884,7 @@
* @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
* @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
}
@@ -911,7 +911,7 @@
* @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
* @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
*/
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
}
@@ -939,7 +939,7 @@
* @arg @ref LL_SPI_SS_LEVEL_HIGH
* @arg @ref LL_SPI_SS_LEVEL_LOW
*/
-__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
}
@@ -972,7 +972,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
}
@@ -1005,7 +1005,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
}
@@ -1038,7 +1038,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
}
@@ -1068,7 +1068,7 @@
* @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
* @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
*/
-__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
}
@@ -1098,7 +1098,7 @@
* @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
* @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
*/
-__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
}
@@ -1126,7 +1126,7 @@
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
* @arg @ref LL_SPI_PROTOCOL_TI
*/
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
}
@@ -1155,7 +1155,7 @@
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
*/
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
}
@@ -1184,7 +1184,7 @@
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
}
@@ -1213,7 +1213,7 @@
* @arg @ref LL_SPI_NSS_POLARITY_LOW
* @arg @ref LL_SPI_NSS_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
}
@@ -1254,7 +1254,7 @@
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
*/
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
}
@@ -1283,7 +1283,7 @@
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
}
@@ -1321,7 +1321,7 @@
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
{
uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
@@ -1352,7 +1352,7 @@
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
-__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
}
@@ -1434,7 +1434,7 @@
* @arg @ref LL_SPI_DATAWIDTH_31BIT
* @arg @ref LL_SPI_DATAWIDTH_32BIT
*/
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
}
@@ -1490,7 +1490,7 @@
* @arg @ref LL_SPI_FIFO_TH_15DATA
* @arg @ref LL_SPI_FIFO_TH_16DATA
*/
-__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
}
@@ -1524,7 +1524,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
}
@@ -1606,7 +1606,7 @@
* @arg @ref LL_SPI_CRC_31BIT
* @arg @ref LL_SPI_CRC_32BIT
*/
-__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
}
@@ -1639,7 +1639,7 @@
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
*/
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
}
@@ -1676,7 +1676,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
}
@@ -1695,7 +1695,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
}
@@ -1706,7 +1706,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
}
@@ -1717,7 +1717,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
}
@@ -1728,7 +1728,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
}
@@ -1739,7 +1739,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
}
@@ -1750,7 +1750,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
@@ -1761,7 +1761,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
}
@@ -1772,7 +1772,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
@@ -1783,7 +1783,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
@@ -1794,7 +1794,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
}
@@ -1805,7 +1805,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
}
@@ -1816,7 +1816,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
}
@@ -1827,7 +1827,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
}
@@ -1838,7 +1838,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
}
@@ -1849,7 +1849,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
}
@@ -1864,7 +1864,7 @@
* @arg @ref LL_SPI_RX_FIFO_2PACKET
* @arg @ref LL_SPI_RX_FIFO_3PACKET
*/
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
}
@@ -2224,7 +2224,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
}
@@ -2235,7 +2235,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
}
@@ -2246,7 +2246,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
}
@@ -2257,7 +2257,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
}
@@ -2268,7 +2268,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
}
@@ -2279,7 +2279,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
}
@@ -2290,7 +2290,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
}
@@ -2301,7 +2301,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
}
@@ -2312,7 +2312,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
}
@@ -2323,7 +2323,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
}
@@ -2334,7 +2334,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
}
@@ -2375,7 +2375,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
}
@@ -2408,7 +2408,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
}
@@ -2418,7 +2418,7 @@
* @param SPIx SPI Instance
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
{
return (uint32_t) &(SPIx->TXDR);
}
@@ -2429,7 +2429,7 @@
* @param SPIx SPI Instance
* @retval Address of data register
*/
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
{
return (uint32_t) &(SPIx->RXDR);
}
@@ -2447,7 +2447,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFF
*/
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
{
return (*((__IO uint8_t *)&SPIx->RXDR));
}
@@ -2458,7 +2458,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
{
#if defined (__GNUC__)
__IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
@@ -2474,7 +2474,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
{
return (*((__IO uint32_t *)&SPIx->RXDR));
}
@@ -2538,7 +2538,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->CRCPOLY));
}
@@ -2561,7 +2561,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->UDRDR));
}
@@ -2572,7 +2572,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->RXCRC));
}
@@ -2583,7 +2583,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->TXCRC));
}
@@ -2597,7 +2597,7 @@
* @{
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
@@ -2884,7 +2884,7 @@
* @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
* @arg @ref LL_I2S_DATAFORMAT_32B
*/
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
}
@@ -2913,7 +2913,7 @@
* @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
* @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
*/
-__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
}
@@ -2946,7 +2946,7 @@
* @param SPIx SPI Handle
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
}
@@ -2973,7 +2973,7 @@
* @arg @ref LL_I2S_POLARITY_LOW
* @arg @ref LL_I2S_POLARITY_HIGH
*/
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
}
@@ -3008,7 +3008,7 @@
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
* @arg @ref LL_I2S_STANDARD_PCM_LONG
*/
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
}
@@ -3043,7 +3043,7 @@
* @arg @ref LL_I2S_MODE_MASTER_RX
* @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
*/
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
}
@@ -3104,7 +3104,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIOSwap(SPIx);
}
@@ -3139,7 +3139,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledGPIOControl(SPIx);
}
@@ -3163,7 +3163,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIOLock(SPIx);
}
@@ -3190,7 +3190,7 @@
* @arg @ref LL_I2S_LSB_FIRST
* @arg @ref LL_I2S_MSB_FIRST
*/
-__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(const SPI_TypeDef *SPIx)
{
return LL_SPI_GetTransferBitOrder(SPIx);
}
@@ -3208,11 +3208,11 @@
/**
* @brief Check if there is an unfinished transfer
- * @rmtoll CR1 CSTART LL_I2S_IsTransferActive
+ * @rmtoll CR1 CSTART LL_I2S_IsActiveTransfer
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveMasterTransfer(SPIx);
}
@@ -3252,7 +3252,7 @@
* @arg @ref LL_I2S_FIFO_TH_07DATA
* @arg @ref LL_I2S_FIFO_TH_08DATA
*/
-__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(const SPI_TypeDef *SPIx)
{
return LL_SPI_GetFIFOThreshold(SPIx);
}
@@ -3276,7 +3276,7 @@
* @param SPIx SPI Instance
* @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
}
@@ -3303,7 +3303,7 @@
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
*/
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
}
@@ -3336,7 +3336,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
}
@@ -3356,7 +3356,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_RXP(SPIx);
}
@@ -3367,7 +3367,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_TXP(SPIx);
}
@@ -3378,7 +3378,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_UDR(SPIx);
}
@@ -3389,7 +3389,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_OVR(SPIx);
}
@@ -3400,7 +3400,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_FRE(SPIx);
}
@@ -3562,7 +3562,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_RXP(SPIx);
}
@@ -3573,7 +3573,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_TXP(SPIx);
}
@@ -3584,7 +3584,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_UDR(SPIx);
}
@@ -3595,7 +3595,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_OVR(SPIx);
}
@@ -3606,7 +3606,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_FRE(SPIx);
}
@@ -3647,7 +3647,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_RX(SPIx);
}
@@ -3680,7 +3680,7 @@
* @param SPIx SPI Instance
* @retval State of bit (1 or 0)
*/
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_TX(SPIx);
}
@@ -3699,7 +3699,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFF
*/
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
{
return LL_SPI_ReceiveData16(SPIx);
}
@@ -3710,7 +3710,7 @@
* @param SPIx SPI Instance
* @retval 0..0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
{
return LL_SPI_ReceiveData32(SPIx);
}
@@ -3750,8 +3750,8 @@
* @{
*/
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
diff --git a/Inc/stm32h7xx_ll_tim.h b/Inc/stm32h7xx_ll_tim.h
index f68a4e0..050f738 100644
--- a/Inc/stm32h7xx_ll_tim.h
+++ b/Inc/stm32h7xx_ll_tim.h
@@ -653,10 +653,10 @@
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
@@ -737,6 +737,15 @@
*/
#endif /* USE_FULL_LL_DRIVER */
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+@endcond
+ */
+
/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
* @{
*/
@@ -752,8 +761,8 @@
#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
/**
* @}
*/
@@ -967,11 +976,11 @@
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
@@ -1157,6 +1166,15 @@
* @}
*/
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_TIM_ReArmBRK(_PARAM_)
+#define LL_TIM_ReArmBRK2(_PARAM_)
+/**
+@endcond
+ */
+
#endif /*TIM_BDTR_BKBID */
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
* @{
@@ -1340,6 +1358,9 @@
#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24 input 1 is connected to CAN TMP */
#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24 input 1 is connected to CAN RTP */
#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
+/**
+ * @}
+ */
#if defined(TIM_BREAK_INPUT_SUPPORT)
/** Legacy definitions for compatibility purpose
@@ -1350,6 +1371,7 @@
@endcond
*/
#endif /* TIM_BREAK_INPUT_SUPPORT */
+
/**
* @}
*/
@@ -1484,11 +1506,6 @@
* @}
*/
-
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
* @{
@@ -1942,6 +1959,17 @@
}
/**
+ * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+ * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
@@ -2085,7 +2113,7 @@
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
{
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
@@ -2171,8 +2199,8 @@
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
@@ -2211,8 +2239,8 @@
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
- * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+ * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
{
@@ -2426,7 +2454,7 @@
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2502,7 +2530,7 @@
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2587,7 +2615,7 @@
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -3136,7 +3164,7 @@
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
@@ -3688,18 +3716,6 @@
SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
}
-/**
- * @brief Re-arm the break input (when it operates in bidirectional mode).
- * @note The Break input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
#endif /*TIM_BDTR_BKBID */
/**
* @brief Enable the break 2 function.
@@ -3828,18 +3844,6 @@
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
}
-/**
- * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
- * @note The Break 2 input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
#endif /*TIM_BDTR_BKBID */
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
@@ -5170,7 +5174,7 @@
* @{
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
diff --git a/Inc/stm32h7xx_ll_usart.h b/Inc/stm32h7xx_ll_usart.h
index 8494c35..d1242eb 100644
--- a/Inc/stm32h7xx_ll_usart.h
+++ b/Inc/stm32h7xx_ll_usart.h
@@ -1567,7 +1567,7 @@
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
*/
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
}
diff --git a/Inc/stm32h7xx_ll_usb.h b/Inc/stm32h7xx_ll_usb.h
index 889aadb..9cfe6a1 100644
--- a/Inc/stm32h7xx_ll_usb.h
+++ b/Inc/stm32h7xx_ll_usb.h
@@ -37,6 +37,13 @@
*/
/* Exported types ------------------------------------------------------------*/
+#ifndef HAL_USB_TIMEOUT
+#define HAL_USB_TIMEOUT 0xF000000U
+#endif /* define HAL_USB_TIMEOUT */
+
+#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
+#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U
+#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
/**
* @brief USB Mode definition
@@ -85,38 +92,39 @@
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
+ uint8_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t Host_channels; /*!< Host Channels number.
+ uint8_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */
+ uint8_t dma_enable; /*!< USB DMA state.
+ If DMA is not supported this parameter shall be set by default to zero */
- uint32_t speed; /*!< USB Core speed.
+ uint8_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+ uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
+ uint8_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
+ uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
+ uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
- uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
+ uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
+ uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_CfgTypeDef;
@@ -179,8 +187,13 @@
(HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
+ uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */
+ uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */
+ uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */
+ uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */
- uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
+ uint8_t hub_port_nbr; /*!< USB HUB port number */
+ uint8_t hub_addr; /*!< USB HUB address */
uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_LL_EP_Type */
@@ -193,7 +206,7 @@
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
- uint32_t XferSize; /*!< OTG Channel transfer size. */
+ uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */
@@ -208,6 +221,7 @@
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
uint32_t ErrCnt; /*!< Host channel error count. */
+ uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */
USB_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_URBStateTypeDef */
@@ -425,6 +439,12 @@
#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU
#define HC_MAX_PKT_CNT 256U
+#define ISO_SPLT_MPS 188U
+
+#define HCSPLT_BEGIN 1U
+#define HCSPLT_MIDDLE 2U
+#define HCSPLT_END 3U
+#define HCSPLT_FULL 4U
#define TEST_J 1U
#define TEST_K 2U
@@ -482,55 +502,55 @@
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len, uint8_t dma);
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup);
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
uint8_t epnum, uint8_t dev_address, uint8_t speed,
uint8_t ep_type, uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
USB_OTG_HCTypeDef *hc, uint8_t dma);
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
diff --git a/Inc/stm32h7xx_ll_utils.h b/Inc/stm32h7xx_ll_utils.h
index 635ea59..41a5aa4 100644
--- a/Inc/stm32h7xx_ll_utils.h
+++ b/Inc/stm32h7xx_ll_utils.h
@@ -345,7 +345,7 @@
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
+ * @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
diff --git a/Release_Notes.html b/Release_Notes.html
index 3d43c4b..0212460 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -11,24 +11,21 @@
span.underline{text-decoration: underline;}
div.column{display: inline-block; vertical-align: top; width: 50%;}
</style>
- <link rel="stylesheet" href="_htmresc/mini-st.css" />
+ <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
+ <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
</head>
<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
-<div class="card fluid">
-<div class="sectione dark">
<center>
<h1 id="release-notes-for-stm32h7xx-hal-drivers"><strong>Release Notes for STM32H7xx HAL Drivers</strong></h1>
<p>Copyright © 2017 STMicroelectronics<br />
</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
+<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
-</div>
-</div>
<h1 id="purpose">Purpose</h1>
<p>The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.</p>
<p>The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.</p>
@@ -43,10 +40,233 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section16" checked aria-hidden="true"> <label for="collapse-section16" aria-hidden="true"><strong>V1.11.1 / 04-November-2022</strong></label>
+<input type="checkbox" id="collapse-section18" checked aria-hidden="true"> <label for="collapse-section18" aria-hidden="true"><strong>V1.11.3 / 15-March-2024</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li>
+<li><strong>HAL Generic</strong>
+<ul>
+<li>Allow redefinition of macro UNUSED(x).</li>
+<li>Update of HAL_GetTickFreq() API brief.</li>
+<li>Update stm32h7xx_hal_conf_template.h file to support legacy HAL ETH driver.</li>
+</ul></li>
+<li><strong>HAL PWR</strong>
+<ul>
+<li>Add macro UNUSED() to avoid the generation of a warning related to the unused argument ‘Regulator’.</li>
+<li>Update HAL_PWREx_PVD_AVD_IRQHandle() API to call right callbacks before performing the clear.</li>
+</ul></li>
+<li><strong>HAL GPIO</strong>
+<ul>
+<li>Add alternative function mappings for CSLEEP, CSTOP and NDSTOP2.</li>
+</ul></li>
+<li><strong>HAL EXTI</strong>
+<ul>
+<li>Add macro UNUSED() to avoid the generation of a warning related to the unused argument ‘Edge’.</li>
+</ul></li>
+<li><strong>HAL CORTEX</strong>
+<ul>
+<li>Updated HAL_MPU_ConfigRegion() API to allow the configuration of the MPU registers independently of the value of Enable/Disable field.</li>
+<li>Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().</li>
+</ul></li>
+<li><strong>HAL RTC_BKP</strong>
+<ul>
+<li>Change RTC_ISR_INITF to RTC_ISR_INIT in the Exit Initialization mode.</li>
+<li>Remove macro __HAL_RTC_TAMPER_GET_IT() as it is redundant with macro __HAL_RTC_TAMPER_GET_FLAG() and create an alias into the hal_legacy.h file.</li>
+<li>Correct misleading note about shadow registers.</li>
+</ul></li>
+<li><strong>HAL PSSI</strong>
+<ul>
+<li>Replace hdmatx by hdmarx in HAL_PSSI_Receive_DMA() API.</li>
+<li>Use MODIFY_REG in HAL_PSSI_Transmit() and HAL_PSSI_Receive() APIs.</li>
+</ul></li>
+<li><strong>HAL/LL TIM</strong>
+<ul>
+<li>Remove multiple volatile reads in interrupt handler for better performance.</li>
+<li>Assert check for the right channels.</li>
+<li>Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init() API.</li>
+<li>Remove useless check on macro IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() API to fix Break Filter configuration problem with specific TIM instances.</li>
+<li>Update interrupt flag is cleared when the update event is generated by software.</li>
+<li>Fix typo in PWM symmetric mode related constants names.</li>
+<li>Improve period configuration parameter check.</li>
+<li>Improve HAL TIM driver’s operational behavior.</li>
+</ul></li>
+<li><strong>HAL LPTIM</strong>
+<ul>
+<li>Remove redundant macro IS_LPTIM_AUTORELOAD().</li>
+</ul></li>
+<li><strong>LL COMP</strong>
+<ul>
+<li>Add new APIs:
+<ul>
+<li>LL_COMP_IsActiveFlag_OutputTrig().</li>
+<li>LL_COMP_ClearFlag_OutputTrig().</li>
+<li>LL_COMP_EnableIT_OutputTrig().</li>
+<li>LL_COMP_DisableIT_OutputTrig().</li>
+<li>LL_COMP_IsEnabledIT_OutputTrig().</li>
+</ul></li>
+</ul></li>
+<li><strong>HAL DSI</strong>
+<ul>
+<li>Align DSI Initialization sequence to the recommended ‘Programing procedure overview’ part to avoid DSI read LCD controller register 0x0A error.</li>
+</ul></li>
+<li><strong>HAL FLASH</strong>
+<ul>
+<li>Add macro UNUSED() to avoid the generation of a warning related to the unused argument ‘Edge’.</li>
+</ul></li>
+<li><strong>HAL NOR</strong>
+<ul>
+<li>Add x8 commands support for NOR Flash driver.</li>
+</ul></li>
+<li><strong>HAL SPDIFRX</strong>
+<ul>
+<li>Prevent hard fault by checking DMA usage.</li>
+<li>Tuning of default SPDIFRX timeout.</li>
+</ul></li>
+<li><strong>HAL HASH</strong>
+<ul>
+<li>Read the last remaining bytes (3 or 2 or 1) of the data in a temporary variable (taking into account swap mode) and enter this variable into the HASH->DIN when the data is not a multiple of 4 bytes.</li>
+<li>Code quality enhancement : Fix MISRA-C Rules 12.1, 10.7, 10.6, 10.4.</li>
+</ul></li>
+<li><strong>HAL CRYP</strong>
+<ul>
+<li>Update CRYP HAL driver to fix the issue of writing out the outputbuffer when the size is not multiple of 4.</li>
+</ul></li>
+<li><strong>HAL OPAMP</strong>
+<ul>
+<li>Fix incorrect word ‘surcharged’ in functions headers.</li>
+</ul></li>
+<li><strong>HAL/LL ADC</strong>
+<ul>
+<li>Update LL_ADC_SetAnalogWDThresholds(), LL_ADC_GetAnalogWDThresholds(), LL_ADC_ConfigAnalogWDThresholds() APIs for ADC3 IP version.</li>
+<li>Update HAL ADC driver to support case of dual mode with 2 DMA channels.</li>
+<li>Update setting of channel preselection for ADC internal channel.</li>
+<li>Update LL_ADC_DeInit() API with reference manual.</li>
+</ul></li>
+<li><strong>HAL DAC</strong>
+<ul>
+<li>Fix incorrect word ‘surcharged’ in functions headers.</li>
+<li>Updated DAC buffer calibration according to RM.</li>
+</ul></li>
+<li><strong>HAL OSPI</strong>
+<ul>
+<li>Update OCTOSPI driver to handle proper abort of the DMA transfer.</li>
+</ul></li>
+<li><strong>HAL CORDIC</strong>
+<ul>
+<li>Fix incorrect word ‘surcharged’ in functions headers.</li>
+</ul></li>
+<li><strong>HAL FMAC</strong>
+<ul>
+<li>Avoid usage of magic numbers.</li>
+<li>Fix incorrect word ‘surcharged’ in functions headers.</li>
+</ul></li>
+<li><strong>HAL/LL SPI</strong>
+<ul>
+<li>Code improvement related to LDRA inside HAL_SPI_TransmitReceive_DMA(), HAL_SPI_Abort() and HAL_SPI_Abort_IT() APIs.</li>
+<li>Update the register field modified by LL_SPI_SetTxCRCInitPattern() API.</li>
+<li>In Full Duplex mode, calling HAL_SPI_TransmitReceive_DMA() API can generate a RX HDMA busy if HDMA TX is not well initialized. To avoid this, now a DMA abort is done on RX path to reset HDMA RX to ready state.</li>
+<li>Feature Reload IT can generate Hardfault at high baudrate. This happens because variable hspi->Reload.Requested is reset before hspi->RxXferCount goes to zero. To avoid this, now hspi->Reload.Requested reset is done inside local ISR pointer instead of HAL_SPI_IRQHandler() API.</li>
+</ul></li>
+<li><strong>HAL QSPI</strong>
+<ul>
+<li>Clear the QSPI.AR register when sCommand.AddressMode is QSPI_ADDRESS_NONE</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong>
+<ul>
+<li>Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.</li>
+<li>Update SMBUS_ITErrorHandler to flash TXDR just in case of error.</li>
+</ul></li>
+<li><strong>HAL ETH</strong>
+<ul>
+<li>Update the entry to critical section without enabling unwanted global interrupts.</li>
+<li>Add missing system time in different PTP APIs.</li>
+<li>Fix ETH_Start_IT sequence.</li>
+<li>HAL ETH Driver general updates to enhance the quality and robustness.</li>
+<li>Add condition to get the TimeStamp only when it was captured (Check on Last Descriptor and TimeStamp flag set).</li>
+<li>Fix comment “CSR Clock Range between 150-250* MHz”.</li>
+<li>Update on Rx descriptor Tail pointer management to avoid race condition.</li>
+<li>Move the section of disable MMC interrupts from HAL_ETH_Start_IT() API to HAL_ETH_Init() API.</li>
+<li>Fix MAC register name to get MAC LPI interrupt.</li>
+</ul></li>
+<li><strong>HAL UART</strong>
+<ul>
+<li>Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings.</li>
+<li>Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback APIs to allow user Rx Event Callback registration when a transmit is ongoing.</li>
+<li>Prevent RTOF flag from being cleared by a transmit process in polling mode.</li>
+</ul></li>
+<li><strong>HAL FDCAN</strong>
+<ul>
+<li>Fix GetIndex issue in HAL_FDCAN_GetRxMessage() API.</li>
+</ul></li>
+<li><strong>HAL SAI</strong>
+<ul>
+<li>Improve audio quality (avoid potential glitch).</li>
+<li>Fix incorrect word ‘surcharged’.</li>
+</ul></li>
+<li><strong>HAL I2C</strong>
+<ul>
+<li>Update I2C_WaitOnRXNEFlagUntilTimeout() function to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.</li>
+<li>Update HAL_I2C_IsDeviceReady() API to support 10_bit addressing mode: Update done on the macro I2C_GENERATE_START.</li>
+<li>Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte</li>
+<li>Update HAL_I2C_Init API to clear ADD10 bit in 7 bit addressing mode.</li>
+<li>Update HAL I2C driver to disable all interrupts after end of transaction.</li>
+<li>Update HAL_I2C_Mem_Write_IT() API to initialize XferSize at 0.</li>
+<li>Update I2C_Slave_ISR_IT(), I2C_Slave_ISR_DMA() and I2C_ITSlaveCplt() functions to prevent the call of HAL_I2C_ListenCpltCallback() API twice.</li>
+<li>In HAL_I2C_IsDeviceReady() API remove the unusable code.</li>
+<li>Update I2C_WaitOnFlagUntilTimeout() function to handle error case.</li>
+<li>Update HAL_I2C_Slave_Transmit() API to check if the received NACK is the good one.</li>
+<li>Update LL_I2C_HandleTranfer() API to prevent undefined behavior of volatile usage before updating the CR2 register.</li>
+</ul></li>
+<li><strong>HAL USB</strong>
+<ul>
+<li>ll_USB.c fix wrong mask to clear USB interrupt in USB_ClearInterrupts() function.</li>
+<li>ll_usb.c: remove useless software setting to setup the frame interval at 80%.</li>
+<li>ll_usb.c hal_hcd.c: adding support of hub split transactions.</li>
+<li>pcd.c/ll_usb.c: fix device connection in case battery charging used with HS instance linked to internal FS PHY.</li>
+<li>ll_usb.c: increase timeout value to allow core reset to complete.</li>
+<li>ll_usb.c: improve delay management to set core mode.</li>
+</ul></li>
+<li><strong>LL UTILS</strong>
+<ul>
+<li>Fix a note about Ticks parameter.</li>
+</ul></li>
+</ul>
+<h2 id="known-limitations">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="backward-compatibility">Backward compatibility</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true"><strong>V1.11.2 / 23-January-2024</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li><strong>HAL ETH</strong>
+<ul>
+<li>Update on Rx descriptor Tail pointer management to avoid race condition.</li>
+</ul></li>
+</ul>
+<h2 id="known-limitations-1">Known Limitations</h2>
+<ul>
+<li>None</li>
+</ul>
+<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<ul>
+<li>None</li>
+</ul>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true"><strong>V1.11.1 / 04-November-2022</strong></label>
+<div>
+<h2 id="main-changes-2">Main Changes</h2>
+<ul>
<li>General updates to fix known defects and implementation enhancements.</li>
<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.</li>
<li><p>HAL code quality enhancement for MISRA-C2012 Rule-2.2_c.</p></li>
@@ -79,7 +299,9 @@
<li>Check if the RTC calendar has been previously initialized before entering Initialization mode.</li>
<li>Clear RSF flag using a single ‘write’ operation instead of a ‘read-modify-write’ sequence to avoid clearing other ISR flags if set in the meantime.</li>
<li>Optimize the use of #ifdef … #endif directives for better readability and maintainability.</li>
+<li>To avoid any possible clearing of other ISR flags during sequence read-modify-write , a direct assignment was applied with a mask of reserved bits to avoid setting them.</li>
<li>Rearrange the de-initialization sequence to be compliant with the reference manual.</li>
+<li>Optimize the CR reset operation (from read-modify-write to write) and enrich related comments.</li>
<li>Move the ‘exit initialization mode’ call after PRER, ALRMAR, ALRMBR, and WUTR registers are reset.</li>
<li>Group the tamper registers reset instruction for better readability.</li>
</ul></li>
@@ -156,11 +378,11 @@
<li>Remove redundant word from <span class="citation" data-cites="note">@note</span> of HAL_InitTick() header description, which may cause confusion when reading the note.</li>
</ul></li>
</ul>
-<h2 id="known-limitations">Known Limitations</h2>
+<h2 id="known-limitations-2">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility">Backward compatibility</h2>
+<h2 id="backward-compatibility-2">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -169,7 +391,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true"><strong>V1.11.0 / 11-February-2022</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements.</li>
<li><strong>The following changes done on the HAL drivers require an update of the application code based on older HAL versions</strong>
@@ -252,11 +474,11 @@
<li>Fix USB BCD data contact timeout</li>
</ul></li>
</ul>
-<h2 id="known-limitations-1">Known Limitations</h2>
+<h2 id="known-limitations-3">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-1">Backward compatibility</h2>
+<h2 id="backward-compatibility-3">Backward compatibility</h2>
<ul>
<li>Compatibility break with HAL ETH driver V1.10.0 available within STM32CubeFW_H7 V1.9.0</li>
</ul>
@@ -265,7 +487,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true"><strong>V1.10.1 / 06-December-2021</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements.</li>
<li>All source files: update disclaimer to add reference to the new license agreement.</li>
@@ -424,14 +646,14 @@
<li>Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).</li>
</ul></li>
</ul>
-<h2 id="known-limitations-2">Known Limitations</h2>
+<h2 id="known-limitations-4">Known Limitations</h2>
<ul>
<li><strong>HAL/ETH</strong>
<ul>
<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-2">Backward compatibility</h2>
+<h2 id="backward-compatibility-4">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -440,7 +662,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true"><strong>V1.10.0 / 12-February-2021</strong></label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li><p>General updates to fix known defects and implementation enhancements</p></li>
<li><p>Fix minor issues related to English typo in comments</p></li>
@@ -726,14 +948,14 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-3">Known Limitations</h2>
+<h2 id="known-limitations-5">Known Limitations</h2>
<ul>
<li><strong>HAL/ETH</strong>
<ul>
<li>A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-3">Backward compatibility</h2>
+<h2 id="backward-compatibility-5">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -742,7 +964,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true"><strong>V1.9.0 / 29-May-2020</strong></label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>First official release of the STM32CubeH7 Firmware Package supporting <strong>STM32H72x/3x</strong> new devices</li>
<li>General updates to fix known defects and implementation enhancements</li>
@@ -1336,11 +1558,11 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-4">Known Limitations</h2>
+<h2 id="known-limitations-6">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-4">Backward compatibility</h2>
+<h2 id="backward-compatibility-6">Backward compatibility</h2>
<ul>
<li>Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 families)</li>
</ul>
@@ -1349,7 +1571,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true"><strong>V1.8.0 / 14-February-2020</strong></label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -1583,7 +1805,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-5">Known Limitations</h2>
+<h2 id="known-limitations-7">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -1593,7 +1815,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-5">Backward compatibility</h2>
+<h2 id="backward-compatibility-7">Backward compatibility</h2>
<ul>
<li>None</li>
</ul>
@@ -1602,7 +1824,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>Official release with support of STM32H7A3/B3xx/B0xx new devices<br />
</li>
@@ -2157,7 +2379,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-6">Known Limitations</h2>
+<h2 id="known-limitations-8">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -2171,7 +2393,7 @@
<li>New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-6">Backward compatibility</h2>
+<h2 id="backward-compatibility-8">Backward compatibility</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -2195,7 +2417,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li><strong>HAL</strong>: generic
@@ -2470,11 +2692,11 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="known-limitations-7">Known Limitations</h2>
+<h2 id="known-limitations-9">Known Limitations</h2>
<ul>
<li>None</li>
</ul>
-<h2 id="backward-compatibility-7">Backward compatibility</h2>
+<h2 id="backward-compatibility-9">Backward compatibility</h2>
<ul>
<li><strong>HAL TIM</strong>:
<ul>
@@ -2492,7 +2714,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add support for VOS0 power regulator voltage scaling with 480MHz over clock</li>
@@ -2962,7 +3184,7 @@
<li>Update LL_Init1msTick and LL_SetSystemCoreClock description for <strong>DUAL CORE</strong> lines</li>
</ul></li>
</ul>
-<h2 id="known-limitations-8">Known Limitations</h2>
+<h2 id="known-limitations-10">Known Limitations</h2>
<ul>
<li><strong>HAL SD</strong>:
<ul>
@@ -2976,7 +3198,7 @@
<li>Full duplex Transmit/receive feature not available</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-8">Backward compatibility</h2>
+<h2 id="backward-compatibility-10">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -3028,7 +3250,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<ul>
<li>General updates to fix known defects and implementation enhancements</li>
<li>Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG</li>
@@ -3297,7 +3519,7 @@
<li>Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled</li>
</ul></li>
</ul>
-<h2 id="known-limitations-9">Known Limitations</h2>
+<h2 id="known-limitations-11">Known Limitations</h2>
<ul>
<li><strong>HAL I2S</strong>:
<ul>
@@ -3305,7 +3527,7 @@
<li>A new version of this driver will be available in next release with full features tested</li>
</ul></li>
</ul>
-<h2 id="backward-compatibility-9">Backward compatibility</h2>
+<h2 id="backward-compatibility-11">Backward compatibility</h2>
<ul>
<li><strong>HAL ADC</strong>:
<ul>
@@ -3345,7 +3567,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<ul>
<li>Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers</li>
<li><strong>HAL Cortex</strong>: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15</li>
@@ -3357,7 +3579,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL SPI</strong>: Driver reworked to fix critical issues</li>
@@ -3368,7 +3590,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<ul>
<li>General updates to fix known defects and enhancements implementation</li>
<li><strong>HAL FLASH</strong>: Add Mass Erase for both banks</li>
@@ -3383,7 +3605,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<ul>
<li>First official release for STM32H743xx/753xx devices</li>
</ul>
diff --git a/Src/stm32h7xx_hal.c b/Src/stm32h7xx_hal.c
index c59b17d..35eeb7e 100644
--- a/Src/stm32h7xx_hal.c
+++ b/Src/stm32h7xx_hal.c
@@ -47,11 +47,11 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
- * @brief STM32H7xx HAL Driver version number V1.11.1
+ * @brief STM32H7xx HAL Driver version number
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */
-#define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */
+#define __STM32H7xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
|(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
diff --git a/Src/stm32h7xx_hal_cec.c b/Src/stm32h7xx_hal_cec.c
index abdddb4..8a2dd6d 100644
--- a/Src/stm32h7xx_hal_cec.c
+++ b/Src/stm32h7xx_hal_cec.c
@@ -830,7 +830,7 @@
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* In all cases transmit the byte */
- hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr;
+ hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
hcec->pTxBuffPtr++;
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
@@ -856,7 +856,7 @@
/* ----------------------------Rx/Tx Error Management----------------------------------*/
if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
- CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
+ CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
{
hcec->ErrorCode = itflag;
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
diff --git a/Src/stm32h7xx_hal_cordic.c b/Src/stm32h7xx_hal_cordic.c
index 05218fe..7eea29c 100644
--- a/Src/stm32h7xx_hal_cordic.c
+++ b/Src/stm32h7xx_hal_cordic.c
@@ -886,8 +886,6 @@
{
uint32_t sizeinbuff;
uint32_t sizeoutbuff;
- uint32_t inputaddr;
- uint32_t outputaddr;
/* Check the parameters */
assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
@@ -960,10 +958,9 @@
sizeoutbuff = NbCalc;
}
- outputaddr = (uint32_t)pOutBuff;
-
/* Enable the DMA stream managing CORDIC output data read */
- if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff) != HAL_OK)
+ if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff)
+ != HAL_OK)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
@@ -995,10 +992,9 @@
sizeinbuff = NbCalc;
}
- inputaddr = (uint32_t)pInBuff;
-
/* Enable the DMA stream managing CORDIC input data write */
- if (HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) != HAL_OK)
+ if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff)
+ != HAL_OK)
{
/* Update the error code */
hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
@@ -1137,7 +1133,7 @@
/*Call registered callback*/
hcordic->CalculateCpltCallback(hcordic);
#else
- /*Call legacy weak (surcharged) callback*/
+ /*Call legacy weak callback*/
HAL_CORDIC_CalculateCpltCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
@@ -1278,7 +1274,7 @@
/*Call registered callback*/
hcordic->CalculateCpltCallback(hcordic);
#else
- /*Call legacy weak (surcharged) callback*/
+ /*Call legacy weak callback*/
HAL_CORDIC_CalculateCpltCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
@@ -1307,7 +1303,7 @@
/*Call registered callback*/
hcordic->CalculateCpltCallback(hcordic);
#else
- /*Call legacy weak (surcharged) callback*/
+ /*Call legacy weak callback*/
HAL_CORDIC_CalculateCpltCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
@@ -1332,7 +1328,7 @@
/*Call registered callback*/
hcordic->ErrorCallback(hcordic);
#else
- /*Call legacy weak (surcharged) callback*/
+ /*Call legacy weak callback*/
HAL_CORDIC_ErrorCallback(hcordic);
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
}
diff --git a/Src/stm32h7xx_hal_cortex.c b/Src/stm32h7xx_hal_cortex.c
index 05730c1..e272cfc 100644
--- a/Src/stm32h7xx_hal_cortex.c
+++ b/Src/stm32h7xx_hal_cortex.c
@@ -288,10 +288,43 @@
__DSB();
__ISB();
}
+
+/**
+ * @brief Enables the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disables the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
/**
* @brief Initializes and configures the Region and the memory to be protected.
- * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
- * the initialization and configuration information.
+ * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+ * the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
@@ -299,38 +332,32 @@
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
- if ((MPU_Init->Enable) != 0UL)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00;
- MPU->RASR = 0x00;
- }
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
diff --git a/Src/stm32h7xx_hal_crc.c b/Src/stm32h7xx_hal_crc.c
index 1deacc0..6690bc8 100644
--- a/Src/stm32h7xx_hal_crc.c
+++ b/Src/stm32h7xx_hal_crc.c
@@ -200,7 +200,7 @@
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+ CLEAR_REG(hcrc->Instance->IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
@@ -403,7 +403,7 @@
* @param hcrc CRC handle
* @retval HAL state
*/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
{
/* Return CRC handle state */
return hcrc->State;
diff --git a/Src/stm32h7xx_hal_crc_ex.c b/Src/stm32h7xx_hal_crc_ex.c
index d62af9d..b4ba3de 100644
--- a/Src/stm32h7xx_hal_crc_ex.c
+++ b/Src/stm32h7xx_hal_crc_ex.c
@@ -94,7 +94,7 @@
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
- /* Ensure that the generating polynomial is odd */
+ /* Ensure that the generating polynomial is odd */
if ((Pol & (uint32_t)(0x1U)) == 0U)
{
status = HAL_ERROR;
@@ -114,7 +114,7 @@
switch (PolyLength)
{
-
+
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
@@ -133,7 +133,7 @@
status = HAL_ERROR;
}
break;
-
+
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
diff --git a/Src/stm32h7xx_hal_cryp.c b/Src/stm32h7xx_hal_cryp.c
index b6c2755..61d732e 100644
--- a/Src/stm32h7xx_hal_cryp.c
+++ b/Src/stm32h7xx_hal_cryp.c
@@ -331,7 +331,7 @@
/* Private struct -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CRYP_Private_Functions_prototypes
+/** @addtogroup CRYP_Private_Functions_Prototypes
* @{
*/
@@ -782,7 +782,7 @@
/**
* @brief Unregister an CRYP Callback
- * CRYP callabck is redirected to the weak predefined callback
+ * CRYP callback is redirected to the weak predefined callback
* @param hcryp cryp handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1807,6 +1807,9 @@
/**
* @}
*/
+/**
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
/** @addtogroup CRYP_Private_Functions
@@ -5241,10 +5244,6 @@
* @}
*/
-/**
- * @}
- */
-
#endif /* HAL_CRYP_MODULE_ENABLED */
diff --git a/Src/stm32h7xx_hal_dac.c b/Src/stm32h7xx_hal_dac.c
index ef9bc02..a5e6225 100644
--- a/Src/stm32h7xx_hal_dac.c
+++ b/Src/stm32h7xx_hal_dac.c
@@ -238,7 +238,7 @@
and a pointer to the user callback function.
Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
(+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
(+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
@@ -253,9 +253,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DAC_Init
+ reset to the legacy weak (overridden) functions in the HAL_DAC_Init
and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -270,7 +270,7 @@
When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
*** DAC HAL driver macros list ***
=============================================
@@ -349,7 +349,7 @@
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
- /* Check DAC handle */
+ /* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
@@ -410,7 +410,7 @@
*/
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
{
- /* Check DAC handle */
+ /* Check the DAC peripheral handle */
if (hdac == NULL)
{
return HAL_ERROR;
@@ -513,6 +513,12 @@
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -568,6 +574,12 @@
*/
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -598,11 +610,17 @@
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment)
{
HAL_StatusTypeDef status;
- uint32_t tmpreg = 0U;
+ uint32_t tmpreg;
+
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -639,12 +657,10 @@
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
- case DAC_ALIGN_8B_R:
+ default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
- default:
- break;
}
}
@@ -673,17 +689,13 @@
/* Get DHR12L2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
break;
- case DAC_ALIGN_8B_R:
+ default: /* case DAC_ALIGN_8B_R */
/* Get DHR8R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
break;
- default:
- break;
}
}
-
- /* Enable the DMA Stream */
if (Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
@@ -732,6 +744,12 @@
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -780,10 +798,13 @@
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
{
- if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+ uint32_t itsource = hdac->Instance->CR;
+ uint32_t itflag = hdac->Instance->SR;
+
+ if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
{
/* Check underrun flag of DAC channel 1 */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+ if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -795,7 +816,7 @@
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -807,10 +828,10 @@
}
- if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+ if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
{
/* Check underrun flag of DAC channel 2 */
- if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+ if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
@@ -822,7 +843,7 @@
__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
/* Disable the selected DAC channel2 DMA request */
- CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+ __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
/* Error callback */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -855,6 +876,12 @@
{
__IO uint32_t tmp = 0UL;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
@@ -972,10 +999,13 @@
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
uint32_t result;
+ /* Check the DAC peripheral handle */
+ assert_param(hdac != NULL);
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -1004,13 +1034,21 @@
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+ const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
+ HAL_StatusTypeDef status = HAL_OK;
uint32_t tmpreg1;
uint32_t tmpreg2;
uint32_t tickstart;
uint32_t connectOnChip;
+ /* Check the DAC peripheral handle and channel configuration struct */
+ if ((hdac == NULL) || (sConfig == NULL))
+ {
+ return HAL_ERROR;
+ }
+
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
@@ -1050,7 +1088,7 @@
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* New check to avoid false timeout detection in case of preemption */
- if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+ if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
@@ -1062,7 +1100,6 @@
}
}
}
- HAL_Delay(1);
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
@@ -1075,7 +1112,7 @@
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
{
/* New check to avoid false timeout detection in case of preemption */
- if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+ if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
@@ -1087,7 +1124,6 @@
}
}
}
- HAL_Delay(1U);
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
}
@@ -1122,6 +1158,8 @@
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
+
+
if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
{
connectOnChip = 0x00000000UL;
@@ -1171,7 +1209,7 @@
__HAL_UNLOCK(hdac);
/* Return function status */
- return HAL_OK;
+ return status;
}
/**
@@ -1200,7 +1238,7 @@
* the configuration information for the specified DAC.
* @retval HAL state
*/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
{
/* Return DAC handle state */
return hdac->State;
@@ -1213,7 +1251,7 @@
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
@@ -1236,7 +1274,9 @@
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DAC Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
+ * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
+ * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1260,6 +1300,12 @@
{
HAL_StatusTypeDef status = HAL_OK;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
if (pCallback == NULL)
{
/* Update the error code */
@@ -1267,9 +1313,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hdac);
-
if (hdac->State == HAL_DAC_STATE_READY)
{
switch (CallbackID)
@@ -1340,14 +1383,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdac);
return status;
}
/**
* @brief Unregister a User DAC Callback
- * DAC Callback is redirected to the weak (surcharged) predefined callback
+ * DAC Callback is redirected to the weak (overridden) predefined callback
+ * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
+ * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1368,8 +1411,11 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hdac);
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
if (hdac->State == HAL_DAC_STATE_READY)
{
@@ -1455,8 +1501,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hdac);
return status;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@@ -1542,8 +1586,6 @@
#endif /* DAC1 || DAC2 */
#endif /* HAL_DAC_MODULE_ENABLED */
-
/**
* @}
*/
-
diff --git a/Src/stm32h7xx_hal_dac_ex.c b/Src/stm32h7xx_hal_dac_ex.c
index c9290be..15d998a 100644
--- a/Src/stm32h7xx_hal_dac_ex.c
+++ b/Src/stm32h7xx_hal_dac_ex.c
@@ -23,7 +23,6 @@
##### How to use this driver #####
==============================================================================
[..]
-
*** Dual mode IO operation ***
==============================
[..]
@@ -45,7 +44,6 @@
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
Channel 1 and Channel 2.
-
*** Signal generation operation ***
===================================
[..]
@@ -81,6 +79,16 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
+
+/* Delay for DAC minimum trimming time. */
+/* Note: minimum time needed between two calibration steps */
+/* The delay below is specified under conditions: */
+/* - DAC channel output buffer enabled */
+/* Literal set to maximum value (refer to device datasheet, */
+/* electrical characteristics, parameter "tTRIM"). */
+/* Unit: us */
+#define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -120,6 +128,12 @@
{
uint32_t tmp_swtrig = 0UL;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Process locked */
__HAL_LOCK(hdac);
@@ -161,6 +175,12 @@
*/
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
@@ -190,12 +210,18 @@
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
- uint32_t Alignment)
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+ const uint32_t *pData, uint32_t Length, uint32_t Alignment)
{
HAL_StatusTypeDef status;
uint32_t tmpreg = 0UL;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
@@ -303,6 +329,12 @@
{
HAL_StatusTypeDef status;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Disable the selected DAC channel DMA request */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
@@ -374,6 +406,12 @@
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -424,6 +462,12 @@
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
{
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -469,6 +513,12 @@
uint32_t data;
uint32_t tmp;
+ /* Check the DAC peripheral handle */
+ if (hdac == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
@@ -576,9 +626,9 @@
{
HAL_StatusTypeDef status = HAL_OK;
- __IO uint32_t tmp;
uint32_t trimmingvalue;
uint32_t delta;
+ __IO uint32_t wait_loop_index;
/* store/restore channel configuration structure purpose */
uint32_t oldmodeconfiguration;
@@ -588,7 +638,7 @@
/* Check the DAC handle allocation */
/* Check if DAC running */
- if (hdac == NULL)
+ if ((hdac == NULL) || (sConfig == NULL))
{
status = HAL_ERROR;
}
@@ -610,20 +660,6 @@
/* Set mode in MCR for calibration */
MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
- /* Set DAC Channel1 DHR register to the middle value */
- tmp = (uint32_t)hdac->Instance;
-
- if (Channel == DAC_CHANNEL_1)
- {
- tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
- }
- else
- {
- tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
- }
-
- *(__IO uint32_t *) tmp = 0x0800UL;
-
/* Enable the selected DAC channel calibration */
/* i.e. set DAC_CR_CENx bit */
SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
@@ -637,9 +673,15 @@
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
- /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
- /* i.e. minimum time needed between two calibration steps */
- HAL_Delay(1);
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+ /* 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
{
@@ -659,9 +701,15 @@
/* Set candidate trimming */
MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
- /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
- /* i.e. minimum time needed between two calibration steps */
- HAL_Delay(1U);
+ /* Wait minimum time needed between two calibration steps (OTRIM) */
+ /* Wait loop initialization and execution */
+ /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+ /* 32 bits register capacity and handle low frequency. */
+ wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+ while (wait_loop_index != 0UL)
+ {
+ wait_loop_index--;
+ }
if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
{
@@ -709,8 +757,8 @@
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
- /* Check the DAC handle allocation */
- if (hdac == NULL)
+ /* Check the DAC handle and channel configuration struct allocation */
+ if ((hdac == NULL) || (sConfig == NULL))
{
status = HAL_ERROR;
}
@@ -742,7 +790,7 @@
* @retval Trimming value : range: 0->31
*
*/
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
{
/* Check the parameter */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -776,7 +824,7 @@
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
{
uint32_t tmp = 0UL;
@@ -877,4 +925,3 @@
/**
* @}
*/
-
diff --git a/Src/stm32h7xx_hal_dma2d.c b/Src/stm32h7xx_hal_dma2d.c
index d535aa9..520841c 100644
--- a/Src/stm32h7xx_hal_dma2d.c
+++ b/Src/stm32h7xx_hal_dma2d.c
@@ -118,7 +118,7 @@
and a pointer to the user callback function.
(#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak (overridden) function.
@ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -130,16 +130,16 @@
(+) MspDeInitCallback : DMA2D MspDeInit.
(#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ all callbacks are reset to the corresponding legacy weak (overridden) functions:
examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+ reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init
and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
- as weak (surcharged) functions. They must be defined by the user to be resorted to.
+ as weak (overridden) functions. They must be defined by the user to be resorted to.
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
@@ -151,7 +151,7 @@
When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
[..]
(@) You can refer to the DMA2D HAL driver header file for more useful macros
@@ -431,7 +431,7 @@
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User DMA2D Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -530,7 +530,7 @@
/**
* @brief Unregister a DMA2D Callback
- * DMA2D Callback is redirected to the weak (surcharged) predefined callback
+ * DMA2D Callback is redirected to the weak (overridden) predefined callback
* @param hdma2d DMA2D handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -571,11 +571,11 @@
break;
case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
break;
default :
@@ -591,11 +591,11 @@
switch (CallbackID)
{
case HAL_DMA2D_MSPINIT_CB_ID :
- hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+ hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
break;
case HAL_DMA2D_MSPDEINIT_CB_ID :
- hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+ hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
break;
default :
diff --git a/Src/stm32h7xx_hal_dsi.c b/Src/stm32h7xx_hal_dsi.c
index ecdacb2..b2ae620 100644
--- a/Src/stm32h7xx_hal_dsi.c
+++ b/Src/stm32h7xx_hal_dsi.c
@@ -130,7 +130,7 @@
all callbacks are set to the corresponding weak functions:
examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
+ reset to the legacy weak (overridden) functions in the HAL_DSI_Init()
and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -395,24 +395,53 @@
}
}
+ __HAL_DSI_ENABLE(hdsi);
+
+ /************************ Set the DSI clock parameters ************************/
+ /* Set the TX escape clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+ hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+
/*************************** Set the PHY parameters ***************************/
-
/* D-PHY clock and digital enable*/
- hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+ hdsi->Instance->PCTLR |= DSI_PCTLR_DEN;
- /* Clock lane configuration */
- hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
- hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+ hdsi->Instance->PCTLR |= DSI_PCTLR_CKE;
+
/* Configure the number of active data lanes */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
- /************************ Set the DSI clock parameters ************************/
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+ {
+ while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC))
+ {
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
- /* Set the TX escape clock division factor */
- hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
- hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+ else
+ {
+ while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \
+ DSI_PSR_PSS1 | DSI_PSR_PSSC))
+ {
+ if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
/* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
/* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
@@ -431,6 +460,12 @@
hdsi->Instance->IER[1U] = 0U;
hdsi->ErrorMsk = 0U;
+ __HAL_DSI_DISABLE(hdsi);
+
+ /* Clock lane configuration */
+ hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+ hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+
/* Initialize the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
@@ -1628,14 +1663,14 @@
uint32_t Mode,
uint32_t NbParams,
uint32_t Param1,
- uint8_t *ParametersTable)
+ const uint8_t *ParametersTable)
{
uint32_t uicounter;
uint32_t nbBytes;
uint32_t count;
uint32_t tickstart;
uint32_t fifoword;
- uint8_t *pparams = ParametersTable;
+ const uint8_t *pparams = ParametersTable;
/* Process locked */
__HAL_LOCK(hdsi);
@@ -1852,6 +1887,16 @@
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
+ else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
/* Verify that there are no ULPS exit or request on data lanes */
if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U)
@@ -2170,6 +2215,16 @@
__HAL_UNLOCK(hdsi);
return HAL_ERROR;
}
+ else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
/* Verify that there are no ULPS exit or request on both data and clock lanes */
if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U)
@@ -3079,7 +3134,7 @@
* the configuration information for the DSI.
* @retval HAL state
*/
-HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
+HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi)
{
return hdsi->State;
}
@@ -3090,7 +3145,7 @@
* the configuration information for the DSI.
* @retval DSI Error Code
*/
-uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi)
{
/* Get the error code */
return hdsi->ErrorCode;
diff --git a/Src/stm32h7xx_hal_eth.c b/Src/stm32h7xx_hal_eth.c
index acee70e..2536a73 100644
--- a/Src/stm32h7xx_hal_eth.c
+++ b/Src/stm32h7xx_hal_eth.c
@@ -202,7 +202,7 @@
#define ETH_MACRFCR_MASK 0x00000003U
#define ETH_MTLTQOMR_MASK 0x00000072U
#define ETH_MTLRQOMR_MASK 0x0000007BU
-
+
#define ETH_DMAMR_MASK 0x00007802U
#define ETH_DMASBMR_MASK 0x0000D001U
#define ETH_DMACCR_MASK 0x00013FFFU
@@ -250,12 +250,13 @@
/** @defgroup ETH_Private_Functions ETH Private Functions
* @{
*/
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
+ uint32_t ItMode);
static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
@@ -410,13 +411,13 @@
heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
- /* Disable Rx MMC Interrupts */
- SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
- ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
+ /* Disable Rx MMC Interrupts */
+ SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
+ ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
- /* Disable Tx MMC Interrupts */
- SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
- ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
+ /* Disable Tx MMC Interrupts */
+ SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
+ ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
heth->ErrorCode = HAL_ETH_ERROR_NONE;
heth->gState = HAL_ETH_STATE_READY;
@@ -514,7 +515,6 @@
{
/* Update the error code */
heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-
return HAL_ERROR;
}
@@ -595,7 +595,7 @@
/**
* @brief Unregister an ETH Callback
- * ETH callabck is redirected to the weak predefined callback
+ * ETH callback is redirected to the weak predefined callback
* @param heth eth handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -720,7 +720,7 @@
{
heth->gState = HAL_ETH_STATE_BUSY;
- /* Set nombre of descriptors to build */
+ /* Set number of descriptors to build */
heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
/* Build all descriptors */
@@ -769,21 +769,12 @@
/* save IT mode to ETH Handle */
heth->RxDescList.ItMode = 1U;
- /* Set nombre of descriptors to build */
+ /* Set number of descriptors to build */
heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
/* Build all descriptors */
ETH_UpdateDescriptor(heth);
- /* Enable the MAC transmission */
- SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
-
- /* Enable the MAC reception */
- SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
- /* Set the Flush Transmit FIFO bit */
- SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
-
/* Enable the DMA transmission */
SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
@@ -793,6 +784,15 @@
/* Clear Tx and Rx process stopped flags */
heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
+ /* Set the Flush Transmit FIFO bit */
+ SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+ /* Enable the MAC transmission */
+ SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+ /* Enable the MAC reception */
+ SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
/* Enable ETH DMA interrupts:
- Tx complete interrupt
- Rx complete interrupt
@@ -822,6 +822,7 @@
{
/* Set the ETH peripheral state to BUSY */
heth->gState = HAL_ETH_STATE_BUSY;
+
/* Disable the DMA transmission */
CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
@@ -880,6 +881,7 @@
/* Disable the MAC reception */
CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
/* Set the Flush Transmit FIFO bit */
SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
@@ -914,7 +916,7 @@
* @param Timeout: timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
{
uint32_t tickstart;
ETH_DMADescTypeDef *dmatxdesc;
@@ -989,7 +991,7 @@
* @param pTxConfig: Hold the configuration of packet to be transmitted
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
{
if (pTxConfig == NULL)
{
@@ -1044,7 +1046,6 @@
uint32_t bufflength;
uint8_t rxdataready = 0U;
-
if (pAppBuff == NULL)
{
heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
@@ -1080,12 +1081,12 @@
heth->RxDescList.RxDataLength = 0;
}
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+ bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
+
/* Check if last descriptor */
- bufflength = heth->Init.RxBuffLen;
if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
{
- bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
-
/* Save Last descriptor index */
heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
@@ -1150,8 +1151,8 @@
*/
static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
{
- uint32_t tailidx;
uint32_t descidx;
+ uint32_t tailidx;
uint32_t desccount;
ETH_DMADescTypeDef *dmarxdesc;
uint8_t *buff = NULL;
@@ -1187,6 +1188,7 @@
if (allocStatus != 0U)
{
+
if (heth->RxDescList.ItMode != 0U)
{
WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC);
@@ -1273,7 +1275,7 @@
/**
* @brief Rx Link callback.
* @param pStart: pointer to packet start
- * @param pStart: pointer to packet end
+ * @param pEnd: pointer to packet end
* @param buff: pointer to received data
* @param Length: received data length
* @retval None
@@ -1332,7 +1334,7 @@
* @param pErrorCode: pointer to uint32_t to hold the error code
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
{
/* Get error bits. */
*pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK);
@@ -1415,7 +1417,7 @@
if (dmatxdesclist->PacketAddress[idx] == NULL)
{
/* No packet in use, skip to next. */
- idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
+ INCR_TX_DESC_INDEX(idx, 1U);
pktInUse = 0U;
}
@@ -1429,13 +1431,13 @@
/* Disable Ptp transmission */
CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U));
- if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD )
- && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
+ if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD)
+ && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
{
- /* Get timestamp low */
- timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
- /* Get timestamp high */
- timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
+ /* Get timestamp low */
+ timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
+ /* Get timestamp high */
+ timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
}
else
{
@@ -1471,7 +1473,7 @@
dmatxdesclist->PacketAddress[idx] = NULL;
/* Update the transmit relesae index and number of buffers in use. */
- idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U);
+ INCR_TX_DESC_INDEX(idx, 1U);
dmatxdesclist->BuffersInUse = numOfBuf;
dmatxdesclist->releaseIndex = idx;
}
@@ -1531,25 +1533,24 @@
if (ptpconfig->TimestampAddendUpdate == ENABLE)
{
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG);
- while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0) {}
- }
+ while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0)
+ {
- /* Enable Update mode */
- if (ptpconfig->TimestampUpdateMode == ENABLE)
- {
- SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCFUPDT);
+ }
}
- /* Initialize Time */
- time.Seconds = 0;
- time.NanoSeconds = 0;
- HAL_ETH_PTP_SetTime(heth, &time);
-
/* Ptp Init */
SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
/* Set PTP Configuration done */
- heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED;
+ heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
+
+ /* Set Seconds */
+ time.Seconds = heth->Instance->MACSTSR;
+ /* Set NanoSeconds */
+ time.NanoSeconds = heth->Instance->MACSTNR;
+
+ HAL_ETH_PTP_SetTime(heth, &time);
/* Return function status */
return HAL_OK;
@@ -1609,13 +1610,13 @@
* @brief Set Seconds and Nanoseconds for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param heth: pointer to a ETH_TimeTypeDef structure that contains
+ * @param time: pointer to a ETH_TimeTypeDef structure that contains
* time to set
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
{
- if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Set Seconds */
heth->Instance->MACSTSUR = time->Seconds;
@@ -1623,6 +1624,9 @@
/* Set NanoSeconds */
heth->Instance->MACSTNUR = time->NanoSeconds;
+ /* the system time is updated */
+ SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
+
/* Return function status */
return HAL_OK;
}
@@ -1637,19 +1641,18 @@
* @brief Get Seconds and Nanoseconds for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param heth: pointer to a ETH_TimeTypeDef structure that contains
+ * @param time: pointer to a ETH_TimeTypeDef structure that contains
* time to get
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
{
- if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Get Seconds */
- time->Seconds = heth->Instance->MACSTSUR;
-
+ time->Seconds = heth->Instance->MACSTSR;
/* Get NanoSeconds */
- time->NanoSeconds = heth->Instance->MACSTNUR;
+ time->NanoSeconds = heth->Instance->MACSTNR;
/* Return function status */
return HAL_OK;
@@ -1665,14 +1668,14 @@
* @brief Update time for the Ethernet PTP registers.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains
+ * @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
* the time update information
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
ETH_TimeTypeDef *timeoffset)
{
- if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE)
{
@@ -1698,6 +1701,8 @@
heth->Instance->MACSTNUR = timeoffset->NanoSeconds;
}
+ SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
+
/* Return function status */
return HAL_OK;
}
@@ -1712,7 +1717,6 @@
* @brief Insert Timestamp in transmission.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param txtimestampconf: Enable or Disable timestamp in transmission
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
@@ -1721,7 +1725,7 @@
uint32_t descidx = dmatxdesclist->CurTxDesc;
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
- if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Enable Time Stamp transmission */
SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE);
@@ -1750,7 +1754,7 @@
uint32_t idx = dmatxdesclist->releaseIndex;
ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
- if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Get timestamp low */
timestamp->TimeStampLow = dmatxdesc->DESC0;
@@ -1777,7 +1781,7 @@
*/
HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
{
- if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED)
+ if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
{
/* Get timestamp low */
timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
@@ -1831,6 +1835,8 @@
/**
* @brief Tx Ptp callback.
* @param buff: pointer to application buffer
+ * @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains
+ * transmission timestamp
* @retval None
*/
__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
@@ -1851,88 +1857,82 @@
*/
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
- uint32_t macirqenable;
+ uint32_t mac_flag = READ_REG(heth->Instance->MACISR);
+ uint32_t dma_flag = READ_REG(heth->Instance->DMACSR);
+ uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER);
+ uint32_t exti_d1_flag = READ_REG(EXTI_D1->PR3);
+#if defined(DUAL_CORE)
+ uint32_t exti_d2_flag = READ_REG(EXTI_D2->PR3);
+#endif /* DUAL_CORE */
+
/* Packet received */
- if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
+ if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U))
{
- if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
- {
- /* Clear the Eth DMA Rx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
+ /* Clear the Eth DMA Rx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- /*Call registered Receive complete callback*/
- heth->RxCpltCallback(heth);
+ /*Call registered Receive complete callback*/
+ heth->RxCpltCallback(heth);
#else
- /* Receive complete callback */
- HAL_ETH_RxCpltCallback(heth);
+ /* Receive complete callback */
+ HAL_ETH_RxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
- }
}
/* Packet transmitted */
- if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
+ if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U))
{
- if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
- {
- /* Clear the Eth DMA Tx IT pending bits */
- __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
+ /* Clear the Eth DMA Tx IT pending bits */
+ __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- /*Call registered Transmit complete callback*/
- heth->TxCpltCallback(heth);
+ /*Call registered Transmit complete callback*/
+ heth->TxCpltCallback(heth);
#else
- /* Transfer complete callback */
- HAL_ETH_TxCpltCallback(heth);
+ /* Transfer complete callback */
+ HAL_ETH_TxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
- }
}
-
/* ETH DMA Error */
- if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
+ if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U))
{
- if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
+ heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+ /* if fatal bus error occurred */
+ if ((dma_flag & ETH_DMACSR_FBE) != 0U)
{
- heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+ /* Get DMA error code */
+ heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
- /* if fatal bus error occurred */
- if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
- {
- /* Get DMA error code */
- heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
+ /* Disable all interrupts */
+ __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
- /* Disable all interrupts */
- __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
-
- /* Set HAL state to ERROR */
- heth->gState = HAL_ETH_STATE_ERROR;
- }
- else
- {
- /* Get DMA error status */
- heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- ETH_DMACSR_RBU | ETH_DMACSR_AIS));
-
- /* Clear the interrupt summary flag */
- __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
- ETH_DMACSR_RBU | ETH_DMACSR_AIS));
- }
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
- /* Call registered Error callback*/
- heth->ErrorCallback(heth);
-#else
- /* Ethernet DMA Error callback */
- HAL_ETH_ErrorCallback(heth);
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
+ /* Set HAL state to ERROR */
+ heth->gState = HAL_ETH_STATE_ERROR;
}
+ else
+ {
+ /* Get DMA error status */
+ heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+
+ /* Clear the interrupt summary flag */
+ __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+ ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+ }
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback*/
+ heth->ErrorCallback(heth);
+#else
+ /* Ethernet DMA Error callback */
+ HAL_ETH_ErrorCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* ETH MAC Error IT */
- macirqenable = heth->Instance->MACIER;
- if (((macirqenable & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
- ((macirqenable & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
+ if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+ ((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
{
heth->ErrorCode |= HAL_ETH_ERROR_MAC;
@@ -1948,12 +1948,11 @@
/* Ethernet Error callback */
HAL_ETH_ErrorCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
heth->MACErrorCode = (uint32_t)(0x0U);
}
/* ETH PMT IT */
- if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
+ if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
{
/* Get MAC Wake-up source and clear the status register pending bit */
heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
@@ -1970,7 +1969,7 @@
}
/* ETH EEE IT */
- if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
+ if ((mac_flag & ETH_MAC_LPI_IT) != 0U)
{
/* Get MAC LPI interrupt source and clear the status register pending bit */
heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU);
@@ -1990,7 +1989,7 @@
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* check ETH WAKEUP exti flag */
- if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -2006,7 +2005,7 @@
else
{
/* check ETH WAKEUP exti flag */
- if (__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ if ((exti_d2_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -2019,9 +2018,9 @@
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
}
-#else /* USE_HAL_ETH_REGISTER_CALLBACKS */
+#else /* DUAL_CORE not defined */
/* check ETH WAKEUP exti flag */
- if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+ if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -2033,7 +2032,7 @@
HAL_ETH_WakeUpCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
-#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+#endif /* DUAL_CORE */
}
/**
@@ -2181,7 +2180,6 @@
return HAL_OK;
}
-
/**
* @brief Writes to a PHY register.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
@@ -2191,7 +2189,7 @@
* @param RegValue: the value to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
uint32_t RegValue)
{
uint32_t tickstart;
@@ -2217,7 +2215,6 @@
MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
-
/* Give the value to the MII data register */
WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
@@ -2264,7 +2261,7 @@
* the configuration of the MAC.
* @retval HAL Status
*/
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
{
if (macconf == NULL)
{
@@ -2305,7 +2302,6 @@
? ENABLE : DISABLE;
macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
-
macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
@@ -2313,8 +2309,6 @@
macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
-
-
macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
? ENABLE : DISABLE;
@@ -2339,7 +2333,7 @@
* the configuration of the ETH DMA.
* @retval HAL Status
*/
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
{
if (dmaconf == NULL)
{
@@ -2361,6 +2355,7 @@
dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
+
return HAL_OK;
}
@@ -2482,7 +2477,7 @@
* the configuration of the ETH MAC filters.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
{
uint32_t filterconfig;
@@ -2516,7 +2511,7 @@
* the configuration of the ETH MAC filters.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
{
if (pFilterConfig == NULL)
{
@@ -2553,7 +2548,8 @@
* @param pMACAddr: Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
+ const uint8_t *pMACAddr)
{
uint32_t macaddrlr;
uint32_t macaddrhr;
@@ -2632,7 +2628,7 @@
* that contains the Power Down configuration
* @retval None.
*/
-void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
{
uint32_t powerdownconfig;
@@ -2727,7 +2723,7 @@
* the configuration information for ETHERNET module
* @retval HAL state
*/
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
+HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
{
return heth->gState;
}
@@ -2738,7 +2734,7 @@
* the configuration information for ETHERNET module
* @retval ETH Error Code
*/
-uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
{
return heth->ErrorCode;
}
@@ -2749,7 +2745,7 @@
* the configuration information for ETHERNET module
* @retval ETH DMA Error Code
*/
-uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
{
return heth->DMAErrorCode;
}
@@ -2760,7 +2756,7 @@
* the configuration information for ETHERNET module
* @retval ETH MAC Error Code
*/
-uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
{
return heth->MACErrorCode;
}
@@ -2771,7 +2767,7 @@
* the configuration information for ETHERNET module
* @retval ETH MAC WakeUp event source
*/
-uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
{
return heth->MACWakeUpEvent;
}
@@ -2788,8 +2784,7 @@
* @{
*/
-
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
{
uint32_t macregval;
@@ -2866,7 +2861,7 @@
MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
}
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
{
uint32_t dmaregval;
@@ -2883,7 +2878,6 @@
/*------------------------ DMACCR Configuration --------------------*/
dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
dmaconf->MaximumSegmentSize);
-
MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
/*------------------------ DMACTCR Configuration --------------------*/
@@ -2925,17 +2919,17 @@
macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
macDefaultConf.ExtendedInterPacketGap = DISABLE;
- macDefaultConf.ExtendedInterPacketGapVal = 0x0;
+ macDefaultConf.ExtendedInterPacketGapVal = 0x0U;
macDefaultConf.ForwardRxErrorPacket = DISABLE;
macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
- macDefaultConf.GiantPacketSizeLimit = 0x618;
+ macDefaultConf.GiantPacketSizeLimit = 0x618U;
macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
macDefaultConf.Jabber = ENABLE;
macDefaultConf.JumboPacket = DISABLE;
macDefaultConf.LoopbackMode = DISABLE;
macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
- macDefaultConf.PauseTime = 0x0;
+ macDefaultConf.PauseTime = 0x0U;
macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
macDefaultConf.ProgrammableWatchdog = DISABLE;
macDefaultConf.ReceiveFlowControl = DISABLE;
@@ -2974,7 +2968,6 @@
ETH_SetDMAConfig(heth, &dmaDefaultConf);
}
-
/**
* @brief Initializes the DMA Tx descriptors.
* called by HAL_ETH_Init() API.
@@ -2992,10 +2985,10 @@
{
dmatxdesc = heth->Init.TxDesc + i;
- WRITE_REG(dmatxdesc->DESC0, 0x0);
- WRITE_REG(dmatxdesc->DESC1, 0x0);
- WRITE_REG(dmatxdesc->DESC2, 0x0);
- WRITE_REG(dmatxdesc->DESC3, 0x0);
+ WRITE_REG(dmatxdesc->DESC0, 0x0U);
+ WRITE_REG(dmatxdesc->DESC1, 0x0U);
+ WRITE_REG(dmatxdesc->DESC2, 0x0U);
+ WRITE_REG(dmatxdesc->DESC3, 0x0U);
WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
@@ -3029,24 +3022,23 @@
{
dmarxdesc = heth->Init.RxDesc + i;
- WRITE_REG(dmarxdesc->DESC0, 0x0);
- WRITE_REG(dmarxdesc->DESC1, 0x0);
- WRITE_REG(dmarxdesc->DESC2, 0x0);
- WRITE_REG(dmarxdesc->DESC3, 0x0);
- WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
- WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
-
+ WRITE_REG(dmarxdesc->DESC0, 0x0U);
+ WRITE_REG(dmarxdesc->DESC1, 0x0U);
+ WRITE_REG(dmarxdesc->DESC2, 0x0U);
+ WRITE_REG(dmarxdesc->DESC3, 0x0U);
+ WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
+ WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
/* Set Rx descritors addresses */
WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
}
- WRITE_REG(heth->RxDescList.RxDescIdx, 0);
- WRITE_REG(heth->RxDescList.RxDescCnt, 0);
- WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0);
- WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0);
- WRITE_REG(heth->RxDescList.ItMode, 0);
+ WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
+ WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
+ WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
+ WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
+ WRITE_REG(heth->RxDescList.ItMode, 0U);
/* Set Receive Descriptor Ring Length */
WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
@@ -3067,7 +3059,8 @@
* @param ItMode: Enable or disable Tx EOT interrept
* @retval Status
*/
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
+ uint32_t ItMode)
{
ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
uint32_t descidx = dmatxdesclist->CurTxDesc;
@@ -3177,7 +3170,7 @@
}
else
{
- WRITE_REG(dmatxdesc->DESC1, 0x0);
+ WRITE_REG(dmatxdesc->DESC1, 0x0U);
/* Set buffer 2 Length */
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
}
@@ -3285,7 +3278,7 @@
}
else
{
- WRITE_REG(dmatxdesc->DESC1, 0x0);
+ WRITE_REG(dmatxdesc->DESC1, 0x0U);
/* Set buffer 2 Length */
MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
}
@@ -3384,4 +3377,3 @@
/**
* @}
*/
-
diff --git a/Src/stm32h7xx_hal_eth_ex.c b/Src/stm32h7xx_hal_eth_ex.c
index ad9870c..feb0cfd 100644
--- a/Src/stm32h7xx_hal_eth_ex.c
+++ b/Src/stm32h7xx_hal_eth_ex.c
@@ -33,7 +33,6 @@
* @{
*/
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
@@ -57,6 +56,9 @@
#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
ETH_MACVIR_VLP | ETH_MACVIR_VLC)
+
+#define ETH_MAC_L4_SRSP_MASK 0x0000FFFFU
+#define ETH_MAC_L4_DSTP_MASK 0xFFFF0000U
/**
* @}
*/
@@ -91,6 +93,7 @@
* the configuration information for ETHERNET module
* @retval None
*/
+
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
{
SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
@@ -133,25 +136,34 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
- ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+ const ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
- __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
-
if (pL4FilterConfig == NULL)
{
return HAL_ERROR;
}
- /* Write configuration to (MACL3L4C0R + filter )register */
- MODIFY_REG(*configreg, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
- pL4FilterConfig->SrcPortFilterMatch |
- pL4FilterConfig->DestPortFilterMatch));
+ if (Filter == ETH_L4_FILTER_0)
+ {
+ /* Write configuration to MACL3L4C0R register */
+ MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
+ pL4FilterConfig->SrcPortFilterMatch |
+ pL4FilterConfig->DestPortFilterMatch));
- configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
+ /* Write configuration to MACL4A0R register */
+ WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
- /* Write configuration to (MACL4A0R + filter )register */
- MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP), (pL4FilterConfig->SourcePort |
- (pL4FilterConfig->DestinationPort << 16)));
+ }
+ else /* Filter == ETH_L4_FILTER_1 */
+ {
+ /* Write configuration to MACL3L4C1R register */
+ MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
+ pL4FilterConfig->SrcPortFilterMatch |
+ pL4FilterConfig->DestPortFilterMatch));
+
+ /* Write configuration to MACL4A1R register */
+ WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
+ }
/* Enable L4 filter */
SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
@@ -172,7 +184,7 @@
* that contains L4 filter configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L4FilterConfigTypeDef *pL4FilterConfig)
{
if (pL4FilterConfig == NULL)
@@ -180,18 +192,32 @@
return HAL_ERROR;
}
- /* Get configuration to (MACL3L4C0R + filter )register */
- pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
- ETH_MACL3L4CR_L4PEN);
- pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
- (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
- pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
- (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
+ if (Filter == ETH_L4_FILTER_0)
+ {
+ /* Get configuration from MACL3L4C0R register */
+ pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN);
+ pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
+ (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
+ pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
+ (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
- /* Get configuration to (MACL3L4C0R + filter )register */
- pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)),
- ETH_MACL4AR_L4DP) >> 16);
- pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
+ /* Get configuration from MACL4A0R register */
+ pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16);
+ pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK);
+ }
+ else /* Filter == ETH_L4_FILTER_1 */
+ {
+ /* Get configuration from MACL3L4C1R register */
+ pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN);
+ pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
+ (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
+ pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
+ (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
+
+ /* Get configuration from MACL4A1R register */
+ pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16);
+ pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK);
+ }
return HAL_OK;
}
@@ -210,43 +236,83 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
- ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+ const ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
- __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
-
if (pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
- /* Write configuration to (MACL3L4C0R + filter )register */
- MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
- pL3FilterConfig->SrcAddrFilterMatch |
- pL3FilterConfig->DestAddrFilterMatch |
- (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
- (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+ if (Filter == ETH_L3_FILTER_0)
+ {
+ /* Write configuration to MACL3L4C0R register */
+ MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+ pL3FilterConfig->SrcAddrFilterMatch |
+ pL3FilterConfig->DestAddrFilterMatch |
+ (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+ (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+ }
+ else /* Filter == ETH_L3_FILTER_1 */
+ {
+ /* Write configuration to MACL3L4C1R register */
+ MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+ pL3FilterConfig->SrcAddrFilterMatch |
+ pL3FilterConfig->DestAddrFilterMatch |
+ (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+ (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+ }
- /* Check if IPv6 protocol is selected */
- if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ if (Filter == ETH_L3_FILTER_0)
{
- /* Set the IPv6 address match */
- /* Set Bits[31:0] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
- /* Set Bits[63:32] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
- /* update Bits[95:64] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
- /* update Bits[127:96] of 128-bit IP addr */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
+ /* Check if IPv6 protocol is selected */
+ if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ {
+ /* Set the IPv6 address match */
+ /* Set Bits[31:0] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]);
+ /* Set Bits[63:32] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]);
+ /* update Bits[95:64] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]);
+ /* update Bits[127:96] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]);
+ }
+ else /* IPv4 protocol is selected */
+ {
+ /* Set the IPv4 source address match */
+ WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr);
+ /* Set the IPv4 destination address match */
+ WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr);
+ }
}
- else /* IPv4 protocol is selected */
+ else /* Filter == ETH_L3_FILTER_1 */
{
- /* Set the IPv4 source address match */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
- /* Set the IPv4 destination address match */
- *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
+ /* Check if IPv6 protocol is selected */
+ if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ {
+ /* Set the IPv6 address match */
+ /* Set Bits[31:0] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]);
+ /* Set Bits[63:32] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]);
+ /* update Bits[95:64] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]);
+ /* update Bits[127:96] of 128-bit IP addr */
+ WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]);
+ }
+ else /* IPv4 protocol is selected */
+ {
+ /* Set the IPv4 source address match */
+ WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr);
+ /* Set the IPv4 destination address match */
+ WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr);
+
+ }
}
+ /* Enable L3 filter */
+ SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+
return HAL_OK;
}
@@ -263,14 +329,13 @@
* that will contain the L3 filter configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
ETH_L3FilterConfigTypeDef *pL3FilterConfig)
{
if (pL3FilterConfig == NULL)
{
return HAL_ERROR;
}
-
pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
ETH_MACL3L4CR_L3PEN);
pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
@@ -282,17 +347,35 @@
pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
ETH_MACL3L4CR_L3HDBM) >> 11);
- if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ if (Filter == ETH_L3_FILTER_0)
{
- pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
- pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
- pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
- pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
+ if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ {
+ WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R);
+ WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R);
+ WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R);
+ WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R);
+ }
+ else
+ {
+ WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R);
+ WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R);
+ }
}
- else
+ else /* ETH_L3_FILTER_1 */
{
- pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
- pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
+ if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+ {
+ WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R);
+ WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R);
+ WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R);
+ WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R);
+ }
+ else
+ {
+ WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R);
+ WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R);
+ }
}
return HAL_OK;
@@ -330,7 +413,7 @@
* that will contain the VLAN filter configuration.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
{
if (pVlanConfig == NULL)
{
@@ -340,12 +423,14 @@
pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripInnerVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
- pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR,
+ ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR,
ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
- pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
+ pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
+ ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR,
(ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
@@ -407,7 +492,7 @@
* that will contain the Tx VLAN filter configuration.
* @retval HAL Status.
*/
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
ETH_TxVLANConfigTypeDef *pVlanConfig)
{
if (pVlanConfig == NULL)
@@ -443,7 +528,7 @@
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
- ETH_TxVLANConfigTypeDef *pVlanConfig)
+ const ETH_TxVLANConfigTypeDef *pVlanConfig)
{
if (VLANTag == ETH_INNER_TX_VLANTAG)
{
@@ -544,14 +629,13 @@
__HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
}
-
/**
* @brief Returns the ETH MAC LPI event
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval ETH MAC WakeUp event
*/
-uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth)
{
return heth->MACLPIEvent;
}
@@ -571,8 +655,6 @@
#endif /* ETH */
#endif /* HAL_ETH_MODULE_ENABLED */
-
/**
* @}
*/
-
diff --git a/Src/stm32h7xx_hal_exti.c b/Src/stm32h7xx_hal_exti.c
index c9090f7..fe54a03 100644
--- a/Src/stm32h7xx_hal_exti.c
+++ b/Src/stm32h7xx_hal_exti.c
@@ -98,7 +98,7 @@
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
- (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+ (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@@ -109,7 +109,7 @@
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
- (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+ (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@@ -742,6 +742,9 @@
uint32_t maskline;
uint32_t offset;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Edge);
+
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
@@ -788,6 +791,9 @@
uint32_t maskline;
uint32_t offset;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Edge);
+
/* Check parameters */
assert_param(IS_EXTI_LINE(hexti->Line));
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
diff --git a/Src/stm32h7xx_hal_fdcan.c b/Src/stm32h7xx_hal_fdcan.c
index b3804c2..a0a86f1 100644
--- a/Src/stm32h7xx_hal_fdcan.c
+++ b/Src/stm32h7xx_hal_fdcan.c
@@ -10,7 +10,6 @@
* + IO operation functions
* + Peripheral Configuration and Control functions
* + Peripheral State and Error functions
- *
******************************************************************************
* @attention
*
@@ -82,7 +81,6 @@
*** Polling mode operation ***
==============================
-
[..]
(#) Reception and transmission states can be monitored via the following
functions:
@@ -124,7 +122,7 @@
For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
- TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
+ TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks:
respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(),
HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(),
@@ -149,7 +147,7 @@
For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
- register callbacks : respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+ register callbacks: respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(),
HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(),
HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(),
@@ -241,14 +239,20 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Variables
+ * @{
+ */
static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+/**
+ * @}
+ */
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup FDCAN_Private_Functions_Prototypes
* @{
*/
static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
const uint8_t *pTxData, uint32_t BufferIndex);
/**
* @}
@@ -524,9 +528,9 @@
/* If FD operation with BRS is selected, set the data bit timing register */
if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
{
- hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
- (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
- (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
+ hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
+ (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
+ (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
(((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
}
@@ -643,7 +647,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspInit could be implemented in the user file
*/
}
@@ -658,7 +662,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_MspDeInit could be implemented in the user file
*/
}
@@ -1227,8 +1231,8 @@
/**
* @brief UnRegister the Tx Buffer Complete FDCAN Callback
- * Tx Buffer Complete FDCAN Callback is redirected to the weak
- * HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+ * Tx Buffer Complete FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
@@ -1289,8 +1293,8 @@
/**
* @brief UnRegister the Tx Buffer Abort FDCAN Callback
- * Tx Buffer Abort FDCAN Callback is redirected to the weak
- * HAL_FDCAN_TxBufferAbortCallback() predefined callback
+ * Tx Buffer Abort FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
@@ -1710,7 +1714,8 @@
SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
/* Configure clock divider */
- MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+ MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV,
+ (sCcuConfig->ClockDivider << FDCANCCU_CCFG_CDIV_Pos));
}
else /* sCcuConfig->ClockCalibration == ENABLE */
{
@@ -1975,7 +1980,7 @@
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @param Mask Extended ID Mask.
- * This parameter must be a number between 0 and 0x1FFFFFFF
+ * This parameter must be a number between 0 and 0x1FFFFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
@@ -2023,12 +2028,12 @@
if (RxFifo == FDCAN_RX_FIFO0)
{
/* Select FIFO 0 Operation Mode */
- MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+ MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, (OperationMode << FDCAN_RXF0C_F0OM_Pos));
}
else /* RxFifo == FDCAN_RX_FIFO1 */
{
/* Select FIFO 1 Operation Mode */
- MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+ MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, (OperationMode << FDCAN_RXF1C_F1OM_Pos));
}
/* Return function status */
@@ -2216,7 +2221,7 @@
* @brief Get the timestamp counter value.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
- * @retval Value Timestamp counter value
+ * @retval Timestamp counter value
*/
uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan)
{
@@ -2270,8 +2275,8 @@
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Select timeout operation and configure period */
- MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP),
- (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+ MODIFY_REG(hfdcan->Instance->TOCC,
+ (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
/* Return function status */
return HAL_OK;
@@ -2339,7 +2344,7 @@
* @brief Get the timeout counter value.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
- * @retval Value Timeout counter value
+ * @retval Timeout counter value
*/
uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan)
{
@@ -2574,21 +2579,22 @@
[..] This section provides functions allowing to:
(+) HAL_FDCAN_Start : Start the FDCAN module
(+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers
- (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the
- corresponding transmission request
+ (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding
+ transmission request
(+) HAL_FDCAN_AddMessageToTxBuffer : Add a message to a dedicated Tx buffer
(+) HAL_FDCAN_EnableTxBufferRequest : Enable transmission request
(+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
(+) HAL_FDCAN_AbortTxRequest : Abort transmission request
(+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx Buffer/FIFO zone into the
message RAM
- (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone into the
- message RAM
+ (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone
+ into the message RAM
(+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
(+) HAL_FDCAN_GetProtocolStatus : Get protocol status
(+) HAL_FDCAN_GetErrorCounters : Get error counter values
(+) HAL_FDCAN_IsRxBufferMessageAvailable : Check if a new message is received in the selected Rx buffer
- (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending on the selected Tx buffer
+ (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending
+ on the selected Tx buffer
(+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
(+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
(+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode
@@ -2995,7 +3001,7 @@
return HAL_ERROR;
}
- /* Check that the Rx FIFO 0 is not empty */
+ /* Check that the Rx FIFO 1 is not empty */
if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
{
/* Update error code */
@@ -3045,7 +3051,7 @@
/* Retrieve Identifier */
if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
{
- pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+ pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
}
else /* Extended ID element */
{
@@ -3065,7 +3071,7 @@
pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
- pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+ pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
/* Retrieve BitRateSwitch */
pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
@@ -3074,17 +3080,17 @@
pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
/* Retrieve FilterIndex */
- pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+ pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
/* Retrieve NonMatchingFrame */
- pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+ pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
/* Increment RxAddress pointer to payload of Rx FIFO element */
RxAddress++;
/* Retrieve Rx payload */
pData = (uint8_t *)RxAddress;
- for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
{
pRxData[ByteCounter] = pData[ByteCounter];
}
@@ -3104,11 +3110,11 @@
/* Clear the New Data flag of the current Rx buffer */
if (RxLocation < FDCAN_RX_BUFFER32)
{
- hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+ hfdcan->Instance->NDAT1 = ((uint32_t)1U << RxLocation);
}
else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
{
- hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+ hfdcan->Instance->NDAT2 = ((uint32_t)1U << (RxLocation & 0x1FU));
}
}
@@ -3190,7 +3196,7 @@
pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
/* Retrieve DataLength */
- pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+ pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
/* Retrieve BitRateSwitch */
pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
@@ -3202,7 +3208,7 @@
pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
/* Retrieve MessageMarker */
- pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+ pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
/* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
hfdcan->Instance->TXEFA = GetIndex;
@@ -3360,7 +3366,7 @@
* This parameter can be one of the following values:
* @arg FDCAN_RX_FIFO0: Rx FIFO 0
* @arg FDCAN_RX_FIFO1: Rx FIFO 1
- * @retval Level Rx FIFO fill level.
+ * @retval Rx FIFO fill level.
*/
uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
{
@@ -3387,7 +3393,7 @@
* elements starting from Tx FIFO GetIndex.
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
- * @retval Level Tx FIFO free level.
+ * @retval Tx FIFO free level.
*/
uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan)
{
@@ -5268,7 +5274,7 @@
if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
{
- /* Disable Interrupt line 1 */
+ /* Disable interrupt line 1 */
CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
}
@@ -5726,7 +5732,7 @@
UNUSED(hfdcan);
UNUSED(ClkCalibrationITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
*/
}
@@ -5745,7 +5751,7 @@
UNUSED(hfdcan);
UNUSED(TxEventFifoITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
*/
}
@@ -5764,7 +5770,7 @@
UNUSED(hfdcan);
UNUSED(RxFifo0ITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
*/
}
@@ -5783,7 +5789,7 @@
UNUSED(hfdcan);
UNUSED(RxFifo1ITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
*/
}
@@ -5799,7 +5805,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
*/
}
@@ -5818,7 +5824,7 @@
UNUSED(hfdcan);
UNUSED(BufferIndexes);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
*/
}
@@ -5837,7 +5843,7 @@
UNUSED(hfdcan);
UNUSED(BufferIndexes);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
*/
}
@@ -5853,7 +5859,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
*/
}
@@ -5869,7 +5875,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
*/
}
@@ -5885,7 +5891,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
*/
}
@@ -5901,7 +5907,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
*/
}
@@ -5917,7 +5923,7 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hfdcan);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorCallback could be implemented in the user file
*/
}
@@ -5936,7 +5942,7 @@
UNUSED(hfdcan);
UNUSED(ErrorStatusITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
*/
}
@@ -5955,7 +5961,7 @@
UNUSED(hfdcan);
UNUSED(TTSchedSyncITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
*/
}
@@ -5974,7 +5980,7 @@
UNUSED(hfdcan);
UNUSED(TTTimeMarkITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
*/
}
@@ -5997,7 +6003,7 @@
UNUSED(SWTime);
UNUSED(SWCycleCount);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
*/
}
@@ -6016,7 +6022,7 @@
UNUSED(hfdcan);
UNUSED(TTGlobTimeITs);
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE: This function Should not be modified, when the callback is needed,
the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
*/
}
@@ -6072,7 +6078,7 @@
* @}
*/
-/** @addtogroup FDCAN_Private_Functions
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
* @{
*/
@@ -6183,9 +6189,9 @@
* @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
* @param pTxData pointer to a buffer containing the payload of the Tx frame.
* @param BufferIndex index of the buffer to be configured.
- * @retval HAL status
+ * @retval none
*/
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
const uint8_t *pTxData, uint32_t BufferIndex)
{
uint32_t TxElementW1;
@@ -6199,7 +6205,7 @@
TxElementW1 = (pTxHeader->ErrorStateIndicator |
FDCAN_STANDARD_ID |
pTxHeader->TxFrameType |
- (pTxHeader->Identifier << 18));
+ (pTxHeader->Identifier << 18U));
}
else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
{
@@ -6210,11 +6216,11 @@
}
/* Build second word of Tx header element */
- TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+ TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
pTxHeader->TxEventFifoControl |
pTxHeader->FDFormat |
pTxHeader->BitRateSwitch |
- pTxHeader->DataLength);
+ (pTxHeader->DataLength << 16U));
/* Calculate Tx element address */
TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
@@ -6226,11 +6232,11 @@
TxAddress++;
/* Write Tx payload to the message RAM */
- for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+ for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
{
- *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
- ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
- ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+ *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+ ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
+ ((uint32_t)pTxData[ByteCounter + 1U] << 8U) |
(uint32_t)pTxData[ByteCounter]);
TxAddress++;
}
@@ -6249,4 +6255,3 @@
*/
#endif /* FDCAN1 */
-
diff --git a/Src/stm32h7xx_hal_flash.c b/Src/stm32h7xx_hal_flash.c
index a3fe346..3706941 100644
--- a/Src/stm32h7xx_hal_flash.c
+++ b/Src/stm32h7xx_hal_flash.c
@@ -123,8 +123,8 @@
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- * @brief Programming operation functions
- *
+ * @brief Programming operation functions
+ *
@verbatim
===============================================================================
##### Programming operation functions #####
@@ -173,6 +173,8 @@
#endif /* FLASH_OPTCR_PG_OTP */
{
bank = FLASH_BANK_1;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(TypeProgram);
}
#if defined (DUAL_BANK)
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
@@ -339,6 +341,8 @@
#endif /* FLASH_OPTCR_PG_OTP */
{
bank = FLASH_BANK_1;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(TypeProgram);
}
#if defined (DUAL_BANK)
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
@@ -655,6 +659,38 @@
HAL_FLASH_OperationErrorCallback(temp);
}
+#if (USE_FLASH_ECC == 1U)
+ /* Check FLASH Bank1 ECC single correction error flag */
+ errorflag = FLASH->SR1 & FLASH_FLAG_SNECCERR_BANK1;
+
+ if(errorflag != 0U)
+ {
+ /* Save the error code */
+ pFlash.ErrorCode |= errorflag;
+
+ /* Call User callback */
+ HAL_FLASHEx_EccCorrectionCallback();
+
+ /* Clear FLASH Bank1 ECC single correction error flag in order to allow new ECC error record */
+ __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+ }
+
+ /* Check FLASH Bank1 ECC double detection error flag */
+ errorflag = FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1;
+
+ if(errorflag != 0U)
+ {
+ /* Save the error code */
+ pFlash.ErrorCode |= errorflag;
+
+ /* Call User callback */
+ HAL_FLASHEx_EccDetectionCallback();
+
+ /* Clear FLASH Bank1 ECC double detection error flag in order to allow new ECC error record */
+ __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+ }
+#endif /* USE_FLASH_ECC */
+
#if defined (DUAL_BANK)
/* Check FLASH Bank2 operation error flags */
#if defined (FLASH_SR_OPERR)
@@ -698,6 +734,39 @@
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(temp);
}
+
+#if (USE_FLASH_ECC == 1U)
+ /* Check FLASH Bank2 ECC single correction error flag */
+ errorflag = FLASH->SR2 & FLASH_FLAG_SNECCERR_BANK2;
+
+ if(errorflag != 0U)
+ {
+ /* Save the error code */
+ pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+ /* Call User callback */
+ HAL_FLASHEx_EccCorrectionCallback();
+
+ /* Clear FLASH Bank2 ECC single correction error flag in order to allow new ECC error record */
+ __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+ }
+
+ /* Check FLASH Bank2 ECC double detection error flag */
+ errorflag = FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2;
+
+ if(errorflag != 0U)
+ {
+ /* Save the error code */
+ pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+ /* Call User callback */
+ HAL_FLASHEx_EccDetectionCallback();
+
+ /* Clear FLASH Bank2 ECC double detection error flag in order to allow new ECC error record */
+ __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+ }
+
+#endif /* USE_FLASH_ECC */
#endif /* DUAL_BANK */
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
@@ -771,8 +840,8 @@
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- * @brief Management functions
- *
+ * @brief Management functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -932,8 +1001,8 @@
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral Errors functions
- *
+ * @brief Peripheral Errors functions
+ *
@verbatim
===============================================================================
##### Peripheral Errors functions #####
@@ -971,7 +1040,7 @@
* @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
* @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
* @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
-*/
+ */
uint32_t HAL_FLASH_GetError(void)
{
diff --git a/Src/stm32h7xx_hal_flash_ex.c b/Src/stm32h7xx_hal_flash_ex.c
index fd4acec..c302c70 100644
--- a/Src/stm32h7xx_hal_flash_ex.c
+++ b/Src/stm32h7xx_hal_flash_ex.c
@@ -58,6 +58,16 @@
(++) Perform the CRC computation
(++) Disable CRC feature
+ (#) Error correction code error functions:
+ (++) Use the HAL_FLASHEx_EnableEccCorrectionInterrupt() and HAL_FLASHEx_DisableEccCorrectionInterrupt()
+ functions to enable and disable the FLASH ECC correction interruption.
+ (++) Use the HAL_FLASHEx_EnableEccDetectionInterrupt() and HAL_FLASHEx_DisableEccDetectionInterrupt()
+ functions to enable and disable the FLASH ECC Detection interruption.
+ (++) Handle ECCD interrupt by calling HAL_FLASHEx_BusFault_IRQHandler()
+ (++) Use HAL_FLASHEx_BusFault_IRQHandler() function called under BusFault_IRQHandler() interrupt subroutine
+ to handle the ECCD interrupt.
+ (++) Use HAL_FLASHEx_GetEccInfo() function to get the flash ECC fail information.
+
@endverbatim
******************************************************************************
* @attention
@@ -818,6 +828,251 @@
* @}
*/
+#if (USE_FLASH_ECC == 1U)
+/** @defgroup FLASHEx_Exported_Functions_Group2 Extended ECC operation functions
+ * @brief Extended ECC operation functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended ECC operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the Extended FLASH
+ ECC Operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable ECC correction interrupts on FLASH BANK1 and BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_EnableEccCorrectionInterrupt(void)
+{
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+ * @brief Disable ECC correction interrupts on FLASH BANK1 and BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_DisableEccCorrectionInterrupt(void)
+{
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+ * @brief Enable ECC correction interrupt on FLASH BANK1.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void)
+{
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
+}
+
+/**
+ * @brief Disable ECC correction interrupt on FLASH BANK1.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void)
+{
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
+}
+
+#if defined (DUAL_BANK)
+/**
+ * @brief Enable ECC correction interrupt on FLASH BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void)
+{
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
+}
+
+/**
+ * @brief Disable ECC correction interrupt on FLASH BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void)
+{
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
+}
+#endif /* DUAL_BANK */
+
+/**
+ * @brief Enable ECC Detection interrupts on FLASH BANK1 and BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_EnableEccDetectionInterrupt(void)
+{
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+ * @brief Disable ECC Detection interrupts on FLASH BANK1 and BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_DisableEccDetectionInterrupt(void)
+{
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+ * @brief Enable ECC Detection interrupt on FLASH BANK1.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void)
+{
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
+}
+
+/**
+ * @brief Disable ECC correction interrupt on FLASH BANK1.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void)
+{
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
+}
+
+#if defined (DUAL_BANK)
+/**
+ * @brief Enable ECC Detection interrupt on FLASH BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void)
+{
+ __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
+}
+
+/**
+ * @brief Disable ECC Detection interrupt on FLASH BANK2.
+ * @param None
+ * @retval None
+ */
+void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void)
+{
+ __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
+}
+#endif /* DUAL_BANK */
+
+/**
+ * @brief Get the ECC error information.
+ * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the
+ * ECC error information.
+ * @note This function should be called before ECC bit is cleared
+ * (in callback function)
+ * @retval None
+ */
+void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
+{
+ uint32_t errorflag;
+
+ /* Check FLASH Bank1 ECC single correction and double detection error flags */
+ errorflag = FLASH->SR1 & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1);
+ if(errorflag != 0U)
+ {
+ pData->Area = FLASH_ECC_AREA_USER_BANK1;
+ pData->Address = ((((FLASH->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK1_BASE);
+ }
+#if defined (DUAL_BANK)
+ /* Check FLASH Bank2 ECC single correction and double detection error flags */
+ errorflag = FLASH->SR2 & (FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2);
+ if(errorflag != 0U)
+ {
+ pData->Area = FLASH_ECC_AREA_USER_BANK2;
+ pData->Address = ((((FLASH->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK2_BASE);
+ }
+#endif /* DUAL_BANK */
+}
+
+/**
+ * @brief Handle Flash ECC Detection interrupt request.
+ * @retval None
+ */
+void HAL_FLASHEx_BusFault_IRQHandler(void)
+{
+ /* Check if the ECC double error occured*/
+ if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0)
+ {
+ /* FLASH ECC detection user callback */
+ HAL_FLASHEx_EccDetectionCallback();
+
+ /* Clear Bank 1 ECC double detection error flag
+ note : this step will clear all the informations related to the flash ECC detection
+ */
+ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1);
+ }
+#if defined (DUAL_BANK)
+ /* Check if the ECC double error occured*/
+ if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0)
+ {
+ /* FLASH ECC detection user callback */
+ HAL_FLASHEx_EccDetectionCallback();
+
+ /* Clear Bank 2 ECC double detection error flag
+ note : this step will clear all the informations related to the flash ECC detection
+ */
+ __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2);
+ }
+#endif /* DUAL_BANK */
+}
+
+/**
+ * @brief FLASH ECC Correction interrupt callback.
+ * @retval None
+ */
+__weak void HAL_FLASHEx_EccCorrectionCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief FLASH ECC Detection interrupt callback.
+ * @retval None
+ */
+__weak void HAL_FLASHEx_EccDetectionCallback(void)
+{
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+#endif /* USE_FLASH_ECC */
+
/**
* @}
*/
diff --git a/Src/stm32h7xx_hal_fmac.c b/Src/stm32h7xx_hal_fmac.c
index 72e77ea..f4cebd0 100644
--- a/Src/stm32h7xx_hal_fmac.c
+++ b/Src/stm32h7xx_hal_fmac.c
@@ -166,7 +166,7 @@
[..]
Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
and the Callback ID.
This function allows to reset following callbacks:
@@ -182,10 +182,10 @@
[..]
By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples GetDataCallback(), OutputDataReadyCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_FMAC_Init()
+ reset to the legacy weak functions in the HAL_FMAC_Init()
and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -202,7 +202,7 @@
[..]
When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -1527,7 +1527,7 @@
* the configuration information for FMAC module.
* @retval HAL_FMAC_StateTypeDef FMAC state
*/
-HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac)
{
/* Return FMAC state */
return hfmac->State;
@@ -1540,7 +1540,7 @@
* @note The returned error is a bit-map combination of possible errors.
* @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
*/
-uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
+uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac)
{
/* Return FMAC error code */
return hfmac->ErrorCode;
diff --git a/Src/stm32h7xx_hal_hash.c b/Src/stm32h7xx_hal_hash.c
index e504c08..c7780ee 100644
--- a/Src/stm32h7xx_hal_hash.c
+++ b/Src/stm32h7xx_hal_hash.c
@@ -1827,7 +1827,7 @@
__IO uint32_t inputaddr = (uint32_t) pInBuffer;
uint32_t tmp;
- for (buffercounter = 0U; buffercounter < Size / 4U; buffercounter++)
+ for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++)
{
/* Write input data 4 bytes at a time */
HASH->DIN = *(uint32_t *)inputaddr;
@@ -1835,10 +1835,10 @@
/* If the suspension flag has been raised and if the processing is not about
to end, suspend processing */
- if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter * 4 + 4U) < Size))
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size))
{
/* wait for flag BUSY not set before Wait for DINIS = 1*/
- if (buffercounter * 4 >= 64U)
+ if ((buffercounter * 4U) >= 64U)
{
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
@@ -1859,14 +1859,14 @@
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashInCount = Size - (buffercounter * 4 + 4U);
+ hhash->HashInCount = Size - ((buffercounter * 4U) + 4U);
}
else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
{
/* Save current reading and writing locations of Input and Output buffers */
hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
/* Save the number of bytes that remain to be processed at this point */
- hhash->HashKeyCount = Size - (buffercounter * 4 + 4U);
+ hhash->HashKeyCount = Size - ((buffercounter * 4U) + 4U);
}
else
{
@@ -1886,17 +1886,17 @@
/* At this point, all the data have been entered to the Peripheral: exit */
- if (Size % 4U != 0U)
+ if ((Size % 4U) != 0U)
{
if (hhash->Init.DataType == HASH_DATATYPE_16B)
{
/* Write remaining input data */
- if (Size % 4U <= 2)
+ if ((Size % 4U) <= 2U)
{
HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
}
- if (Size % 4U == 3)
+ if ((Size % 4U) == 3U)
{
HASH->DIN = *(uint32_t *)inputaddr;
}
@@ -1906,19 +1906,19 @@
|| (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */
{
/* Write remaining input data */
- if (Size % 4U == 1)
+ if ((Size % 4U) == 1U)
{
HASH->DIN = (uint32_t) * (uint8_t *)inputaddr;
}
- if (Size % 4U == 2)
+ if ((Size % 4U) == 2U)
{
HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
}
- if (Size % 4U == 3)
+ if ((Size % 4U) == 3U)
{
tmp = *(uint8_t *)inputaddr;
- tmp |= *(uint8_t *)(inputaddr + 1U) << 8U ;
- tmp |= *(uint8_t *)(inputaddr + 2U) << 16U;
+ tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U;
+ tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U;
HASH->DIN = tmp;
}
diff --git a/Src/stm32h7xx_hal_hcd.c b/Src/stm32h7xx_hal_hcd.c
index 4d39cf6..17f99ed 100644
--- a/Src/stm32h7xx_hal_hcd.c
+++ b/Src/stm32h7xx_hal_hcd.c
@@ -109,7 +109,6 @@
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
-
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
@@ -151,13 +150,25 @@
__HAL_HCD_DISABLE(hhcd);
/* Init the Core (common init.) */
- (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+ if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
- /* Force Host Mode*/
- (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+ /* Force Host Mode */
+ if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init Host */
- (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+ if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+ {
+ hhcd->State = HAL_HCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
hhcd->State = HAL_HCD_STATE_READY;
@@ -192,15 +203,18 @@
uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
{
HAL_StatusTypeDef status;
+ uint32_t HostCoreSpeed;
+ uint32_t HCcharMps = mps;
__HAL_LOCK(hhcd);
hhcd->hc[ch_num].do_ping = 0U;
hhcd->hc[ch_num].dev_addr = dev_address;
- hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
+ (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num);
+
if ((epnum & 0x80U) == 0x80U)
{
hhcd->hc[ch_num].ep_is_in = 1U;
@@ -210,10 +224,26 @@
hhcd->hc[ch_num].ep_is_in = 0U;
}
+ HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
+
+ if (ep_type == EP_TYPE_ISOC)
+ {
+ /* FS device plugged to HS HUB */
+ if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
+ {
+ if (HCcharMps > ISO_SPLT_MPS)
+ {
+ /* ISO Max Packet Size for Split mode */
+ HCcharMps = ISO_SPLT_MPS;
+ }
+ }
+ }
+
hhcd->hc[ch_num].speed = speed;
+ hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps;
status = USB_HC_Init(hhcd->Instance, ch_num, epnum,
- dev_address, speed, ep_type, mps);
+ dev_address, speed, ep_type, (uint16_t)HCcharMps);
__HAL_UNLOCK(hhcd);
@@ -371,24 +401,41 @@
switch (ep_type)
{
case EP_TYPE_CTRL:
- if ((token == 1U) && (direction == 0U)) /*send data */
+ if (token == 1U) /* send data */
{
- if (length == 0U)
+ if (direction == 0U)
{
- /* For Status OUT stage, Length==0, Status Out PID = 1 */
- hhcd->hc[ch_num].toggle_out = 1U;
- }
+ if (length == 0U)
+ {
+ /* For Status OUT stage, Length == 0U, Status Out PID = 1 */
+ hhcd->hc[ch_num].toggle_out = 1U;
+ }
- /* Set the Data Toggle bit as per the Flag */
- if (hhcd->hc[ch_num].toggle_out == 0U)
- {
- /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ /* Set the Data Toggle bit as per the Flag */
+ if (hhcd->hc[ch_num].toggle_out == 0U)
+ {
+ /* Put the PID 0 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ /* Put the PID 1 */
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
}
else
{
- /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ if (hhcd->hc[ch_num].do_ssplit == 1U)
+ {
+ if (hhcd->hc[ch_num].toggle_in == 0U)
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ }
+ else
+ {
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+ }
+ }
}
}
break;
@@ -556,16 +603,6 @@
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
- /* Handle Rx Queue Level Interrupts */
- if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
- {
- USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
- HCD_RXQLVL_IRQHandler(hhcd);
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
- }
-
/* Handle Host channel Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
@@ -586,6 +623,16 @@
}
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
}
+
+ /* Handle Rx Queue Level Interrupts */
+ if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
+ {
+ USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+ HCD_RXQLVL_IRQHandler(hhcd);
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+ }
}
}
@@ -1058,7 +1105,7 @@
* @param hhcd HCD handle
* @retval HAL state
*/
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd)
{
return hhcd->State;
}
@@ -1077,7 +1124,7 @@
* URB_ERROR/
* URB_STALL
*/
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].urb_state;
}
@@ -1090,7 +1137,7 @@
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].xfer_count;
}
@@ -1112,7 +1159,7 @@
* HC_BBLERR/
* HC_DATATGLERR
*/
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
{
return hhcd->hc[chnum].state;
}
@@ -1138,6 +1185,54 @@
}
/**
+ * @brief Set host channel Hub information.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @param addr Hub address
+ * @param PortNbr Hub port number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+ uint8_t addr, uint8_t PortNbr)
+{
+ uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
+
+ /* LS/FS device plugged to HS HUB */
+ if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
+ {
+ hhcd->hc[ch_num].do_ssplit = 1U;
+
+ if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U))
+ {
+ hhcd->hc[ch_num].toggle_in = 1U;
+ }
+ }
+
+ hhcd->hc[ch_num].hub_addr = addr;
+ hhcd->hc[ch_num].hub_port_nbr = PortNbr;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Clear host channel hub information.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
+ * This parameter can be a value from 1 to 15
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+ hhcd->hc[ch_num].do_ssplit = 0U;
+ hhcd->hc[ch_num].do_csplit = 0U;
+ hhcd->hc[ch_num].hub_addr = 0U;
+ hhcd->hc[ch_num].hub_port_nbr = 0U;
+
+ return HAL_OK;
+}
+/**
* @}
*/
@@ -1157,7 +1252,7 @@
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1206,6 +1301,12 @@
/* Clear any pending ACK IT */
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+ if (hhcd->hc[chnum].do_csplit == 1U)
+ {
+ hhcd->hc[chnum].do_csplit = 0U;
+ __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+ }
+
if (hhcd->Init.dma_enable != 0U)
{
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
@@ -1253,10 +1354,19 @@
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+
+ if (hhcd->hc[chnum].do_ssplit == 1U)
+ {
+ hhcd->hc[chnum].do_csplit = 1U;
+ hhcd->hc[chnum].state = HC_ACK;
+
+ (void)USB_HC_Halt(hhcd->Instance, chnum);
+ }
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+
if (hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[chnum].state = HC_HALTED;
@@ -1275,26 +1385,96 @@
if (hhcd->hc[chnum].ErrCnt > 2U)
{
hhcd->hc[chnum].ErrCnt = 0U;
+
+ if (hhcd->hc[chnum].do_ssplit == 1U)
+ {
+ hhcd->hc[chnum].do_csplit = 0U;
+ hhcd->hc[chnum].ep_ss_schedule = 0U;
+ __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+ }
+
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
- /* re-activate the channel */
- tmpreg = USBx_HC(chnum)->HCCHAR;
- tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
- tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ /* re-activate the channel */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
+ }
}
}
else if (hhcd->hc[chnum].state == HC_NYET)
{
hhcd->hc[chnum].state = HC_HALTED;
+
+ if (hhcd->hc[chnum].do_csplit == 1U)
+ {
+ if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ {
+ hhcd->hc[chnum].NyetErrCnt++;
+ if (hhcd->hc[chnum].NyetErrCnt > 2U)
+ {
+ hhcd->hc[chnum].NyetErrCnt = 0U;
+ hhcd->hc[chnum].do_csplit = 0U;
+
+ if (hhcd->hc[chnum].ErrCnt < 3U)
+ {
+ hhcd->hc[chnum].ep_ss_schedule = 1U;
+ }
+ __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+ hhcd->hc[chnum].urb_state = URB_ERROR;
+ }
+ else
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+ }
+ else
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ /* re-activate the channel */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
+ }
+ }
}
else if (hhcd->hc[chnum].state == HC_ACK)
{
hhcd->hc[chnum].state = HC_HALTED;
+
+ if (hhcd->hc[chnum].do_csplit == 1U)
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+ /* Set Complete split and re-activate the channel */
+ USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+ USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
+ USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK;
+
+ if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ /* re-activate the channel */
+ tmpreg = USBx_HC(chnum)->HCCHAR;
+ tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ tmpreg |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
+ }
+ }
}
else if (hhcd->hc[chnum].state == HC_NAK)
{
@@ -1335,7 +1515,11 @@
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
hhcd->hc[chnum].state = HC_NYET;
- hhcd->hc[chnum].ErrCnt = 0U;
+
+ if (hhcd->hc[chnum].do_ssplit == 0U)
+ {
+ hhcd->hc[chnum].ErrCnt = 0U;
+ }
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
@@ -1352,7 +1536,7 @@
{
hhcd->hc[chnum].ErrCnt = 0U;
- if (hhcd->Init.dma_enable == 0U)
+ if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U))
{
hhcd->hc[chnum].state = HC_NAK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
@@ -1362,6 +1546,14 @@
{
/* ... */
}
+
+ if (hhcd->hc[chnum].do_csplit == 1U)
+ {
+ hhcd->hc[chnum].do_csplit = 0U;
+ __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+ __HAL_HCD_UNMASK_ACK_HC_INT(chnum);
+ }
+
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else
@@ -1379,7 +1571,7 @@
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
uint32_t num_packets;
@@ -1401,6 +1593,20 @@
hhcd->hc[chnum].state = HC_ACK;
(void)USB_HC_Halt(hhcd->Instance, chnum);
}
+
+ if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U))
+ {
+ if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
+ {
+ hhcd->hc[chnum].do_csplit = 1U;
+ }
+
+ hhcd->hc[chnum].state = HC_ACK;
+ (void)USB_HC_Halt(hhcd->Instance, chnum);
+
+ /* reset error_count */
+ hhcd->hc[chnum].ErrCnt = 0U;
+ }
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
{
@@ -1417,6 +1623,13 @@
hhcd->hc[chnum].do_ping = 1U;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
}
+
+ if (hhcd->hc[chnum].do_csplit != 0U)
+ {
+ hhcd->hc[chnum].do_csplit = 0U;
+ __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+ }
+
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
hhcd->hc[chnum].state = HC_XFRC;
(void)USB_HC_Halt(hhcd->Instance, chnum);
@@ -1424,7 +1637,12 @@
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
{
hhcd->hc[chnum].state = HC_NYET;
- hhcd->hc[chnum].do_ping = 1U;
+
+ if (hhcd->hc[chnum].do_ssplit == 0U)
+ {
+ hhcd->hc[chnum].do_ping = 1U;
+ }
+
hhcd->hc[chnum].ErrCnt = 0U;
(void)USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
@@ -1488,10 +1706,12 @@
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+
if (hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[chnum].state = HC_HALTED;
- hhcd->hc[chnum].urb_state = URB_DONE;
+ hhcd->hc[chnum].urb_state = URB_DONE;
+
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
{
@@ -1514,11 +1734,22 @@
else if (hhcd->hc[chnum].state == HC_ACK)
{
hhcd->hc[chnum].state = HC_HALTED;
+
+ if (hhcd->hc[chnum].do_csplit == 1U)
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
}
else if (hhcd->hc[chnum].state == HC_NAK)
{
hhcd->hc[chnum].state = HC_HALTED;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+ if (hhcd->hc[chnum].do_csplit == 1U)
+ {
+ hhcd->hc[chnum].do_csplit = 0U;
+ __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+ }
}
else if (hhcd->hc[chnum].state == HC_NYET)
{
@@ -1564,7 +1795,7 @@
}
else
{
- /* ... */
+ return;
}
}
@@ -1575,7 +1806,7 @@
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t pktsts;
uint32_t pktcnt;
@@ -1641,7 +1872,7 @@
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
diff --git a/Src/stm32h7xx_hal_i2c.c b/Src/stm32h7xx_hal_i2c.c
index b461b3d..39b2d68 100644
--- a/Src/stm32h7xx_hal_i2c.c
+++ b/Src/stm32h7xx_hal_i2c.c
@@ -400,9 +400,15 @@
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Macro
+ * @{
+ */
/* Macro to get remaining data to transfer on DMA side */
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -418,6 +424,7 @@
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
+
/* Private functions to handle IT transfer */
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
@@ -601,7 +608,12 @@
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+ }
+ else
+ {
+ /* Clear the I2C ADD10 bit */
+ CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
@@ -1367,6 +1379,8 @@
uint32_t Timeout)
{
uint32_t tickstart;
+ uint16_t tmpXferCount;
+ HAL_StatusTypeDef error;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1460,31 +1474,48 @@
}
/* Wait until AF flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+ if (error != HAL_OK)
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+
+ tmpXferCount = hi2c->XferCount;
+ if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ {
+ /* Reset ErrorCode to NONE */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
}
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ else
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
- return HAL_ERROR;
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
@@ -1991,8 +2022,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+ (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@@ -2013,7 +2044,8 @@
{
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
+ xfermode, I2C_GENERATE_START_WRITE);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -2462,6 +2494,7 @@
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2911,6 +2944,7 @@
return HAL_BUSY;
}
}
+
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -3307,22 +3341,6 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
@@ -3393,7 +3411,8 @@
xfermode = hi2c->XferOptions;
}
- if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+ (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
@@ -3507,7 +3526,8 @@
xfermode = hi2c->XferOptions;
}
- if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+ if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+ (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
{
/* Preload TX register */
/* Write data to TXDR */
@@ -3556,8 +3576,8 @@
hi2c->hdmatx->XferAbortCallback = NULL;
/* Enable the DMA stream or channel depends on Instance */
- dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
- hi2c->XferSize);
+ dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+ (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
}
else
{
@@ -4601,7 +4621,7 @@
* the configuration information for the specified I2C.
* @retval None
*/
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Get current IT Flags and IT sources value */
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
@@ -6248,8 +6268,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
- if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (tmpstate == HAL_I2C_STATE_LISTEN))
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
@@ -6259,6 +6278,11 @@
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
+ else if (tmpstate == HAL_I2C_STATE_LISTEN)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
else
{
/* Do nothing */
@@ -6503,6 +6527,7 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
{
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
uint32_t tmppreviousstate;
/* Reset handle parameters */
@@ -6559,6 +6584,7 @@
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
+
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
@@ -6733,6 +6759,7 @@
}
}
+
/**
* @brief DMA I2C slave transmit process complete callback.
* @param hdma DMA handle
@@ -6761,6 +6788,7 @@
}
}
+
/**
* @brief DMA I2C master receive process complete callback.
* @param hdma DMA handle
@@ -6811,6 +6839,7 @@
}
}
+
/**
* @brief DMA I2C slave receive process complete callback.
* @param hdma DMA handle
@@ -6839,6 +6868,7 @@
}
}
+
/**
* @brief DMA I2C communication error callback.
* @param hdma DMA handle
@@ -6877,6 +6907,7 @@
}
}
+
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
@@ -6901,6 +6932,7 @@
I2C_TreatErrorCallback(hi2c);
}
+
/**
* @brief This function handles I2C Communication Timeout. It waits
* until a flag is no longer in the specified status.
@@ -6917,6 +6949,12 @@
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
@@ -7274,8 +7312,9 @@
{
uint32_t tmpisr = 0U;
- if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+ (hi2c->XferISR != I2C_Mem_ISR_DMA))
{
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
@@ -7283,32 +7322,6 @@
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if (InterruptRequest == I2C_XFER_ERROR_IT)
- {
- /* Enable ERR and NACK interrupts */
- tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
- }
-
- if (InterruptRequest == I2C_XFER_CPLT_IT)
- {
- /* Enable STOP interrupts */
- tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
- }
-
- if (InterruptRequest == I2C_XFER_RELOAD_IT)
- {
- /* Enable TC interrupts */
- tmpisr |= I2C_IT_TCI;
- }
- }
- else
- {
- if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
- {
- /* Enable ERR, STOP, NACK, and ADDR interrupts */
- tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
- }
-
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
@@ -7334,6 +7347,45 @@
}
}
+ else
+ {
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ {
+ /* Enable ERR, STOP, NACK and ADDR interrupts */
+ tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+ }
+
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ {
+ /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+ }
+
+ if (InterruptRequest == I2C_XFER_ERROR_IT)
+ {
+ /* Enable ERR and NACK interrupts */
+ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+ }
+
+ if (InterruptRequest == I2C_XFER_CPLT_IT)
+ {
+ /* Enable STOP interrupts */
+ tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
+ }
+
+ if (InterruptRequest == I2C_XFER_RELOAD_IT)
+ {
+ /* Enable TC interrupts */
+ tmpisr |= I2C_IT_TCI;
+ }
+ }
+
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
diff --git a/Src/stm32h7xx_hal_i2s.c b/Src/stm32h7xx_hal_i2s.c
index ea7fe37..d449267 100644
--- a/Src/stm32h7xx_hal_i2s.c
+++ b/Src/stm32h7xx_hal_i2s.c
@@ -170,7 +170,7 @@
When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -543,6 +543,8 @@
* the configuration information for the specified I2S.
* @param CallbackID ID of the callback to be registered
* @param pCallback pointer to the Callback function
+ * @note The HAL_I2S_RegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+ * to register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
@@ -557,8 +559,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hi2s);
if (HAL_I2S_STATE_READY == hi2s->State)
{
@@ -640,8 +640,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
return status;
}
@@ -651,15 +649,14 @@
* @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for the specified I2S.
* @param CallbackID ID of the callback to be unregistered
+ * @note The HAL_I2S_UnRegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+ * to un-register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hi2s);
-
if (HAL_I2S_STATE_READY == hi2s->State)
{
switch (CallbackID)
@@ -739,8 +736,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hi2s);
return status;
}
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
diff --git a/Src/stm32h7xx_hal_irda.c b/Src/stm32h7xx_hal_irda.c
index e4c80fc..124d7fe 100644
--- a/Src/stm32h7xx_hal_irda.c
+++ b/Src/stm32h7xx_hal_irda.c
@@ -142,7 +142,7 @@
[..]
Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -159,10 +159,10 @@
[..]
By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init()
+ reset to the legacy weak functions in the HAL_IRDA_Init()
and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -179,7 +179,7 @@
[..]
When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
******************************************************************************
@@ -462,7 +462,7 @@
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User IRDA Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
* to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
@@ -2437,7 +2437,6 @@
hirda->gState = HAL_IRDA_STATE_READY;
}
-
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
diff --git a/Src/stm32h7xx_hal_lptim.c b/Src/stm32h7xx_hal_lptim.c
index 5a5016f..eb49bb0 100644
--- a/Src/stm32h7xx_hal_lptim.c
+++ b/Src/stm32h7xx_hal_lptim.c
@@ -188,7 +188,7 @@
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
/* Exported functions --------------------------------------------------------*/
@@ -343,10 +343,10 @@
{
if (hlptim->Instance == LPTIM3)
{
- /* Check LPTIM3 Input1 source */
+ /* Check LPTIM Input1 source */
assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
- /* Configure LPTIM3 Input1 source */
+ /* Configure LPTIM Input1 source */
hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
}
}
@@ -2272,7 +2272,7 @@
* @param hlptim LPTIM handle
* @retval HAL state
*/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
{
/* Return LPTIM handle state */
return hlptim->State;
@@ -2319,7 +2319,7 @@
* @param flag The lptim flag
* @retval HAL status
*/
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
diff --git a/Src/stm32h7xx_hal_ltdc.c b/Src/stm32h7xx_hal_ltdc.c
index 8277402..80fe3ad 100644
--- a/Src/stm32h7xx_hal_ltdc.c
+++ b/Src/stm32h7xx_hal_ltdc.c
@@ -555,7 +555,7 @@
break;
case HAL_LTDC_MSPINIT_CB_ID :
- hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
+ hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */
break;
case HAL_LTDC_MSPDEINIT_CB_ID :
@@ -2192,7 +2192,8 @@
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
- LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 7U));
+ LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) |
+ (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 7U));
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
diff --git a/Src/stm32h7xx_hal_ltdc_ex.c b/Src/stm32h7xx_hal_ltdc_ex.c
index fec1737..2ffdb1d 100644
--- a/Src/stm32h7xx_hal_ltdc_ex.c
+++ b/Src/stm32h7xx_hal_ltdc_ex.c
@@ -74,16 +74,18 @@
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
+#if !defined(POLARITIES_INVERSION_UPDATED)
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
-
+#else
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
- /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
- hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
- hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
+ hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
+ hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
+ hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29;
+#endif /* POLARITIES_INVERSION_UPDATED */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
@@ -115,17 +117,18 @@
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
+#if !defined(POLARITIES_INVERSION_UPDATED)
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
-
+#else
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
- /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
- hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
- hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
-
+ hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
+ hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
+ hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29;
+#endif /* POLARITIES_INVERSION_UPDATED */
return HAL_OK;
}
diff --git a/Src/stm32h7xx_hal_nand.c b/Src/stm32h7xx_hal_nand.c
index 74f6c6c..87c492d 100644
--- a/Src/stm32h7xx_hal_nand.c
+++ b/Src/stm32h7xx_hal_nand.c
@@ -77,15 +77,15 @@
and a pointer to the user callback function.
Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NAND MspInit.
(+) MspDeInitCallback : NAND MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_NAND_Init
+ reset to the legacy weak (overridden) functions in the HAL_NAND_Init
and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -100,7 +100,7 @@
When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -516,8 +516,8 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -674,8 +674,8 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -842,8 +842,8 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -851,7 +851,7 @@
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
- uint8_t *buff = pBuffer;
+ const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -995,8 +995,8 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
- uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1004,7 +1004,7 @@
uint32_t numpageswritten = 0U;
uint32_t nandaddress;
uint32_t nbpages = NumPageToWrite;
- uint16_t *buff = pBuffer;
+ const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1159,8 +1159,8 @@
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
- uint32_t NumSpareAreaToRead)
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
@@ -1324,7 +1324,7 @@
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
@@ -1489,8 +1489,8 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1499,7 +1499,7 @@
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
- uint8_t *buff = pBuffer;
+ const uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1652,8 +1652,8 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
- uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+ const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
@@ -1662,7 +1662,7 @@
uint32_t nandaddress;
uint32_t columnaddress;
uint32_t nbspare = NumSpareAreaTowrite;
- uint16_t *buff = pBuffer;
+ const uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1813,7 +1813,7 @@
* @param pAddress pointer to NAND address structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
{
uint32_t deviceaddress;
@@ -1869,7 +1869,7 @@
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
*/
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
uint32_t status = NAND_VALID_ADDRESS;
@@ -1900,7 +1900,7 @@
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NAND Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1920,9 +1920,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hnand);
-
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -1964,14 +1961,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnand);
return status;
}
/**
* @brief Unregister a User NAND Callback
- * NAND Callback is redirected to the weak (surcharged) predefined callback
+ * NAND Callback is redirected to the weak predefined callback
* @param hnand : NAND handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1984,9 +1979,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hnand);
-
if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
@@ -2028,8 +2020,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnand);
return status;
}
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
@@ -2180,7 +2170,7 @@
* the configuration information for NAND module.
* @retval HAL state
*/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
{
return hnand->State;
}
@@ -2191,7 +2181,7 @@
* the configuration information for NAND module.
* @retval NAND status
*/
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
{
uint32_t data;
uint32_t deviceaddress;
diff --git a/Src/stm32h7xx_hal_nor.c b/Src/stm32h7xx_hal_nor.c
index 487caa9..71a7669 100644
--- a/Src/stm32h7xx_hal_nor.c
+++ b/Src/stm32h7xx_hal_nor.c
@@ -74,15 +74,15 @@
and a pointer to the user callback function.
Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : NOR MspInit.
(+) MspDeInitCallback : NOR MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_NOR_Init
+ reset to the legacy weak (overridden) functions in the HAL_NOR_Init
and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -97,7 +97,7 @@
When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -327,8 +327,8 @@
{
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
}
- hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
- NOR_ADDRESS_COMMAND_SET);
+
+ hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
status = HAL_NOR_ReturnToReadMode(hnor);
}
@@ -1311,7 +1311,7 @@
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User NOR Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1331,9 +1331,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hnor);
-
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1357,14 +1354,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnor);
return status;
}
/**
* @brief Unregister a User NOR Callback
- * NOR Callback is redirected to the weak (surcharged) predefined callback
+ * NOR Callback is redirected to the weak predefined callback
* @param hnor : NOR handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1377,9 +1372,6 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
- /* Process locked */
- __HAL_LOCK(hnor);
-
state = hnor->State;
if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
@@ -1403,8 +1395,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hnor);
return status;
}
#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
@@ -1521,7 +1511,7 @@
* the configuration information for NOR module.
* @retval NOR controller state
*/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
{
return hnor->State;
}
diff --git a/Src/stm32h7xx_hal_opamp.c b/Src/stm32h7xx_hal_opamp.c
index 6a06f36..688ff3e 100644
--- a/Src/stm32h7xx_hal_opamp.c
+++ b/Src/stm32h7xx_hal_opamp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32h7xx_hal_opamp.c
* @author MCD Application Team
- * @brief OPAMP HAL module driver.
- * This file provides firmware functions to manage the following
+ * @brief OPAMP HAL module driver.
+ * This file provides firmware functions to manage the following
* functionalities of the operational amplifier(s) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
@@ -25,9 +25,9 @@
================================================================================
##### OPAMP Peripheral Features #####
================================================================================
-
+
[..] The device integrates 2 operational amplifiers OPAMP1 & OPAMP2
-
+
(#) The OPAMP(s) provides several exclusive running modes.
(++) Standalone mode
(++) Programmable Gain Amplifier (PGA) modes
@@ -35,36 +35,36 @@
(#) Each OPAMP(s) can be configured in normal and high speed mode.
- (#) The OPAMP(s) provide(s) calibration capabilities.
+ (#) The OPAMP(s) provide(s) calibration capabilities.
(++) Calibration aims at correcting some offset for running mode.
- (++) The OPAMP uses either factory calibration settings OR user defined
+ (++) The OPAMP uses either factory calibration settings OR user defined
calibration (trimming) settings (i.e. trimming mode).
- (++) The user defined settings can be figured out using self calibration
+ (++) The user defined settings can be figured out using self calibration
handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
(++) HAL_OPAMP_SelfCalibrate:
- (+++) Runs automatically the calibration in 2 steps.
+ (+++) Runs automatically the calibration in 2 steps.
(90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
- (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
+ (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
appropriate and enough in most cases).
(+++) Runs automatically the calibration.
(+++) Enables the user trimming mode
- (+++) Updates the init structure with trimming values with fresh calibration
- results.
- The user may store the calibration results for larger
- (ex monitoring the trimming as a function of temperature
+ (+++) Updates the init structure with trimming values with fresh calibration
+ results.
+ The user may store the calibration results for larger
+ (ex monitoring the trimming as a function of temperature
for instance)
(+++) HAL_OPAMPEx_SelfCalibrateAll
runs calibration of all OPAMPs in parallel to save search time.
-
- (#) Running mode: Standalone mode
+
+ (#) Running mode: Standalone mode
(++) Gain is set externally (gain depends on external loads).
(++) Follower mode also possible externally by connecting the inverting input to
the output.
-
+
(#) Running mode: Follower mode
(++) No Inverting Input is connected.
-
- (#) Running mode: Programmable Gain Amplifier (PGA) mode
+
+ (#) Running mode: Programmable Gain Amplifier (PGA) mode
(Resistor feedback output)
(#) The OPAMP(s) output(s) can be internally connected to resistor feedback
output.
@@ -72,7 +72,7 @@
(##) Gain of x2, x4, x8 or x16 for non inverting mode with:
(+++) VREF- referenced.
- (+++) Filtering on VINM0, VREF- referenced.
+ (+++) Filtering on VINM0, VREF- referenced.
(+++) VINM0 node for bias voltage and VINP0 for input signal.
(+++) VINM0 node for bias voltage and VINP0 for input signal, VINM1 node for filtering.
@@ -80,16 +80,16 @@
(+++) VINM0 node for input signal and VINP0 for bias.
(+++) VINM0 node for input signal and VINP0 for bias voltage, VINM1 node for filtering.
- (#) The OPAMPs inverting input can be selected according to the Reference Manual
+ (#) The OPAMPs inverting input can be selected according to the Reference Manual
"OPAMP functional description" chapter.
- (#) The OPAMPs non inverting input can be selected according to the Reference Manual
+ (#) The OPAMPs non inverting input can be selected according to the Reference Manual
"OPAMP functional description" chapter.
##### How to use this driver #####
================================================================================
- [..]
+ [..]
*** High speed / normal power mode ***
============================================
@@ -103,7 +103,7 @@
============================================
[..] To run the OPAMP calibration self calibration:
- (#) Start calibration using HAL_OPAMP_SelfCalibrate.
+ (#) Start calibration using HAL_OPAMP_SelfCalibrate.
Store the calibration results.
*** Running mode ***
@@ -113,7 +113,7 @@
(#) Fill in the HAL_OPAMP_MspInit() to
(++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
- (++) Configure the OPAMP input AND output in analog mode using
+ (++) Configure the OPAMP input AND output in analog mode using
HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
(#) Registrate Callbacks
@@ -122,20 +122,20 @@
(++) Use Functions HAL_OPAMP_RegisterCallback() to register a user callback,
it allows to register following callbacks:
- (+++) MspInitCallback : OPAMP MspInit.
+ (+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
(++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
- (+++) MspInitCallback : OPAMP MspInit.
+ weak (overridden) function. It allows to reset following callbacks:
+ (+++) MspInitCallback : OPAMP MspInit.
(+++) MspDeInitCallback : OPAMP MspDeInit.
(+++) All Callbacks
(#) Configure the OPAMP using HAL_OPAMP_Init() function:
(++) Select the mode
(++) Select the inverting input
- (++) Select the non-inverting input
+ (++) Select the non-inverting input
(++) If PGA mode is enabled, Select if inverting input is connected.
(++) Select either factory or user defined trimming mode.
(++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
@@ -146,7 +146,7 @@
(#) Disable the OPAMP using HAL_OPAMP_Stop() function.
(#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
- Caution: On STM32H7, HAL OPAMP lock is software lock only (not
+ Caution: On STM32H7, HAL OPAMP lock is software lock only (not
hardware lock as on some other STM32 devices)
(#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
@@ -160,8 +160,8 @@
(#) Configure the OPAMP using HAL_OPAMP_Init() function:
(++) As in configure case, select first the parameters you wish to modify.
- (#) Change from high speed mode to normal power mode (& vice versa) requires
- first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
+ (#) Change from high speed mode to normal power mode (& vice versa) requires
+ first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
alone.
@@ -205,7 +205,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
-
+
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@@ -224,7 +224,7 @@
* @{
*/
-/* CSR register reset value */
+/* CSR register reset value */
#define OPAMP_CSR_RESET_VALUE 0x00000000U
/* CSR Init masks */
@@ -234,14 +234,14 @@
#define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL| OPAMP_CSR_VPSEL \
- | OPAMP_CSR_USERTRIM)
+ | OPAMP_CSR_USERTRIM)
#define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL \
| OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@@ -251,14 +251,14 @@
* @{
*/
-/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
-
+
@endverbatim
* @{
*/
@@ -272,7 +272,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
uint32_t updateotrlpotr;
@@ -285,7 +285,7 @@
else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
return HAL_ERROR;
- }
+ }
else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
{
return HAL_ERROR;
@@ -294,15 +294,15 @@
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
+
/* Set OPAMP parameters */
assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
-
+
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if(hopamp->State == HAL_OPAMP_STATE_RESET)
- {
+ {
if(hopamp->MspInitCallback == NULL)
{
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
@@ -314,14 +314,14 @@
assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
}
- if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
+ if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
{
assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
}
-
- assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
+
+ assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
{
@@ -336,7 +336,7 @@
assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNHighSpeed));
}
}
-
+
if(hopamp->State == HAL_OPAMP_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -344,15 +344,15 @@
}
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
- hopamp->MspInitCallback(hopamp);
-#else
+ hopamp->MspInitCallback(hopamp);
+#else
/* Call MSP init function */
HAL_OPAMP_MspInit(hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/* Set operating mode */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
- /* In PGA mode InvertingInput is Not Applicable */
+ /* In PGA mode InvertingInput is Not Applicable */
if (hopamp->Init.Mode == OPAMP_PGA_MODE)
{
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
@@ -363,7 +363,7 @@
hopamp->Init.NonInvertingInput | \
hopamp->Init.UserTrimming);
}
-
+
if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
{
/* In Follower mode InvertingInput is Not Applicable */
@@ -371,9 +371,9 @@
hopamp->Init.PowerMode | \
hopamp->Init.Mode | \
hopamp->Init.NonInvertingInput | \
- hopamp->Init.UserTrimming);
- }
-
+ hopamp->Init.UserTrimming);
+ }
+
if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
{
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
@@ -382,8 +382,8 @@
hopamp->Init.InvertingInput | \
hopamp->Init.NonInvertingInput | \
hopamp->Init.UserTrimming);
- }
-
+ }
+
if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
{
/* Set power mode and associated calibration parameters */
@@ -394,7 +394,7 @@
/* transistors differential pair high (PMOS) and low (NMOS) for */
/* normal mode. */
updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
- | (hopamp->Init.TrimmingValueN));
+ | (hopamp->Init.TrimmingValueN));
MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
}
else
@@ -403,11 +403,11 @@
/* transistors differential pair high (PMOS) and low (NMOS) for */
/* high speed mode. */
updateotrlpotr = (((hopamp->Init.TrimmingValuePHighSpeed) << (OPAMP_INPUT_NONINVERTING)) \
- | (hopamp->Init.TrimmingValueNHighSpeed));
- MODIFY_REG(hopamp->Instance->HSOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
+ | (hopamp->Init.TrimmingValueNHighSpeed));
+ MODIFY_REG(hopamp->Instance->HSOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
}
- }
-
+ }
+
/* Update the OPAMP state*/
if (hopamp->State == HAL_OPAMP_STATE_RESET)
{
@@ -420,7 +420,7 @@
}
/**
- * @brief DeInitialize the OPAMP peripheral
+ * @brief DeInitialize the OPAMP peripheral
* @note Deinitialization can be performed if the OPAMP configuration is locked.
* (the lock is SW in H7)
* @param hopamp OPAMP handle
@@ -429,7 +429,7 @@
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check the OPAMP handle allocation */
/* DeInit not allowed if calibration is on going */
if(hopamp == NULL)
@@ -448,7 +448,7 @@
/* Set OPAMP_CSR register to reset value */
WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
- /* DeInit the low level hardware */
+ /* DeInit the low level hardware */
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if(hopamp->MspDeInitCallback == NULL)
{
@@ -461,7 +461,7 @@
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/* Update the OPAMP state*/
- hopamp->State = HAL_OPAMP_STATE_RESET;
+ hopamp->State = HAL_OPAMP_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hopamp);
@@ -505,13 +505,13 @@
*/
-/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
+/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to manage the OPAMP
start, stop and calibration actions.
@@ -526,9 +526,9 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
if(hopamp == NULL)
@@ -538,39 +538,39 @@
else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
{
status = HAL_ERROR;
- }
+ }
else
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
+
if(hopamp->State == HAL_OPAMP_STATE_READY)
{
/* Enable the selected opamp */
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
- /* Update the OPAMP state*/
+ /* Update the OPAMP state*/
/* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
- hopamp->State = HAL_OPAMP_STATE_BUSY;
+ hopamp->State = HAL_OPAMP_STATE_BUSY;
}
else
{
status = HAL_ERROR;
}
-
+
}
return status;
}
/**
- * @brief Stop the OPAMP.
+ * @brief Stop the OPAMP.
* @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
-
+
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
/* Check if OPAMP calibration ongoing */
@@ -582,7 +582,7 @@
{
status = HAL_ERROR;
}
- else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
+ else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
{
status = HAL_ERROR;
}
@@ -594,9 +594,9 @@
if(hopamp->State == HAL_OPAMP_STATE_BUSY)
{
/* Disable the selected opamp */
- CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Update the OPAMP state*/
+ CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+ /* Update the OPAMP state*/
/* From HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
hopamp->State = HAL_OPAMP_STATE_READY;
}
@@ -619,17 +619,17 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
-{
+{
HAL_StatusTypeDef status = HAL_OK;
-
+
uint32_t trimmingvaluen;
uint32_t trimmingvaluep;
uint32_t delta;
uint32_t opampmode;
-
+
__IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or HSOTR */
-
+
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
if(hopamp == NULL)
@@ -642,7 +642,7 @@
}
else
{
-
+
/* Check if OPAMP in calibration mode and calibration not yet enable */
if(hopamp->State == HAL_OPAMP_STATE_READY)
{
@@ -651,12 +651,12 @@
assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_VMSEL);
-
- /* Use of standalone mode */
- MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
+
+ /* Use of standalone mode */
+ MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
/* user trimming values are used for offset calibration */
SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
-
+
/* Select trimming settings depending on power mode */
if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
{
@@ -669,7 +669,7 @@
tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
}
-
+
/* Enable calibration */
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
@@ -681,25 +681,25 @@
/* Enable the selected opamp */
SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-
- /* Init trimming counter */
+
+ /* Init trimming counter */
/* Medium value */
trimmingvaluen = 16U;
delta = 8U;
-
+
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMAL */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
-
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
-
- if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
- {
+
+ if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+ {
/* OPAMP_CSR_CALOUT is HIGH try higher trimming */
trimmingvaluen += delta;
}
@@ -708,22 +708,22 @@
/* OPAMP_CSR_CALOUT is LOW try lower trimming */
trimmingvaluen -= delta;
}
- /* Divide range by 2 to continue dichotomy sweep */
+ /* Divide range by 2 to continue dichotomy sweep */
delta >>= 1;
}
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
-
+
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
-
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
-
+
if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) != 0U)
- {
+ {
/* Trimming value is actually one value more */
trimmingvaluen++;
/* Set right trimming */
@@ -732,25 +732,25 @@
/* 2nd calibration - P */
MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
-
- /* Init trimming counter */
+
+ /* Init trimming counter */
/* Medium value */
- trimmingvaluep = 16U;
+ trimmingvaluep = 16U;
delta = 8U;
-
+
while (delta != 0U)
{
/* Set candidate trimming */
/* OPAMP_POWERMODE_NORMAL */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
- if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
- {
+ if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
+ {
/* OPAMP_CSR_CALOUT is HIGH try higher trimming */
trimmingvaluep += delta;
}
@@ -759,28 +759,28 @@
/* OPAMP_CSR_CALOUT is LOW try lower trimming */
trimmingvaluep -= delta;
}
-
+
/* Divide range by 2 to continue dichotomy sweep */
delta >>= 1U;
}
-
+
/* Still need to check if right calibration is current value or one step below */
/* Indeed the first value that causes the OUTCAL bit to change from 1 to 0 */
/* Set candidate trimming */
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
- /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
+ /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
/* Offset trim time: during calibration, minimum time needed between */
/* two steps to have 1 mV accuracy */
HAL_Delay(OPAMP_TRIMMING_DELAY);
-
- if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+
+ if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
{
/* Trimming value is actually one value more */
trimmingvaluep++;
MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
}
-
+
/* Disable calibration & set normal mode (operating mode) */
CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
@@ -789,11 +789,11 @@
/* Set operating mode back */
CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
-
+
/* Self calibration is successful */
/* Store calibration(user trimming) results in init structure. */
- /* Set user trimming mode */
+ /* Set user trimming mode */
hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
/* Affect calibration parameters depending on mode normal/high speed */
@@ -817,9 +817,9 @@
else
{
- /* OPAMP can not be calibrated from this mode */
+ /* OPAMP can not be calibrated from this mode */
status = HAL_ERROR;
- }
+ }
}
return status;
}
@@ -828,15 +828,15 @@
* @}
*/
-/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
+/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the OPAMP data
+ This subsection provides a set of functions allowing to control the OPAMP data
transfers.
@@ -847,8 +847,8 @@
/**
* @brief Lock the selected OPAMP configuration.
- * @note On STM32H7, HAL OPAMP lock is software lock only (in
- * contrast of hardware lock available on some other STM32
+ * @note On STM32H7, HAL OPAMP lock is software lock only (in
+ * contrast of hardware lock available on some other STM32
* devices)
* @param hopamp OPAMP handle
* @retval HAL status
@@ -859,13 +859,13 @@
/* Check the OPAMP handle allocation */
/* Check if OPAMP locked */
- /* OPAMP can be locked when enabled and running in normal mode */
+ /* OPAMP can be locked when enabled and running in normal mode */
/* It is meaningless otherwise */
if(hopamp == NULL)
{
status = HAL_ERROR;
}
-
+
else if(hopamp->State != HAL_OPAMP_STATE_BUSY)
{
status = HAL_ERROR;
@@ -874,29 +874,29 @@
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
+
/* OPAMP state changed to locked */
hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
- }
- return status;
+ }
+ return status;
}
/**
* @brief Return the OPAMP factory trimming value.
- * @note On STM32H7 OPAMP, user can retrieve factory trimming if
+ * @note On STM32H7 OPAMP, user can retrieve factory trimming if
* OPAMP has never been set to user trimming before.
- * Therefore, this function must be called when OPAMP init
- * parameter "UserTrimming" is set to trimming factory,
- * and before OPAMP calibration (function
+ * Therefore, this function must be called when OPAMP init
+ * parameter "UserTrimming" is set to trimming factory,
+ * and before OPAMP calibration (function
* "HAL_OPAMP_SelfCalibrate()").
- * Otherwise, factory trimming value cannot be retrieved and
+ * Otherwise, factory trimming value cannot be retrieved and
* error status is returned.
* @param hopamp OPAMP handle
* @param trimmingoffset Trimming offset (P or N)
* This parameter must be a value of @ref OPAMP_FactoryTrimming
- * @note Calibration parameter retrieved is corresponding to the mode
- * specified in OPAMP init structure (mode normal or high-speed).
- * To retrieve calibration parameters for both modes, repeat this
+ * @note Calibration parameter retrieved is corresponding to the mode
+ * specified in OPAMP init structure (mode normal or high-speed).
+ * To retrieve calibration parameters for both modes, repeat this
* function after OPAMP init structure accordingly updated.
* @retval Trimming value (P or N): range: 0->31
* or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
@@ -906,23 +906,23 @@
{
HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
__IO uint32_t* tmp_opamp_reg_trimming; /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-
+
/* Check the OPAMP handle allocation */
/* Value can be retrieved in HAL_OPAMP_STATE_READY state */
if(hopamp == NULL)
{
return OPAMP_FACTORYTRIMMING_DUMMY;
}
-
+
if(hopamp->State == HAL_OPAMP_STATE_READY)
{
/* Check the parameter */
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-
+
/* Check the trimming mode */
- if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)!= 0U)
+ if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)!= 0U)
{
/* This function must called when OPAMP init parameter "UserTrimming" */
/* is set to trimming factory, and before OPAMP calibration (function */
@@ -941,8 +941,8 @@
else
{
tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
- }
-
+ }
+
/* Get factory trimming */
if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
{
@@ -960,26 +960,26 @@
{
return OPAMP_FACTORYTRIMMING_DUMMY;
}
-
+
return trimmingvalue;
}
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User OPAMP Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used instead of the weak (overridden) predefined callback
* @param hopamp OPAMP handle
* @param CallbackId ID of the callback to be registered
* This parameter can be one of the following values:
- * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID
- * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID
+ * @arg @ref HAL_OPAMP_MSPINIT_CB_ID OPAMP MspInit callback ID
+ * @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID OPAMP MspDeInit callback ID
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
-
+
if(pCallback == NULL)
{
return HAL_ERROR;
@@ -987,7 +987,7 @@
/* Process locked */
__HAL_LOCK(hopamp);
-
+
if(hopamp->State == HAL_OPAMP_STATE_READY)
{
switch (CallbackId)
@@ -1033,7 +1033,7 @@
/**
* @brief Unregister a User OPAMP Callback
- * OPAMP Callback is redirected to the weak (surcharged) predefined callback
+ * OPAMP Callback is redirected to the weak (overridden) predefined callback
* @param hopamp OPAMP handle
* @param CallbackId ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -1048,11 +1048,11 @@
/* Process locked */
__HAL_LOCK(hopamp);
-
+
if(hopamp->State == HAL_OPAMP_STATE_READY)
{
switch (CallbackId)
- {
+ {
case HAL_OPAMP_MSPINIT_CB_ID :
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
break;
@@ -1103,13 +1103,13 @@
*/
-/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
diff --git a/Src/stm32h7xx_hal_ospi.c b/Src/stm32h7xx_hal_ospi.c
index f60f71d..46474bf 100644
--- a/Src/stm32h7xx_hal_ospi.c
+++ b/Src/stm32h7xx_hal_ospi.c
@@ -52,7 +52,7 @@
and the CS boundary using the HAL_OSPI_Init() function.
[..]
When using Hyperbus, configure the RW recovery time, the access time,
- the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
+ the write latency and the latency mode using the HAL_OSPI_HyperbusCfg()
function.
*** Indirect functional mode ***
@@ -123,22 +123,29 @@
(+) MDMA settings for write operation :
(++) The DestinationInc should be MDMA_DEST_INC_DISABLE
(++) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
- (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
+ (++) The SourceDataSize must be a value of @ref MDMA Source data size
+ (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Source_increment_mode .
- (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ (++) The DestDataSize must be a value of @ref MDMA Destination data size
+ (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
(+) MDMA settings for read operation :
(++) The SourceInc should be MDMA_SRC_INC_DISABLE
- (++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
- (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
- (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+ (++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode
+ (Except the MDMA_DEST_INC_DOUBLEWORD).
+ (++) The SourceDataSize must be a value of @ref MDMA Source data size
+ (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
+ (++) The DestDataSize must be a value of @ref MDMA Destination data size
+ (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
aligned with @ref MDMA_Destination_increment_mode.
(+) The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi.
[..]
In case of wrong MDMA setting
(+) For write operation :
- (++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA().
+ (++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled
+ by the HAL_OSPI_Transmit_DMA().
(+) For read operation :
- (++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA().
+ (++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled
+ by the HAL_OSPI_Receive_DMA().
*** Memory-mapped functional mode ***
=====================================
@@ -214,7 +221,7 @@
[..]
Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) FifoThresholdCallback : callback when the fifo threshold is reached.
@@ -232,9 +239,9 @@
[..]
By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
+ reset to the legacy weak (overridden) functions in the HAL_OSPI_Init()
and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -251,7 +258,7 @@
[..]
When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -300,13 +307,13 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void OSPI_DMACplt (MDMA_HandleTypeDef *hmdma);
-static void OSPI_DMAError (MDMA_HandleTypeDef *hmdma);
-static void OSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma);
+static void OSPI_DMACplt(MDMA_HandleTypeDef *hmdma);
+static void OSPI_DMAError(MDMA_HandleTypeDef *hmdma);
+static void OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma);
static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
-static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
+static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
static void OSPI_DMAAbortOnError(MDMA_HandleTypeDef *hmdma);
/**
@endcond
@@ -340,7 +347,7 @@
* @param hospi : OSPI handle
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
+HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart = HAL_GetTick();
@@ -354,20 +361,20 @@
else
{
/* Check the parameters of the initialization structure */
- assert_param(IS_OSPI_FIFO_THRESHOLD (hospi->Init.FifoThreshold));
- assert_param(IS_OSPI_DUALQUAD_MODE (hospi->Init.DualQuad));
- assert_param(IS_OSPI_MEMORY_TYPE (hospi->Init.MemoryType));
- assert_param(IS_OSPI_DEVICE_SIZE (hospi->Init.DeviceSize));
- assert_param(IS_OSPI_CS_HIGH_TIME (hospi->Init.ChipSelectHighTime));
- assert_param(IS_OSPI_FREE_RUN_CLK (hospi->Init.FreeRunningClock));
- assert_param(IS_OSPI_CLOCK_MODE (hospi->Init.ClockMode));
- assert_param(IS_OSPI_WRAP_SIZE (hospi->Init.WrapSize));
- assert_param(IS_OSPI_CLK_PRESCALER (hospi->Init.ClockPrescaler));
+ assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold));
+ assert_param(IS_OSPI_DUALQUAD_MODE(hospi->Init.DualQuad));
+ assert_param(IS_OSPI_MEMORY_TYPE(hospi->Init.MemoryType));
+ assert_param(IS_OSPI_DEVICE_SIZE(hospi->Init.DeviceSize));
+ assert_param(IS_OSPI_CS_HIGH_TIME(hospi->Init.ChipSelectHighTime));
+ assert_param(IS_OSPI_FREE_RUN_CLK(hospi->Init.FreeRunningClock));
+ assert_param(IS_OSPI_CLOCK_MODE(hospi->Init.ClockMode));
+ assert_param(IS_OSPI_WRAP_SIZE(hospi->Init.WrapSize));
+ assert_param(IS_OSPI_CLK_PRESCALER(hospi->Init.ClockPrescaler));
assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
- assert_param(IS_OSPI_DHQC (hospi->Init.DelayHoldQuarterCycle));
- assert_param(IS_OSPI_CS_BOUNDARY (hospi->Init.ChipSelectBoundary));
- assert_param(IS_OSPI_DLYBYP (hospi->Init.DelayBlockBypass));
- assert_param(IS_OSPI_MAXTRAN (hospi->Init.MaxTran));
+ assert_param(IS_OSPI_DHQC(hospi->Init.DelayHoldQuarterCycle));
+ assert_param(IS_OSPI_CS_BOUNDARY(hospi->Init.ChipSelectBoundary));
+ assert_param(IS_OSPI_DLYBYP(hospi->Init.DelayBlockBypass));
+ assert_param(IS_OSPI_MAXTRAN(hospi->Init.MaxTran));
/* Initialize error code */
hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
@@ -388,7 +395,7 @@
hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
- if(hospi->MspInitCallback == NULL)
+ if (hospi->MspInitCallback == NULL)
{
hospi->MspInitCallback = HAL_OSPI_MspInit;
}
@@ -432,14 +439,14 @@
{
/* Configure clock prescaler */
MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
- ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+ ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
/* Configure Dual Quad mode */
MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
/* Configure sample shifting and delay hold quarter cycle */
MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
- (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+ (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
/* Enable OctoSPI */
__HAL_OSPI_ENABLE(hospi);
@@ -499,27 +506,27 @@
}
else
{
- /* Disable OctoSPI */
- __HAL_OSPI_DISABLE(hospi);
+ /* Disable OctoSPI */
+ __HAL_OSPI_DISABLE(hospi);
- /* Disable free running clock if needed : must be done after OSPI disable */
- CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+ /* Disable free running clock if needed : must be done after OSPI disable */
+ CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
- if(hospi->MspDeInitCallback == NULL)
- {
- hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
- }
+ if (hospi->MspDeInitCallback == NULL)
+ {
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ }
- /* DeInit the low level hardware */
- hospi->MspDeInitCallback(hospi);
+ /* DeInit the low level hardware */
+ hospi->MspDeInitCallback(hospi);
#else
- /* De-initialize the low-level hardware */
- HAL_OSPI_MspDeInit(hospi);
+ /* De-initialize the low-level hardware */
+ HAL_OSPI_MspDeInit(hospi);
#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
- /* Reset the driver state */
- hospi->State = HAL_OSPI_STATE_RESET;
+ /* Reset the driver state */
+ hospi->State = HAL_OSPI_STATE_RESET;
}
return status;
@@ -625,7 +632,7 @@
hospi->pBuffPtr++;
hospi->XferCount--;
}
- else if(hospi->XferCount == 0U)
+ else if (hospi->XferCount == 0U)
{
/* Clear flag */
hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
@@ -818,21 +825,21 @@
assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
{
- assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize));
+ assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
}
assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
- assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
}
assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
{
- assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize));
+ assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
}
@@ -841,20 +848,20 @@
{
if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
{
- assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
}
assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
- assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
+ assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
}
- assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
/* Check the state of the driver */
state = hospi->State;
if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
- || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
+ || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) ||
(cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
{
@@ -949,33 +956,33 @@
assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
{
- assert_param(IS_OSPI_INSTRUCTION_SIZE (cmd->InstructionSize));
+ assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
}
assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
{
- assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
}
assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
{
- assert_param(IS_OSPI_ALT_BYTES_SIZE (cmd->AlternateBytesSize));
+ assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
}
assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
if (cmd->DataMode != HAL_OSPI_DATA_NONE)
{
- assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
- assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
+ assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
}
- assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
/* Check the state of the driver */
@@ -999,7 +1006,7 @@
if (status == HAL_OK)
{
/* Update the state */
- hospi->State = HAL_OSPI_STATE_BUSY_CMD;
+ hospi->State = HAL_OSPI_STATE_BUSY_CMD;
/* Enable the transfer complete and transfer error interrupts */
__HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE);
@@ -1030,10 +1037,10 @@
uint32_t tickstart = HAL_GetTick();
/* Check the parameters of the hyperbus configuration structure */
- assert_param(IS_OSPI_RW_RECOVERY_TIME (cfg->RWRecoveryTime));
- assert_param(IS_OSPI_ACCESS_TIME (cfg->AccessTime));
+ assert_param(IS_OSPI_RW_RECOVERY_TIME(cfg->RWRecoveryTime));
+ assert_param(IS_OSPI_ACCESS_TIME(cfg->AccessTime));
assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency));
- assert_param(IS_OSPI_LATENCY_MODE (cfg->LatencyMode));
+ assert_param(IS_OSPI_LATENCY_MODE(cfg->LatencyMode));
/* Check the state of the driver */
state = hospi->State;
@@ -1077,9 +1084,9 @@
/* Check the parameters of the hyperbus command structure */
assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace));
- assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
- assert_param(IS_OSPI_NUMBER_DATA (cmd->NbData));
- assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+ assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
+ assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
+ assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
/* Check the state of the driver */
if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS))
@@ -1263,7 +1270,7 @@
*hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
hospi->pBuffPtr++;
hospi->XferCount--;
- } while(hospi->XferCount > 0U);
+ } while (hospi->XferCount > 0U);
if (status == HAL_OK)
{
@@ -1461,21 +1468,22 @@
/* Clear the MDMA abort callback */
hospi->hmdma->XferAbortCallback = NULL;
- /* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment to disable */
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
+ /* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment
+ to disable */
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_DISABLE);
/* Update MDMA configuration with the correct SourceInc field for Write operation */
if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
{
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_BYTE);
}
else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
{
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_HALFWORD);
}
else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
{
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_WORD);
}
else
{
@@ -1485,20 +1493,21 @@
}
/* Enable the transmit MDMA Channel */
- if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+ if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize, 1) == \
+ HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
- /* Enable the DMA transfer by setting the DMAEN bit */
- SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -1565,20 +1574,20 @@
hospi->hmdma->XferAbortCallback = NULL;
/* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_DISABLE);
/* Update MDMA configuration with the correct DestinationInc field for read operation */
if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
{
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_BYTE);
}
else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
{
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_HALFWORD);
}
else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
{
- MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
+ MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_WORD);
}
else
{
@@ -1588,37 +1597,38 @@
}
/* Enable the transmit MDMA Channel */
- if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == HAL_OK)
- {
- /* Enable the transfer error interrupt */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+ if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize, 1) == \
+ HAL_OK)
+ {
+ /* Enable the transfer error interrupt */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
- /* Trig the transfer by re-writing address or instruction register */
- if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ /* Trig the transfer by re-writing address or instruction register */
+ if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)
+ {
+ WRITE_REG(hospi->Instance->AR, addr_reg);
+ }
+ else
+ {
+ if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
{
WRITE_REG(hospi->Instance->AR, addr_reg);
}
else
{
- if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE)
- {
- WRITE_REG(hospi->Instance->AR, addr_reg);
- }
- else
- {
- WRITE_REG(hospi->Instance->IR, ir_reg);
- }
+ WRITE_REG(hospi->Instance->IR, ir_reg);
}
+ }
- /* Enable the DMA transfer by setting the DMAEN bit */
- SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
- }
- else
- {
- status = HAL_ERROR;
- hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
- hospi->State = HAL_OSPI_STATE_READY;
- }
+ /* Enable the DMA transfer by setting the DMAEN bit */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+ }
+ else
+ {
+ status = HAL_ERROR;
+ hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+ hospi->State = HAL_OSPI_STATE_READY;
+ }
}
}
else
@@ -1651,10 +1661,10 @@
#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
- assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
- assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop));
- assert_param(IS_OSPI_INTERVAL (cfg->Interval));
- assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
+ assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+ assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
/* Check the state */
if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE))
@@ -1665,10 +1675,10 @@
if (status == HAL_OK)
{
/* Configure registers */
- WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
- WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
- WRITE_REG (hospi->Instance->PIR, cfg->Interval);
- MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+ WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+ WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+ WRITE_REG(hospi->Instance->PIR, cfg->Interval);
+ MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
(cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
/* Trig the transfer by re-writing address or instruction register */
@@ -1729,10 +1739,10 @@
#endif /* USE_FULL_ASSERT */
/* Check the parameters of the autopolling configuration structure */
- assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode));
- assert_param(IS_OSPI_AUTOMATIC_STOP (cfg->AutomaticStop));
- assert_param(IS_OSPI_INTERVAL (cfg->Interval));
- assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
+ assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+ assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+ assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+ assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
/* Check the state */
if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
@@ -1743,10 +1753,10 @@
if (status == HAL_OK)
{
/* Configure registers */
- WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
- WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
- WRITE_REG (hospi->Instance->PIR, cfg->Interval);
- MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+ WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+ WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+ WRITE_REG(hospi->Instance->PIR, cfg->Interval);
+ MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
(cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
/* Clear flags related to interrupt */
@@ -1921,7 +1931,7 @@
* @param hospi : OSPI handle
* @retval None
*/
- __weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
+__weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hospi);
@@ -1994,7 +2004,7 @@
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
/**
* @brief Register a User OSPI Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -2018,77 +2028,77 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
/* Update the error code */
hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
return HAL_ERROR;
}
- if(hospi->State == HAL_OSPI_STATE_READY)
+ if (hospi->State == HAL_OSPI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_OSPI_ERROR_CB_ID :
- hospi->ErrorCallback = pCallback;
- break;
- case HAL_OSPI_ABORT_CB_ID :
- hospi->AbortCpltCallback = pCallback;
- break;
- case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
- hospi->FifoThresholdCallback = pCallback;
- break;
- case HAL_OSPI_CMD_CPLT_CB_ID :
- hospi->CmdCpltCallback = pCallback;
- break;
- case HAL_OSPI_RX_CPLT_CB_ID :
- hospi->RxCpltCallback = pCallback;
- break;
- case HAL_OSPI_TX_CPLT_CB_ID :
- hospi->TxCpltCallback = pCallback;
- break;
- case HAL_OSPI_RX_HALF_CPLT_CB_ID :
- hospi->RxHalfCpltCallback = pCallback;
- break;
- case HAL_OSPI_TX_HALF_CPLT_CB_ID :
- hospi->TxHalfCpltCallback = pCallback;
- break;
- case HAL_OSPI_STATUS_MATCH_CB_ID :
- hospi->StatusMatchCallback = pCallback;
- break;
- case HAL_OSPI_TIMEOUT_CB_ID :
- hospi->TimeOutCallback = pCallback;
- break;
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = pCallback;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_ERROR_CB_ID :
+ hospi->ErrorCallback = pCallback;
+ break;
+ case HAL_OSPI_ABORT_CB_ID :
+ hospi->AbortCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+ hospi->FifoThresholdCallback = pCallback;
+ break;
+ case HAL_OSPI_CMD_CPLT_CB_ID :
+ hospi->CmdCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_RX_CPLT_CB_ID :
+ hospi->RxCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_TX_CPLT_CB_ID :
+ hospi->TxCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+ hospi->RxHalfCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+ hospi->TxHalfCpltCallback = pCallback;
+ break;
+ case HAL_OSPI_STATUS_MATCH_CB_ID :
+ hospi->StatusMatchCallback = pCallback;
+ break;
+ case HAL_OSPI_TIMEOUT_CB_ID :
+ hospi->TimeOutCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hospi->State == HAL_OSPI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = pCallback;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = pCallback;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = pCallback;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -2104,7 +2114,7 @@
/**
* @brief Unregister a User OSPI Callback
- * OSPI Callback is redirected to the weak (surcharged) predefined callback
+ * OSPI Callback is redirected to the weak predefined callback
* @param hospi : OSPI handle
* @param CallbackID : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -2122,74 +2132,74 @@
* @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- if(hospi->State == HAL_OSPI_STATE_READY)
+ if (hospi->State == HAL_OSPI_STATE_READY)
{
switch (CallbackID)
{
- case HAL_OSPI_ERROR_CB_ID :
- hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
- break;
- case HAL_OSPI_ABORT_CB_ID :
- hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
- break;
- case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
- hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
- break;
- case HAL_OSPI_CMD_CPLT_CB_ID :
- hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
- break;
- case HAL_OSPI_RX_CPLT_CB_ID :
- hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
- break;
- case HAL_OSPI_TX_CPLT_CB_ID :
- hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
- break;
- case HAL_OSPI_RX_HALF_CPLT_CB_ID :
- hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
- break;
- case HAL_OSPI_TX_HALF_CPLT_CB_ID :
- hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
- break;
- case HAL_OSPI_STATUS_MATCH_CB_ID :
- hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
- break;
- case HAL_OSPI_TIMEOUT_CB_ID :
- hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
- break;
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = HAL_OSPI_MspInit;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_ERROR_CB_ID :
+ hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
+ break;
+ case HAL_OSPI_ABORT_CB_ID :
+ hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
+ break;
+ case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+ hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
+ break;
+ case HAL_OSPI_CMD_CPLT_CB_ID :
+ hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
+ break;
+ case HAL_OSPI_RX_CPLT_CB_ID :
+ hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
+ break;
+ case HAL_OSPI_TX_CPLT_CB_ID :
+ hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
+ break;
+ case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+ hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
+ break;
+ case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+ hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
+ break;
+ case HAL_OSPI_STATUS_MATCH_CB_ID :
+ hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
+ break;
+ case HAL_OSPI_TIMEOUT_CB_ID :
+ hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
+ break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = HAL_OSPI_MspInit;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else if (hospi->State == HAL_OSPI_STATE_RESET)
{
switch (CallbackID)
{
- case HAL_OSPI_MSP_INIT_CB_ID :
- hospi->MspInitCallback = HAL_OSPI_MspInit;
- break;
- case HAL_OSPI_MSP_DEINIT_CB_ID :
- hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
- break;
- default :
- /* Update the error code */
- hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_OSPI_MSP_INIT_CB_ID :
+ hospi->MspInitCallback = HAL_OSPI_MspInit;
+ break;
+ case HAL_OSPI_MSP_DEINIT_CB_ID :
+ hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+ break;
+ default :
+ /* Update the error code */
+ hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -2228,10 +2238,10 @@
*/
/**
-* @brief Abort the current transmission.
-* @param hospi : OSPI handle
-* @retval HAL status
-*/
+ * @brief Abort the current transmission.
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2296,10 +2306,10 @@
}
/**
-* @brief Abort the current transmission (non-blocking function)
-* @param hospi : OSPI handle
-* @retval HAL status
-*/
+ * @brief Abort the current transmission (non-blocking function)
+ * @param hospi : OSPI handle
+ * @retval HAL status
+ */
HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2389,7 +2399,7 @@
hospi->Init.FifoThreshold = Threshold;
/* Configure new fifo threshold */
- MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos));
+ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
}
else
@@ -2406,7 +2416,7 @@
* @param hospi : OSPI handle.
* @retval Fifo threshold
*/
-uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi)
{
return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
}
@@ -2423,11 +2433,11 @@
}
/**
-* @brief Return the OSPI error code.
-* @param hospi : OSPI handle
-* @retval OSPI Error Code
-*/
-uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
+ * @brief Return the OSPI error code.
+ * @param hospi : OSPI handle
+ * @retval OSPI Error Code
+ */
+uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi)
{
return hospi->ErrorCode;
}
@@ -2437,7 +2447,7 @@
* @param hospi : OSPI handle
* @retval HAL state
*/
-uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi)
{
/* Return OSPI handle state */
return hospi->State;
@@ -2503,7 +2513,7 @@
/**************** Get current configuration of the instances ****************/
for (index = 0U; index < OSPI_NB_INSTANCE; index++)
{
- if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK)
+ if (OSPIM_GetConfig(index + 1U, &(IOM_cfg[index])) != HAL_OK)
{
status = HAL_ERROR;
hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
@@ -2525,7 +2535,7 @@
}
/***************** Deactivation of previous configuration *****************/
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
/* De-multiplexing should be performed */
@@ -2533,18 +2543,20 @@
if (other_instance == 1U)
{
- SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKSRC);
if (IOM_cfg[other_instance].DQSPort != 0U)
{
- SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
+ SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSSRC);
}
if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], \
+ OCTOSPIM_PCR_IOLSRC_1);
}
if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
+ SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], \
+ OCTOSPIM_PCR_IOHSRC_1);
}
}
}
@@ -2552,18 +2564,18 @@
{
if (IOM_cfg[instance].ClkPort != 0U)
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
if (IOM_cfg[instance].DQSPort != 0U)
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
}
if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
}
if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
}
}
}
@@ -2583,28 +2595,28 @@
}
else
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
if (IOM_cfg[other_instance].DQSPort != 0U)
{
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
}
- CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+ CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
OCTOSPIM_PCR_IOLEN);
}
if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+ CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
OCTOSPIM_PCR_IOHEN);
}
}
}
/******************** Activation of new configuration *********************/
- MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
- (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
+ (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
{
@@ -2613,84 +2625,84 @@
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
if (cfg->DQSPort != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
}
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
}
else
{
- /* Nothing to do */
+ /* Nothing to do */
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
}
else
{
- /* Nothing to do */
+ /* Nothing to do */
}
}
else
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
- (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
+ (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
if (cfg->DQSPort != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
- (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+ MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
+ (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
}
if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
}
else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
}
else
{
- /* Nothing to do */
+ /* Nothing to do */
}
if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
- (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+ (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
}
else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
{
- MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
- (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+ MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+ (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
}
else
{
- /* Nothing to do */
+ /* Nothing to do */
}
}
@@ -2723,7 +2735,7 @@
*/
static void OSPI_DMACplt(MDMA_HandleTypeDef *hmdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
hospi->XferCount = 0;
/* Disable the DMA transfer on the OctoSPI side */
@@ -2743,7 +2755,7 @@
*/
static void OSPI_DMAError(MDMA_HandleTypeDef *hmdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
hospi->XferCount = 0;
hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
@@ -2753,23 +2765,23 @@
/* Disable all interrupts */
__HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_ABORT;
+
+ /* Disable the DMA transfer on the DMA side */
+ hospi->hmdma->XferAbortCallback = OSPI_DMAAbortOnError;
+ if (HAL_MDMA_Abort_IT(hospi->hmdma) != HAL_OK)
+ {
/* Update state */
- hospi->State = HAL_OSPI_STATE_ABORT;
+ hospi->State = HAL_OSPI_STATE_READY;
- /* Disable the DMA transfer on the DMA side */
- hospi->hmdma->XferAbortCallback = OSPI_DMAAbortOnError;
- if (HAL_MDMA_Abort_IT(hospi->hmdma) != HAL_OK)
- {
- /* Update state */
- hospi->State = HAL_OSPI_STATE_READY;
-
- /* Error callback */
+ /* Error callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
- hospi->ErrorCallback(hospi);
+ hospi->ErrorCallback(hospi);
#else
- HAL_OSPI_ErrorCallback(hospi);
+ HAL_OSPI_ErrorCallback(hospi);
#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
- }
+ }
}
/**
@@ -2779,24 +2791,24 @@
*/
static void OSPI_DMAAbortOnError(MDMA_HandleTypeDef *hmdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
- /* DMA abort called by OctoSPI abort */
- if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
- {
- /* Clear transfer complete flag */
- __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+ /* DMA abort called by OctoSPI abort */
+ if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
+ {
+ /* Clear transfer complete flag */
+ __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
- /* Enable the transfer complete interrupts */
- __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
+ /* Enable the transfer complete interrupts */
+ __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
- /* Perform an abort of the OctoSPI */
- SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
- }
- else
- {
- /* Update state */
- hospi->State = HAL_OSPI_STATE_READY;
+ /* Perform an abort of the OctoSPI */
+ SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
+ }
+ else
+ {
+ /* Update state */
+ hospi->State = HAL_OSPI_STATE_READY;
/* Error callback */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
@@ -2804,7 +2816,7 @@
#else
HAL_OSPI_ErrorCallback(hospi);
#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
- }
+ }
}
/**
@@ -2814,7 +2826,7 @@
*/
static void OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
{
- OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
+ OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
hospi->XferCount = 0;
/* Check the state */
@@ -2873,12 +2885,12 @@
FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
{
/* Wait until flag is in expected state */
- while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
+ while ((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
- if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
hospi->State = HAL_OSPI_STATE_ERROR;
hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
@@ -2945,7 +2957,7 @@
/* Configure the CCR register with alternate bytes communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
- (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
+ (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
}
/* Configure the TCR register with the number of dummy cycles */
@@ -2972,9 +2984,9 @@
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
- cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
- cmd->DataMode | cmd->DataDtrMode));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
+ cmd->DataMode | cmd->DataDtrMode));
}
else
{
@@ -2983,8 +2995,8 @@
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
- cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
/* The DHQC bit is linked with DDTR bit which should be activated */
if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
@@ -3009,8 +3021,8 @@
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
- cmd->DataMode | cmd->DataDtrMode));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+ cmd->DataMode | cmd->DataDtrMode));
}
else
{
@@ -3018,7 +3030,7 @@
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
- (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
+ (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
/* The DHQC bit is linked with DDTR bit which should be activated */
if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
@@ -3044,8 +3056,8 @@
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
- (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize |
- cmd->DataMode | cmd->DataDtrMode));
+ (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | cmd->DataMode |
+ cmd->DataDtrMode));
}
else
{
@@ -3053,7 +3065,7 @@
/* Configure the CCR register with all communication parameters */
MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
- (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
+ (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
}
/* Configure the AR register with the instruction value */
@@ -3103,7 +3115,7 @@
if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
{
value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
- | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+ | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
}
else
{
@@ -3122,7 +3134,7 @@
if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC))
{
/* The clock correspond to the instance passed as parameter */
- cfg->ClkPort = index+1U;
+ cfg->ClkPort = index + 1U;
}
}
@@ -3132,7 +3144,7 @@
if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC))
{
/* The DQS correspond to the instance passed as parameter */
- cfg->DQSPort = index+1U;
+ cfg->DQSPort = index + 1U;
}
}
@@ -3142,7 +3154,7 @@
if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC))
{
/* The nCS correspond to the instance passed as parameter */
- cfg->NCSPort = index+1U;
+ cfg->NCSPort = index + 1U;
}
}
@@ -3154,11 +3166,11 @@
/* The IO Low correspond to the instance passed as parameter */
if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U)
{
- cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
+ cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
}
else
{
- cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
+ cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
}
}
}
@@ -3171,11 +3183,11 @@
/* The IO High correspond to the instance passed as parameter */
if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U)
{
- cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
+ cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
}
else
{
- cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
+ cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
}
}
}
diff --git a/Src/stm32h7xx_hal_pcd.c b/Src/stm32h7xx_hal_pcd.c
index ae72dcd..221cdfc 100644
--- a/Src/stm32h7xx_hal_pcd.c
+++ b/Src/stm32h7xx_hal_pcd.c
@@ -178,8 +178,12 @@
return HAL_ERROR;
}
- /* Force Device Mode*/
- (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+ /* Force Device Mode */
+ if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
+ {
+ hpcd->State = HAL_PCD_STATE_ERROR;
+ return HAL_ERROR;
+ }
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
@@ -1865,7 +1869,7 @@
* @param ep_addr endpoint address
* @retval Data Size
*/
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
{
return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
}
@@ -2073,7 +2077,7 @@
* @param hpcd PCD handle
* @retval HAL state
*/
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
{
return hpcd->State;
}
@@ -2085,9 +2089,9 @@
* @param testmode USB Device high speed test mode
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode)
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
switch (testmode)
@@ -2189,9 +2193,9 @@
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_EPTypeDef *ep;
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
@@ -2300,9 +2304,9 @@
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
diff --git a/Src/stm32h7xx_hal_pssi.c b/Src/stm32h7xx_hal_pssi.c
index d74efad..7824ebb 100644
--- a/Src/stm32h7xx_hal_pssi.c
+++ b/Src/stm32h7xx_hal_pssi.c
@@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
- * Copyright (c) 2017 STMicroelectronics.
+ * Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
@@ -53,7 +53,6 @@
(#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
(GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
-
(#) For PSSI IO operations, two operation modes are available within this driver :
*** Polling mode IO operation ***
@@ -179,11 +178,12 @@
* @{
*/
/* Private functions to handle DMA transfer */
+#if defined(HAL_DMA_MODULE_ENABLED)
void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
void PSSI_DMAError(DMA_HandleTypeDef *hdma);
void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
-
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Private functions to handle IT transfer */
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
@@ -264,6 +264,7 @@
/* Allocate lock resource and initialize it */
hpssi->Lock = HAL_UNLOCKED;
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Init the PSSI Callback settings */
hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
@@ -277,7 +278,10 @@
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hpssi->MspInitCallback(hpssi);
-
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_PSSI_MspInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
}
hpssi->State = HAL_PSSI_STATE_BUSY;
@@ -320,6 +324,7 @@
/* Disable the PSSI Peripheral Clock */
HAL_PSSI_DISABLE(hpssi);
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
if (hpssi->MspDeInitCallback == NULL)
{
hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
@@ -327,6 +332,10 @@
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
hpssi->MspDeInitCallback(hpssi);
+#else
+ /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+ HAL_PSSI_MspDeInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
hpssi->State = HAL_PSSI_STATE_RESET;
@@ -354,7 +363,7 @@
}
/**
- * @brief DeInitialize the PSSI MSP.
+ * @brief De-Initialize the PSSI MSP.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval None
@@ -364,16 +373,17 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(hpssi);
- /* NOTE : This function should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified; when the callback is needed,
the HAL_PSSI_MspDeInit can be implemented in the user file
*/
}
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User PSSI Callback
* To be used instead of the weak predefined callback
- * @note The HAL_PSSI_RegisterCallback() may be called before HAL_PSSI_Init() in
- * HAL_PSSI_STATE_RESET to register callbacks for HAL_PSSI_MSPINIT_CB_ID
+ * @note The HAL_PSSI_RegisterCallback() may be called before HAL_PSSI_Init() in
+ * HAL_PSSI_STATE_RESET to register callbacks for HAL_PSSI_MSPINIT_CB_ID
* and HAL_PSSI_MSPDEINIT_CB_ID.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
@@ -474,8 +484,8 @@
/**
* @brief Unregister an PSSI Callback
* PSSI callback is redirected to the weak predefined callback
- * @note The HAL_PSSI_UnRegisterCallback() may be called before HAL_PSSI_Init() in
- * HAL_PSSI_STATE_RESET to un-register callbacks for HAL_PSSI_MSPINIT_CB_ID
+ * @note The HAL_PSSI_UnRegisterCallback() may be called before HAL_PSSI_Init() in
+ * HAL_PSSI_STATE_RESET to un-register callbacks for HAL_PSSI_MSPINIT_CB_ID
* and HAL_PSSI_MSPDEINIT_CB_ID.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
@@ -498,27 +508,27 @@
switch (CallbackID)
{
case HAL_PSSI_TX_COMPLETE_CB_ID :
- hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_PSSI_RX_COMPLETE_CB_ID :
- hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_PSSI_ERROR_CB_ID :
- hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */
+ hpssi->ErrorCallback = HAL_PSSI_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_PSSI_ABORT_CB_ID :
- hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_PSSI_MSPINIT_CB_ID :
- hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
+ hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
break;
case HAL_PSSI_MSPDEINIT_CB_ID :
- hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
+ hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
@@ -535,11 +545,11 @@
switch (CallbackID)
{
case HAL_PSSI_MSPINIT_CB_ID :
- hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
+ hpssi->MspInitCallback = HAL_PSSI_MspInit; /* Legacy weak MspInit */
break;
case HAL_PSSI_MSPDEINIT_CB_ID :
- hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
+ hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit */
break;
default :
@@ -563,6 +573,7 @@
return status;
}
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
@@ -639,10 +650,13 @@
HAL_PSSI_DISABLE(hpssi);
/* Configure transfer parameters */
- hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL);
+ MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+ (PSSI_CR_OUTEN_OUTPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
/* DMA Disable */
hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
@@ -696,7 +710,6 @@
/* Increment Buffer pointer */
pbuffer++;
transfer_size -= 2U;
-
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
@@ -722,7 +735,6 @@
pbuffer++;
transfer_size -= 4U;
}
-
}
else
{
@@ -758,7 +770,6 @@
}
}
-
/**
* @brief Receives an amount of data in blocking mode.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -792,11 +803,13 @@
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
/* Configure transfer parameters */
- hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |
- ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL);
+ MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+ (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL)));
+#if defined(HAL_DMA_MODULE_ENABLED)
/* DMA Disable */
hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* Enable the selected PSSI peripheral */
HAL_PSSI_ENABLE(hpssi);
@@ -846,7 +859,6 @@
*pbuffer = *dr;
pbuffer++;
transfer_size -= 2U;
-
}
}
else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
@@ -871,7 +883,6 @@
*pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
pbuffer++;
transfer_size -= 4U;
-
}
}
else
@@ -892,7 +903,6 @@
return HAL_ERROR;
}
-
hpssi->State = HAL_PSSI_STATE_READY;
/* Process Unlocked */
@@ -906,6 +916,7 @@
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -992,8 +1003,6 @@
if (dmaxferstatus == HAL_OK)
{
-
-
/* Update XferCount value */
hpssi->XferCount -= hpssi->XferSize;
@@ -1038,7 +1047,6 @@
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
}
-
return HAL_OK;
}
else
@@ -1088,10 +1096,9 @@
{
if (hpssi->hdmarx != NULL)
{
-
/* Configure BusWidth */
- if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
- {
+ if (hpssi->hdmarx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+ {
MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
}
@@ -1165,7 +1172,6 @@
}
else
{
-
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
@@ -1181,8 +1187,6 @@
}
}
-
-
/**
* @brief Abort a DMA process communication with Interrupt.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1191,7 +1195,6 @@
*/
HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
{
-
/* Process Locked */
__HAL_LOCK(hpssi);
@@ -1206,7 +1209,6 @@
{
if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
{
-
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmatx != NULL)
@@ -1222,12 +1224,10 @@
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
-
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
{
-
hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
if (hpssi->hdmarx != NULL)
@@ -1246,12 +1246,16 @@
}
else
{
+
/* Call the error callback */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
-
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
@@ -1261,14 +1265,14 @@
HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
return HAL_OK;
-
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @}
*/
-/** @defgroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
@@ -1284,13 +1288,12 @@
if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
{
/* Reset handle parameters */
-
hpssi->XferCount = 0U;
/* Disable all interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort DMA TX transfer if any */
if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
{
@@ -1317,7 +1320,6 @@
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
-
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
@@ -1346,10 +1348,15 @@
}
else
{
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Call the corresponding callback to inform upper layer of the error */
hpssi->ErrorCallback(hpssi);
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* If state is an abort treatment on going, don't change state */
if (hpssi->State == HAL_PSSI_STATE_ABORT)
@@ -1359,9 +1366,12 @@
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->AbortCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
else
{
@@ -1370,15 +1380,16 @@
/* Process Unlocked */
__HAL_UNLOCK(hpssi);
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
/* Call the corresponding callback to inform upper layer of End of Transfer */
hpssi->ErrorCallback(hpssi);
-
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
}
}
-
/**
* @brief Tx Transfer complete callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1411,7 +1422,6 @@
*/
}
-
/**
* @brief PSSI error callback.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1469,20 +1479,19 @@
* the configuration information for the specified PSSI.
* @retval HAL state
*/
-HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi)
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi)
{
/* Return PSSI handle state */
return hpssi->State;
}
-
/**
* @brief Return the PSSI error code.
* @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains
* the configuration information for the specified PSSI.
* @retval PSSI Error Code
*/
-uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
+uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi)
{
return hpssi->ErrorCode;
}
@@ -1507,9 +1516,7 @@
*/
static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
{
-
/* Reset handle parameters */
-
hpssi->XferCount = 0U;
/* Set new error code */
@@ -1518,7 +1525,7 @@
/* Disable all interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
-
+#if defined(HAL_DMA_MODULE_ENABLED)
/* Abort DMA TX transfer if any */
if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
{
@@ -1542,7 +1549,6 @@
hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
}
}
-
}
/* Abort DMA RX transfer if any */
else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
@@ -1571,6 +1577,7 @@
/*Nothing to do*/
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/* If state is an abort treatment on going, don't change state */
if (hpssi->State == HAL_PSSI_STATE_ABORT)
@@ -1581,9 +1588,11 @@
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->AbortCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
else
{
@@ -1594,11 +1603,15 @@
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
-
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
+#if defined(HAL_DMA_MODULE_ENABLED)
/**
* @brief DMA PSSI slave transmit process complete callback.
* @param hdma DMA handle
@@ -1611,7 +1624,6 @@
uint32_t tmperror;
-
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
@@ -1633,12 +1645,12 @@
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->TxCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_TxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
-
}
/**
@@ -1653,7 +1665,6 @@
uint32_t tmperror;
-
/* Disable Interrupts */
HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
@@ -1675,11 +1686,12 @@
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->RxCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_RxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
-
}
/**
@@ -1703,16 +1715,23 @@
hpssi->State = HAL_PSSI_STATE_READY;
/* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->AbortCpltCallback(hpssi);
-
+#else
+ HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
else
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
}
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
* @brief This function handles PSSI Communication Timeout.
@@ -1746,6 +1765,8 @@
}
return HAL_OK;
}
+
+#if defined(HAL_DMA_MODULE_ENABLED)
void PSSI_DMAError(DMA_HandleTypeDef *hdma)
{
/* Derogation MISRAC2012-Rule-11.5 */
@@ -1753,7 +1774,6 @@
uint32_t tmperror;
-
/* Disable the selected PSSI peripheral */
HAL_PSSI_DISABLE(hpssi);
@@ -1777,12 +1797,14 @@
__HAL_UNLOCK(hpssi);
/* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
hpssi->ErrorCallback(hpssi);
-
+#else
+ HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
}
-
}
-
+#endif /*HAL_DMA_MODULE_ENABLED*/
/**
diff --git a/Src/stm32h7xx_hal_pwr.c b/Src/stm32h7xx_hal_pwr.c
index aeb9933..4621780 100644
--- a/Src/stm32h7xx_hal_pwr.c
+++ b/Src/stm32h7xx_hal_pwr.c
@@ -567,6 +567,9 @@
assert_param (IS_PWR_REGULATOR (Regulator));
assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Regulator);
+
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
diff --git a/Src/stm32h7xx_hal_pwr_ex.c b/Src/stm32h7xx_hal_pwr_ex.c
index 5d51ceb..4b1a86e 100644
--- a/Src/stm32h7xx_hal_pwr_ex.c
+++ b/Src/stm32h7xx_hal_pwr_ex.c
@@ -2058,8 +2058,11 @@
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
- /* Clear PWR EXTI D1/CD pending bit */
- __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+ if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
+ {
+ /* Clear PWR EXTI D1/CD pending bit */
+ __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+ }
}
}
#if defined (DUAL_CORE)
@@ -2071,8 +2074,11 @@
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback ();
- /* Clear PWR EXTI D2 pending bit */
- __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
+ if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
+ {
+ /* Clear PWR EXTI D2 pending bit */
+ __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
+ }
}
}
#endif /* defined (DUAL_CORE) */
@@ -2091,8 +2097,11 @@
/* PWR AVD interrupt user callback */
HAL_PWREx_AVDCallback ();
- /* Clear PWR EXTI D1/CD pending bit */
- __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+ if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
+ {
+ /* Clear PWR EXTI D1/CD pending bit */
+ __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+ }
}
}
#if defined (DUAL_CORE)
@@ -2104,8 +2113,11 @@
/* PWR AVD interrupt user callback */
HAL_PWREx_AVDCallback ();
- /* Clear PWR EXTI D2 pending bit */
- __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+ if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
+ {
+ /* Clear PWR EXTI D2 pending bit */
+ __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+ }
}
}
#endif /* defined (DUAL_CORE) */
diff --git a/Src/stm32h7xx_hal_qspi.c b/Src/stm32h7xx_hal_qspi.c
index 822b0c9..fc0a603 100644
--- a/Src/stm32h7xx_hal_qspi.c
+++ b/Src/stm32h7xx_hal_qspi.c
@@ -181,7 +181,7 @@
and a pointer to the user callback function.
Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) ErrorCallback : callback when error occurs.
(+) AbortCpltCallback : callback when abort is completed.
(+) FifoThresholdCallback : callback when the fifo threshold is reached.
@@ -195,9 +195,9 @@
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init
+ reset to the legacy weak (overridden) functions in the HAL_QSPI_Init
and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -212,7 +212,7 @@
When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
*** Workarounds linked to Silicon Limitation ***
====================================================
@@ -1900,7 +1900,7 @@
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User QSPI Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hqspi QSPI handle
* @param CallbackId ID of the callback to be registered
* This parameter can be one of the following values:
@@ -2006,7 +2006,7 @@
/**
* @brief Unregister a User QSPI Callback
- * QSPI Callback is redirected to the weak (surcharged) predefined callback
+ * QSPI Callback is redirected to the weak predefined callback
* @param hqspi QSPI handle
* @param CallbackId ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -2130,7 +2130,7 @@
* @param hqspi QSPI handle
* @retval HAL state
*/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi)
{
/* Return QSPI handle state */
return hqspi->State;
@@ -2141,7 +2141,7 @@
* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi)
{
return hqspi->ErrorCode;
}
@@ -2323,7 +2323,7 @@
* @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi)
{
return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
}
diff --git a/Src/stm32h7xx_hal_ramecc.c b/Src/stm32h7xx_hal_ramecc.c
index 0c0116b..2915206 100644
--- a/Src/stm32h7xx_hal_ramecc.c
+++ b/Src/stm32h7xx_hal_ramecc.c
@@ -80,6 +80,31 @@
flag.
(+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected
flag.
+
+ ##### Callback registration #####
+ ==================================
+ [..]
+ (#) The compilation define USE_HAL_RAMECC_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callback.
+
+ [..]
+ (#) Use Function HAL_RAMECC_RegisterCallback() to register a user callback.
+ (#) Function HAL_RAMECC_RegisterCallback() allows to register following callback:
+ (+) RAMECCErrorCode : RAMECC error code detection.
+ (#) This function takes as parameters the HAL peripheral handle
+ and a pointer to the user callback function.
+
+ [..]
+ (#) Use function HAL_RAMECC_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ (#) HAL_RAMECC_UnRegisterCallback() takes as parameters the HAL peripheral handle.
+ (#) This function allows to reset following callback:
+ (+) RAMECCErrorCode : RAMECC error code detection.
+ [..]
+ (#) When The compilation define USE_HAL_RAMECC_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available
+ and weak callbacks are used.
+
@endverbatim
*/
@@ -132,7 +157,7 @@
* Monitor.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc)
{
/* Check the RAMECC peripheral handle */
if (hramecc == NULL)
@@ -163,6 +188,9 @@
/* Initialise the RAMECC error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
+ /* Initialise the RAMECC error detected code */
+ hramecc->RAMECCErrorCode = HAL_RAMECC_NO_ERROR;
+
/* Update the RAMECC state */
hramecc->State = HAL_RAMECC_STATE_READY;
@@ -170,7 +198,6 @@
return HAL_OK;
}
-
/**
* @brief DeInitializes the RAMECC peripheral.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -178,7 +205,7 @@
* Monitor.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc)
{
/* Check the RAMECC peripheral handle */
if (hramecc == NULL)
@@ -203,18 +230,24 @@
/* Clear RAMECC monitor flags */
__HAL_RAMECC_CLEAR_FLAG (hramecc, RAMECC_FLAGS_ALL);
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
/* Clean callback */
hramecc->DetectErrorCallback = NULL;
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
- /* Initialise the RAMECC error code */
+ /* Initialize the RAMECC error code */
hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
+ /* Initialize the RAMECC error detected code */
+ hramecc->RAMECCErrorCode = HAL_RAMECC_NO_ERROR;
+
/* Change RAMECC peripheral state */
hramecc->State = HAL_RAMECC_STATE_RESET;
/* Return HAL status */
return HAL_OK;
}
+
/**
* @}
*/
@@ -242,7 +275,7 @@
* Monitor.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -272,7 +305,6 @@
return HAL_OK;
}
-
/**
* @brief Stop the RAMECC latching error information.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -280,7 +312,7 @@
* Monitor.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -310,7 +342,6 @@
return HAL_OK;
}
-
/**
* @brief Enable the RAMECC error interrupts.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that
@@ -319,7 +350,7 @@
* @param Notifications Select the notification.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
+HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -350,7 +381,6 @@
return HAL_OK;
}
-
/**
* @brief Disable the RAMECC error interrupts.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that
@@ -359,7 +389,7 @@
* @param Notifications Select the notification.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
+HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -390,7 +420,31 @@
return HAL_OK;
}
+/**
+ * @}
+ */
+/** @addtogroup RAMECC_Exported_Functions_Group3
+ *
+@verbatim
+ ===============================================================================
+ ##### Handle Interrupt and Callbacks Functions #####
+ ===============================================================================
+ [..]
+ This section provides functions to handle RAMECC interrupts and
+ Register / UnRegister the different callbacks.
+ [..]
+ The HAL_RAMECC_IRQHandler() function allows the user to handle the active RAMECC
+ interrupt request.
+ The HAL_RAMECC_RegisterCallback() function allows the user to register the selected
+ RAMECC callbacks.
+ The HAL_RAMECC_UnRegisterCallback() function allows the user to unregister the
+ selected RAMECC callbacks.
+@endverbatim
+ * @{
+ */
+
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
/**
* @brief Register callbacks.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -434,7 +488,6 @@
return status;
}
-
/**
* @brief UnRegister callbacks.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -442,7 +495,7 @@
* Monitor.
* @retval HAL status.
*/
-HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -450,7 +503,7 @@
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
/* Check RAMECC state */
- if(hramecc->State == HAL_RAMECC_STATE_READY)
+ if (hramecc->State == HAL_RAMECC_STATE_READY)
{
hramecc->DetectErrorCallback = NULL;
}
@@ -466,7 +519,7 @@
/* Return HAL status */
return status;
}
-
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
/**
* @brief Handles RAMECC interrupt request.
@@ -475,11 +528,11 @@
* Monitor.
* @retval None.
*/
-void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
+void HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc)
{
uint32_t ier_reg = ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER;
uint32_t cr_reg = hramecc->Instance->CR >> 1U;
- uint32_t sr_reg = hramecc->Instance->SR << 1U;
+ uint32_t sr_reg = hramecc->Instance->SR;
/* Update global interrupt variables */
if ((ier_reg & RAMECC_IER_GIE) == RAMECC_IER_GIE)
@@ -487,21 +540,55 @@
ier_reg = RAMECC_IT_GLOBAL_ALL;
}
+ /* Store the ECC Single error detected */
+ if ((sr_reg & RAMECC_SR_SEDCF) == RAMECC_SR_SEDCF)
+ {
+ hramecc->RAMECCErrorCode |= HAL_RAMECC_SINGLEERROR_DETECTED;
+ }
+
+ /* Store the ECC double error detected */
+ if ((sr_reg & (RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)) != 0U)
+ {
+ hramecc->RAMECCErrorCode |= HAL_RAMECC_DOUBLEERROR_DETECTED;
+ }
+
/* Clear active flags */
- __HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & sr_reg) >> 1U));
+ __HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & (sr_reg << 1U)) >> 1U));
/* Check if a valid double error callback is registered */
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
+ /* Check if a valid error callback is registered */
if (hramecc->DetectErrorCallback != NULL)
{
/* Error detection callback */
hramecc->DetectErrorCallback(hramecc);
}
+#else
+ HAL_RAMECC_DetectErrorCallback(hramecc);
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
}
+
+/**
+ * @brief RAMECC error detection callback.
+ * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains
+ * the configuration information for the specified RAMECC.
+ * @retval None.
+ */
+__weak void HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hramecc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_RAMECC_DetectDoubleErrorCallback can be implemented in
+ the user file. */
+}
+
/**
* @}
*/
-/** @addtogroup RAMECC_Exported_Functions_Group3
+/** @addtogroup RAMECC_Exported_Functions_Group4
*
@verbatim
===============================================================================
@@ -526,7 +613,7 @@
* Monitor.
* @retval Failing address offset.
*/
-uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -535,7 +622,6 @@
return hramecc->Instance->FAR;
}
-
/**
* @brief Return the RAMECC data low.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -543,7 +629,7 @@
* Monitor.
* @retval Failing data low.
*/
-uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -552,7 +638,6 @@
return hramecc->Instance->FDRL;
}
-
/**
* @brief Return the RAMECC data high.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -560,7 +645,7 @@
* Monitor.
* @retval Failing data high.
*/
-uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -569,7 +654,6 @@
return hramecc->Instance->FDRH;
}
-
/**
* @brief Return the RAMECC Hamming bits injected.
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -577,7 +661,7 @@
* Monitor.
* @retval Hamming bits injected.
*/
-uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -593,7 +677,7 @@
* Monitor.
* @retval State of bit (1 or 0).
*/
-uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -609,7 +693,7 @@
* Monitor.
* @retval State of bit (1 or 0).
*/
-uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc)
{
/* Check the parameters */
assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -617,12 +701,12 @@
/* Return the state of DEDF | DEBWDF flags */
return ((READ_BIT(hramecc->Instance->SR, (RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)) != 0U) ? 1UL : 0UL);
}
+
/**
* @}
*/
-
-/** @addtogroup RAMECC_Exported_Functions_Group4
+/** @addtogroup RAMECC_Exported_Functions_Group5
*
@verbatim
===============================================================================
@@ -636,6 +720,8 @@
state.
The HAL_RAMECC_GetError() function allows to Get the RAMECC peripheral error
code.
+ The HAL_RAMECC_GetRAMECCError() function allows to Get the RAMECC error code
+ detected.
@endverbatim
* @{
@@ -648,7 +734,7 @@
* specified RAMECC instance.
* @retval RAMECC state.
*/
-HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
+HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc)
{
/* Return the RAMECC state */
return hramecc->State;
@@ -661,14 +747,24 @@
* specified RAMECC instance.
* @retval RAMECC error code.
*/
-uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc)
{
/* Return the RAMECC error code */
return hramecc->ErrorCode;
}
+
/**
- * @}
+ * @brief Get the RAMECC error code detected.
+ * @param hramecc : Pointer to a RAMECC_HandleTypeDef structure that
+ * contains the configuration information for the
+ * specified RAMECC instance.
+ * @retval RAMECC error code detected.
*/
+uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc)
+{
+ /* Return the RAMECC error code detected*/
+ return hramecc->RAMECCErrorCode;
+}
/**
* @}
@@ -681,4 +777,3 @@
/**
* @}
*/
-
diff --git a/Src/stm32h7xx_hal_rng.c b/Src/stm32h7xx_hal_rng.c
index 76d1601..ef60299 100644
--- a/Src/stm32h7xx_hal_rng.c
+++ b/Src/stm32h7xx_hal_rng.c
@@ -52,7 +52,7 @@
[..]
Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak (overridden) function.
HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -66,10 +66,10 @@
[..]
By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak (overridden) functions:
example HAL_RNG_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_RNG_Init()
+ reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -86,7 +86,7 @@
[..]
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -213,7 +213,6 @@
/* Clock Error Detection Configuration when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
-
#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/*!< magic number must be written immediately before to RNG_HTCRG */
WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
@@ -709,8 +708,6 @@
/* Update the error code and status */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
status = HAL_ERROR;
- /* Clear bit DRDY */
- CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
}
else /* No seed error */
{
@@ -792,18 +789,19 @@
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
uint32_t rngclockerror = 0U;
+ uint32_t itflag = hrng->Instance->SR;
/* RNG clock error interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+ if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
{
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U;
}
- else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
{
/* Check if Seed Error Current Status (SECS) is set */
- if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS)
{
/* RNG IP performed the reset automatically (auto-reset) */
/* Clear bit SEIS */
@@ -843,7 +841,7 @@
}
/* Check RNG data ready interrupt occurred */
- if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+ if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
@@ -875,7 +873,7 @@
* the configuration information for RNG.
* @retval random value
*/
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng)
{
return (hrng->RandomNumber);
}
@@ -942,7 +940,7 @@
* the configuration information for RNG.
* @retval HAL state
*/
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng)
{
return hrng->State;
}
@@ -952,7 +950,7 @@
* @param hrng: pointer to a RNG_HandleTypeDef structure.
* @retval RNG Error Code
*/
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng)
{
/* Return RNG Error Code */
return hrng->ErrorCode;
diff --git a/Src/stm32h7xx_hal_rng_ex.c b/Src/stm32h7xx_hal_rng_ex.c
index 97190ac..70c5540 100644
--- a/Src/stm32h7xx_hal_rng_ex.c
+++ b/Src/stm32h7xx_hal_rng_ex.c
@@ -66,11 +66,11 @@
/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RNG_Ex_Exported_Functions
+/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
* @{
*/
-/** @addtogroup RNG_Ex_Exported_Functions_Group1
+/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions
* @brief Configuration functions
*
@verbatim
@@ -90,12 +90,12 @@
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * @param pConf pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf)
{
uint32_t tickstart;
uint32_t cr_value;
@@ -189,7 +189,7 @@
* RNG_ConfigTypeDef.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param pConf: pointer to a RNG_ConfigTypeDef structure that contains
+ * @param pConf pointer to a RNG_ConfigTypeDef structure that contains
* the configuration information for RNG module
* @retval HAL status
@@ -283,12 +283,12 @@
* @}
*/
-/** @addtogroup RNG_Ex_Exported_Functions_Group2
+/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function
* @brief Recover from seed error function
*
@verbatim
===============================================================================
- ##### Configuration and lock functions #####
+ ##### Recover from seed error function #####
===============================================================================
[..] This section provide function allowing to:
(+) Recover from a seed error
diff --git a/Src/stm32h7xx_hal_sai.c b/Src/stm32h7xx_hal_sai.c
index 25dcd56..6a11433 100644
--- a/Src/stm32h7xx_hal_sai.c
+++ b/Src/stm32h7xx_hal_sai.c
@@ -172,7 +172,7 @@
[..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
@@ -187,10 +187,10 @@
[..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ all callbacks are reset to the corresponding legacy weak functions:
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ reset to the legacy weak functions in the HAL_SAI_Init
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -207,7 +207,7 @@
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
*/
diff --git a/Src/stm32h7xx_hal_sdram.c b/Src/stm32h7xx_hal_sdram.c
index ee80dac..8859a08 100644
--- a/Src/stm32h7xx_hal_sdram.c
+++ b/Src/stm32h7xx_hal_sdram.c
@@ -82,15 +82,15 @@
and a pointer to the user callback function.
Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : SDRAM MspInit.
(+) MspDeInitCallback : SDRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
+ reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -105,7 +105,7 @@
When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -793,7 +793,7 @@
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SDRAM Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsdram : SDRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -814,9 +814,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsdram);
-
state = hsdram->State;
if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
@@ -859,14 +856,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsdram);
return status;
}
/**
* @brief Unregister a User SDRAM Callback
- * SDRAM Callback is redirected to the weak (surcharged) predefined callback
+ * SDRAM Callback is redirected to the weak predefined callback
* @param hsdram : SDRAM handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -882,9 +877,6 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SDRAM_StateTypeDef state;
- /* Process locked */
- __HAL_LOCK(hsdram);
-
state = hsdram->State;
if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
@@ -933,14 +925,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsdram);
return status;
}
/**
* @brief Register a User SDRAM Callback for DMA transfers
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsdram : SDRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
diff --git a/Src/stm32h7xx_hal_smartcard.c b/Src/stm32h7xx_hal_smartcard.c
index c248622..4641fc2 100644
--- a/Src/stm32h7xx_hal_smartcard.c
+++ b/Src/stm32h7xx_hal_smartcard.c
@@ -136,7 +136,7 @@
[..]
Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -153,10 +153,10 @@
[..]
By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ reset to the legacy weak functions in the HAL_SMARTCARD_Init()
and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -173,7 +173,7 @@
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -467,7 +467,7 @@
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SMARTCARD Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
* in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
* and HAL_SMARTCARD_MSPDEINIT_CB_ID
diff --git a/Src/stm32h7xx_hal_smbus.c b/Src/stm32h7xx_hal_smbus.c
index 0aec996..f821427 100644
--- a/Src/stm32h7xx_hal_smbus.c
+++ b/Src/stm32h7xx_hal_smbus.c
@@ -926,7 +926,7 @@
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
- uint32_t sizetoxfer = 0U;
+ uint32_t sizetoxfer;
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -960,20 +960,27 @@
}
sizetoxfer = hsmbus->XferSize;
- if ((hsmbus->XferSize > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
- (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
- (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
- (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
+ if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
+ (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
{
- /* Preload TX register */
- /* Write data to TXDR */
- hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+ if (hsmbus->pBuffPtr != NULL)
+ {
+ /* Preload TX register */
+ /* Write data to TXDR */
+ hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
- /* Increment Buffer pointer */
- hsmbus->pBuffPtr++;
+ /* Increment Buffer pointer */
+ hsmbus->pBuffPtr++;
- hsmbus->XferCount--;
- hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ hsmbus->XferSize--;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
/* Send Slave Address */
@@ -1014,8 +1021,15 @@
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
{
- hsmbus->XferSize--;
- hsmbus->XferCount--;
+ if (hsmbus->XferSize > 0U)
+ {
+ hsmbus->XferSize--;
+ hsmbus->XferCount--;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
}
@@ -2605,8 +2619,11 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Flush TX register */
- SMBUS_Flush_TXDR(hsmbus);
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+ }
/* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
diff --git a/Src/stm32h7xx_hal_spdifrx.c b/Src/stm32h7xx_hal_spdifrx.c
index 7bef68a..bf61ef9 100644
--- a/Src/stm32h7xx_hal_spdifrx.c
+++ b/Src/stm32h7xx_hal_spdifrx.c
@@ -33,10 +33,12 @@
(##) SPDIFRX pins configuration:
(+++) Enable the clock for the SPDIFRX GPIOs.
(+++) Configure these SPDIFRX pins as alternate function pull-up.
- (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
+ (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and
+ HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
(+++) Configure the SPDIFRX interrupt priority.
(+++) Enable the NVIC SPDIFRX IRQ handle.
- (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's).
+ (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and
+ HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's).
(+++) Declare a DMA handle structure for the reception of the Data Flow channel.
(+++) Declare a DMA handle structure for the reception of the Control Flow channel.
(+++) Enable the DMAx interface clock.
@@ -46,8 +48,8 @@
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
DMA CtrlRx/DataRx channel.
- (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
- using HAL_SPDIFRX_Init() function.
+ (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format,
+ stereo mode and masking of user bits using HAL_SPDIFRX_Init() function.
-@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
__SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
@@ -90,7 +92,7 @@
=============================================
[..]
Below the list of most used macros in SPDIFRX HAL driver.
- (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
+ (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDLE State)
(+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
(+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
(+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
@@ -173,8 +175,13 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-#define SPDIFRX_TIMEOUT_VALUE 0xFFFFU
-
+/** @defgroup SPDIFRX_Private_Defines SPDIFRX Private Defines
+ * @{
+ */
+#define SPDIFRX_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -900,7 +907,8 @@
{
if (count == 0U)
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+ process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -985,7 +993,8 @@
{
if (count == 0U)
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+ process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -1059,7 +1068,8 @@
hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) !=
+ HAL_OK)
{
/* Set SPDIFRX error */
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
@@ -1086,7 +1096,8 @@
{
if (count == 0U)
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+ process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -1160,7 +1171,8 @@
hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
/* Enable the DMA request */
- if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK)
+ if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) !=
+ HAL_OK)
{
/* Set SPDIFRX error */
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
@@ -1187,7 +1199,8 @@
{
if (count == 0U)
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+ process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -1236,8 +1249,14 @@
hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
/* Disable the SPDIFRX DMA channel */
- __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
- __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+ if (hspdif->hdmaDrRx != NULL)
+ {
+ __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
+ }
+ if (hspdif->hdmaCsRx != NULL)
+ {
+ __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+ }
/* Disable SPDIFRX peripheral */
__HAL_SPDIFRX_IDLE(hspdif);
@@ -1590,8 +1609,8 @@
* @param tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status,
- uint32_t Timeout, uint32_t tickstart)
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag,
+ FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
{
/* Wait until flag is set */
while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
@@ -1601,7 +1620,8 @@
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+ process */
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
__HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
diff --git a/Src/stm32h7xx_hal_spi.c b/Src/stm32h7xx_hal_spi.c
index 5e38d94..932eb3f 100644
--- a/Src/stm32h7xx_hal_spi.c
+++ b/Src/stm32h7xx_hal_spi.c
@@ -111,9 +111,8 @@
using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
or HAL_SPI_Init() function.
- When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined,
+ the callback registering feature is not available and weak callbacks are used.
SuspendCallback restriction:
SuspendCallback is called only when MasterReceiverAutoSusp is enabled and
@@ -152,7 +151,6 @@
* @{
*/
#define SPI_DEFAULT_TIMEOUT 100UL
-#define MAX_FIFO_LENGTH 16UL
/**
* @}
*/
@@ -173,8 +171,8 @@
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
- uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag,
+ FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart);
static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
@@ -183,7 +181,7 @@
static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
-static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
+static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi);
/**
@@ -242,6 +240,9 @@
{
uint32_t crc_length;
uint32_t packet_length;
+#if (USE_SPI_CRC != 0UL)
+ uint32_t crc_poly_msb_mask;
+#endif /* USE_SPI_CRC */
/* Check the SPI handle allocation */
if (hspi == NULL)
@@ -311,6 +312,9 @@
crc_length = hspi->Init.CRCLength;
}
+ /* Verify the correctness of polynom size */
+ assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length));
+
/* Verify that the CRC Length is higher than DataSize */
if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
{
@@ -427,15 +431,21 @@
if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT)))
{
+ /* Set SPI_CR1_CRC33_17 bit */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+ /* Write CRC polynomial in SPI Register */
+ WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
}
else
{
+ /* Clear SPI_CR1_CRC33_17 bit */
CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
- }
- /* Write CRC polynomial in SPI Register */
- WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
+ /* Write CRC polynomial and set MSB bit at 1 in SPI Register */
+ /* Set MSB is mandatory for a correct CRC computation */
+ crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U));
+ WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask);
+ }
}
#endif /* USE_SPI_CRC */
@@ -554,6 +564,8 @@
* the configuration information for the specified SPI.
* @param CallbackID ID of the callback to be registered
* @param pCallback pointer to the Callback function
+ * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
+ * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
@@ -568,8 +580,6 @@
return HAL_ERROR;
}
- /* Lock the process */
- __HAL_LOCK(hspi);
if (HAL_SPI_STATE_READY == hspi->State)
{
@@ -658,8 +668,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hspi);
return status;
}
@@ -669,15 +677,14 @@
* @param hspi Pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI.
* @param CallbackID ID of the callback to be unregistered
+ * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
+ * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
{
HAL_StatusTypeDef status = HAL_OK;
- /* Lock the process */
- __HAL_LOCK(hspi);
-
if (HAL_SPI_STATE_READY == hspi->State)
{
switch (CallbackID)
@@ -765,8 +772,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hspi);
return status;
}
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
@@ -823,31 +828,26 @@
#endif /* __GNUC__ */
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -905,11 +905,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -949,11 +950,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -998,11 +1000,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -1018,16 +1021,19 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- hspi->State = HAL_SPI_STATE_READY;
-
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
return HAL_ERROR;
}
- return errorcode;
+ else
+ {
+ return HAL_OK;
+ }
}
/**
@@ -1042,7 +1048,9 @@
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
- HAL_StatusTypeDef errorcode = HAL_OK;
+ uint32_t temp_sr_reg;
+ uint16_t init_max_data_in_fifo;
+ init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
#if defined (__GNUC__)
__IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
#endif /* __GNUC__ */
@@ -1050,26 +1058,22 @@
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1112,8 +1116,18 @@
/* Transfer loop */
while (hspi->RxXferCount > 0UL)
{
- /* Check the RXWNE/EOT flag */
- if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL)
+ /* Evaluate state of SR register */
+ temp_sr_reg = hspi->Instance->SR;
+
+ /* Check the RXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount--;
+ }
+ /* Check RXWNE flag if RXP cannot be reached */
+ else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
{
*((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
hspi->pRxBuffPtr += sizeof(uint32_t);
@@ -1127,11 +1141,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -1143,6 +1158,9 @@
/* Transfer loop */
while (hspi->RxXferCount > 0UL)
{
+ /* Evaluate state of SR register */
+ temp_sr_reg = hspi->Instance->SR;
+
/* Check the RXP flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
{
@@ -1154,6 +1172,34 @@
hspi->pRxBuffPtr += sizeof(uint16_t);
hspi->RxXferCount--;
}
+ /* Check RXWNE flag if RXP cannot be reached */
+ else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ }
+ /* Check RXPLVL flags when RXWNE cannot be reached */
+ else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ }
else
{
/* Timeout management */
@@ -1162,11 +1208,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -1178,6 +1225,9 @@
/* Transfer loop */
while (hspi->RxXferCount > 0UL)
{
+ /* Evaluate state of SR register */
+ temp_sr_reg = hspi->Instance->SR;
+
/* Check the RXP flag */
if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
{
@@ -1185,6 +1235,26 @@
hspi->pRxBuffPtr += sizeof(uint8_t);
hspi->RxXferCount--;
}
+ /* Check RXWNE flag if RXP cannot be reached */
+ else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount -= (uint16_t)4UL;
+ }
+ /* Check RXPLVL flags when RXWNE cannot be reached */
+ else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ }
else
{
/* Timeout management */
@@ -1193,11 +1263,12 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
return HAL_TIMEOUT;
}
}
@@ -1218,16 +1289,20 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- hspi->State = HAL_SPI_STATE_READY;
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
return HAL_ERROR;
}
- return errorcode;
+ else
+ {
+ return HAL_OK;
+ }
}
/**
@@ -1243,22 +1318,22 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
#if defined (__GNUC__)
__IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
__IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
#endif /* __GNUC__ */
uint32_t tickstart;
+ uint32_t fifo_length;
+ uint32_t temp_sr_reg;
uint16_t initial_TxXferCount;
uint16_t initial_RxXferCount;
+ uint16_t init_max_data_in_fifo;
+ init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -1267,18 +1342,17 @@
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1296,6 +1370,16 @@
/* Set Full-Duplex mode */
SPI_2LINES(hspi);
+ /* Initialize FIFO length */
+ if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
+ {
+ fifo_length = SPI_HIGHEND_FIFO_SIZE;
+ }
+ else
+ {
+ fifo_length = SPI_LOWEND_FIFO_SIZE;
+ }
+
/* Set the number of data at current transfer */
MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
@@ -1310,10 +1394,14 @@
/* Transmit and Receive data in 32 Bit mode */
if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
{
+ /* Adapt fifo length to 32bits data width */
+ fifo_length = (fifo_length / 4UL);
+
while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
{
/* Check TXP flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+ (initial_RxXferCount < (initial_TxXferCount + fifo_length)))
{
*((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint32_t);
@@ -1321,37 +1409,58 @@
initial_TxXferCount = hspi->TxXferCount;
}
- /* Check RXWNE/EOT flag */
- if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL))
+ /* Evaluate state of SR register */
+ temp_sr_reg = hspi->Instance->SR;
+
+ if (initial_RxXferCount > 0UL)
{
- *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint32_t);
- hspi->RxXferCount --;
- initial_RxXferCount = hspi->RxXferCount;
- }
+ /* Check the RXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ /* Check RXWNE flag if RXP cannot be reached */
+ else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+ {
+ *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint32_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
- /* Unlock the process */
- __HAL_UNLOCK(hspi);
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
}
}
}
/* Transmit and Receive data in 16 Bit mode */
else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
{
+ /* Adapt fifo length to 16bits data width */
+ fifo_length = (fifo_length / 2UL);
+
while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
{
/* Check the TXP flag */
- if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+ (initial_RxXferCount < (initial_TxXferCount + fifo_length)))
{
#if defined (__GNUC__)
*ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
@@ -1363,31 +1472,70 @@
initial_TxXferCount = hspi->TxXferCount;
}
- /* Check the RXP flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL))
+ /* Evaluate state of SR register */
+ temp_sr_reg = hspi->Instance->SR;
+
+ if (initial_RxXferCount > 0UL)
{
+ /* Check the RXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+ {
#if defined (__GNUC__)
- *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
#else
- *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
#endif /* __GNUC__ */
- hspi->pRxBuffPtr += sizeof(uint16_t);
- hspi->RxXferCount--;
- initial_RxXferCount = hspi->RxXferCount;
- }
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ /* Check RXWNE flag if RXP cannot be reached */
+ else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount -= (uint16_t)2UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ /* Check RXPLVL flags when RXWNE cannot be reached */
+ else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
+ {
+#if defined (__GNUC__)
+ *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+ *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
- /* Unlock the process */
- __HAL_UNLOCK(hspi);
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
}
}
}
@@ -1397,7 +1545,8 @@
while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
{
/* Check the TXP flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+ (initial_RxXferCount < (initial_TxXferCount + fifo_length)))
{
*((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
hspi->pTxBuffPtr += sizeof(uint8_t);
@@ -1405,27 +1554,58 @@
initial_TxXferCount = hspi->TxXferCount;
}
- /* Check the RXP flag */
- if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL))
+ /* Evaluate state of SR register */
+ temp_sr_reg = hspi->Instance->SR;
+
+ if (initial_RxXferCount > 0UL)
{
- *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
- hspi->pRxBuffPtr += sizeof(uint8_t);
- hspi->RxXferCount--;
- initial_RxXferCount = hspi->RxXferCount;
- }
+ /* Check the RXP flag */
+ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ /* Check RXWNE flag if RXP cannot be reached */
+ else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount -= (uint16_t)4UL;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ /* Check RXPLVL flags when RXWNE cannot be reached */
+ else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
+ {
+ *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+ hspi->pRxBuffPtr += sizeof(uint8_t);
+ hspi->RxXferCount--;
+ initial_RxXferCount = hspi->RxXferCount;
+ }
+ else
+ {
+ /* Timeout management */
+ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+ {
+ /* Call standard close procedure with error check */
+ SPI_CloseTransfer(hspi);
- /* Timeout management */
- if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
- {
- /* Call standard close procedure with error check */
- SPI_CloseTransfer(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+ hspi->State = HAL_SPI_STATE_READY;
- /* Unlock the process */
- __HAL_UNLOCK(hspi);
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
- hspi->State = HAL_SPI_STATE_READY;
- return HAL_TIMEOUT;
+ return HAL_TIMEOUT;
+ }
+ }
}
}
}
@@ -1439,16 +1619,19 @@
/* Call standard close procedure with error check */
SPI_CloseTransfer(hspi);
+ hspi->State = HAL_SPI_STATE_READY;
+
/* Unlock the process */
__HAL_UNLOCK(hspi);
- hspi->State = HAL_SPI_STATE_READY;
-
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
return HAL_ERROR;
}
- return errorcode;
+ else
+ {
+ return HAL_OK;
+ }
}
/**
@@ -1461,28 +1644,22 @@
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
if ((pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1496,6 +1673,12 @@
hspi->RxXferCount = (uint16_t) 0UL;
hspi->RxISR = NULL;
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ hspi->Reload.Requested = 0UL;
+ hspi->Reload.pTxBuffPtr = NULL;
+ hspi->Reload.TxXferSize = NULL;
+#endif /* USE_SPI_RELOAD_TRANSFER */
+
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
{
@@ -1526,6 +1709,9 @@
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
/* Enable EOT, TXP, FRE, MODF, UDR and TSERF interrupts */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
@@ -1535,8 +1721,7 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1549,28 +1734,22 @@
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1584,6 +1763,12 @@
hspi->TxXferCount = (uint16_t) 0UL;
hspi->TxISR = NULL;
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ hspi->Reload.Requested = 0UL;
+ hspi->Reload.pRxBuffPtr = NULL;
+ hspi->Reload.RxXferSize = NULL;
+#endif /* USE_SPI_RELOAD_TRANSFER */
+
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
{
@@ -1618,6 +1803,9 @@
/* Enable SPI peripheral */
__HAL_SPI_ENABLE(hspi);
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
/* Enable EOT, RXP, OVR, FRE, MODF and TSERF interrupts */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
@@ -1627,9 +1815,7 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- /* Unlock the process */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
/**
@@ -1644,9 +1830,7 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
uint32_t tmp_TxXferCount;
-
#if defined (__GNUC__)
__IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
#endif /* __GNUC__ */
@@ -1654,23 +1838,19 @@
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -1682,6 +1862,14 @@
hspi->RxXferCount = Size;
tmp_TxXferCount = hspi->TxXferCount;
+#if defined(USE_SPI_RELOAD_TRANSFER)
+ hspi->Reload.Requested = 0UL;
+ hspi->Reload.pRxBuffPtr = NULL;
+ hspi->Reload.RxXferSize = NULL;
+ hspi->Reload.pTxBuffPtr = NULL;
+ hspi->Reload.TxXferSize = NULL;
+#endif /* USE_SPI_RELOAD_TRANSFER */
+
/* Set the function for IT treatment */
if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
{
@@ -1741,6 +1929,9 @@
}
}
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
/* Enable EOT, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR |
SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
@@ -1751,9 +1942,7 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
}
- /* Unlock the process */
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_OK;
}
#if defined(USE_SPI_RELOAD_TRANSFER)
@@ -1767,28 +1956,16 @@
*/
HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
- HAL_SPI_StateTypeDef tmp_state;
-
- /* Lock the process */
- __HAL_LOCK(hspi);
-
- if ((pData == NULL) || (Size == 0UL))
+ /* check if there is already a request to reload */
+ if ((hspi->Reload.Requested == 1UL) || (pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
if (hspi->State == HAL_SPI_STATE_BUSY_TX)
{
- /* check if there is already a request to reload */
- if (hspi->Reload.Requested == 1UL)
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
+ /* Lock the process */
+ __HAL_LOCK(hspi);
/* Insert the new number of data to be sent just after the current one */
MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
@@ -1798,27 +1975,15 @@
hspi->Reload.pTxBuffPtr = (const uint8_t *)pData;
hspi->Reload.TxXferSize = Size;
- tmp_state = hspi->State;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
- /* Check if the current transmit is already completed */
- if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
- {
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
- hspi->Reload.Requested = 0UL;
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
+ return HAL_OK;
}
else
{
- errorcode = HAL_ERROR;
- return errorcode;
+ return HAL_ERROR;
}
-
- __HAL_UNLOCK(hspi);
- return errorcode;
}
#endif /* USE_SPI_RELOAD_TRANSFER */
@@ -1833,28 +1998,16 @@
*/
HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
- HAL_SPI_StateTypeDef tmp_state;
-
- /* Lock the process */
- __HAL_LOCK(hspi);
-
- if ((pData == NULL) || (Size == 0UL))
+ /* check if there is already a request to reload */
+ if ((hspi->Reload.Requested == 1UL) || (pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
if (hspi->State == HAL_SPI_STATE_BUSY_RX)
{
- /* check if there is already a request to reload */
- if (hspi->Reload.Requested == 1UL)
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
+ /* Lock the process */
+ __HAL_LOCK(hspi);
/* Insert the new number of data that will be received just after the current one */
MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
@@ -1864,27 +2017,15 @@
hspi->Reload.pRxBuffPtr = (uint8_t *)pData;
hspi->Reload.RxXferSize = Size;
- tmp_state = hspi->State;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
- /* Check if the current reception is already completed */
- if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
- {
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
- hspi->Reload.Requested = 0UL;
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
+ return HAL_OK;
}
else
{
- errorcode = HAL_ERROR;
- return errorcode;
+ return HAL_ERROR;
}
-
- __HAL_UNLOCK(hspi);
- return errorcode;
}
#endif /* USE_SPI_RELOAD_TRANSFER */
@@ -1901,28 +2042,16 @@
HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData,
uint8_t *pRxData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
- HAL_SPI_StateTypeDef tmp_state;
-
- /* Lock the process */
- __HAL_LOCK(hspi);
-
- if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+ /* check if there is already a request to reload */
+ if ((hspi->Reload.Requested == 1UL) || (pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
if (hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
{
- /* check if there is already a request to reload */
- if (hspi->Reload.Requested == 1UL)
- {
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
+ /* Lock the process */
+ __HAL_LOCK(hspi);
/* Insert the new number of data that will be sent and received just after the current one */
MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
@@ -1934,27 +2063,15 @@
hspi->Reload.pRxBuffPtr = (uint8_t *)pRxData;
hspi->Reload.RxXferSize = Size;
- tmp_state = hspi->State;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
- /* Check if the current transmit is already completed */
- if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
- {
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
- MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
- hspi->Reload.Requested = 0UL;
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
- }
+ return HAL_OK;
}
else
{
- errorcode = HAL_ERROR;
- return errorcode;
+ return HAL_ERROR;
}
-
- __HAL_UNLOCK(hspi);
- return errorcode;
}
#endif /* USE_SPI_RELOAD_TRANSFER */
@@ -1968,28 +2085,23 @@
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -2020,9 +2132,8 @@
(hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
{
/* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
__HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
/* Adjust XferCount according to DMA alignment / Data size */
@@ -2070,13 +2181,12 @@
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
/* Unlock the process */
__HAL_UNLOCK(hspi);
- hspi->State = HAL_SPI_STATE_READY;
- errorcode = HAL_ERROR;
- return errorcode;
+ return HAL_ERROR;
}
/* Set the number of data at current transfer */
@@ -2106,7 +2216,8 @@
/* Unlock the process */
__HAL_UNLOCK(hspi);
- return errorcode;
+
+ return HAL_OK;
}
/**
@@ -2120,28 +2231,26 @@
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
__HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
__HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -2171,9 +2280,8 @@
(hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
{
/* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
__HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
/* Clear RXDMAEN bit */
@@ -2221,13 +2329,12 @@
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
/* Unlock the process */
__HAL_UNLOCK(hspi);
- hspi->State = HAL_SPI_STATE_READY;
- errorcode = HAL_ERROR;
- return errorcode;
+ return HAL_ERROR;
}
/* Set the number of data at current transfer */
@@ -2257,7 +2364,8 @@
/* Unlock the process */
__HAL_UNLOCK(hspi);
- return errorcode;
+
+ return HAL_OK;
}
/**
@@ -2273,28 +2381,22 @@
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size)
{
- HAL_StatusTypeDef errorcode = HAL_OK;
-
/* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
- /* Lock the process */
- __HAL_LOCK(hspi);
-
if (hspi->State != HAL_SPI_STATE_READY)
{
- errorcode = HAL_BUSY;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_BUSY;
}
if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
{
- errorcode = HAL_ERROR;
- __HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
+ /* Lock the process */
+ __HAL_LOCK(hspi);
+
/* Set the transaction information */
hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
@@ -2321,10 +2423,9 @@
(hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
{
/* Restriction the DMA data received is not allowed in this mode */
- errorcode = HAL_ERROR;
/* Unlock the process */
__HAL_UNLOCK(hspi);
- return errorcode;
+ return HAL_ERROR;
}
/* Adjust XferCount according to DMA alignment / Data size */
@@ -2379,13 +2480,12 @@
{
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
/* Unlock the process */
__HAL_UNLOCK(hspi);
- hspi->State = HAL_SPI_STATE_READY;
- errorcode = HAL_ERROR;
- return errorcode;
+ return HAL_ERROR;
}
/* Enable Rx DMA Request */
@@ -2404,17 +2504,17 @@
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
hspi->TxXferCount))
{
- HAL_DMA_Abort(hspi->hdmarx);
+ /* Abort Rx DMA Channel already started */
+ (void)HAL_DMA_Abort(hspi->hdmarx);
/* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
/* Unlock the process */
__HAL_UNLOCK(hspi);
- hspi->State = HAL_SPI_STATE_READY;
- errorcode = HAL_ERROR;
- return errorcode;
+ return HAL_ERROR;
}
if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
@@ -2443,7 +2543,8 @@
/* Unlock the process */
__HAL_UNLOCK(hspi);
- return errorcode;
+
+ return HAL_OK;
}
/**
@@ -2488,8 +2589,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
+ } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
/* Request a Suspend transfer */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
@@ -2501,8 +2601,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
/* Clear SUSP flag */
__HAL_SPI_CLEAR_SUSPFLAG(hspi);
@@ -2514,8 +2613,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
+ } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
}
/* Disable the SPI DMA Tx request if enabled */
@@ -2571,12 +2669,12 @@
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
}
- /* Unlock the process */
- __HAL_UNLOCK(hspi);
-
/* Restore hspi->state to ready */
hspi->State = HAL_SPI_STATE_READY;
+ /* Unlock the process */
+ __HAL_UNLOCK(hspi);
+
return errorcode;
}
@@ -2622,8 +2720,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
+ } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
/* Request a Suspend transfer */
SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
@@ -2635,8 +2732,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
/* Clear SUSP flag */
__HAL_SPI_CLEAR_SUSPFLAG(hspi);
@@ -2648,8 +2744,7 @@
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
break;
}
- }
- while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
+ } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
}
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
@@ -2845,7 +2940,6 @@
/* SPI Reload -------------------------------------------------*/
if (HAL_IS_BIT_SET(trigger, SPI_FLAG_TSERF))
{
- hspi->Reload.Requested = 0UL;
__HAL_SPI_CLEAR_TSERFFLAG(hspi);
}
#endif /* USE_SPI_RELOAD_TRANSFER */
@@ -3042,7 +3136,7 @@
* the configuration information for SPI module.
* @retval None
*/
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3058,7 +3152,7 @@
* the configuration information for SPI module.
* @retval None
*/
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3074,7 +3168,7 @@
* the configuration information for SPI module.
* @retval None
*/
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3090,7 +3184,7 @@
* the configuration information for SPI module.
* @retval None
*/
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3106,7 +3200,7 @@
* the configuration information for SPI module.
* @retval None
*/
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3122,7 +3216,7 @@
* the configuration information for SPI module.
* @retval None
*/
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3138,7 +3232,7 @@
* the configuration information for SPI module.
* @retval None
*/
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3156,7 +3250,7 @@
* @param hspi SPI handle.
* @retval None
*/
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3171,7 +3265,7 @@
* @param hspi SPI handle.
* @retval None
*/
-__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
@@ -3327,9 +3421,10 @@
* the configuration information for the specified DMA module.
* @retval None
*/
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+ ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
hspi->TxHalfCpltCallback(hspi);
@@ -3344,9 +3439,10 @@
* the configuration information for the specified DMA module.
* @retval None
*/
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+ ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
hspi->RxHalfCpltCallback(hspi);
@@ -3361,9 +3457,10 @@
* the configuration information for the specified DMA module.
* @retval None
*/
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
{
- SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+ ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
hspi->TxRxHalfCpltCallback(hspi);
@@ -3517,6 +3614,7 @@
hspi->RxXferSize = hspi->Reload.RxXferSize;
hspi->RxXferCount = hspi->Reload.RxXferSize;
hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
+ hspi->Reload.Requested = 0UL;
}
else
{
@@ -3560,6 +3658,7 @@
hspi->RxXferSize = hspi->Reload.RxXferSize;
hspi->RxXferCount = hspi->Reload.RxXferSize;
hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
+ hspi->Reload.Requested = 0UL;
}
else
{
@@ -3597,6 +3696,7 @@
hspi->RxXferSize = hspi->Reload.RxXferSize;
hspi->RxXferCount = hspi->Reload.RxXferSize;
hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr;
+ hspi->Reload.Requested = 0UL;
}
else
{
@@ -3634,6 +3734,12 @@
hspi->TxXferSize = hspi->Reload.TxXferSize;
hspi->TxXferCount = hspi->Reload.TxXferSize;
hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
+
+ /* In full duplex mode the reload request is reset in RX side */
+ if (hspi->State == HAL_SPI_STATE_BUSY_TX)
+ {
+ hspi->Reload.Requested = 0UL;
+ }
}
else
{
@@ -3676,6 +3782,12 @@
hspi->TxXferSize = hspi->Reload.TxXferSize;
hspi->TxXferCount = hspi->Reload.TxXferSize;
hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
+
+ /* In full duplex mode the reload request is reset in RX side */
+ if (hspi->State == HAL_SPI_STATE_BUSY_TX)
+ {
+ hspi->Reload.Requested = 0UL;
+ }
}
else
{
@@ -3712,6 +3824,12 @@
hspi->TxXferSize = hspi->Reload.TxXferSize;
hspi->TxXferCount = hspi->Reload.TxXferSize;
hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr;
+
+ /* In full duplex mode the reload request is reset in RX side */
+ if (hspi->State == HAL_SPI_STATE_BUSY_TX)
+ {
+ hspi->Reload.Requested = 0UL;
+ }
}
else
{
@@ -3847,7 +3965,7 @@
* @param Tickstart: Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
/* Wait until flag is set */
@@ -3868,7 +3986,7 @@
* the configuration information for SPI module.
* @retval Packet size occupied in the fifo
*/
-static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
+static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi)
{
uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL;
diff --git a/Src/stm32h7xx_hal_sram.c b/Src/stm32h7xx_hal_sram.c
index d773210..94d93ca 100644
--- a/Src/stm32h7xx_hal_sram.c
+++ b/Src/stm32h7xx_hal_sram.c
@@ -83,15 +83,15 @@
and a pointer to the user callback function.
Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
+ weak (overridden) function. It allows to reset following callbacks:
(+) MspInitCallback : SRAM MspInit.
(+) MspDeInitCallback : SRAM MspDeInit.
This function) takes as parameters the HAL peripheral handle and the Callback ID.
By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ all callbacks are reset to the corresponding legacy weak (overridden) functions.
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init
+ reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -106,7 +106,7 @@
When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak (overridden) callbacks are used.
@endverbatim
******************************************************************************
@@ -739,7 +739,7 @@
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User SRAM Callback
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -759,9 +759,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsram);
-
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
@@ -785,14 +782,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsram);
return status;
}
/**
* @brief Unregister a User SRAM Callback
- * SRAM Callback is redirected to the weak (surcharged) predefined callback
+ * SRAM Callback is redirected to the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -807,9 +802,6 @@
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- /* Process locked */
- __HAL_LOCK(hsram);
-
state = hsram->State;
if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
@@ -855,14 +847,12 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsram);
return status;
}
/**
* @brief Register a User SRAM Callback for DMA transfers
- * To be used instead of the weak (surcharged) predefined callback
+ * To be used to override the weak predefined callback
* @param hsram : SRAM handle
* @param CallbackId : ID of the callback to be registered
* This parameter can be one of the following values:
@@ -1026,7 +1016,7 @@
* the configuration information for SRAM module.
* @retval HAL state
*/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
{
return hsram->State;
}
diff --git a/Src/stm32h7xx_hal_tim.c b/Src/stm32h7xx_hal_tim.c
index 8764065..1020295 100644
--- a/Src/stm32h7xx_hal_tim.c
+++ b/Src/stm32h7xx_hal_tim.c
@@ -888,7 +888,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -980,7 +980,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1059,7 +1059,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1221,7 +1221,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1557,7 +1557,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -1649,7 +1649,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -1728,7 +1728,7 @@
uint32_t tmpsmcr;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Set the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1889,7 +1889,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -2133,7 +2133,7 @@
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2181,7 +2181,7 @@
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
{
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Disable the Input Capture channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
@@ -2217,7 +2217,7 @@
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2305,7 +2305,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
switch (Channel)
{
@@ -2381,7 +2381,7 @@
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Set the TIM channel state */
@@ -2536,7 +2536,7 @@
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
- assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+ assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
/* Disable the Input Capture channel */
@@ -3027,7 +3027,7 @@
* @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;
@@ -3842,7 +3842,7 @@
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -3874,7 +3874,7 @@
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3904,7 +3904,7 @@
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3934,7 +3934,7 @@
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3964,7 +3964,7 @@
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -3973,11 +3973,12 @@
}
}
/* TIM Break input event */
- if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
+ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+ ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@@ -4003,7 +4004,7 @@
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@@ -4016,7 +4017,7 @@
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@@ -4568,7 +4569,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -6970,6 +6972,13 @@
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -6984,11 +6993,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7059,11 +7069,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7092,7 +7103,6 @@
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
@@ -7135,11 +7145,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7209,11 +7220,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
@@ -7270,11 +7282,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7323,11 +7336,12 @@
uint32_t tmpccer;
uint32_t tmpcr2;
+ /* Get the TIMx CCER register value */
+ tmpccer = TIMx->CCER;
+
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
@@ -7521,9 +7535,9 @@
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC1E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
@@ -7611,9 +7625,9 @@
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
@@ -7650,9 +7664,9 @@
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC2E;
tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
@@ -7694,9 +7708,9 @@
uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC3E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC3S;
@@ -7742,9 +7756,9 @@
uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
+ tmpccer = TIMx->CCER;
TIMx->CCER &= ~TIM_CCER_CC4E;
tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
diff --git a/Src/stm32h7xx_hal_tim_ex.c b/Src/stm32h7xx_hal_tim_ex.c
index ad4cbee..21ef06b 100644
--- a/Src/stm32h7xx_hal_tim_ex.c
+++ b/Src/stm32h7xx_hal_tim_ex.c
@@ -849,7 +849,7 @@
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1095,17 +1095,6 @@
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
@endverbatim
* @{
*/
@@ -1331,7 +1320,7 @@
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1812,6 +1801,9 @@
* @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
* @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
* @arg TIM_TS_NONE: No trigger is needed
+ *
+ * (*) Value not defined in all devices.
+ *
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@@ -1868,9 +1860,12 @@
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
- * @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+ * @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+ * @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
* @arg TIM_TS_NONE: No trigger is needed
+ *
+ * (*) Value not defined in all devices.
+ *
* @param CommutationSource the Commutation Event source
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@@ -1928,8 +1923,8 @@
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
- * @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
- * @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+ * @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+ * @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
* @arg TIM_TS_NONE: No trigger is needed
*
* (*) Value not defined in all devices.
@@ -2079,6 +2074,9 @@
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+#if defined(TIM_BDTR_BKBID)
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+#endif /* TIM_BDTR_BKBID */
/* Check input state */
__HAL_LOCK(htim);
@@ -2095,39 +2093,26 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
-
#if defined(TIM_BDTR_BKBID)
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
-
- /* Set BREAK AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
- }
-
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
#endif /* TIM_BDTR_BKBID */
+
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
{
/* Check the parameters */
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+#if defined(TIM_BDTR_BKBID)
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+#endif /* TIM_BDTR_BKBID */
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
#if defined(TIM_BDTR_BKBID)
-
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
-
- /* Set BREAK2 AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
- }
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
#endif /* TIM_BDTR_BKBID */
}
@@ -2153,7 +2138,6 @@
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmporx;
@@ -2381,49 +2365,49 @@
* @arg TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP
*
* For TIM8, the parameter is one of the following values:
- * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
- * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
+ * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
+ * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
*
* For TIM12, the parameter can have the following values: (*)
- * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
- * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
+ * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
+ * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
*
* For TIM15, the parameter is one of the following values:
- * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
- * @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1
- * @arg TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1
- * @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1
- * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
- * @arg TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI
- * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
- * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
- * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
- * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
- * @arg TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2
+ * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
+ * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1
+ * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1
+ * @arg TIM_TIM15_TI1_TIM4_CH1: TIM15 TI1 is connected to TIM4 CH1
+ * @arg TIM_TIM15_TI1_RCC_LSE: TIM15 TI1 is connected to LSE
+ * @arg TIM_TIM15_TI1_RCC_CSI: TIM15 TI1 is connected to CSI
+ * @arg TIM_TIM15_TI1_RCC_MCO2: TIM15 TI1 is connected to MCO2
+ * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
+ * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2
+ * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2
+ * @arg TIM_TIM15_TI2_TIM4_CH2: TIM15 TI2 is connected to TIM4 CH2
*
* For TIM16, the parameter can have the following values:
- * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
- * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
- * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
- * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
+ * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
+ * @arg TIM_TIM16_TI1_RCC_LSI: TIM16 TI1 is connected to LSI
+ * @arg TIM_TIM16_TI1_RCC_LSE: TIM16 TI1 is connected to LSE
+ * @arg TIM_TIM16_TI1_WKUP_IT: TIM16 TI1 is connected to RTC wakeup interrupt
*
* For TIM17, the parameter can have the following values:
- * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
- * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
- * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
- * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
+ * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
+ * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
+ * @arg TIM_TIM17_TI1_RCC_HSE1MHZ: TIM17 TI1 is connected to HSE 1MHz
+ * @arg TIM_TIM17_TI1_RCC_MCO1: TIM17 TI1 is connected to MCO1
*
* For TIM23, the parameter can have the following values: (*)
- * @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO
- * @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output
- * @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output
- * @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
+ * @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO
+ * @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output
+ * @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output
+ * @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
*
* For TIM24, the parameter can have the following values: (*)
- * @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO
- * @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP
- * @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP
- * @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC
+ * @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO
+ * @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP
+ * @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP
+ * @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC
*
* (*) Value not defined in all devices. \n
* @retval HAL status
@@ -2518,7 +2502,7 @@
uint32_t tmpbdtr;
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
switch (BreakInput)
@@ -2535,7 +2519,6 @@
}
break;
}
-
case TIM_BREAKINPUT_BRK2:
{
/* Check initial conditions */
@@ -2567,13 +2550,13 @@
* @note Break input is automatically armed as soon as MOE bit is set.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
switch (BreakInput)
@@ -2653,7 +2636,7 @@
*/
/**
- * @brief Hall commutation changed callback in non-blocking mode
+ * @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2667,7 +2650,7 @@
*/
}
/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2682,7 +2665,7 @@
}
/**
- * @brief Hall Break detection callback in non-blocking mode
+ * @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2697,7 +2680,7 @@
}
/**
- * @brief Hall Break2 detection callback in non blocking mode
+ * @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
@@ -2848,15 +2831,6 @@
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
else
{
/* nothing to do */
@@ -2925,13 +2899,13 @@
{
uint32_t tmp;
- tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
/* Reset the CCxNE Bit */
TIMx->CCER &= ~tmp;
/* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
}
/**
* @}
diff --git a/Src/stm32h7xx_hal_uart.c b/Src/stm32h7xx_hal_uart.c
index 9064a76..3465d29 100644
--- a/Src/stm32h7xx_hal_uart.c
+++ b/Src/stm32h7xx_hal_uart.c
@@ -107,7 +107,7 @@
[..]
Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -131,10 +131,10 @@
[..]
By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+ reset to the legacy weak functions in the HAL_UART_Init()
and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -151,7 +151,7 @@
[..]
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -197,8 +197,8 @@
/** @addtogroup UART_Private_Functions
* @{
*/
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -704,7 +704,7 @@
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User UART Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
@@ -3427,20 +3427,20 @@
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
{
- /* Clear Overrun Error flag*/
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ /* Clear Overrun Error flag*/
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- /* Blocking error : transfer is aborted
- Set the UART state ready to be able to start again the process,
- Disable Rx Interrupts if ongoing */
- UART_EndRxTransfer(huart);
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts if ongoing */
+ UART_EndRxTransfer(huart);
- huart->ErrorCode = HAL_UART_ERROR_ORE;
+ huart->ErrorCode = HAL_UART_ERROR_ORE;
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
- return HAL_ERROR;
+ return HAL_ERROR;
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
{
diff --git a/Src/stm32h7xx_hal_uart_ex.c b/Src/stm32h7xx_hal_uart_ex.c
index 01479f9..6e5c0b2 100644
--- a/Src/stm32h7xx_hal_uart_ex.c
+++ b/Src/stm32h7xx_hal_uart_ex.c
@@ -835,7 +835,7 @@
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- HAL_StatusTypeDef status;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
@@ -849,24 +849,20 @@
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
huart->RxEventType = HAL_UART_RXEVENT_TC;
- status = UART_Start_Receive_IT(huart, pData, Size);
+ (void)UART_Start_Receive_IT(huart, pData, Size);
- /* Check Rx process has been successfully started */
- if (status == HAL_OK)
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
- if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- {
- __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- }
- else
- {
- /* In case of errors already pending when reception is started,
- Interrupts may have already been raised and lead to reception abortion.
- (Overrun error for instance).
- In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
- status = HAL_ERROR;
- }
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
}
return status;
@@ -962,7 +958,7 @@
* @param huart UART handle.
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
*/
-HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
{
/* Return Rx Event type value, as stored in UART handle */
return (huart->RxEventType);
diff --git a/Src/stm32h7xx_hal_usart.c b/Src/stm32h7xx_hal_usart.c
index bed9d16..85ccef2 100644
--- a/Src/stm32h7xx_hal_usart.c
+++ b/Src/stm32h7xx_hal_usart.c
@@ -91,7 +91,7 @@
[..]
Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
@@ -109,10 +109,10 @@
[..]
By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
- all callbacks are set to the corresponding weak (surcharged) functions:
+ all callbacks are set to the corresponding weak functions:
examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_USART_Init()
+ reset to the legacy weak functions in the HAL_USART_Init()
and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -129,7 +129,7 @@
[..]
When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
@@ -406,7 +406,7 @@
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief Register a User USART Callback
- * To be used instead of the weak predefined callback
+ * To be used to override the weak predefined callback
* @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
* to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
diff --git a/Src/stm32h7xx_ll_adc.c b/Src/stm32h7xx_ll_adc.c
index ce0edd7..86ef027 100644
--- a/Src/stm32h7xx_ll_adc.c
+++ b/Src/stm32h7xx_ll_adc.c
@@ -513,11 +513,6 @@
/* Disable ADC instance if not already disabled. */
if (LL_ADC_IsEnabled(ADCx) == 1UL)
{
- /* Set ADC group regular trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
/* Stop potential ADC conversion on going on ADC group regular. */
if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
{
@@ -527,11 +522,6 @@
}
}
- /* Set ADC group injected trigger source to SW start to ensure to not */
- /* have an external trigger event occurring during the conversion stop */
- /* ADC disable process. */
- LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
/* Stop potential ADC conversion on going on ADC group injected. */
if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
{
diff --git a/Src/stm32h7xx_ll_bdma.c b/Src/stm32h7xx_ll_bdma.c
index 4abaed3..9ba6ff0 100644
--- a/Src/stm32h7xx_ll_bdma.c
+++ b/Src/stm32h7xx_ll_bdma.c
@@ -44,39 +44,45 @@
/** @addtogroup BDMA_LL_Private_Macros
* @{
*/
-#define IS_LL_BDMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
- ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
- ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
+#define IS_LL_BDMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
-#define IS_LL_BDMA_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
- ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
+#define IS_LL_BDMA_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
-#define IS_LL_BDMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
- ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
+#define IS_LL_BDMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
-#define IS_LL_BDMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
- ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
+#define IS_LL_BDMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
-#define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
+#define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
-#define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
+#define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
-#define IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+#define IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#if defined(ADC3)
-#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
+#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
#else
-#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0)
+#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0)
#endif /* ADC3 */
-#define IS_LL_BDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_BDMA_PRIORITY_LOW) || \
- ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
- ((__VALUE__) == LL_BDMA_PRIORITY_HIGH) || \
- ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
+#define IS_LL_BDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_BDMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_BDMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_BDMA_DOUBLEBUFFER_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_DISABLE) || \
+ ((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_ENABLE))
+
+#define IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(__VALUE__) (((__VALUE__) == LL_BDMA_CURRENTTARGETMEM0) || \
+ ((__VALUE__) == LL_BDMA_CURRENTTARGETMEM1))
#define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == BDMA) && \
(((CHANNEL) == LL_BDMA_CHANNEL_0) || \
@@ -253,26 +259,33 @@
assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData));
assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest));
assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority));
+ assert_param(IS_LL_BDMA_DOUBLEBUFFER_MODE(BDMA_InitStruct->DoubleBufferMode));
+ assert_param(IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(BDMA_InitStruct->TargetMemInDoubleBufferMode));
/*---------------------------- DMAx CCR Configuration ------------------------
* Configure DMAx_Channely: data transfer direction, data transfer mode,
* peripheral and memory increment mode,
* data size alignment and priority level with parameters :
- * - Direction: BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
- * - Mode: BDMA_CCR_CIRC bit
- * - PeriphOrM2MSrcIncMode: BDMA_CCR_PINC bit
- * - MemoryOrM2MDstIncMode: BDMA_CCR_MINC bit
- * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits
- * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits
- * - Priority: BDMA_CCR_PL[1:0] bits
+ * - Direction: BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
+ * - Mode: BDMA_CCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: BDMA_CCR_PINC bit
+ * - MemoryOrM2MDstIncMode: BDMA_CCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits
+ * - Priority: BDMA_CCR_PL[1:0] bits
+ * - DoubleBufferMode: BDMA_CCR_DBM bit
+ * - TargetMemInDoubleBufferMode: BDMA_CCR_CT bit
*/
- LL_BDMA_ConfigTransfer(BDMAx, Channel, BDMA_InitStruct->Direction | \
+ LL_BDMA_ConfigTransfer(BDMAx, Channel,
+ BDMA_InitStruct->Direction | \
BDMA_InitStruct->Mode | \
BDMA_InitStruct->PeriphOrM2MSrcIncMode | \
BDMA_InitStruct->MemoryOrM2MDstIncMode | \
BDMA_InitStruct->PeriphOrM2MSrcDataSize | \
BDMA_InitStruct->MemoryOrM2MDstDataSize | \
- BDMA_InitStruct->Priority);
+ BDMA_InitStruct->Priority | \
+ BDMA_InitStruct->DoubleBufferMode | \
+ BDMA_InitStruct->TargetMemInDoubleBufferMode);
/*-------------------------- DMAx CMAR Configuration -------------------------
* Configure the memory or destination base address with parameter :
@@ -309,17 +322,19 @@
void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct)
{
/* Set BDMA_InitStruct fields to default values */
- BDMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
- BDMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
- BDMA_InitStruct->Direction = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
- BDMA_InitStruct->Mode = LL_BDMA_MODE_NORMAL;
- BDMA_InitStruct->PeriphOrM2MSrcIncMode = LL_BDMA_PERIPH_NOINCREMENT;
- BDMA_InitStruct->MemoryOrM2MDstIncMode = LL_BDMA_MEMORY_NOINCREMENT;
- BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE;
- BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE;
- BDMA_InitStruct->NbData = 0x00000000U;
- BDMA_InitStruct->PeriphRequest = LL_DMAMUX2_REQ_MEM2MEM;
- BDMA_InitStruct->Priority = LL_BDMA_PRIORITY_LOW;
+ BDMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ BDMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ BDMA_InitStruct->Direction = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
+ BDMA_InitStruct->Mode = LL_BDMA_MODE_NORMAL;
+ BDMA_InitStruct->PeriphOrM2MSrcIncMode = LL_BDMA_PERIPH_NOINCREMENT;
+ BDMA_InitStruct->MemoryOrM2MDstIncMode = LL_BDMA_MEMORY_NOINCREMENT;
+ BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE;
+ BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE;
+ BDMA_InitStruct->NbData = 0x00000000U;
+ BDMA_InitStruct->PeriphRequest = LL_DMAMUX2_REQ_MEM2MEM;
+ BDMA_InitStruct->Priority = LL_BDMA_PRIORITY_LOW;
+ BDMA_InitStruct->DoubleBufferMode = LL_BDMA_DOUBLEBUFFER_MODE_DISABLE;
+ BDMA_InitStruct->TargetMemInDoubleBufferMode = LL_BDMA_CURRENTTARGETMEM0;
}
/**
diff --git a/Src/stm32h7xx_ll_crc.c b/Src/stm32h7xx_ll_crc.c
index e1f29c0..34f0dd1 100644
--- a/Src/stm32h7xx_ll_crc.c
+++ b/Src/stm32h7xx_ll_crc.c
@@ -59,7 +59,7 @@
* - SUCCESS: CRC registers are de-initialized
* - ERROR: CRC registers are not de-initialized
*/
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32h7xx_ll_dac.c b/Src/stm32h7xx_ll_dac.c
index 29c3ca9..aedbc66 100644
--- a/Src/stm32h7xx_ll_dac.c
+++ b/Src/stm32h7xx_ll_dac.c
@@ -46,13 +46,13 @@
* @{
*/
#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \
- ( ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
- || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+ (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
)
#if defined (HRTIM1)
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
@@ -69,7 +69,7 @@
)
#elif defined (DAC2)
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
@@ -85,7 +85,7 @@
)
#else
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
- ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
@@ -100,58 +100,58 @@
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM23_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM24_TRGO) \
)
-#endif
+#endif /* HRTIM1 */
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
- ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \
( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
+ && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
) \
||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
- && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
- || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
+ && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
) \
)
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
- ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
- || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
)
#define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \
- ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
- || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
+ (((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \
+ || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \
)
#define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \
- ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
- || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
+ (((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \
+ || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \
)
/**
@@ -178,19 +178,19 @@
* - SUCCESS: DAC registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(DACx));
- if(DACx == DAC1)
+ if (DACx == DAC1)
{
/* Force reset of DAC clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC12);
/* Release reset of DAC clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC12);
- }
+ }
#if defined (DAC2)
else
{
@@ -200,8 +200,7 @@
/* Release reset of DAC clock */
LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_DAC2);
}
-#endif
-
+#endif /* DAC2 */
return SUCCESS;
}
@@ -231,7 +230,7 @@
* - SUCCESS: DAC registers are initialized
* - ERROR: DAC registers are not initialized
*/
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
{
ErrorStatus status = SUCCESS;
@@ -343,4 +342,3 @@
*/
#endif /* USE_FULL_LL_DRIVER */
-
diff --git a/Src/stm32h7xx_ll_dma.c b/Src/stm32h7xx_ll_dma.c
index b7e32d2..183cd74 100644
--- a/Src/stm32h7xx_ll_dma.c
+++ b/Src/stm32h7xx_ll_dma.c
@@ -43,42 +43,48 @@
/** @addtogroup DMA_LL_Private_Macros
* @{
*/
-#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
- ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
- ((__VALUE__) == LL_DMA_MODE_PFCTRL))
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
+ ((__VALUE__) == LL_DMA_MODE_PFCTRL))
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
- ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
- ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#if defined(TIM24)
-#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_TIM24_TRIG))
+#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_TIM24_TRIG))
#elif defined(ADC3)
-#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3))
+#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3))
#else
-#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
+#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX))
#endif /* TIM24 */
-#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
- ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
- ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
- ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_DMA_DOUBLEBUFFER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_DISABLE) || \
+ ((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_ENABLE))
+
+#define IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(__VALUE__) (((__VALUE__) == LL_DMA_CURRENTTARGETMEM0) || \
+ ((__VALUE__) == LL_DMA_CURRENTTARGETMEM1))
#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
(((STREAM) == LL_DMA_STREAM_0) || \
@@ -101,23 +107,23 @@
((STREAM) == LL_DMA_STREAM_7) || \
((STREAM) == LL_DMA_STREAM_ALL))))
-#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
- ((STATE) == LL_DMA_FIFOMODE_ENABLE))
+#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
+ ((STATE) == LL_DMA_FIFOMODE_ENABLE))
-#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
- ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
- ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
- ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
+#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
+ ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
+ ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
+ ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
-#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
- ((BURST) == LL_DMA_MBURST_INC4) || \
- ((BURST) == LL_DMA_MBURST_INC8) || \
- ((BURST) == LL_DMA_MBURST_INC16))
+#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
+ ((BURST) == LL_DMA_MBURST_INC4) || \
+ ((BURST) == LL_DMA_MBURST_INC8) || \
+ ((BURST) == LL_DMA_MBURST_INC16))
-#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
- ((BURST) == LL_DMA_PBURST_INC4) || \
- ((BURST) == LL_DMA_PBURST_INC8) || \
- ((BURST) == LL_DMA_PBURST_INC16))
+#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
+ ((BURST) == LL_DMA_PBURST_INC4) || \
+ ((BURST) == LL_DMA_PBURST_INC8) || \
+ ((BURST) == LL_DMA_PBURST_INC16))
/**
* @}
@@ -296,6 +302,8 @@
assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
+ assert_param(IS_LL_DMA_DOUBLEBUFFER_MODE(DMA_InitStruct->DoubleBufferMode));
+ assert_param(IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(DMA_InitStruct->TargetMemInDoubleBufferMode));
/* Check the memory burst, peripheral burst and FIFO threshold parameters only
when FIFO mode is enabled */
@@ -310,22 +318,26 @@
* Configure DMAx_Streamy: data transfer direction, data transfer mode,
* peripheral and memory increment mode,
* data size alignment and priority level with parameters :
- * - Direction: DMA_SxCR_DIR[1:0] bits
- * - Mode: DMA_SxCR_CIRC bit
- * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
- * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
- * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
- * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
- * - Priority: DMA_SxCR_PL[1:0] bits
+ * - Direction: DMA_SxCR_DIR[1:0] bits
+ * - Mode: DMA_SxCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
+ * - Priority: DMA_SxCR_PL[1:0] bits
+ * - DoubleBufferMode: DMA_SxCR_DBM bit
+ * - TargetMemInDoubleBufferMode: DMA_SxCR_CT bit
*/
- LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
+ LL_DMA_ConfigTransfer(DMAx, Stream,
+ DMA_InitStruct->Direction | \
DMA_InitStruct->Mode | \
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
DMA_InitStruct->MemoryOrM2MDstIncMode | \
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
DMA_InitStruct->MemoryOrM2MDstDataSize | \
- DMA_InitStruct->Priority
- );
+ DMA_InitStruct->Priority | \
+ DMA_InitStruct->DoubleBufferMode | \
+ DMA_InitStruct->TargetMemInDoubleBufferMode);
if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
{
@@ -384,21 +396,23 @@
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Set DMA_InitStruct fields to default values */
- DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
- DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
- DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
- DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
- DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
- DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
- DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
- DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
- DMA_InitStruct->NbData = 0x00000000U;
- DMA_InitStruct->PeriphRequest = LL_DMAMUX1_REQ_MEM2MEM;
- DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
- DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
- DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
- DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
- DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = 0x00000000U;
+ DMA_InitStruct->PeriphRequest = LL_DMAMUX1_REQ_MEM2MEM;
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+ DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
+ DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
+ DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
+ DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
+ DMA_InitStruct->DoubleBufferMode = LL_DMA_DOUBLEBUFFER_MODE_DISABLE;
+ DMA_InitStruct->TargetMemInDoubleBufferMode = LL_DMA_CURRENTTARGETMEM0;
}
/**
diff --git a/Src/stm32h7xx_ll_fmac.c b/Src/stm32h7xx_ll_fmac.c
index 74be426..eab7ae8 100644
--- a/Src/stm32h7xx_ll_fmac.c
+++ b/Src/stm32h7xx_ll_fmac.c
@@ -90,7 +90,7 @@
* - SUCCESS: FMAC registers are de-initialized
* - ERROR: FMAC registers are not de-initialized
*/
-ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx)
+ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32h7xx_ll_fmc.c b/Src/stm32h7xx_ll_fmc.c
index eb53261..b9fa468 100644
--- a/Src/stm32h7xx_ll_fmc.c
+++ b/Src/stm32h7xx_ll_fmc.c
@@ -60,7 +60,8 @@
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
-#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
+ || defined(HAL_SRAM_MODULE_ENABLED)
/** @defgroup FMC_LL FMC Low Layer
* @brief FMC driver modules
@@ -1043,7 +1044,7 @@
* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
* FMC_SDRAM_POWER_DOWN_MODE.
*/
-uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
{
uint32_t tmpreg;
diff --git a/Src/stm32h7xx_ll_i2c.c b/Src/stm32h7xx_ll_i2c.c
index 34ae9d8..69f7923 100644
--- a/Src/stm32h7xx_ll_i2c.c
+++ b/Src/stm32h7xx_ll_i2c.c
@@ -83,7 +83,7 @@
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
@@ -149,7 +149,7 @@
* - SUCCESS: I2C registers are initialized
* - ERROR: Not applicable
*/
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
diff --git a/Src/stm32h7xx_ll_lptim.c b/Src/stm32h7xx_ll_lptim.c
index 7c11980..54dc528 100644
--- a/Src/stm32h7xx_ll_lptim.c
+++ b/Src/stm32h7xx_ll_lptim.c
@@ -92,7 +92,7 @@
* - SUCCESS: LPTIMx registers are de-initialized
* - ERROR: invalid LPTIMx instance
*/
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx)
{
ErrorStatus result = SUCCESS;
diff --git a/Src/stm32h7xx_ll_rng.c b/Src/stm32h7xx_ll_rng.c
index d69312b..02981e2 100644
--- a/Src/stm32h7xx_ll_rng.c
+++ b/Src/stm32h7xx_ll_rng.c
@@ -59,7 +59,7 @@
#define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
#define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
-#endif /* RNG_CR_CONDRST*/
+#endif /* RNG_CR_CONDRST */
/**
* @}
*/
@@ -81,7 +81,7 @@
* - SUCCESS: RNG registers are de-initialized
* - ERROR: not applicable
*/
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32h7xx_ll_spi.c b/Src/stm32h7xx_ll_spi.c
index d78aaf0..5705699 100644
--- a/Src/stm32h7xx_ll_spi.c
+++ b/Src/stm32h7xx_ll_spi.c
@@ -236,7 +236,7 @@
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
@@ -547,7 +547,7 @@
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
{
return LL_SPI_DeInit(SPIx);
}
@@ -565,17 +565,20 @@
* - SUCCESS: SPI registers are Initialized
* - ERROR: SPI registers are not Initialized
*/
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct)
{
uint32_t i2sdiv = 0UL;
uint32_t i2sodd = 0UL;
uint32_t packetlength = 1UL;
uint32_t ispcm = 0UL;
uint32_t tmp;
- uint32_t sourceclock;
+ uint32_t sourceclock = 0UL;
ErrorStatus status = ERROR;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(sourceclock);
+
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
diff --git a/Src/stm32h7xx_ll_tim.c b/Src/stm32h7xx_ll_tim.c
index de652f3..89ccf5f 100644
--- a/Src/stm32h7xx_ll_tim.c
+++ b/Src/stm32h7xx_ll_tim.c
@@ -66,8 +66,8 @@
|| ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
|| ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
@@ -223,7 +223,7 @@
* - SUCCESS: TIMx registers are de-initialized
* - ERROR: invalid TIMx instance
*/
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
{
ErrorStatus result = SUCCESS;
@@ -739,7 +739,7 @@
TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
#if defined(TIM_BDTR_BKBID)
TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT;
-#endif /*TIM_BDTR_BKBID */
+#endif /* TIM_BDTR_BKBID */
TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE;
TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW;
TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
@@ -778,6 +778,10 @@
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+#if defined(TIM_BDTR_BKBID)
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+#endif /*TIM_BDTR_BKBID */
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -790,14 +794,9 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
#if defined(TIM_BDTR_BKBID)
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
-#else
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
#endif /*TIM_BDTR_BKBID */
if (IS_TIM_BKIN2_INSTANCE(TIMx))
@@ -854,8 +853,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -883,8 +880,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -933,8 +932,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -962,8 +959,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -1012,8 +1011,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -1041,8 +1038,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1091,8 +1090,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1120,7 +1117,6 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
/* Set the Output Idle state */
@@ -1387,7 +1383,7 @@
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
- /* Select the Polarity and set the CC2E Bit */
+ /* Select the Polarity and set the CC4E Bit */
MODIFY_REG(TIMx->CCER,
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
diff --git a/Src/stm32h7xx_ll_usb.c b/Src/stm32h7xx_ll_usb.c
index b090870..ed2ca0f 100644
--- a/Src/stm32h7xx_ll_usb.c
+++ b/Src/stm32h7xx_ll_usb.c
@@ -262,9 +262,9 @@
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else if (mode == USB_DEVICE_MODE)
{
@@ -272,16 +272,16 @@
do
{
- HAL_Delay(1U);
- ms++;
- } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
+ HAL_Delay(10U);
+ ms += 10U;
+ } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
}
else
{
return HAL_ERROR;
}
- if (ms == 50U)
+ if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
{
return HAL_ERROR;
}
@@ -458,7 +458,7 @@
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -472,7 +472,7 @@
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -495,7 +495,7 @@
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -509,7 +509,7 @@
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -529,7 +529,7 @@
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @retval Hal status
*/
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -545,7 +545,7 @@
* @arg USBD_HS_SPEED: High speed mode
* @arg USBD_FS_SPEED: Full speed mode
*/
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t speed;
@@ -574,7 +574,7 @@
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -612,7 +612,7 @@
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -651,7 +651,7 @@
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -698,7 +698,7 @@
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -912,7 +912,7 @@
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
__IO uint32_t count = 0U;
HAL_StatusTypeDef ret = HAL_OK;
@@ -976,7 +976,7 @@
* 1 : DMA feature used
* @retval HAL status
*/
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1007,7 +1007,7 @@
* @param len Number of bytes to read
* @retval pointer to destination buffer
*/
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint8_t *pDest = dest;
@@ -1049,7 +1049,7 @@
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -1080,7 +1080,7 @@
* @param ep pointer to endpoint structure
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t epnum = (uint32_t)ep->num;
@@ -1150,7 +1150,7 @@
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1165,7 +1165,7 @@
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1182,7 +1182,7 @@
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1199,7 +1199,7 @@
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
-uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
{
uint32_t tmpreg;
@@ -1215,7 +1215,7 @@
* @param chnum Channel number
* @retval USB Channel Interrupt status
*/
-uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1231,7 +1231,7 @@
* @param USBx Selected device
* @retval USB Device OUT EP interrupt status
*/
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1247,7 +1247,7 @@
* @param USBx Selected device
* @retval USB Device IN EP interrupt status
*/
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1265,7 +1265,7 @@
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1283,7 +1283,7 @@
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg;
@@ -1317,7 +1317,7 @@
* 0 : Host
* 1 : Device
*/
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
return ((USBx->GINTSTS) & 0x1U);
}
@@ -1327,7 +1327,7 @@
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1349,10 +1349,10 @@
* @param psetup pointer to setup packet
* @retval HAL status
*/
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
{
uint32_t USBx_BASE = (uint32_t)USBx;
- uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+ uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
{
@@ -1391,7 +1391,7 @@
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1405,7 +1405,7 @@
{
count++;
- if (count > 200000U)
+ if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1509,7 +1509,7 @@
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1539,7 +1539,7 @@
* @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
*/
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1566,7 +1566,7 @@
* 1 : Activate VBUS
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0 = 0U;
@@ -1596,7 +1596,7 @@
* @arg HCD_SPEED_FULL: Full speed mode
* @arg HCD_SPEED_LOW: Low speed mode
*/
-uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
__IO uint32_t hprt0 = 0U;
@@ -1610,7 +1610,7 @@
* @param USBx Selected device
* @retval current frame number
*/
-uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1710,6 +1710,9 @@
break;
}
+ /* Clear Hub Start Split transaction */
+ USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
+
/* Enable host channel Halt interrupt */
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
@@ -1793,36 +1796,93 @@
(void)USB_DoPing(USBx, hc->ch_num);
return HAL_OK;
}
-
}
- /* Compute the expected number of packets associated to the transfer */
- if (hc->xfer_len > 0U)
+ if (hc->do_ssplit == 1U)
{
- num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+ /* Set number of packet to 1 for Split transaction */
+ num_packets = 1U;
- if (num_packets > max_hc_pkt_count)
+ if (hc->ep_is_in != 0U)
{
- num_packets = max_hc_pkt_count;
hc->XferSize = (uint32_t)num_packets * hc->max_packet;
}
+ else
+ {
+ if (hc->ep_type == EP_TYPE_ISOC)
+ {
+ if (hc->xfer_len > ISO_SPLT_MPS)
+ {
+ /* Isochrone Max Packet Size for Split mode */
+ hc->XferSize = hc->max_packet;
+ hc->xfer_len = hc->XferSize;
+
+ if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE))
+ {
+ hc->iso_splt_xactPos = HCSPLT_MIDDLE;
+ }
+ else
+ {
+ hc->iso_splt_xactPos = HCSPLT_BEGIN;
+ }
+ }
+ else
+ {
+ hc->XferSize = hc->xfer_len;
+
+ if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE))
+ {
+ hc->iso_splt_xactPos = HCSPLT_FULL;
+ }
+ else
+ {
+ hc->iso_splt_xactPos = HCSPLT_END;
+ }
+ }
+ }
+ else
+ {
+ if ((dma == 1U) && (hc->xfer_len > hc->max_packet))
+ {
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+ }
+ else
+ {
+ hc->XferSize = hc->xfer_len;
+ }
+ }
+ }
}
else
{
- num_packets = 1U;
- }
+ /* Compute the expected number of packets associated to the transfer */
+ if (hc->xfer_len > 0U)
+ {
+ num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
- /*
- * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
- * max_packet size.
- */
- if (hc->ep_is_in != 0U)
- {
- hc->XferSize = (uint32_t)num_packets * hc->max_packet;
- }
- else
- {
- hc->XferSize = hc->xfer_len;
+ if (num_packets > max_hc_pkt_count)
+ {
+ num_packets = max_hc_pkt_count;
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+ }
+ }
+ else
+ {
+ num_packets = 1U;
+ }
+
+ /*
+ * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
+ * max_packet size.
+ */
+ if (hc->ep_is_in != 0U)
+ {
+ hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+ }
+ else
+ {
+ hc->XferSize = hc->xfer_len;
+ }
}
/* Initialize the HCTSIZn register */
@@ -1840,6 +1900,65 @@
USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
+ if (hc->do_ssplit == 1U)
+ {
+ /* Set Hub start Split transaction */
+ USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) |
+ (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN;
+
+ /* unmask ack & nyet for IN/OUT transactions */
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM |
+ USB_OTG_HCINTMSK_NYET);
+
+ if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U))
+ {
+ USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+ USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
+ }
+
+ if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) &&
+ (hc->do_csplit == 1U) && (hc->ep_is_in == 1U))
+ {
+ USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+ }
+
+ /* Position management for iso out transaction on split mode */
+ if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U))
+ {
+ /* Set data payload position */
+ switch (hc->iso_splt_xactPos)
+ {
+ case HCSPLT_BEGIN:
+ /* First data payload for OUT Transaction */
+ USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1;
+ break;
+
+ case HCSPLT_MIDDLE:
+ /* Middle data payload for OUT Transaction */
+ USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos;
+ break;
+
+ case HCSPLT_END:
+ /* End data payload for OUT Transaction */
+ USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0;
+ break;
+
+ case HCSPLT_FULL:
+ /* Entire data payload for OUT Transaction */
+ USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS;
+ break;
+
+ default:
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* Clear Hub Start Split transaction */
+ USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
+ }
+
/* Set host channel enable */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
@@ -1861,7 +1980,7 @@
return HAL_OK;
}
- if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+ if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U))
{
switch (hc->ep_type)
{
@@ -1907,7 +2026,7 @@
* @param USBx Selected device
* @retval HAL state
*/
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -1921,16 +2040,21 @@
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t hcnum = (uint32_t)hc_num;
__IO uint32_t count = 0U;
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
+ uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31;
- if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
- (ChannelEna == 0U))
+ /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels.
+ At the end of the next uframe/frame (in the worst case), the core generates a channel halted
+ and disables the channel automatically. */
+
+ if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) &&
+ ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR)))))
{
return HAL_OK;
}
@@ -2000,7 +2124,7 @@
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
{
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t chnum = (uint32_t)ch_num;
@@ -2089,7 +2213,7 @@
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
@@ -2107,7 +2231,7 @@
* @param USBx Selected device
* @retval HAL status
*/
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
{
uint32_t USBx_BASE = (uint32_t)USBx;
diff --git a/Src/stm32h7xx_ll_utils.c b/Src/stm32h7xx_ll_utils.c
index 865129e..8117ecb 100644
--- a/Src/stm32h7xx_ll_utils.c
+++ b/Src/stm32h7xx_ll_utils.c
@@ -250,6 +250,7 @@
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_IsPLLsReady(void);
+static uint32_t UTILS_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
/**
* @}
*/
@@ -522,7 +523,7 @@
/* Check VCO Output frequency */
#ifdef USE_FULL_ASSERT
- vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
+ vcooutput_freq = UTILS_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
#endif
assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
@@ -618,7 +619,7 @@
/* Check VCO output frequency */
#ifdef USE_FULL_ASSERT
- vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
+ vcooutput_freq = UTILS_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
#endif
assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
@@ -926,7 +927,7 @@
assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
- pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
+ pllfreq = UTILS_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
return pllfreq;
}
@@ -966,6 +967,27 @@
}
/**
+ * @brief Helper function to calculate the PLL frequency output
+ * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
+ * @param M Between 1 and 63
+ * @param N Between 4 and 512
+ * @param FRACN Between 0 and 0x1FFF
+ * @param PQR VCO output divider (P, Q or R)
+ * Between 1 and 128, except for PLL1P Odd value not allowed
+ * @retval PLL1 clock frequency (in Hz)
+ */
+static uint32_t UTILS_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
+{
+ float_t freq;
+
+ freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
+
+ freq = freq / (float_t)PQR;
+
+ return (uint32_t)freq;
+}
+
+/**
* @brief Function to enable PLL and switch system clock to PLL
* @param SYSCLK_Frequency SYSCLK frequency
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
diff --git a/_htmresc/favicon.png b/_htmresc/favicon.png
new file mode 100644
index 0000000..06713ee
--- /dev/null
+++ b/_htmresc/favicon.png
Binary files differ
diff --git a/_htmresc/mini-st.css b/_htmresc/mini-st_2020.css
similarity index 77%
rename from _htmresc/mini-st.css
rename to _htmresc/mini-st_2020.css
index eb41d56..986f4d4 100644
--- a/_htmresc/mini-st.css
+++ b/_htmresc/mini-st_2020.css
@@ -1,39 +1,39 @@
@charset "UTF-8";
/*
- Flavor name: Default (mini-default)
- Author: Angelos Chalaris (chalarangelo@gmail.com)
- Maintainers: Angelos Chalaris
- mini.css version: v3.0.0-alpha.3
+ Flavor name: Custom (mini-custom)
+ Generated online - https://minicss.org/flavors
+ mini.css version: v3.0.1
*/
/*
Browsers resets and base typography.
*/
/* Core module CSS variable definitions */
:root {
- --fore-color: #111;
- --secondary-fore-color: #444;
- --back-color: #f8f8f8;
- --secondary-back-color: #f0f0f0;
- --blockquote-color: #f57c00;
- --pre-color: #1565c0;
- --border-color: #aaa;
- --secondary-border-color: #ddd;
- --heading-ratio: 1.19;
+ --fore-color: #03234b;
+ --secondary-fore-color: #03234b;
+ --back-color: #ffffff;
+ --secondary-back-color: #ffffff;
+ --blockquote-color: #e6007e;
+ --pre-color: #e6007e;
+ --border-color: #3cb4e6;
+ --secondary-border-color: #3cb4e6;
+ --heading-ratio: 1.2;
--universal-margin: 0.5rem;
- --universal-padding: 0.125rem;
- --universal-border-radius: 0.125rem;
- --a-link-color: #0277bd;
- --a-visited-color: #01579b; }
+ --universal-padding: 0.25rem;
+ --universal-border-radius: 0.075rem;
+ --background-margin: 1.5%;
+ --a-link-color: #3cb4e6;
+ --a-visited-color: #8c0078; }
html {
- font-size: 14px; }
+ font-size: 13.5px; }
a, b, del, em, i, ins, q, span, strong, u {
font-size: 1em; }
html, * {
- font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Ubuntu, "Helvetica Neue", Helvetica, sans-serif;
- line-height: 1.4;
+ font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif;
+ line-height: 1.25;
-webkit-text-size-adjust: 100%; }
* {
@@ -42,7 +42,10 @@
body {
margin: 0;
color: var(--fore-color);
- background: var(--back-color); }
+ @background: var(--back-color);
+ background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top;
+ background-size: var(--background-margin);
+ }
details {
display: block; }
@@ -62,9 +65,9 @@
height: auto; }
h1, h2, h3, h4, h5, h6 {
- line-height: 1.2;
+ line-height: 1.25;
margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
- font-weight: 500; }
+ font-weight: 400; }
h1 small, h2 small, h3 small, h4 small, h5 small, h6 small {
color: var(--secondary-fore-color);
display: block;
@@ -74,21 +77,15 @@
font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); }
h2 {
- font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio); );
- background: var(--mark-back-color);
- font-weight: 600;
- padding: 0.1em 0.5em 0.2em 0.5em;
- color: var(--mark-fore-color); }
-
+ font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) );
+ border-style: none none solid none ;
+ border-width: thin;
+ border-color: var(--border-color); }
h3 {
- font-size: calc(1rem * var(--heading-ratio));
- padding-left: calc(2 * var(--universal-margin));
- /* background: var(--border-color); */
- }
+ font-size: calc(1rem * var(--heading-ratio) ); }
h4 {
- font-size: 1rem;);
- padding-left: calc(4 * var(--universal-margin)); }
+ font-size: calc(1rem * var(--heading-ratio)); }
h5 {
font-size: 1rem; }
@@ -101,7 +98,7 @@
ol, ul {
margin: var(--universal-margin);
- padding-left: calc(6 * var(--universal-margin)); }
+ padding-left: calc(3 * var(--universal-margin)); }
b, strong {
font-weight: 700; }
@@ -111,7 +108,7 @@
border: 0;
line-height: 1.25em;
margin: var(--universal-margin);
- height: 0.0625rem;
+ height: 0.0714285714rem;
background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); }
blockquote {
@@ -121,16 +118,16 @@
color: var(--secondary-fore-color);
margin: var(--universal-margin);
padding: calc(3 * var(--universal-padding));
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.375rem solid var(--blockquote-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.3rem solid var(--blockquote-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
blockquote:before {
position: absolute;
top: calc(0rem - var(--universal-padding));
left: 0;
font-family: sans-serif;
- font-size: 3rem;
- font-weight: 700;
+ font-size: 2rem;
+ font-weight: 800;
content: "\201c";
color: var(--blockquote-color); }
blockquote[cite]:after {
@@ -160,8 +157,8 @@
background: var(--secondary-back-color);
padding: calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
- border: 0.0625rem solid var(--secondary-border-color);
- border-left: 0.25rem solid var(--pre-color);
+ border: 0.0714285714rem solid var(--secondary-border-color);
+ border-left: 0.2857142857rem solid var(--pre-color);
border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; }
sup, sub, code, kbd {
@@ -204,7 +201,8 @@
box-sizing: border-box;
display: flex;
flex: 0 1 auto;
- flex-flow: row wrap; }
+ flex-flow: row wrap;
+ margin: 0 0 0 var(--background-margin); }
.col-sm,
[class^='col-sm-'],
@@ -565,9 +563,9 @@
order: 999; } }
/* Card component CSS variable definitions */
:root {
- --card-back-color: #f8f8f8;
- --card-fore-color: #111;
- --card-border-color: #ddd; }
+ --card-back-color: #3cb4e6;
+ --card-fore-color: #03234b;
+ --card-border-color: #03234b; }
.card {
display: flex;
@@ -578,7 +576,7 @@
width: 100%;
background: var(--card-back-color);
color: var(--card-fore-color);
- border: 0.0625rem solid var(--card-border-color);
+ border: 0.0714285714rem solid var(--card-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
overflow: hidden; }
@@ -592,7 +590,7 @@
margin: 0;
border: 0;
border-radius: 0;
- border-bottom: 0.0625rem solid var(--card-border-color);
+ border-bottom: 0.0714285714rem solid var(--card-border-color);
padding: var(--universal-padding);
width: 100%; }
.card > .sectione.media {
@@ -617,17 +615,18 @@
width: auto; }
.card.warning {
-/* --card-back-color: #ffca28; */
--card-back-color: #e5b8b7;
- --card-border-color: #e8b825; }
+ --card-fore-color: #3b234b;
+ --card-border-color: #8c0078; }
.card.error {
- --card-back-color: #b71c1c;
- --card-fore-color: #f8f8f8;
- --card-border-color: #a71a1a; }
+ --card-back-color: #464650;
+ --card-fore-color: #ffffff;
+ --card-border-color: #8c0078; }
.card > .sectione.dark {
- --card-back-color: #e0e0e0; }
+ --card-back-color: #3b234b;
+ --card-fore-color: #ffffff; }
.card > .sectione.double-padded {
padding: calc(1.5 * var(--universal-padding)); }
@@ -637,12 +636,12 @@
*/
/* Input_control module CSS variable definitions */
:root {
- --form-back-color: #f0f0f0;
- --form-fore-color: #111;
- --form-border-color: #ddd;
- --input-back-color: #f8f8f8;
- --input-fore-color: #111;
- --input-border-color: #ddd;
+ --form-back-color: #ffe97f;
+ --form-fore-color: #03234b;
+ --form-border-color: #3cb4e6;
+ --input-back-color: #ffffff;
+ --input-fore-color: #03234b;
+ --input-border-color: #3cb4e6;
--input-focus-color: #0288d1;
--input-invalid-color: #d32f2f;
--button-back-color: #e2e2e2;
@@ -655,13 +654,13 @@
form {
background: var(--form-back-color);
color: var(--form-fore-color);
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin);
padding: calc(2 * var(--universal-padding)) var(--universal-padding); }
fieldset {
- border: 0.0625rem solid var(--form-border-color);
+ border: 0.0714285714rem solid var(--form-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 4);
padding: var(--universal-padding); }
@@ -671,7 +670,7 @@
display: table;
max-width: 100%;
white-space: normal;
- font-weight: 700;
+ font-weight: 500;
padding: calc(var(--universal-padding) / 2); }
label {
@@ -716,7 +715,7 @@
box-sizing: border-box;
background: var(--input-back-color);
color: var(--input-fore-color);
- border: 0.0625rem solid var(--input-border-color);
+ border: 0.0714285714rem solid var(--input-border-color);
border-radius: var(--universal-border-radius);
margin: calc(var(--universal-margin) / 2);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); }
@@ -763,8 +762,8 @@
[type="radio"]:checked:before {
border-radius: 100%;
content: '';
- top: calc(0.0625rem + var(--universal-padding) / 2);
- left: calc(0.0625rem + var(--universal-padding) / 2);
+ top: calc(0.0714285714rem + var(--universal-padding) / 2);
+ left: calc(0.0714285714rem + var(--universal-padding) / 2);
background: var(--input-fore-color);
width: 0.5rem;
height: 0.5rem; }
@@ -793,7 +792,7 @@
display: inline-block;
background: var(--button-back-color);
color: var(--button-fore-color);
- border: 0.0625rem solid var(--button-border-color);
+ border: 0.0714285714rem solid var(--button-border-color);
border-radius: var(--universal-border-radius);
padding: var(--universal-padding) calc(1.5 * var(--universal-padding));
margin: var(--universal-margin);
@@ -814,7 +813,7 @@
.button-group {
display: flex;
- border: 0.0625rem solid var(--button-group-border-color);
+ border: 0.0714285714rem solid var(--button-group-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
.button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] {
@@ -826,13 +825,13 @@
border-radius: 0;
box-shadow: none; }
.button-group > :not(:first-child) {
- border-left: 0.0625rem solid var(--button-group-border-color); }
+ border-left: 0.0714285714rem solid var(--button-group-border-color); }
@media screen and (max-width: 499px) {
.button-group {
flex-direction: column; }
.button-group > :not(:first-child) {
border: 0;
- border-top: 0.0625rem solid var(--button-group-border-color); } }
+ border-top: 0.0714285714rem solid var(--button-group-border-color); } }
/*
Custom elements for forms and input elements.
@@ -874,29 +873,29 @@
*/
/* Navigation module CSS variable definitions */
:root {
- --header-back-color: #f8f8f8;
- --header-hover-back-color: #f0f0f0;
- --header-fore-color: #444;
- --header-border-color: #ddd;
- --nav-back-color: #f8f8f8;
- --nav-hover-back-color: #f0f0f0;
- --nav-fore-color: #444;
- --nav-border-color: #ddd;
- --nav-link-color: #0277bd;
- --footer-fore-color: #444;
- --footer-back-color: #f8f8f8;
- --footer-border-color: #ddd;
- --footer-link-color: #0277bd;
- --drawer-back-color: #f8f8f8;
- --drawer-hover-back-color: #f0f0f0;
- --drawer-border-color: #ddd;
- --drawer-close-color: #444; }
+ --header-back-color: #03234b;
+ --header-hover-back-color: #ffd200;
+ --header-fore-color: #ffffff;
+ --header-border-color: #3cb4e6;
+ --nav-back-color: #ffffff;
+ --nav-hover-back-color: #ffe97f;
+ --nav-fore-color: #e6007e;
+ --nav-border-color: #3cb4e6;
+ --nav-link-color: #3cb4e6;
+ --footer-fore-color: #ffffff;
+ --footer-back-color: #03234b;
+ --footer-border-color: #3cb4e6;
+ --footer-link-color: #3cb4e6;
+ --drawer-back-color: #ffffff;
+ --drawer-hover-back-color: #ffe97f;
+ --drawer-border-color: #3cb4e6;
+ --drawer-close-color: #e6007e; }
header {
- height: 3.1875rem;
+ height: 2.75rem;
background: var(--header-back-color);
color: var(--header-fore-color);
- border-bottom: 0.0625rem solid var(--header-border-color);
+ border-bottom: 0.0714285714rem solid var(--header-border-color);
padding: calc(var(--universal-padding) / 4) 0;
white-space: nowrap;
overflow-x: auto;
@@ -927,7 +926,7 @@
nav {
background: var(--nav-back-color);
color: var(--nav-fore-color);
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-radius: var(--universal-border-radius);
margin: var(--universal-margin); }
nav * {
@@ -946,10 +945,10 @@
nav .sublink-1:before {
position: absolute;
left: calc(var(--universal-padding) - 1 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
nav .sublink-2 {
position: relative;
@@ -957,16 +956,16 @@
nav .sublink-2:before {
position: absolute;
left: calc(var(--universal-padding) - 3 * var(--universal-padding));
- top: -0.0625rem;
+ top: -0.0714285714rem;
content: '';
height: 100%;
- border: 0.0625rem solid var(--nav-border-color);
+ border: 0.0714285714rem solid var(--nav-border-color);
border-left: 0; }
footer {
background: var(--footer-back-color);
color: var(--footer-fore-color);
- border-top: 0.0625rem solid var(--footer-border-color);
+ border-top: 0.0714285714rem solid var(--footer-border-color);
padding: calc(2 * var(--universal-padding)) var(--universal-padding);
font-size: 0.875rem; }
footer a, footer a:visited {
@@ -1013,7 +1012,7 @@
height: 100vh;
overflow-y: auto;
background: var(--drawer-back-color);
- border: 0.0625rem solid var(--drawer-border-color);
+ border: 0.0714285714rem solid var(--drawer-border-color);
border-radius: 0;
margin: 0;
z-index: 1110;
@@ -1060,38 +1059,36 @@
*/
/* Table module CSS variable definitions. */
:root {
- --table-border-color: #aaa;
- --table-border-separator-color: #666;
- --table-head-back-color: #e6e6e6;
- --table-head-fore-color: #111;
- --table-body-back-color: #f8f8f8;
- --table-body-fore-color: #111;
- --table-body-alt-back-color: #eee; }
+ --table-border-color: #03234b;
+ --table-border-separator-color: #03234b;
+ --table-head-back-color: #03234b;
+ --table-head-fore-color: #ffffff;
+ --table-body-back-color: #ffffff;
+ --table-body-fore-color: #03234b;
+ --table-body-alt-back-color: #f4f4f4; }
table {
border-collapse: separate;
border-spacing: 0;
- : margin: calc(1.5 * var(--universal-margin)) var(--universal-margin);
+ margin: 0;
display: flex;
flex: 0 1 auto;
flex-flow: row wrap;
padding: var(--universal-padding);
- padding-top: 0;
- margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); }
+ padding-top: 0; }
table caption {
- font-size: 1.25 * rem;
+ font-size: 1rem;
margin: calc(2 * var(--universal-margin)) 0;
max-width: 100%;
- flex: 0 0 100%;
- text-align: left;}
+ flex: 0 0 100%; }
table thead, table tbody {
display: flex;
flex-flow: row wrap;
- border: 0.0625rem solid var(--table-border-color); }
+ border: 0.0714285714rem solid var(--table-border-color); }
table thead {
z-index: 999;
border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0;
- border-bottom: 0.0625rem solid var(--table-border-separator-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-separator-color); }
table tbody {
border-top: 0;
margin-top: calc(0 - var(--universal-margin));
@@ -1109,11 +1106,11 @@
table td {
background: var(--table-body-back-color);
color: var(--table-body-fore-color);
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table:not(.horizontal) {
overflow: auto;
- max-height: 850px; }
+ max-height: 100%; }
table:not(.horizontal) thead, table:not(.horizontal) tbody {
max-width: 100%;
flex: 0 0 100%; }
@@ -1134,32 +1131,33 @@
border: 0; }
table.horizontal thead, table.horizontal tbody {
border: 0;
+ flex: .2 0 0;
flex-flow: row nowrap; }
table.horizontal tbody {
overflow: auto;
justify-content: space-between;
- flex: 1 0 0;
- margin-left: calc( 4 * var(--universal-margin));
+ flex: .8 0 0;
+ margin-left: 0;
padding-bottom: calc(var(--universal-padding) / 4); }
table.horizontal tr {
flex-direction: column;
flex: 1 0 auto; }
table.horizontal th, table.horizontal td {
- width: 100%;
+ width: auto;
border: 0;
- border-bottom: 0.0625rem solid var(--table-border-color); }
+ border-bottom: 0.0714285714rem solid var(--table-border-color); }
table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) {
border-top: 0; }
table.horizontal th {
text-align: right;
- border-left: 0.0625rem solid var(--table-border-color);
- border-right: 0.0625rem solid var(--table-border-separator-color); }
+ border-left: 0.0714285714rem solid var(--table-border-color);
+ border-right: 0.0714285714rem solid var(--table-border-separator-color); }
table.horizontal thead tr:first-child {
padding-left: 0; }
table.horizontal th:first-child, table.horizontal td:first-child {
- border-top: 0.0625rem solid var(--table-border-color); }
+ border-top: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td {
- border-right: 0.0625rem solid var(--table-border-color); }
+ border-right: 0.0714285714rem solid var(--table-border-color); }
table.horizontal tbody tr:last-child td:first-child {
border-top-right-radius: 0.25rem; }
table.horizontal tbody tr:last-child td:last-child {
@@ -1191,12 +1189,12 @@
display: table-row-group; }
table tr, table.horizontal tr {
display: block;
- border: 0.0625rem solid var(--table-border-color);
+ border: 0.0714285714rem solid var(--table-border-color);
border-radius: var(--universal-border-radius);
- background: #fafafa;
+ background: #ffffff;
padding: var(--universal-padding);
margin: var(--universal-margin);
- margin-bottom: calc(2 * var(--universal-margin)); }
+ margin-bottom: calc(1 * var(--universal-margin)); }
table th, table td, table.horizontal th, table.horizontal td {
width: auto; }
table td, table.horizontal td {
@@ -1211,9 +1209,6 @@
border-top: 0; }
table tbody tr:last-child td, table.horizontal tbody tr:last-child td {
border-right: 0; } }
-:root {
- --table-body-alt-back-color: #eee; }
-
table tr:nth-of-type(2n) > td {
background: var(--table-body-alt-back-color); }
@@ -1234,8 +1229,8 @@
*/
/* Contextual module CSS variable definitions */
:root {
- --mark-back-color: #0277bd;
- --mark-fore-color: #fafafa; }
+ --mark-back-color: #3cb4e6;
+ --mark-fore-color: #ffffff; }
mark {
background: var(--mark-back-color);
@@ -1243,11 +1238,11 @@
font-size: 0.95em;
line-height: 1em;
border-radius: var(--universal-border-radius);
- padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); }
+ padding: calc(var(--universal-padding) / 4) var(--universal-padding); }
mark.inline-block {
display: inline-block;
font-size: 1em;
- line-height: 1.5;
+ line-height: 1.4;
padding: calc(var(--universal-padding) / 2) var(--universal-padding); }
:root {
@@ -1314,8 +1309,8 @@
:root {
--modal-overlay-color: rgba(0, 0, 0, 0.45);
- --modal-close-color: #444;
- --modal-close-hover-color: #f0f0f0; }
+ --modal-close-color: #e6007e;
+ --modal-close-hover-color: #ffe97f; }
[type="checkbox"].modal {
height: 1px;
@@ -1368,13 +1363,14 @@
z-index: 1211; }
:root {
- --collapse-label-back-color: #e8e8e8;
- --collapse-label-fore-color: #212121;
- --collapse-label-hover-back-color: #f0f0f0;
- --collapse-selected-label-back-color: #ececec;
- --collapse-border-color: #ddd;
- --collapse-content-back-color: #fafafa;
- --collapse-selected-label-border-color: #0277bd; }
+ --collapse-label-back-color: #03234b;
+ --collapse-label-fore-color: #ffffff;
+ --collapse-label-hover-back-color: #3cb4e6;
+ --collapse-selected-label-back-color: #3cb4e6;
+ --collapse-border-color: var(--collapse-label-back-color);
+ --collapse-selected-border-color: #ceecf8;
+ --collapse-content-back-color: #ffffff;
+ --collapse-selected-label-border-color: #3cb4e6; }
.collapse {
width: calc(100% - 2 * var(--universal-margin));
@@ -1395,13 +1391,13 @@
.collapse > label {
flex-grow: 1;
display: inline-block;
- height: 1.5rem;
+ height: 1.25rem;
cursor: pointer;
- transition: background 0.3s;
+ transition: background 0.2s;
color: var(--collapse-label-fore-color);
background: var(--collapse-label-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
- padding: calc(1.5 * var(--universal-padding)); }
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
+ padding: calc(1.25 * var(--universal-padding)); }
.collapse > label:hover, .collapse > label:focus {
background: var(--collapse-label-hover-back-color); }
.collapse > label + div {
@@ -1418,7 +1414,7 @@
max-height: 1px; }
.collapse > :checked + label {
background: var(--collapse-selected-label-back-color);
- border-bottom-color: var(--collapse-selected-label-border-color); }
+ border-color: var(--collapse-selected-label-border-color); }
.collapse > :checked + label + div {
box-sizing: border-box;
position: relative;
@@ -1427,13 +1423,13 @@
overflow: auto;
margin: 0;
background: var(--collapse-content-back-color);
- border: 0.0625rem solid var(--collapse-border-color);
+ border: 0.0714285714rem solid var(--collapse-selected-border-color);
border-top: 0;
padding: var(--universal-padding);
clip: auto;
-webkit-clip-path: inset(0%);
clip-path: inset(0%);
- max-height: 850px; }
+ max-height: 100%; }
.collapse > label:not(:first-of-type) {
border-top: 0; }
.collapse > label:first-of-type {
@@ -1450,11 +1446,8 @@
/*
Custom elements for contextual background elements, toasts and tooltips.
*/
-mark.secondary {
- --mark-back-color: #d32f2f; }
-
mark.tertiary {
- --mark-back-color: #308732; }
+ --mark-back-color: #3cb4e6; }
mark.tag {
padding: calc(var(--universal-padding)/2) var(--universal-padding);
@@ -1465,7 +1458,7 @@
*/
/* Progress module CSS variable definitions */
:root {
- --progress-back-color: #ddd;
+ --progress-back-color: #3cb4e6;
--progress-fore-color: #555; }
progress {
@@ -1558,45 +1551,53 @@
filter: invert(100%); }
span.icon-alert {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-bookmark {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-calendar {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-credit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-edit {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); }
span.icon-link {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-help {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-home {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-info {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-lock {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-mail {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); }
span.icon-location {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-phone {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-rss {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); }
span.icon-search {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-settings {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-share {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-cart {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); }
span.icon-upload {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); }
span.icon-user {
- background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%23111' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+ background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); }
+
+/*
+ Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26).
+*/
+span.icon-st-update {
+ background-image: url("Update.svg"); }
+span.icon-st-add {
+ background-image: url("Add button.svg"); }
/*
Definitions for utilities and helper classes.
@@ -1604,7 +1605,7 @@
/* Utility module CSS variable definitions */
:root {
--generic-border-color: rgba(0, 0, 0, 0.3);
- --generic-box-shadow: 0 0.25rem 0.25rem 0 rgba(0, 0, 0, 0.125), 0 0.125rem 0.125rem -0.125rem rgba(0, 0, 0, 0.25); }
+ --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); }
.hidden {
display: none !important; }
@@ -1622,7 +1623,7 @@
overflow: hidden !important; }
.bordered {
- border: 0.0625rem solid var(--generic-border-color) !important; }
+ border: 0.0714285714rem solid var(--generic-border-color) !important; }
.rounded {
border-radius: var(--universal-border-radius) !important; }
@@ -1697,4 +1698,14 @@
clip-path: inset(100%) !important;
overflow: hidden !important; } }
-/*# sourceMappingURL=mini-default.css.map */
+/*# sourceMappingURL=mini-custom.css.map */
+
+img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; }
+img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;}
+
+.figure {
+ display: block;
+ margin-left: auto;
+ margin-right: auto;
+ text-align: center;
+}
\ No newline at end of file
diff --git a/_htmresc/st_logo.png b/_htmresc/st_logo.png
deleted file mode 100644
index 8b80057..0000000
--- a/_htmresc/st_logo.png
+++ /dev/null
Binary files differ
diff --git a/_htmresc/st_logo_2020.png b/_htmresc/st_logo_2020.png
new file mode 100644
index 0000000..d6cebb5
--- /dev/null
+++ b/_htmresc/st_logo_2020.png
Binary files differ
