Release v1.14.1
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 5a2c67e..cd7dab3 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -3643,7 +3643,8 @@
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
- defined(STM32WL) || defined(STM32C0)
+ defined(STM32WL) || defined(STM32C0)
+
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3892,7 +3893,8 @@
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
+ defined (STM32WBA) || defined (STM32H5) || \
+ defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -3929,7 +3931,8 @@
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
defined (STM32H7) || \
- defined (STM32L0) || defined (STM32L1)
+ defined (STM32L0) || defined (STM32L1) || \
+ defined (STM32WB)
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
#endif
diff --git a/Inc/stm32wbxx_hal_i2c.h b/Inc/stm32wbxx_hal_i2c.h
index c862c65..0c95999 100644
--- a/Inc/stm32wbxx_hal_i2c.h
+++ b/Inc/stm32wbxx_hal_i2c.h
@@ -118,8 +118,6 @@
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
diff --git a/Inc/stm32wbxx_hal_lptim.h b/Inc/stm32wbxx_hal_lptim.h
index 7ca18f3..2444921 100644
--- a/Inc/stm32wbxx_hal_lptim.h
+++ b/Inc/stm32wbxx_hal_lptim.h
@@ -657,9 +657,9 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
pLPTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
diff --git a/Inc/stm32wbxx_hal_rtc_ex.h b/Inc/stm32wbxx_hal_rtc_ex.h
index f660fb0..1715df8 100644
--- a/Inc/stm32wbxx_hal_rtc_ex.h
+++ b/Inc/stm32wbxx_hal_rtc_ex.h
@@ -794,14 +794,6 @@
*
* @retval None
*/
-#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
- ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
- ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))
-#else
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__)\
- == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U))
-#endif /* RTC_TAMPER1_SUPPORT || RTC_TAMPER3_SUPPORT */
/**************************************************************************************************/
diff --git a/Inc/stm32wbxx_hal_smbus.h b/Inc/stm32wbxx_hal_smbus.h
index cdddf89..69a3aec 100644
--- a/Inc/stm32wbxx_hal_smbus.h
+++ b/Inc/stm32wbxx_hal_smbus.h
@@ -100,8 +100,6 @@
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
-#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
-#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
diff --git a/Inc/stm32wbxx_hal_tim.h b/Inc/stm32wbxx_hal_tim.h
index 95f1188..18a619e 100644
--- a/Inc/stm32wbxx_hal_tim.h
+++ b/Inc/stm32wbxx_hal_tim.h
@@ -402,29 +402,28 @@
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
-
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
@@ -1866,8 +1865,9 @@
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
-#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
- ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+ (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
+ ((__PERIOD__) > 0U))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
@@ -1920,7 +1920,6 @@
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
-
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
@@ -2317,7 +2316,8 @@
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
diff --git a/Inc/stm32wbxx_ll_i2c.h b/Inc/stm32wbxx_ll_i2c.h
index 4d0c6f2..0f5f380 100644
--- a/Inc/stm32wbxx_ll_i2c.h
+++ b/Inc/stm32wbxx_ll_i2c.h
@@ -2133,11 +2133,18 @@
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
+ ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
+ (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+ (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
+
+ /* update CR2 register */
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
- SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
+ tmp);
}
/**
diff --git a/Inc/stm32wbxx_ll_tim.h b/Inc/stm32wbxx_ll_tim.h
index a7249de..10fab60 100644
--- a/Inc/stm32wbxx_ll_tim.h
+++ b/Inc/stm32wbxx_ll_tim.h
@@ -664,10 +664,10 @@
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
@@ -1132,6 +1132,15 @@
* @}
*/
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_TIM_ReArmBRK(_PARAM_)
+#define LL_TIM_ReArmBRK2(_PARAM_)
+/**
+@endcond
+ */
+
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
* @{
*/
@@ -1278,8 +1287,8 @@
/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
* @{
*/
-#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
-#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
+#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
+#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
/**
* @}
*/
@@ -1879,6 +1888,17 @@
}
/**
+ * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+ * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+ return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
@@ -3533,18 +3553,6 @@
}
/**
- * @brief Re-arm the break input (when it operates in bidirectional mode).
- * @note The Break input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
-}
-
-/**
* @brief Enable the break 2 function.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
@@ -3634,18 +3642,6 @@
}
/**
- * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
- * @note The Break 2 input is automatically armed as soon as MOE bit is set.
- * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
-}
-
-/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
diff --git a/Inc/stm32wbxx_ll_usb.h b/Inc/stm32wbxx_ll_usb.h
index 11211ff..52b7ec9 100644
--- a/Inc/stm32wbxx_ll_usb.h
+++ b/Inc/stm32wbxx_ll_usb.h
@@ -53,26 +53,26 @@
*/
typedef struct
{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
+ uint8_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref PCD_Speed/HCD_Speed
- (HCD_SPEED_xxx, HCD_SPEED_xxx) */
+ uint8_t speed; /*!< USB Core speed.
+ This parameter can be any value of @ref PCD_Speed/HCD_Speed
+ (HCD_SPEED_xxx, HCD_SPEED_xxx) */
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
+ uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
+ uint8_t phy_itface; /*!< Select the used PHY interface.
+ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
+ uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
+ uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
+ uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
+ uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
diff --git a/Release_Notes.html b/Release_Notes.html
index 9b27cea..ad7371d 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -40,7 +40,7 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section16" checked aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.14.0 / 07-June-2023</label>
+<input type="checkbox" id="collapse-section17" checked aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V1.14.1 / 31-October-2023</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
@@ -50,6 +50,72 @@
<h2 id="contents">Contents</h2>
<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
<ul>
+<li><strong>HAL I2C</strong> driver
+<ul>
+<li>Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice</li>
+<li>Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE</li>
+<li>Remove the unusable code in function HAL_I2C_IsDeviceReady</li>
+<li>Update I2C_WaitOnFlagUntilTimeout to handle error case</li>
+</ul></li>
+<li><strong>HAL SAI</strong> driver
+<ul>
+<li>Improve audio quality (avoid potential glitch)</li>
+</ul></li>
+<li><strong>HAL QSPI</strong> driver
+<ul>
+<li>Clear the QSPI.AR register when sCommand.AddressMode is “QSPI_ADDRESS_NONE”</li>
+</ul></li>
+<li><strong>HAL TIM</strong> driver
+<ul>
+<li>Removing multiple volatile reads or writes in interrupt handler</li>
+<li>Improved period configuration parameter check</li>
+<li>Assert check for the right channels</li>
+</ul></li>
+<li><strong>HAL RTC</strong> driver
+<ul>
+<li>Remove macro __HAL_RTC_TAMPER_GET_IT() as it is redundant with macro __HAL_RTC_TAMPER_GET_FLAG() and create an alias into the hal_legacy.h file</li>
+</ul></li>
+<li><strong>HAL UART</strong> driver
+<ul>
+<li>Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing</li>
+<li>Avoid RTOF flag to be cleared by a transmit process in polling mode</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<ul>
+<li><strong>LL I2C</strong> driver
+<ul>
+<li>Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register</li>
+</ul></li>
+<li><strong>LL TIM</strong> driver
+<ul>
+<li>Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init()</li>
+<li>User manual quality improvement</li>
+</ul></li>
+<li><strong>LL RTC</strong> driver
+<ul>
+<li>Correct misleading note about shadow registers</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.14.0 / 07-June-2023</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
+<li>HAL/LL code quality enhancement</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<ul>
<li><strong>HAL CRYP</strong> driver
<ul>
<li>Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment</li>
@@ -87,7 +153,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL USB</strong> driver
<ul>
@@ -96,20 +162,20 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.13.0 / 8-February-2023</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
<li>HAL/LL code quality enhancement</li>
</ul>
-<h2 id="contents-1">Contents</h2>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-2">Contents</h2>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL FLASH</strong> driver
<ul>
@@ -140,20 +206,20 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.12.0 / 09-November-2022</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
<li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)</li>
</ul>
-<h2 id="contents-2">Contents</h2>
-<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-3">Contents</h2>
+<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
@@ -200,7 +266,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL ADC</strong> driver
<ul>
@@ -221,20 +287,20 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.11.0 / 01-June-2022</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
<li>Correct English spelling errors and typos</li>
</ul>
-<h2 id="contents-3">Contents</h2>
-<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-4">Contents</h2>
+<h3 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL EXTI</strong> driver
<ul>
@@ -310,7 +376,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL I2C</strong> driver
<ul>
@@ -346,19 +412,19 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.10.1 / 27-March-2022</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>Patch release of <strong>HAL and Low Layer</strong> drivers</li>
</ul>
-<h2 id="contents-4">Contents</h2>
-<h3 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-5">Contents</h2>
+<h3 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL COMP</strong> driver
<ul>
@@ -367,7 +433,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL COMP</strong> driver
<ul>
@@ -376,21 +442,21 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-4">Backward Compatibility</h2>
+<h2 id="backward-compatibility-5">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.10.0 / 12-November-2021</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>All source files: update disclaimer to add reference to the new license agreement</li>
<li>Correct English spelling errors and typos</li>
</ul>
-<h2 id="contents-5">Contents</h2>
-<h3 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-6">Contents</h2>
+<h3 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
@@ -461,7 +527,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL ADC</strong> driver
<ul>
@@ -476,14 +542,14 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-5">Backward Compatibility</h2>
+<h2 id="backward-compatibility-6">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.9.0 / 24-June-2021</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus
@@ -497,8 +563,8 @@
</ul>
<p><br />
</p>
-<h2 id="contents-6">Contents</h2>
-<h3 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-7">Contents</h2>
+<h3 id="hal-drivers-updates-7"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL CORTEX</strong> driver
<ul>
@@ -574,7 +640,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-6"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL DMA</strong> driver
<ul>
@@ -601,14 +667,14 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-6">Backward Compatibility</h2>
+<h2 id="backward-compatibility-7">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">v1.8.0 / 12-February-2021</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<h3 id="add-support-for-stm32wb15xx-and-stm32wb10xx">Add support for STM32WB15xx and STM32WB10xx</h3>
<table>
<thead>
@@ -744,14 +810,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-7">Backward Compatibility</h2>
+<h2 id="backward-compatibility-8">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">v1.7.0 / 30-October-2020</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<h3 id="maitenance-release">Maitenance release</h3>
<p>All peripheral</p>
<table>
@@ -824,14 +890,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-8">Backward Compatibility</h2>
+<h2 id="backward-compatibility-9">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">v1.6.0 / 05-June-2020</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<h3 id="maitenance-release-1">Maitenance release</h3>
<p>All peripheral</p>
<table>
@@ -936,14 +1002,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-9">Backward Compatibility</h2>
+<h2 id="backward-compatibility-10">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.5.0 / 12-February-2020</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<h3 id="introduction-of-stm32wb5m-stm32wb35xx-and-stm32wb30xx-product">Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product</h3>
<p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
<p>Added features:</p>
@@ -988,14 +1054,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-10">Backward Compatibility</h2>
+<h2 id="backward-compatibility-11">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-December-2019</label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<h3 id="maitenance-release-2">Maitenance release</h3>
<table>
<thead>
@@ -1039,7 +1105,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-11">Backward Compatibility</h2>
+<h2 id="backward-compatibility-12">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1049,7 +1115,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<h3 id="maitenance-release-3">Maitenance release</h3>
<table>
<thead>
@@ -1121,7 +1187,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-12">Backward Compatibility</h2>
+<h2 id="backward-compatibility-13">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-1">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1131,7 +1197,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3>
<p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p>
<table>
@@ -1200,7 +1266,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-13">Backward Compatibility</h2>
+<h2 id="backward-compatibility-14">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-2">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1210,7 +1276,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p>
<table>
@@ -1264,7 +1330,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-14">Backward Compatibility</h2>
+<h2 id="backward-compatibility-15">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-3">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1274,7 +1340,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p>
</div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c
index 7c01352..ec62ac7 100644
--- a/Src/stm32wbxx_hal.c
+++ b/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_HAL_VERSION_SUB1 (0x0EU) /*!< [23:16] sub1 version */
-#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32WBxx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
|(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32wbxx_hal_i2c.c b/Src/stm32wbxx_hal_i2c.c
index d5771ce..05f58e6 100644
--- a/Src/stm32wbxx_hal_i2c.c
+++ b/Src/stm32wbxx_hal_i2c.c
@@ -3332,22 +3332,6 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Check if the maximum allowed number of trials has been reached */
- if (I2C_Trials == Trials)
- {
- /* Generate Stop */
- hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
- {
- return HAL_ERROR;
- }
-
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- }
-
/* Increment Trials */
I2C_Trials++;
} while (I2C_Trials < Trials);
@@ -6291,8 +6275,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Disable Interrupts and Store Previous state */
- if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (tmpstate == HAL_I2C_STATE_LISTEN))
+ if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
@@ -6302,6 +6285,11 @@
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
}
+ else if (tmpstate == HAL_I2C_STATE_LISTEN)
+ {
+ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+ hi2c->PreviousState = I2C_STATE_NONE;
+ }
else
{
/* Do nothing */
@@ -6955,6 +6943,12 @@
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
+ /* Check if an error is detected */
+ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
diff --git a/Src/stm32wbxx_hal_lptim.c b/Src/stm32wbxx_hal_lptim.c
index 28e14a8..cbace79 100644
--- a/Src/stm32wbxx_hal_lptim.c
+++ b/Src/stm32wbxx_hal_lptim.c
@@ -43,7 +43,7 @@
(++) Clock: the counter clock.
(+++) Source : it can be either the ULPTIM input (IN1) or one of
the internal clock; (APB, LSE, LSI or MSI).
- CAUTION: if LSI2 is selected as LPTIM cock source, LSI1 has
+ CAUTION: if LSI2 is selected as LPTIM clock source, LSI1 has
to be enabled as well (for further information please
refer to errata sheet ES0394).
(+++) Prescaler: select the clock divider.
diff --git a/Src/stm32wbxx_hal_sai.c b/Src/stm32wbxx_hal_sai.c
index f6ad077..6ee833a 100644
--- a/Src/stm32wbxx_hal_sai.c
+++ b/Src/stm32wbxx_hal_sai.c
@@ -170,7 +170,7 @@
[..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function.
+ weak function.
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
@@ -185,10 +185,10 @@
[..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+ all callbacks are reset to the corresponding legacy weak functions:
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+ reset to the legacy weak functions in the HAL_SAI_Init
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -205,7 +205,7 @@
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ and weak callbacks are used.
@endverbatim
******************************************************************************
diff --git a/Src/stm32wbxx_hal_smbus.c b/Src/stm32wbxx_hal_smbus.c
index bb0cfb1..84f9329 100644
--- a/Src/stm32wbxx_hal_smbus.c
+++ b/Src/stm32wbxx_hal_smbus.c
@@ -926,7 +926,7 @@
uint8_t *pData, uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
- uint32_t sizetoxfer = 0U;
+ uint32_t sizetoxfer;
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -960,10 +960,10 @@
}
sizetoxfer = hsmbus->XferSize;
- if ((hsmbus->XferSize > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
- (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
- (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
- (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
+ if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
+ (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
+ (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
{
if (hsmbus->pBuffPtr != NULL)
{
diff --git a/Src/stm32wbxx_hal_tim.c b/Src/stm32wbxx_hal_tim.c
index ddbb0cb..930bb22 100644
--- a/Src/stm32wbxx_hal_tim.c
+++ b/Src/stm32wbxx_hal_tim.c
@@ -3850,7 +3850,7 @@
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
{
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
@@ -3882,7 +3882,7 @@
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3912,7 +3912,7 @@
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3942,7 +3942,7 @@
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3972,7 +3972,7 @@
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
@@ -3981,11 +3981,12 @@
}
}
/* TIM Break input event */
- if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
+ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+ ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
@@ -4011,7 +4012,7 @@
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
@@ -4024,7 +4025,7 @@
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
{
- __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+ __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
@@ -4575,7 +4576,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
- uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
+ uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+ uint32_t BurstLength)
{
HAL_StatusTypeDef status;
@@ -6988,6 +6990,13 @@
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
+
+ /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+ if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+ {
+ /* Clear the update flag */
+ CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+ }
}
/**
@@ -7112,7 +7121,6 @@
tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
-
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
diff --git a/Src/stm32wbxx_hal_tim_ex.c b/Src/stm32wbxx_hal_tim_ex.c
index 5e90810..8b327a5 100644
--- a/Src/stm32wbxx_hal_tim_ex.c
+++ b/Src/stm32wbxx_hal_tim_ex.c
@@ -873,7 +873,7 @@
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -1119,17 +1119,6 @@
(+) Stop the Complementary PWM and disable interrupts.
(+) Start the Complementary PWM and enable DMA transfers.
(+) Stop the Complementary PWM and disable DMA transfers.
- (+) Start the Complementary Input Capture measurement.
- (+) Stop the Complementary Input Capture.
- (+) Start the Complementary Input Capture and enable interrupts.
- (+) Stop the Complementary Input Capture and disable interrupts.
- (+) Start the Complementary Input Capture and enable DMA transfers.
- (+) Stop the Complementary Input Capture and disable DMA transfers.
- (+) Start the Complementary One Pulse generation.
- (+) Stop the Complementary One Pulse.
- (+) Start the Complementary One Pulse and enable interrupts.
- (+) Stop the Complementary One Pulse and disable interrupts.
-
@endverbatim
* @{
*/
@@ -1355,7 +1344,7 @@
/* Disable the TIM Break interrupt (only if no more channel is active) */
tmpccer = htim->Instance->CCER;
- if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+ if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
{
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
}
@@ -2090,6 +2079,7 @@
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+ assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Check input state */
__HAL_LOCK(htim);
@@ -2106,15 +2096,7 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
-
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
-
- /* Set BREAK AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
- }
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
{
@@ -2122,20 +2104,13 @@
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+ assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
-
- if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
- {
- /* Check the parameters */
- assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
-
- /* Set BREAK2 AF mode */
- MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
- }
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
}
/* Set TIMx_BDTR */
@@ -2159,7 +2134,6 @@
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tmporx;
@@ -2414,7 +2388,7 @@
uint32_t tmpbdtr;
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
switch (BreakInput)
@@ -2431,7 +2405,6 @@
}
break;
}
-
case TIM_BREAKINPUT_BRK2:
{
/* Check initial conditions */
@@ -2469,7 +2442,7 @@
uint32_t tickstart;
/* Check the parameters */
- assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
switch (BreakInput)
@@ -2548,7 +2521,7 @@
*/
/**
- * @brief Hall commutation changed callback in non-blocking mode
+ * @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2562,7 +2535,7 @@
*/
}
/**
- * @brief Hall commutation changed half complete callback in non-blocking mode
+ * @brief Commutation half complete callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2577,7 +2550,7 @@
}
/**
- * @brief Hall Break detection callback in non-blocking mode
+ * @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
@@ -2592,7 +2565,7 @@
}
/**
- * @brief Hall Break2 detection callback in non blocking mode
+ * @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
@@ -2743,15 +2716,6 @@
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
}
}
- else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
- {
- htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
- if (hdma->Init.Mode == DMA_NORMAL)
- {
- TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
- }
- }
else
{
/* nothing to do */
diff --git a/Src/stm32wbxx_hal_uart.c b/Src/stm32wbxx_hal_uart.c
index 57cd74c..bb6a338 100644
--- a/Src/stm32wbxx_hal_uart.c
+++ b/Src/stm32wbxx_hal_uart.c
@@ -981,10 +981,7 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = pCallback;
}
@@ -995,9 +992,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -1011,10 +1005,7 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(huart);
-
- if (huart->gState == HAL_UART_STATE_READY)
+ if (huart->RxState == HAL_UART_STATE_READY)
{
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
}
@@ -1025,8 +1016,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(huart);
return status;
}
@@ -3477,7 +3466,7 @@
return HAL_TIMEOUT;
}
- if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+ if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
{
diff --git a/Src/stm32wbxx_ll_tim.c b/Src/stm32wbxx_ll_tim.c
index e59f9c2..643b2d8 100644
--- a/Src/stm32wbxx_ll_tim.c
+++ b/Src/stm32wbxx_ll_tim.c
@@ -698,6 +698,8 @@
assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -710,8 +712,6 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
@@ -765,8 +765,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 1: Reset the CC1E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -794,8 +792,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -844,8 +844,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 2: Reset the CC2E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -873,8 +871,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -923,8 +923,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
/* Disable the Channel 3: Reset the CC3E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -952,8 +950,10 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
/* Set the complementary output Polarity */
MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1002,8 +1002,6 @@
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
/* Disable the Channel 4: Reset the CC4E Bit */
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1031,7 +1029,6 @@
if (IS_TIM_BREAK_INSTANCE(TIMx))
{
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
/* Set the Output Idle state */
@@ -1298,7 +1295,7 @@
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
- /* Select the Polarity and set the CC2E Bit */
+ /* Select the Polarity and set the CC4E Bit */
MODIFY_REG(TIMx->CCER,
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
