diff --git a/Inc/stm32wbxx_ll_adc.h b/Inc/stm32wbxx_ll_adc.h
index d66703c..40a8e4c 100644
--- a/Inc/stm32wbxx_ll_adc.h
+++ b/Inc/stm32wbxx_ll_adc.h
@@ -282,7 +282,7 @@
 #define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
 #define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
 #define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 /* Definition of channels sampling time information to be inserted into       */
 /* channels literals definition.                                              */
@@ -320,7 +320,8 @@
 #define ADC_SAMPLING_TIME_SMP_MASK         (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK   (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
+
 /* Internal mask for ADC mode single or differential ended:                   */
 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
 /* the relevant bits for:                                                     */
@@ -364,7 +365,7 @@
 #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
 #define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 #define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
 
@@ -386,12 +387,11 @@
 #define ADC_OFR4_REGOFFSET                 (0x00000003UL)
 #define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
 
-
 /* ADC registers bits positions */
 #if defined (ADC_SUPPORT_2_5_MSPS)
 #define ADC_CFGR1_RES_BITOFFSET_POS        ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */
 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS     (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
-#define ADC_TR1_HT1_BITOFFSET_POS          (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
+#define ADC_TR_HT_BITOFFSET_POS            (16UL) /* Value equivalent to bitfield "ADC_TR_HT" position in register */
 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS    ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS    ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS    ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
@@ -422,7 +422,7 @@
 #define ADC_CFGR_AWD1EN_BITOFFSET_POS      (23UL) /* Value equivalent to bitfield "ADC_CFGR_AWD1EN" position in register */
 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (24UL) /* Value equivalent to bitfield "ADC_CFGR_JAWD1EN" position in register */
 #define ADC_TR1_HT1_BITOFFSET_POS          (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 
 /* ADC registers bits groups */
@@ -430,7 +430,7 @@
 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
 #else
 #define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 
 /* ADC internal channels related definitions */
@@ -531,7 +531,7 @@
                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
                                              For more details, refer to description of this function. */
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
   uint32_t Resolution;                  /*!< Set ADC resolution.
                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
 
@@ -680,7 +680,7 @@
 #if defined(ADC_SUPPORT_2_5_MSPS)
 #define LL_ADC_FLAG_CCRDY                  ADC_ISR_CCRDY      /*!< ADC flag ADC channel configuration ready */
 #else
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 #define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */
 #define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */
 #define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
@@ -693,7 +693,7 @@
 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
 #if defined(ADC_SUPPORT_2_5_MSPS)
 #define LL_ADC_FLAG_EOCAL                  ADC_ISR_EOCAL      /*!< ADC flag end of calibration */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -706,7 +706,7 @@
 #if defined(ADC_SUPPORT_2_5_MSPS)
 #define LL_ADC_IT_CCRDY                    ADC_IER_CCRDYIE    /*!< ADC interruption channel configuration ready */
 #else
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 #define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */
 #define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */
 #define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
@@ -719,7 +719,7 @@
 #define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
 #if defined(ADC_SUPPORT_2_5_MSPS)
 #define LL_ADC_IT_EOCAL                    ADC_IER_EOCALIE    /*!< ADC interruption ADC end of calibration */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -742,7 +742,7 @@
 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */
 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
 #define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */
 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */
 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */
@@ -786,7 +786,7 @@
 /**
   * @}
   */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
   * @{
@@ -818,7 +818,7 @@
 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF    (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
 #else
 #define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -842,7 +842,7 @@
   * @}
   */
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number
   * @{
   */
@@ -870,7 +870,7 @@
 #if !defined (ADC_SUPPORT_2_5_MSPS)
 #define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
 #define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -925,7 +925,7 @@
 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Temperature sensor. */
 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. */
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -951,7 +951,7 @@
 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1006,7 +1006,7 @@
   * @}
   */
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
   * @{
   */
@@ -1036,7 +1036,7 @@
 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1051,7 +1051,7 @@
   * @}
   */
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
   * @{
   */
@@ -1205,7 +1205,7 @@
 #define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
 #define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 247.5 ADC clock cycles */
 #define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1219,7 +1219,7 @@
 #define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
 #define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1233,7 +1233,7 @@
 #else
 #define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
 #define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1345,9 +1345,15 @@
 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
   * @{
   */
+#if defined (ADC_SUPPORT_2_5_MSPS)
+#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR_HT            )   /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (            ADC_TR_LT)   /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR_HT | ADC_TR_LT)   /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+#else
 #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1              ) /*!< ADC analog watchdog threshold high */
 #define LL_ADC_AWD_THRESHOLD_LOW           (              ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1364,7 +1370,7 @@
 #define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
 #define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */
 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1377,7 +1383,7 @@
 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TOVS)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
 #else
 #define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -1956,7 +1962,7 @@
    :                                                                                                      \
    (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
   )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 /**
   * @brief  Helper macro to set the value of ADC analog watchdog threshold high
@@ -2413,7 +2419,7 @@
   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
 #else
   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -2447,7 +2453,7 @@
   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
 #else
   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -2645,7 +2651,7 @@
 {
   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
 }
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 #if defined (ADC_SUPPORT_2_5_MSPS)
 /**
@@ -2790,7 +2796,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -2811,7 +2817,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -2835,7 +2841,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -2854,7 +2860,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -2918,7 +2924,7 @@
   MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -2977,7 +2983,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 #if defined(ADC_SUPPORT_2_5_MSPS)
@@ -3023,7 +3029,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 #if defined(ADC_SUPPORT_2_5_MSPS)
 /**
   * @brief  Set sampling time common to a group of channels.
@@ -3112,7 +3118,7 @@
                     >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 #if defined(ADC_SUPPORT_2_5_MSPS)
 /* Feature "ADC offset" not available on ADC peripheral of this STM32WB device */
@@ -3344,7 +3350,7 @@
   return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 
 /**
   * @}
@@ -3401,7 +3407,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -3464,7 +3470,7 @@
            & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
           | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
          );
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -3484,7 +3490,7 @@
   return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
 #else
   return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -3508,7 +3514,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -3527,7 +3533,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 #if defined(ADC_SUPPORT_2_5_MSPS)
@@ -3588,7 +3594,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Set ADC group regular sequencer length and scan direction.
   * @note   Description of ADC group regular sequencer features:
@@ -3668,7 +3674,7 @@
   SET_BIT(ADCx->CHSELR, SequencerNbRanks);
 #else
   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -3751,7 +3757,7 @@
   return SequencerLength;
 #else
   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 #if defined(ADC_SUPPORT_2_5_MSPS)
@@ -3793,7 +3799,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Set ADC group regular sequencer discontinuous mode:
   *         sequence subdivided and scan conversions interrupted every selected
@@ -3829,7 +3835,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -3858,7 +3864,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -3973,7 +3979,7 @@
   MODIFY_REG(*preg,
              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
              ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -4077,7 +4083,7 @@
                               ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
                    );
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 #if defined(ADC_SUPPORT_2_5_MSPS)
@@ -4436,7 +4442,7 @@
            | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
          );
 }
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Set ADC continuous conversion mode on ADC group regular.
   * @note   Description of ADC continuous conversion mode:
@@ -4462,7 +4468,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -4483,7 +4489,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -4525,7 +4531,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -4562,7 +4568,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 
@@ -4592,7 +4598,7 @@
   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
 #else
   MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -4610,7 +4616,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -5461,7 +5467,7 @@
   MODIFY_REG(*preg,
              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
              SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 #endif /* ADC_SUPPORT_2_5_MSPS */
 
@@ -5530,12 +5536,12 @@
 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
 {
   __IO uint32_t smpr = READ_REG(ADCx->SMPR);
-  
+
   /* Retrieve sampling time bit corresponding to the selected channel            */
   /* and shift it to position 0.                                                 */ 
   uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
                                            >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & 0x1FUL));
-  
+
   /* Select sampling time bitfield depending on sampling time bit value 0 or 1.  */
   return(  (~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
          | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2)   );
@@ -5628,7 +5634,7 @@
                              ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
                     >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
                    );
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 #endif /* ADC_SUPPORT_2_5_MSPS */
 
@@ -5888,7 +5894,7 @@
   MODIFY_REG(*preg,
              (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
              AWDChannelGroup & AWDy);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6099,7 +6105,7 @@
   }
 
   return AnalogWDMonitChannels;
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6145,6 +6151,7 @@
   *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
   *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
   *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
+  * @note For devices STM32WB15xx and STM32WB10xx, register ADC_TR is equivalent to ADC_TR1 (generic naming)
   * @param  ADCx ADC instance
   * @param  AWDy This parameter can be one of the following values:
   *         @arg @ref LL_ADC_AWD1
@@ -6168,16 +6175,16 @@
   /* Prevent unused argument(s) compilation warning */
   (void)(AWDy);
 
-  MODIFY_REG(ADCx->TR1,
-             ADC_TR1_HT1 | ADC_TR1_LT1,
-             (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+  MODIFY_REG(ADCx->TR,
+             ADC_TR_HT | ADC_TR_LT,
+             (AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue);
 #else
   __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
 
   MODIFY_REG(*preg,
              ADC_TR1_HT1 | ADC_TR1_LT1,
              (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6223,6 +6230,7 @@
   *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
   *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
   *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
+  * @note For devices STM32WB15xx and STM32WB10xx, register ADC_TR is equivalent to ADC_TR1 (generic naming)
   * @param  ADCx ADC instance
   * @param  AWDy This parameter can be one of the following values:
   *         @arg @ref LL_ADC_AWD1
@@ -6248,7 +6256,7 @@
   /* Prevent unused argument(s) compilation warning */
   (void)(AWDy);
 
-  MODIFY_REG(ADCx->TR1,
+  MODIFY_REG(ADCx->TR,
              AWDThresholdsHighLow,
              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
 #else
@@ -6257,7 +6265,7 @@
   MODIFY_REG(*preg,
              AWDThresholdsHighLow,
              AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6277,6 +6285,7 @@
   *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
   *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
   *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
+  * @note For devices STM32WB15xx and STM32WB10xx, register ADC_TR is equivalent to ADC_TR1 (generic naming)
   * @param  ADCx ADC instance
   * @param  AWDy This parameter can be one of the following values:
   *         @arg @ref LL_ADC_AWD1
@@ -6296,9 +6305,9 @@
   /* Prevent unused argument(s) compilation warning */
   (void)(AWDy);
 
-  return (uint32_t)(READ_BIT(ADCx->TR1,
-                             (AWDThresholdsHighLow | ADC_TR1_LT1))
-                    >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
+  return (uint32_t)(READ_BIT(ADCx->TR,
+                             (AWDThresholdsHighLow | ADC_TR_LT))
+                    >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR_LT))
                    );
 #else
   const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
@@ -6307,7 +6316,7 @@
                              (AWDThresholdsHighLow | ADC_TR1_LT1))
                     >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
                    );
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6354,7 +6363,7 @@
   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
 #else
   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6385,7 +6394,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6416,7 +6425,7 @@
   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
 #else
   MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -6439,7 +6448,7 @@
   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
 #else
   return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 }
 
 /**
@@ -7192,7 +7201,7 @@
 }
 
 #else
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Get flag ADC group regular end of unitary conversion.
   * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
@@ -7347,7 +7356,7 @@
 }
 
 #else
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Clear flag ADC group regular end of unitary conversion.
   * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
@@ -7474,7 +7483,7 @@
   WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -7507,7 +7516,7 @@
 }
 
 #else
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Enable interruption ADC group regular end of unitary conversion.
   * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
@@ -7634,7 +7643,7 @@
   SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Disable interruption ADC ready.
   * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
@@ -7659,7 +7668,7 @@
 }
 
 #else
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Disable interruption ADC group regular end of unitary conversion.
   * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
@@ -7786,7 +7795,7 @@
   CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Get state of interruption ADC ready
   *         (0: interrupt disabled, 1: interrupt enabled).
@@ -7812,7 +7821,7 @@
 }
 
 #else
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @brief  Get state of interruption ADC group regular end of unitary conversion
   *         (0: interrupt disabled, 1: interrupt enabled).
@@ -7950,7 +7959,7 @@
   return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
 }
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
@@ -7984,7 +7993,7 @@
 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
 void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
 
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
 /**
   * @}
   */
diff --git a/README.md b/README.md
index c279b27..7100ccb 100644
--- a/README.md
+++ b/README.md
@@ -45,7 +45,7 @@
 Tag v1.8.0    | Tag v1.8.0      | Tag v5.6.0_cm4 | Tag v1.11.0 (and following, if any, till next tag)
 Tag v1.9.0    | Tag v1.9.0      | Tag v5.6.0_cm4 | Tag v1.12.0 (and following, if any, till next tag)
 Tag v1.10.0   | Tag v1.10.0     | Tag v5.6.0_cm4 | Tag v1.13.0 (and following, if any, till next tag)
-
+Tag v1.10.1   | Tag v1.10.1     | Tag v5.6.0_cm4 | Tag v1.13.3 (and following, if any, till next tag)
 
 The full **STM32CubeWB** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWB).
 
@@ -53,4 +53,4 @@
 
 If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32wbxx_hal_driver/issues/new/choose).
 
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/topic/0TO0X000000BSqSWAW/stm32-mcus).
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
diff --git a/Release_Notes.html b/Release_Notes.html
index bc55c88..a5cbcb2 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -40,16 +40,46 @@
 <div class="col-sm-12 col-lg-8">
 <h1 id="update-history">Update History</h1>
 <div class="collapse">
-<input type="checkbox" id="collapse-section11" checked aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.10.0 / 12-November-2021</label>
+<input type="checkbox" id="collapse-section12" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.10.1 / 27-March-2022</label>
 <div>
 <h2 id="main-changes">Main Changes</h2>
 <ul>
+<li>Patch release of <strong>HAL and Low Layer</strong> drivers</li>
+</ul>
+<h2 id="contents">Contents</h2>
+<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
+<ul>
+<li><strong>HAL ADC</strong> driver
+<ul>
+<li>Align ADC Registers naming on Reference Manual for STM32WB15xx &amp; STM32WB10xx</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<ul>
+<li><strong>LL ADC</strong> driver
+<ul>
+<li>Align ADC Registers naming on Reference Manual for STM32WB15xx &amp; STM32WB10xx</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.10.0 / 12-November-2021</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
 <li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
 <li>All source files: update disclaimer to add reference to the new license agreement</li>
 <li>Correct English spelling errors and typos</li>
 </ul>
-<h2 id="contents">Contents</h2>
-<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-1">Contents</h2>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
 <ul>
 <li><strong>HAL ADC</strong> driver
 <ul>
@@ -120,7 +150,7 @@
 </ul>
 <p><br />
 </p>
-<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
 <ul>
 <li><strong>LL ADC</strong> driver
 <ul>
@@ -135,14 +165,14 @@
 </ul>
 <p><br />
 </p>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.9.0 / 24-June-2021</label>
 <div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
 <ul>
 <li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
 <li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus
@@ -156,8 +186,8 @@
 </ul>
 <p><br />
 </p>
-<h2 id="contents-1">Contents</h2>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-2">Contents</h2>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
 <ul>
 <li><strong>HAL CORTEX</strong> driver
 <ul>
@@ -233,7 +263,7 @@
 </ul>
 <p><br />
 </p>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
 <ul>
 <li><strong>LL DMA</strong> driver
 <ul>
@@ -260,14 +290,14 @@
 </ul>
 <p><br />
 </p>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">v1.8.0 / 12-February-2021</label>
 <div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
 <h3 id="add-support-for-stm32wb15xx-and-stm32wb10xx">Add support for STM32WB15xx and STM32WB10xx</h3>
 <table>
 <thead>
@@ -403,14 +433,14 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section8"  aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">v1.7.0 / 30-October-2020</label>
 <div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
 <h3 id="maitenance-release">Maitenance release</h3>
 <p>All peripheral</p>
 <table>
@@ -483,14 +513,14 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">v1.6.0 / 05-June-2020</label>
 <div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
 <h3 id="maitenance-release-1">Maitenance release</h3>
 <p>All peripheral</p>
 <table>
@@ -595,14 +625,14 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-4">Backward Compatibility</h2>
+<h2 id="backward-compatibility-5">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.5.0 / 12-February-2020</label>
 <div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
 <h3 id="introduction-of-stm32wb5m-stm32wb35xx-and-stm32wb30xx-product">Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product</h3>
 <p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
 <p>Added features:</p>
@@ -647,14 +677,14 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-5">Backward Compatibility</h2>
+<h2 id="backward-compatibility-6">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 </div>
 </div>
 <div class="collapse">
 <input type="checkbox" id="collapse-section5"  aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-December-2019</label>
 <div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
 <h3 id="maitenance-release-2">Maitenance release</h3>
 <table>
 <thead>
@@ -698,7 +728,7 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-6">Backward Compatibility</h2>
+<h2 id="backward-compatibility-7">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 <h2 id="dependencies">Dependencies</h2>
 <p>This software release is compatible with:</p>
@@ -708,7 +738,7 @@
 <div class="collapse">
 <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
 <div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
 <h3 id="maitenance-release-3">Maitenance release</h3>
 <table>
 <thead>
@@ -780,7 +810,7 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-7">Backward Compatibility</h2>
+<h2 id="backward-compatibility-8">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 <h2 id="dependencies-1">Dependencies</h2>
 <p>This software release is compatible with:</p>
@@ -790,7 +820,7 @@
 <div class="collapse">
 <input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
 <div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
 <h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3>
 <p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p>
 <table>
@@ -859,7 +889,7 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-8">Backward Compatibility</h2>
+<h2 id="backward-compatibility-9">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 <h2 id="dependencies-2">Dependencies</h2>
 <p>This software release is compatible with:</p>
@@ -869,7 +899,7 @@
 <div class="collapse">
 <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
 <div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
 <h3 id="maintenance-release">Maintenance release</h3>
 <p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p>
 <table>
@@ -923,7 +953,7 @@
 </tr>
 </tbody>
 </table>
-<h2 id="backward-compatibility-9">Backward Compatibility</h2>
+<h2 id="backward-compatibility-10">Backward Compatibility</h2>
 <p>This release is compatible with the previous versions.</p>
 <h2 id="dependencies-3">Dependencies</h2>
 <p>This software release is compatible with:</p>
@@ -933,7 +963,7 @@
 <div class="collapse">
 <input type="checkbox" id="collapse-section1"  aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
 <div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
 <h3 id="first-release">First release</h3>
 <p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p>
 </div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c
index 1d1d671..5b387e1 100644
--- a/Src/stm32wbxx_hal.c
+++ b/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
    */
 #define __STM32WBxx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
 #define __STM32WBxx_HAL_VERSION_SUB1   (0x0AU) /*!< [23:16] sub1 version */
-#define __STM32WBxx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32WBxx_HAL_VERSION_SUB2   (0x01U) /*!< [15:8]  sub2 version */
 #define __STM32WBxx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32WBxx_HAL_VERSION         ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
                                         |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32wbxx_hal_adc.c b/Src/stm32wbxx_hal_adc.c
index 7288fcd..7369aad 100644
--- a/Src/stm32wbxx_hal_adc.c
+++ b/Src/stm32wbxx_hal_adc.c
@@ -1014,10 +1014,10 @@
   
   /* Reset register CFGR1 */
   hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH   | ADC_CFGR1_AWD1EN  | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
-                             ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD |     
+                             ADC_CFGR1_AUTOFF  | ADC_CFGR1_WAIT   | ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD |
                              ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN  | ADC_CFGR1_RES    |
                              ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN                      );
-  
+
   /* Reset register CFGR2 */
   /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
   /*       already done above.                                              */
@@ -1025,13 +1025,13 @@
   
   /* Reset register SMPR */
   hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
-  
-  /* Reset register TR1 */
-  hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1);
-  
+
+  /* Reset register TR */
+  hadc->Instance->TR &= ~(ADC_TR_HT | ADC_TR_LT);
+
   /* Reset register CHSELR */
   hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
-  
+
   /* Reset register DR */
   /* bits in access mode read only, no direct reset applicable */
 
@@ -1043,7 +1043,7 @@
                               ADC_IT_EOCAL | ADC_IT_CCRDY |
 #else
                               ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
-                              ADC_IT_JEOS  | ADC_IT_JEOC | ADC_IT_JQOVF | 
+                              ADC_IT_JEOS  | ADC_IT_JEOC | ADC_IT_JQOVF |
 #endif
                               ADC_IT_EOS   | ADC_IT_EOC  | ADC_IT_OVR   |
                               ADC_IT_EOSMP | ADC_IT_RDY));
diff --git a/Src/stm32wbxx_ll_adc.c b/Src/stm32wbxx_ll_adc.c
index 6495557..807be01 100644
--- a/Src/stm32wbxx_ll_adc.c
+++ b/Src/stm32wbxx_ll_adc.c
@@ -631,13 +631,13 @@
                | ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN   | ADC_CFGR1_RES
                | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN                     )
              );
-    
+
     /* Reset register SMPR */
     CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
-    
-    /* Reset register TR1 */
-    MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
-    
+
+    /* Reset register TR */
+    MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
+
     /* Reset register CHSELR */
     CLEAR_BIT(ADCx->CHSELR,
               (  ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
@@ -646,7 +646,7 @@
                | ADC_CHSELR_CHSEL7  | ADC_CHSELR_CHSEL6  | ADC_CHSELR_CHSEL5  | ADC_CHSELR_CHSEL4
                | ADC_CHSELR_CHSEL3  | ADC_CHSELR_CHSEL2  | ADC_CHSELR_CHSEL1  | ADC_CHSELR_CHSEL0 )
              );
-    
+
     /* Wait for ADC channel configuration ready */
     timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
     while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
@@ -659,7 +659,7 @@
         break;
       }
     }
-    
+
     /* Clear flag ADC channel configuration ready */
     LL_ADC_ClearFlag_CCRDY(ADCx);