commit 0e1483284cd5087e31af952beb5624b5894fc55a
author karim <karim.rabhi-ext@st.com> Fri Sep 27 09:53:20 2024 +0100
committer karim <karim.rabhi-ext@st.com> Fri Sep 27 09:57:15 2024 +0100
tree c132c75d4f21b208f71e1e272c956c37d376f1c2
parent 56ce1761952a019f1c1dc6e7868079cf2d37283c

[HAL][SMBUS] Update SMBUS_ITErrorHandler to flush TXDR just in case of error

Src/stm32wlxx_hal_smbus.c

diff --git a/Src/stm32wlxx_hal_smbus.c b/Src/stm32wlxx_hal_smbus.c
index c572fcc..b5a9a1f 100644
--- a/Src/stm32wlxx_hal_smbus.c
+++ b/Src/stm32wlxx_hal_smbus.c
@@ -2605,8 +2605,11 @@
     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
   }
 
-  /* Flush TX register */
-  SMBUS_Flush_TXDR(hsmbus);
+  if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+  {
+    /* Flush TX register */
+    SMBUS_Flush_TXDR(hsmbus);
+  }
 
   /* Store current volatile hsmbus->ErrorCode, misra rule */
   tmperror = hsmbus->ErrorCode;