)]}'
{
  "commit": "4770838f9d09f1a932b2b31a3ab3366abfbd4e7b",
  "tree": "29b6049b2adf14175ac0b99db20dba66c7e2850a",
  "parents": [
    "ce145d2f07f4d78a27b6aacc04150164796be8c6"
  ],
  "author": {
    "name": "Abseil Team",
    "email": "absl-team@google.com",
    "time": "Wed Oct 07 19:47:28 2026 -0700"
  },
  "committer": {
    "name": "Copybara-Service",
    "email": "copybara-worker@google.com",
    "time": "Fri Oct 30 12:45:41 2026 -0700"
  },
  "message": "Improve CRC32C default CPU dispatch using AVX2 and ARM64 detection\n\nUnrecognized x86_64 and ARM64 CPUs in\n`TryNewCRC32AcceleratedX86ARMCombined` previously fell back to a\nsingle-stream CRC32C implementation even when hardware carry-less\nmultiplication and SHA3 (`EOR3`) were available, and ARM64 builds\nwithout `-march\u003darmv8-a+crc+crypto` disabled hardware CRC32C entirely.\n\nAdd `SupportsAvx2()` and `SupportsArmSHA3()` runtime feature checks to\n`cpu_detect`, enable ARM64 CRC32/PMULL intrinsics via `.arch_extension`\npragmas guarded by runtime detection, and dispatch multi-stream `PCLMUL`\n/ `NEON_PCLMUL_EOR3` kernels by default when supported.\n\nPiperOrigin-RevId: 995516057\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
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      "new_mode": 33188,
      "new_path": "absl/base/internal/cpu_detect.cc"
    },
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      "new_path": "absl/base/internal/cpu_detect.h"
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      "new_id": "1bfc8319ea33ded67a148f637434e65639da305f",
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      "new_path": "absl/base/internal/cpu_detect_test.cc"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "absl/crc/internal/crc32_x86_arm_combined_simd.h",
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      "new_mode": 33188,
      "new_path": "absl/crc/internal/crc32_x86_arm_combined_simd.h"
    },
    {
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      "old_path": "absl/crc/internal/crc32c_inline.h",
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      "new_mode": 33188,
      "new_path": "absl/crc/internal/crc32c_inline.h"
    },
    {
      "type": "modify",
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      "old_path": "absl/crc/internal/crc_x86_arm_combined.cc",
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      "new_path": "absl/crc/internal/crc_x86_arm_combined.cc"
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}