systemrdl: Correct the default register width to 32 bits.

This fixes major errors in the soc_ifc offsets, as unlike the other
register blocks, the soc_ifc RDL didn't define a default register width.
Whoops. To validate, compare the offsets to the addresses from the python scripts:

  CLP_SOC_IFC_REG_CPTRA_HW_ERROR_FATAL                  0x30030000
  CLP_SOC_IFC_REG_CPTRA_HW_ERROR_NON_FATAL              0x30030004
  CLP_SOC_IFC_REG_CPTRA_FW_ERROR_FATAL                  0x30030008
  CLP_SOC_IFC_REG_CPTRA_FW_ERROR_NON_FATAL              0x3003000c
  CLP_SOC_IFC_REG_CPTRA_HW_ERROR_ENC                    0x30030010
  CLP_SOC_IFC_REG_CPTRA_FW_ERROR_ENC                    0x30030014
  CLP_SOC_IFC_REG_CPTRA_BOOT_STATUS                     0x30030018
  CLP_SOC_IFC_REG_CPTRA_FLOW_STATUS                     0x3003001c
  CLP_SOC_IFC_REG_CPTRA_RESET_REASON                    0x30030020
  CLP_SOC_IFC_REG_CPTRA_SECURITY_STATE                  0x30030024
  CLP_SOC_IFC_REG_CPTRA_VALID_PAUSER_0                  0x30030028
  CLP_SOC_IFC_REG_CPTRA_PAUSER_LOCK_0                   0x3003003c
  CLP_SOC_IFC_REG_CPTRA_TRNG_VALID_PAUSER               0x30030050
  CLP_SOC_IFC_REG_CPTRA_TRNG_PAUSER_LOCK                0x30030054
  CLP_SOC_IFC_REG_CPTRA_TRNG_DATA_0                     0x30030058
  CLP_SOC_IFC_REG_CPTRA_TRNG_STATUS                     0x30030088
  CLP_SOC_IFC_REG_CPTRA_FUSE_WR_DONE                    0x3003008c
  CLP_SOC_IFC_REG_CPTRA_TIMER_CONFIG                    0x30030090
  CLP_SOC_IFC_REG_CPTRA_BOOTFSM_GO                      0x30030094
  CLP_SOC_IFC_REG_CPTRA_DBG_MANUF_SERVICE_REG           0x30030098
  CLP_SOC_IFC_REG_CPTRA_CLK_GATING_EN                   0x3003009c
  CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0           0x300300a0
  CLP_SOC_IFC_REG_CPTRA_GENERIC_OUTPUT_WIRES_0          0x300300a8
  CLP_SOC_IFC_REG_FUSE_UDS_SEED_0                       0x30030200
  CLP_SOC_IFC_REG_FUSE_FIELD_ENTROPY_0                  0x30030230
  CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_0           0x30030250
  CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_PK_HASH_MASK        0x30030280
  CLP_SOC_IFC_REG_FUSE_OWNER_PK_HASH_0                  0x30030284
  CLP_SOC_IFC_REG_FUSE_KEY_MANIFEST_SVN                 0x300302b4
  CLP_SOC_IFC_REG_FUSE_RUNTIME_SVN_0                    0x300302b8
  CLP_SOC_IFC_REG_FUSE_ANTI_ROLLBACK_DISABLE            0x300302c8
  CLP_SOC_IFC_REG_FUSE_IDEVID_CERT_ATTR_0               0x300302cc
  CLP_SOC_IFC_REG_FUSE_IDEVID_MANUF_HSM_ID_0            0x3003032c
  CLP_SOC_IFC_REG_FUSE_LIFE_CYCLE                       0x3003033c
  CLP_SOC_IFC_REG_INTERNAL_OBF_KEY_0                    0x30030600
  CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK                    0x30030620
  CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET              0x30030624
  CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES  0x30030628
  CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR                   0x3003062c