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| |
| <p>Queue Element Transfer Descriptor (section 3.5) |
| <a href="structehci__qtd__t.html#details">More...</a></p> |
| |
| <p><code>#include <<a class="el" href="ehci_8h_source.html">ehci.h</a>></code></p> |
| <table class="memberdecls"> |
| <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> |
| Data Fields</h2></td></tr> |
| <tr class="memitem:a8f18d97ad3c8b23a16c6b07c3ce58113"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8f18d97ad3c8b23a16c6b07c3ce58113"></a> |
| <a class="el" href="unionehci__link__t.html">ehci_link_t</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a8f18d97ad3c8b23a16c6b07c3ce58113">next</a></td></tr> |
| <tr class="memdesc:a8f18d97ad3c8b23a16c6b07c3ce58113"><td class="mdescLeft"> </td><td class="mdescRight">Word 0: Next QTD Pointer. <br/></td></tr> |
| <tr class="separator:a8f18d97ad3c8b23a16c6b07c3ce58113"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ac1fb742b97bc51c5bdefd18c7624a854"><td class="memItemLeft" ><a class="anchor" id="ac1fb742b97bc51c5bdefd18c7624a854"></a> |
| union {</td></tr> |
| <tr class="memitem:a2d656b24a289bce22fa7180a54b0e9f7"><td class="memItemLeft" ><a class="anchor" id="a2d656b24a289bce22fa7180a54b0e9f7"></a> |
|    <a class="el" href="unionehci__link__t.html">ehci_link_t</a>   <b>alternate</b></td></tr> |
| <tr class="separator:a2d656b24a289bce22fa7180a54b0e9f7"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a2ee6a60584817def95f0c6db8df1ff56"><td class="memItemLeft" ><a class="anchor" id="a2ee6a60584817def95f0c6db8df1ff56"></a> |
|    struct {</td></tr> |
| <tr class="memitem:a3e57c2ef1c3ffb36722f000cc1156824"><td class="memItemLeft" ><a class="anchor" id="a3e57c2ef1c3ffb36722f000cc1156824"></a> |
|       uint32_t   <b>__pad0__</b>: 5</td></tr> |
| <tr class="separator:a3e57c2ef1c3ffb36722f000cc1156824"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a5e1ebda31e026934b2091d2d0051818a"><td class="memItemLeft" ><a class="anchor" id="a5e1ebda31e026934b2091d2d0051818a"></a> |
|       uint32_t   <b>used</b>: 1</td></tr> |
| <tr class="separator:a5e1ebda31e026934b2091d2d0051818a"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a6712ba6dd1d5b43d2d56ff8ac4e275a7"><td class="memItemLeft" ><a class="anchor" id="a6712ba6dd1d5b43d2d56ff8ac4e275a7"></a> |
|       uint32_t   <b>__pad1__</b>: 10</td></tr> |
| <tr class="separator:a6712ba6dd1d5b43d2d56ff8ac4e275a7"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ad4aa318988b065f700e50ebfd3e8c996"><td class="memItemLeft" ><a class="anchor" id="ad4aa318988b065f700e50ebfd3e8c996"></a> |
|       uint32_t   <b>expected_bytes</b>: 16</td></tr> |
| <tr class="separator:ad4aa318988b065f700e50ebfd3e8c996"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a2ee6a60584817def95f0c6db8df1ff56"><td class="memItemLeft" valign="top">   } </td><td class="memItemRight" valign="bottom"></td></tr> |
| <tr class="separator:a2ee6a60584817def95f0c6db8df1ff56"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ac1fb742b97bc51c5bdefd18c7624a854"><td class="memItemLeft" valign="top">}; </td><td class="memItemRight" valign="bottom"></td></tr> |
| <tr class="memdesc:ac1fb742b97bc51c5bdefd18c7624a854"><td class="mdescLeft"> </td><td class="mdescRight">Word 1: Alternate Next QTD Pointer (not used) <br/></td></tr> |
| <tr class="separator:ac1fb742b97bc51c5bdefd18c7624a854"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ad11316a45c6c93ce6ed877a85bae22cc"><td class="memItemLeft" align="right" valign="top">volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#ad11316a45c6c93ce6ed877a85bae22cc">pingstate_err</a>: 1</td></tr> |
| <tr class="memdesc:ad11316a45c6c93ce6ed877a85bae22cc"><td class="mdescLeft"> </td><td class="mdescRight">Word 2: qTQ Token. <a href="#ad11316a45c6c93ce6ed877a85bae22cc">More...</a><br/></td></tr> |
| <tr class="separator:ad11316a45c6c93ce6ed877a85bae22cc"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a3c59cc1abe2e59d21b7eec030756a05c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3c59cc1abe2e59d21b7eec030756a05c"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a3c59cc1abe2e59d21b7eec030756a05c">non_hs_split_state</a>: 1</td></tr> |
| <tr class="memdesc:a3c59cc1abe2e59d21b7eec030756a05c"><td class="mdescLeft"> </td><td class="mdescRight">This bit is ignored by the host controller unless the QH.EPSfield indicates a full- or low-speed endpoint. When a Full- or Low-speed device, the host controller uses this bit to track the state of the split-transaction. The functional requirements of the host controller for managing this state bit and the split transaction protocol depends on whether the endpoint is in the periodic or asynchronous schedule. 0b=Start Split 1b=Complete Split. <br/></td></tr> |
| <tr class="separator:a3c59cc1abe2e59d21b7eec030756a05c"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a498b5535c7cf059f57a3589bce719798"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a498b5535c7cf059f57a3589bce719798"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a498b5535c7cf059f57a3589bce719798">non_hs_period_missed_uframe</a>: 1</td></tr> |
| <tr class="memdesc:a498b5535c7cf059f57a3589bce719798"><td class="mdescLeft"> </td><td class="mdescRight">This bit is ignored unless the QH.EPSfield indicates a full- or low-speed endpoint and the queue head is in the periodic list. This bit is set when the host controller detected that a host-induced hold-off caused the host controller to miss a required complete-split transaction. If the host controller sets this bit to a one, then it remains a one for the duration of the transfer. <br/></td></tr> |
| <tr class="separator:a498b5535c7cf059f57a3589bce719798"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:aa4df80679605a496760b6d1d1c9a58b1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa4df80679605a496760b6d1d1c9a58b1"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#aa4df80679605a496760b6d1d1c9a58b1">xact_err</a>: 1</td></tr> |
| <tr class="memdesc:aa4df80679605a496760b6d1d1c9a58b1"><td class="mdescLeft"> </td><td class="mdescRight">Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.) <br/></td></tr> |
| <tr class="separator:aa4df80679605a496760b6d1d1c9a58b1"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a55dfaf1427c6b0df79f79b7b3be5990c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a55dfaf1427c6b0df79f79b7b3be5990c"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a55dfaf1427c6b0df79f79b7b3be5990c">babble_err</a>: 1</td></tr> |
| <tr class="memdesc:a55dfaf1427c6b0df79f79b7b3be5990c"><td class="mdescLeft"> </td><td class="mdescRight">Set to a 1 by the Host Controller during status update when a babble is detected during the transaction. In addition to setting this bit, the Host Controller also sets the Haltedbit to a 1. <br/></td></tr> |
| <tr class="separator:a55dfaf1427c6b0df79f79b7b3be5990c"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:ac5db4563dd2d98e90747f9969a338033"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac5db4563dd2d98e90747f9969a338033"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#ac5db4563dd2d98e90747f9969a338033">buffer_err</a>: 1</td></tr> |
| <tr class="memdesc:ac5db4563dd2d98e90747f9969a338033"><td class="mdescLeft"> </td><td class="mdescRight">Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun) <br/></td></tr> |
| <tr class="separator:ac5db4563dd2d98e90747f9969a338033"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:afba6c232011eb90b18a032d8b8d0c821"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afba6c232011eb90b18a032d8b8d0c821"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#afba6c232011eb90b18a032d8b8d0c821">halted</a>: 1</td></tr> |
| <tr class="memdesc:afba6c232011eb90b18a032d8b8d0c821"><td class="mdescLeft"> </td><td class="mdescRight">Set to a 1 by the Host Controller during status updates to indicate that a serious error has occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the error counter counting down to zero, or reception of the STALL handshake from the device during a transaction. Any time that a transaction results in the Halted bit being set to a one, the Active bit is also set to 0. <br/></td></tr> |
| <tr class="separator:afba6c232011eb90b18a032d8b8d0c821"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a4e55231d0adda8f7262ab94d443cc7af"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4e55231d0adda8f7262ab94d443cc7af"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a4e55231d0adda8f7262ab94d443cc7af">active</a>: 1</td></tr> |
| <tr class="memdesc:a4e55231d0adda8f7262ab94d443cc7af"><td class="mdescLeft"> </td><td class="mdescRight">Set to 1 by software to enable the execution of transactions by the Host Controller. <br/></td></tr> |
| <tr class="separator:a4e55231d0adda8f7262ab94d443cc7af"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:aec32162d9dc3fde2c76d766af522dae5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aec32162d9dc3fde2c76d766af522dae5"></a> |
| uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#aec32162d9dc3fde2c76d766af522dae5">pid</a>: 2</td></tr> |
| <tr class="memdesc:aec32162d9dc3fde2c76d766af522dae5"><td class="mdescLeft"> </td><td class="mdescRight">This field is an encoding of the token which should be used for transactions associated with this transfer descriptor. 00=OUT 01=IN 10=SETUP. <br/></td></tr> |
| <tr class="separator:aec32162d9dc3fde2c76d766af522dae5"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a64178f7682c6e5c0d4e75f9eb7ab6ceb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a64178f7682c6e5c0d4e75f9eb7ab6ceb"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a64178f7682c6e5c0d4e75f9eb7ab6ceb">cerr</a>: 2</td></tr> |
| <tr class="memdesc:a64178f7682c6e5c0d4e75f9eb7ab6ceb"><td class="mdescLeft"> </td><td class="mdescRight">Error Counter, This field is a 2-bit down counter that keeps track of the number of consecutive Errors detected while executing this qTD. <br/></td></tr> |
| <tr class="separator:a64178f7682c6e5c0d4e75f9eb7ab6ceb"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a77f2f1b04b66aeb3651fc2c42bc61302"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a77f2f1b04b66aeb3651fc2c42bc61302"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a77f2f1b04b66aeb3651fc2c42bc61302">current_page</a>: 3</td></tr> |
| <tr class="memdesc:a77f2f1b04b66aeb3651fc2c42bc61302"><td class="mdescLeft"> </td><td class="mdescRight">This field is used as an index into the qTD buffer pointer list. <br/></td></tr> |
| <tr class="separator:a77f2f1b04b66aeb3651fc2c42bc61302"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a0696e82e3bbfbb1798cc96c8fe0cb218"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0696e82e3bbfbb1798cc96c8fe0cb218"></a> |
| uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a0696e82e3bbfbb1798cc96c8fe0cb218">int_on_complete</a>: 1</td></tr> |
| <tr class="memdesc:a0696e82e3bbfbb1798cc96c8fe0cb218"><td class="mdescLeft"> </td><td class="mdescRight">If this bit is set to a one, it specifies that when this qTD is completed, the Host Controller should issue an interrupt at the next interrupt threshold. <br/></td></tr> |
| <tr class="separator:a0696e82e3bbfbb1798cc96c8fe0cb218"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:aef59a84424da042ebcfce5c9bc7a229d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aef59a84424da042ebcfce5c9bc7a229d"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#aef59a84424da042ebcfce5c9bc7a229d">total_bytes</a>: 15</td></tr> |
| <tr class="memdesc:aef59a84424da042ebcfce5c9bc7a229d"><td class="mdescLeft"> </td><td class="mdescRight">This field specifies the total number of bytes to be moved with this transfer descriptor. <br/></td></tr> |
| <tr class="separator:aef59a84424da042ebcfce5c9bc7a229d"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:a531c19a9795e64ce69fc75d99acda659"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a531c19a9795e64ce69fc75d99acda659"></a> |
| volatile uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#a531c19a9795e64ce69fc75d99acda659">data_toggle</a>: 1</td></tr> |
| <tr class="memdesc:a531c19a9795e64ce69fc75d99acda659"><td class="mdescLeft"> </td><td class="mdescRight">This is the data toggle sequence bit. <br/></td></tr> |
| <tr class="separator:a531c19a9795e64ce69fc75d99acda659"><td class="memSeparator" colspan="2"> </td></tr> |
| <tr class="memitem:aedf420ce97c6830704676786330d6bb2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aedf420ce97c6830704676786330d6bb2"></a> |
| uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structehci__qtd__t.html#aedf420ce97c6830704676786330d6bb2">buffer</a> [5]</td></tr> |
| <tr class="memdesc:aedf420ce97c6830704676786330d6bb2"><td class="mdescLeft"> </td><td class="mdescRight">Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page. <br/></td></tr> |
| <tr class="separator:aedf420ce97c6830704676786330d6bb2"><td class="memSeparator" colspan="2"> </td></tr> |
| </table> |
| <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2> |
| <div class="textblock"><p>Queue Element Transfer Descriptor (section 3.5) </p> |
| |
| <p>Definition at line <a class="el" href="ehci_8h_source.html#l00113">113</a> of file <a class="el" href="ehci_8h_source.html">ehci.h</a>.</p> |
| </div><h2 class="groupheader">Field Documentation</h2> |
| <a class="anchor" id="ad11316a45c6c93ce6ed877a85bae22cc"></a> |
| <div class="memitem"> |
| <div class="memproto"> |
| <table class="memname"> |
| <tr> |
| <td class="memname">volatile uint32_t pingstate_err</td> |
| </tr> |
| </table> |
| </div><div class="memdoc"> |
| |
| <p>Word 2: qTQ Token. </p> |
| <p>If the QH.EPSfield indicates a High-speed device and the PID_Codeindicates an OUT endpoint, then this is the state bit for the Ping protocol. 0b=OUT 1b=PING </p> |
| |
| <p>Definition at line <a class="el" href="ehci_8h_source.html#l00130">130</a> of file <a class="el" href="ehci_8h_source.html">ehci.h</a>.</p> |
| |
| </div> |
| </div> |
| <hr/>The documentation for this struct was generated from the following file:<ul> |
| <li>tinyusb/host/ehci/<a class="el" href="ehci_8h_source.html">ehci.h</a></li> |
| </ul> |
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