ch32h417: fix USBHS EP0 SETUP re-detect, EP0-OUT toggle, SOF dispatch

Apply correctness-review findings on the USB2 HS dcd (still pre-hardware):

- EP0 control OUT arming now writes the full UEP0_RX_CTRL byte (DATA1|ACK) instead
  of a read-modify-write, so RB_UEP_R_SETUP_IS is cleared - otherwise the data/
  status OUT following a SETUP would be re-detected as a new SETUP and every control
  transfer after the first would break. The SETUP handler likewise writes full
  TX/RX bytes. This also fixes the missing DATA1 expected-toggle on a control-write
  data stage.
- Add the SOF interrupt branch (USBHS_UDIF_RX_SOF is a top-level INT_FG bit on this
  IP, not an INT_ST token): dcd_sof_enable() armed SOF but the ISR dropped it, so
  dcd_event_sof() was never delivered.
- Drop the extra INT_FG=USBHS_UDIF_TRANSFER write: the vendor acknowledges a
  transfer solely by clearing the per-endpoint DONE bit; the aggregate write could
  clear a second endpoint's still-pending completion (only one is serviced per IRQ).

Build-verified (SPEED=high links). Hardware validation still pending.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01QWhrtHjbSVMKcY68vxBwBm