stm32u5 nucleo: clear the VBUS override while VBUS is absent

A tud_deinit()/tud_init() pair inside one 1 ms ADC sample is not seen by
the ISR, so the resync window is not re-armed: dcd_init() forces the
override on and, with VBUS sensed absent and unchanged, the ISR never
writes it again. The core then reports a valid session with no VBUS.

While VBUS is sensed absent, read the override bits and clear them when
set. No host is attached then, so no slave-mode TX FIFO push can collide
with the reads; with VBUS present OTG is still touched only on change.