)]}'
{
  "commit": "8a9210069b5a37dd89ed118a783945502a30a4ae",
  "tree": "070437e7039f01f4feb7b7713c0ce6f38bbd9aef",
  "parents": [
    "e414c0446436ed34151de3158d18f8ae32e55d03"
  ],
  "author": {
    "name": "fbarchard",
    "email": "fbarchard@google.com",
    "time": "Fri Aug 08 07:49:05 2025 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Aug 08 07:49:05 2025 -0700"
  },
  "message": "Add Intel Tremont uarch (#305)\n\nTremont is the e-core (10nm Atom) in Jasperlake,Elkhart Lake, Jacobville and Lakefield\n\nThe family/model are supported by linux\nhttps://github.com/torvalds/linux/blob/master/arch/x86/include/asm/intel-family.h#L176-L178\nDocumented on wikichip\nhttps://en.wikichip.org/wiki/intel/cpuid#Small_Cores\nSupported by Intel sde -tnt\n\nReordered e-core uarch by generation\ndarkmont is an e-core used in both hybrid laptops and server, so move to ecore\ngracemont model 0xBE is confirmed for Alderlake N, so redocument support\n\nPredecessor Goldmont Plus\nSuccessor Gracemont",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "891416abda6be266f46e9115b7d7d06ea74e8c62",
      "old_mode": 33188,
      "old_path": "include/cpuinfo.h",
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      "new_mode": 33188,
      "new_path": "include/cpuinfo.h"
    },
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      "old_id": "2f4292bbb4e4629f2ec8fa4149743fc4cdba9508",
      "old_mode": 33188,
      "old_path": "src/x86/uarch.c",
      "new_id": "a0c900f4350ecdd61e906a8d9e24a803f1e71773",
      "new_mode": 33188,
      "new_path": "src/x86/uarch.c"
    },
    {
      "type": "modify",
      "old_id": "d1ba2d48f7b695a1557e879d1fd670c549c7a77d",
      "old_mode": 33188,
      "old_path": "tools/cpu-info.c",
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      "new_mode": 33188,
      "new_path": "tools/cpu-info.c"
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}