)]}'
{
  "commit": "3681f0ce1446167d01dfe125d6db96ba2ac31c3c",
  "tree": "e7ff9a6a208587e7a4a4ec1ff377fca2a70b2668",
  "parents": [
    "e829e80faba35db623b5e272c867ad72146adcda"
  ],
  "author": {
    "name": "Nicolas Pitre",
    "email": "nico@fluxnic.net",
    "time": "Thu Apr 30 19:06:12 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Apr 30 16:06:12 2026 -0700"
  },
  "message": "Add Cortex-A320 to MIDR decode table (#384)\n\nARM Cortex-A320 (MIDR part 0xD8F) is an ARMv9.2-A efficiency core.\nAdd its uarch enum and MIDR mapping so XNNPACK can select optimized\nkernels when running on this core.\n\nSigned-off-by: Nicolas Pitre \u003cnpitre@baylibre.com\u003e",
  "tree_diff": [
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