)]}'
{
  "commit": "aa17d6d98218683e6cd3d8a55939e8279e9bc2b1",
  "tree": "bb3e5330f518a9d232fe5d9e1c550bb8abdb812b",
  "parents": [
    "a7b796d5e6fa1b066757982b805ab59c5fa53e71"
  ],
  "author": {
    "name": "Jonathan Bell",
    "email": "jonathan@raspberrypi.com",
    "time": "Wed May 14 14:10:48 2025 +0100"
  },
  "committer": {
    "name": "P33M",
    "email": "2474547+P33M@users.noreply.github.com",
    "time": "Wed May 14 14:16:56 2025 +0100"
  },
  "message": "probe: correct SWCLK calculations\n\nUse the actual clk_sys frequency and Round divisors up, otherwise high\nswclk speeds get significantly overclocked.\n",
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      "new_path": "blah.patch"
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