)]}'
{
  "commit": "ae5bdb082da25d3f0fa59db22db17c00c741a4f4",
  "tree": "a53252b7964d81f0e7f120c6e6ec893507600d89",
  "parents": [
    "491b96c1d499f3a79d173db1452022112631e531"
  ],
  "author": {
    "name": "Luke Wren",
    "email": "wren6991@gmail.com",
    "time": "Tue May 09 11:29:43 2023 +0100"
  },
  "committer": {
    "name": "Luke Wren",
    "email": "wren6991@gmail.com",
    "time": "Tue May 09 11:29:53 2023 +0100"
  },
  "message": "Reduce SWCLK frequency from SM/2 to SM/4, to reduce dead cycles.\nAlso fix divider becoming 0 when extremely high SWCLK frequencies\nare requested (this would have been safe but you would get an\nextremely slow SWCLK).\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6f544f035b80e2a8379765c4f92997fb0f3c598f",
      "old_mode": 33188,
      "old_path": "src/probe.c",
      "new_id": "b1d0d9d504903f254014b0cfd223b343171169b2",
      "new_mode": 33188,
      "new_path": "src/probe.c"
    },
    {
      "type": "modify",
      "old_id": "b1769490a858b6f54a748a55b4c94686fd1df85c",
      "old_mode": 33188,
      "old_path": "src/probe.pio",
      "new_id": "e3b2a259bc27c27977cf98ab601c242680c3dce5",
      "new_mode": 33188,
      "new_path": "src/probe.pio"
    }
  ]
}