src/rp2040/hardware_regs/rp2040.svd

<?xml version="1.0" encoding="utf-8"?>
<!--
  Copyright (c) 2020 Raspberry Pi (Trading) Ltd.

  SPDX-License-Identifier: BSD-3-Clause
-->
<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  <addressUnitBits>8</addressUnitBits>
  <vendor>Raspberry Pi</vendor>
  <name>RP2040</name>
  <licenseText>
    Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n
    \n
    SPDX-License-Identifier: BSD-3-Clause
  </licenseText>
  <version>0.1</version>
  <width>32</width>
  <cpu>
    <name>CM0PLUS</name>
    <revision>r0p1</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <nvicPrioBits>2</nvicPrioBits>
    <vtorPresent>1</vtorPresent>
    <vendorSystickConfig>false</vendorSystickConfig>
    <deviceNumInterrupts>26</deviceNumInterrupts>
  </cpu>
  <peripherals>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x0020</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x14000000</baseAddress>
      <description>QSPI flash execute-in-place block</description>
      <interrupt>
        <name>XIP_IRQ</name>
        <value>6</value>
      </interrupt>
      <name>XIP_CTRL</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Cache control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>When 1, the cache memories are powered down. They retain state,\n
                but can not be accessed. This reduces static power dissipation.\n
                Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n
                be enabled when powered down.\n
                Cache-as-SRAM accesses will produce a bus error response when\n
                the cache is powered down.</description>
              <name>POWER_DOWN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>When 1, writes to any alias other than 0x0 (caching, allocating)\n
                will produce a bus fault. When 0, these writes are silently ignored.\n
                In either case, writes to the 0x0 alias will deallocate on tag match,\n
                as usual.</description>
              <name>ERR_BADWRITE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>When 1, enable the cache. When the cache is disabled, all XIP accesses\n
                will go straight to the flash, without querying the cache. When enabled,\n
                cacheable XIP accesses will query the cache, and the flash will\n
                not be accessed if the tag matches and the valid bit is set.\n\n
                If the cache is enabled, cache-as-SRAM accesses have no effect on the\n
                cache data RAM, and will produce a bus error response.</description>
              <name>EN</name>
            </field>
          </fields>
          <name>CTRL</name>
          <resetValue>0x00000003</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Cache Flush control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Write 1 to flush the cache. This clears the tag memory, but\n
                the data memory retains its contents. (This means cache-as-SRAM\n
                contents is not affected by flush or reset.)\n
                Reading will hold the bus (stall the processor) until the flush\n
                completes. Alternatively STAT can be polled until completion.</description>
              <modifiedWriteValues>clear</modifiedWriteValues>
              <name>FLUSH</name>
            </field>
          </fields>
          <name>FLUSH</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Cache Status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>When 1, indicates the XIP streaming FIFO is completely full.\n
                The streaming FIFO is 2 entries deep, so the full and empty\n
                flag allow its level to be ascertained.</description>
              <name>FIFO_FULL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>When 1, indicates the XIP streaming FIFO is completely empty.</description>
              <name>FIFO_EMPTY</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Reads as 0 while a cache flush is in progress, and 1 otherwise.\n
                The cache is flushed whenever the XIP block is reset, and also\n
                when requested via the FLUSH register.</description>
              <name>FLUSH_READY</name>
            </field>
          </fields>
          <name>STAT</name>
          <resetValue>0x00000002</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x000c</addressOffset>
          <description>Cache Hit counter\n
            A 32 bit saturating counter that increments upon each cache hit,\n
            i.e. when an XIP access is serviced directly from cached data.\n
            Write any value to clear.</description>
          <modifiedWriteValues>oneToClear</modifiedWriteValues>
          <name>CTR_HIT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0010</addressOffset>
          <description>Cache Access counter\n
            A 32 bit saturating counter that increments upon each XIP access,\n
            whether the cache is hit or not. This includes noncacheable accesses.\n
            Write any value to clear.</description>
          <modifiedWriteValues>oneToClear</modifiedWriteValues>
          <name>CTR_ACC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>FIFO stream address</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:2]</bitRange>
              <description>The address of the next word to be streamed from flash to the streaming FIFO.\n
                Increments automatically after each flash access.\n
                Write the initial access address here before starting a streaming read.</description>
              <name>STREAM_ADDR</name>
            </field>
          </fields>
          <name>STREAM_ADDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>FIFO stream control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[21:0]</bitRange>
              <description>Write a nonzero value to start a streaming read. This will then\n
                progress in the background, using flash idle cycles to transfer\n
                a linear data block from flash to the streaming FIFO.\n
                Decrements automatically (1 at a time) as the stream\n
                progresses, and halts on reaching 0.\n
                Write 0 to halt an in-progress stream, and discard any in-flight\n
                read, so that a new stream can immediately be started (after\n
                draining the FIFO and reinitialising STREAM_ADDR)</description>
              <name>STREAM_CTR</name>
            </field>
          </fields>
          <name>STREAM_CTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x001c</addressOffset>
          <description>FIFO stream data\n
            Streamed data is buffered here, for retrieval by the system DMA.\n
            This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n
            the DMA to bus stalls caused by other XIP traffic.</description>
          <name>STREAM_FIFO</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x0100</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x18000000</baseAddress>
      <description>DW_apb_ssi has the following features:\n
        * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n
        * APB3 and APB4 protocol support.\n
        * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n
        * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n
        * Programmable Dual/Quad/Octal SPI support in Master Mode.\n
        * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n
        * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n
        * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n
        * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n
        * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n
        * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n
        * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n
        * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n
        * Programmable features:\n
        - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n
        - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n
        - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n
        * Configured features:\n
        - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n
        - 1 slave select output.\n
        - Hardware slave-select – Dedicated hardware slave-select line.\n
        - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n
        - Interrupt polarity – active high interrupt lines.\n
        - Serial clock polarity – low serial-clock polarity directly after reset.\n
        - Serial clock phase – capture on first edge of serial-clock directly after reset.</description>
      <name>XIP_SSI</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Control register 0</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <description>Slave select toggle enable</description>
              <name>SSTE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:21]</bitRange>
              <description>SPI frame format</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex</description>
                  <name>STD</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Dual-SPI frame format; two bits per SCK, half-duplex</description>
                  <name>DUAL</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Quad-SPI frame format; four bits per SCK, half-duplex</description>
                  <name>QUAD</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SPI_FRF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:16]</bitRange>
              <description>Data frame size in 32b transfer mode\n
                Value of n -&gt; n+1 clocks per frame.</description>
              <name>DFS_32</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:12]</bitRange>
              <description>Control frame size\n
                Value of n -&gt; n+1 clocks per frame.</description>
              <name>CFS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Shift register loop (test mode)</description>
              <name>SRL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Slave output enable</description>
              <name>SLV_OE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Transfer mode</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Both transmit and receive</description>
                  <name>TX_AND_RX</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Transmit only (not for FRF == 0, standard SPI mode)</description>
                  <name>TX_ONLY</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Receive only (not for FRF == 0, standard SPI mode)</description>
                  <name>RX_ONLY</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>EEPROM read mode (TX then RX; RX starts after control data TX'd)</description>
                  <name>EEPROM_READ</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TMOD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Serial clock polarity</description>
              <name>SCPOL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Serial clock phase</description>
              <name>SCPH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:4]</bitRange>
              <description>Frame format</description>
              <name>FRF</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <description>Data frame size</description>
              <name>DFS</name>
            </field>
          </fields>
          <name>CTRLR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Master Control register 1</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>Number of data frames</description>
              <name>NDF</name>
            </field>
          </fields>
          <name>CTRLR1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>SSI Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>SSI enable</description>
              <name>SSI_EN</name>
            </field>
          </fields>
          <name>SSIENR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Microwire Control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Microwire handshaking</description>
              <name>MHS</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Microwire control</description>
              <name>MDD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Microwire transfer mode</description>
              <name>MWMOD</name>
            </field>
          </fields>
          <name>MWCR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Slave enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>For each bit:\n
                0 -&gt; slave not selected\n
                1 -&gt; slave selected</description>
              <name>SER</name>
            </field>
          </fields>
          <name>SER</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Baud rate</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[15:0]</bitRange>
              <description>SSI clock divider</description>
              <name>SCKDV</name>
            </field>
          </fields>
          <name>BAUDR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>TX FIFO threshold level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Transmit FIFO threshold</description>
              <name>TFT</name>
            </field>
          </fields>
          <name>TXFTLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>RX FIFO threshold level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive FIFO threshold</description>
              <name>RFT</name>
            </field>
          </fields>
          <name>RXFTLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0020</addressOffset>
          <description>TX FIFO level</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>Transmit FIFO level</description>
              <name>TFTFL</name>
            </field>
          </fields>
          <name>TXFLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>RX FIFO level</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive FIFO level</description>
              <name>RXTFL</name>
            </field>
          </fields>
          <name>RXFLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Status register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <description>Data collision error</description>
              <name>DCOL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Transmission error</description>
              <name>TXE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full</description>
              <name>RFF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO not empty</description>
              <name>RFNE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Transmit FIFO empty</description>
              <name>TFE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO not full</description>
              <name>TFNF</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>SSI busy flag</description>
              <name>BUSY</name>
            </field>
          </fields>
          <name>SR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x002c</addressOffset>
          <description>Interrupt mask</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Multi-master contention interrupt mask</description>
              <name>MSTIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full interrupt mask</description>
              <name>RXFIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO overflow interrupt mask</description>
              <name>RXOIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO underflow interrupt mask</description>
              <name>RXUIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO overflow interrupt mask</description>
              <name>TXOIM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Transmit FIFO empty interrupt mask</description>
              <name>TXEIM</name>
            </field>
          </fields>
          <name>IMR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Interrupt status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Multi-master contention interrupt status</description>
              <name>MSTIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full interrupt status</description>
              <name>RXFIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO overflow interrupt status</description>
              <name>RXOIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO underflow interrupt status</description>
              <name>RXUIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO overflow interrupt status</description>
              <name>TXOIS</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Transmit FIFO empty interrupt status</description>
              <name>TXEIS</name>
            </field>
          </fields>
          <name>ISR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Raw interrupt status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <description>Multi-master contention raw interrupt status</description>
              <name>MSTIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Receive FIFO full raw interrupt status</description>
              <name>RXFIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <description>Receive FIFO overflow raw interrupt status</description>
              <name>RXOIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <description>Receive FIFO underflow raw interrupt status</description>
              <name>RXUIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit FIFO overflow raw interrupt status</description>
              <name>TXOIR</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Transmit FIFO empty raw interrupt status</description>
              <name>TXEIR</name>
            </field>
          </fields>
          <name>RISR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0038</addressOffset>
          <description>TX FIFO overflow interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read transmit FIFO overflow interrupt</description>
              <name>TXOICR</name>
            </field>
          </fields>
          <name>TXOICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>RX FIFO overflow interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read receive FIFO overflow interrupt</description>
              <name>RXOICR</name>
            </field>
          </fields>
          <name>RXOICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>RX FIFO underflow interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read receive FIFO underflow interrupt</description>
              <name>RXUICR</name>
            </field>
          </fields>
          <name>RXUICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0044</addressOffset>
          <description>Multi-master interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read multi-master contention interrupt</description>
              <name>MSTICR</name>
            </field>
          </fields>
          <name>MSTICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Interrupt clear</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clear-on-read all active interrupts</description>
              <name>ICR</name>
            </field>
          </fields>
          <name>ICR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x004c</addressOffset>
          <description>DMA control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Transmit DMA enable</description>
              <name>TDMAE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Receive DMA enable</description>
              <name>RDMAE</name>
            </field>
          </fields>
          <name>DMACR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0050</addressOffset>
          <description>DMA TX data level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Transmit data watermark level</description>
              <name>DMATDL</name>
            </field>
          </fields>
          <name>DMATDLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>DMA RX data level</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Receive data watermark level (DMARDLR+1)</description>
              <name>DMARDL</name>
            </field>
          </fields>
          <name>DMARDLR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Identification register</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:0]</bitRange>
              <description>Peripheral dentification code</description>
              <name>IDCODE</name>
            </field>
          </fields>
          <name>IDR</name>
          <resetValue>0x51535049</resetValue>
        </register>
        <register>
          <addressOffset>0x005c</addressOffset>
          <description>Version ID</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:0]</bitRange>
              <description>SNPS component version (format X.YY)</description>
              <name>SSI_COMP_VERSION</name>
            </field>
          </fields>
          <name>SSI_VERSION_ID</name>
          <resetValue>0x3430312a</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Data Register 0 (of 36)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:0]</bitRange>
              <description>First data register of 36</description>
              <name>DR</name>
            </field>
          </fields>
          <name>DR0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f0</addressOffset>
          <description>RX sample delay</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>RXD sample delay (in SCLK cycles)</description>
              <name>RSD</name>
            </field>
          </fields>
          <name>RX_SAMPLE_DLY</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f4</addressOffset>
          <description>SPI control</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:24]</bitRange>
              <description>SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)</description>
              <name>XIP_CMD</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <description>Read data strobe enable</description>
              <name>SPI_RXDS_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <description>Instruction DDR transfer enable</description>
              <name>INST_DDR_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>SPI DDR transfer enable</description>
              <name>SPI_DDR_EN</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:11]</bitRange>
              <description>Wait cycles between control frame transmit and data reception (in SCLK cycles)</description>
              <name>WAIT_CYCLES</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Instruction length (0/4/8/16b)</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>No instruction</description>
                  <name>NONE</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>4-bit instruction</description>
                  <name>4B</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>8-bit instruction</description>
                  <name>8B</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>16-bit instruction</description>
                  <name>16B</name>
                  <value>3</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>INST_L</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:2]</bitRange>
              <description>Address length (0b-60b in 4b increments)</description>
              <name>ADDR_L</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:0]</bitRange>
              <description>Address and instruction transfer format</description>
              <enumeratedValues>
                <enumeratedValue>
                  <description>Command and address both in standard SPI frame format</description>
                  <name>1C1A</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Command in standard SPI format, address in format specified by FRF</description>
                  <name>1C2A</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <description>Command and address both in format specified by FRF (e.g. Dual-SPI)</description>
                  <name>2C2A</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>TRANS_TYPE</name>
            </field>
          </fields>
          <name>SPI_CTRLR0</name>
          <resetValue>0x03000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00f8</addressOffset>
          <description>TX drive edge</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>TXD drive edge</description>
              <name>TDE</name>
            </field>
          </fields>
          <name>TXD_DRIVE_EDGE</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40000000</baseAddress>
      <name>SYSINFO</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>JEDEC JEP-106 compliant chip identifier.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:28]</bitRange>
              <name>REVISION</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:12]</bitRange>
              <name>PART</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:0]</bitRange>
              <name>MANUFACTURER</name>
            </field>
          </fields>
          <name>CHIP_ID</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Platform register. Allows software to know what environment it is running in.</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>ASIC</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>FPGA</name>
            </field>
          </fields>
          <name>PLATFORM</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0040</addressOffset>
          <description>Git hash of the chip source. Used to identify chip version.</description>
          <name>GITREF_RP2040</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40004000</baseAddress>
      <description>Register block for various chip control signals</description>
      <name>SYSCFG</name>
      <registers>
        <register>
          <access>read-write</access>
          <addressOffset>0x0000</addressOffset>
          <description>Processor core 0 NMI source mask\n
            Set a bit high to enable NMI from that IRQ</description>
          <name>PROC0_NMI_MASK</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-write</access>
          <addressOffset>0x0004</addressOffset>
          <description>Processor core 1 NMI source mask\n
            Set a bit high to enable NMI from that IRQ</description>
          <name>PROC1_NMI_MASK</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0008</addressOffset>
          <description>Configuration for processors</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:28]</bitRange>
              <description>Configure proc1 DAP instance ID.\n
                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
                WARNING: do not set to 15 as this is reserved for RescueDP</description>
              <name>PROC1_DAP_INSTID</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:24]</bitRange>
              <description>Configure proc0 DAP instance ID.\n
                Recommend that this is NOT changed until you require debug access in multi-chip environment\n
                WARNING: do not set to 15 as this is reserved for RescueDP</description>
              <name>PROC0_DAP_INSTID</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <description>Indication that proc1 has halted</description>
              <name>PROC1_HALTED</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Indication that proc0 has halted</description>
              <name>PROC0_HALTED</name>
            </field>
          </fields>
          <name>PROC_CONFIG</name>
          <resetValue>0x10000000</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
            and the GPIO input register in the SIO. The input synchronizers should\n
            generally be unbypassed, to avoid injecting metastabilities into processors.\n
            If you're feeling brave, you can bypass to save two cycles of input\n
            latency. This register applies to GPIO 0...29.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[29:0]</bitRange>
              <name>PROC_IN_SYNC_BYPASS</name>
            </field>
          </fields>
          <name>PROC_IN_SYNC_BYPASS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>For each bit, if 1, bypass the input synchronizer between that GPIO\n
            and the GPIO input register in the SIO. The input synchronizers should\n
            generally be unbypassed, to avoid injecting metastabilities into processors.\n
            If you're feeling brave, you can bypass to save two cycles of input\n
            latency. This register applies to GPIO 30...35 (the QSPI IOs).</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[5:0]</bitRange>
              <name>PROC_IN_SYNC_BYPASS_HI</name>
            </field>
          </fields>
          <name>PROC_IN_SYNC_BYPASS_HI</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0014</addressOffset>
          <description>Directly control the SWD debug port of either processor</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <description>Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
              <name>PROC1_ATTACH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <description>Directly drive processor 1 SWCLK, if PROC1_ATTACH is set</description>
              <name>PROC1_SWCLK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <description>Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set</description>
              <name>PROC1_SWDI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Observe the value of processor 1 SWDIO output.</description>
              <name>PROC1_SWDO</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <description>Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.</description>
              <name>PROC0_ATTACH</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <description>Directly drive processor 0 SWCLK, if PROC0_ATTACH is set</description>
              <name>PROC0_SWCLK</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <description>Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set</description>
              <name>PROC0_SWDI</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Observe the value of processor 0 SWDIO output.</description>
              <name>PROC0_SWDO</name>
            </field>
          </fields>
          <name>DBGFORCE</name>
          <resetValue>0x00000066</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Control power downs to memories. Set high to power down memories.\n
            Use with extreme caution</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>ROM</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>USB</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>SRAM5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>SRAM4</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>SRAM3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>SRAM2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>SRAM1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>SRAM0</name>
            </field>
          </fields>
          <name>MEMPOWERDOWN</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x40008000</baseAddress>
      <interrupt>
        <name>CLOCKS_IRQ</name>
        <value>17</value>
      </interrupt>
      <name>CLOCKS</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT0_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0004</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT0_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0008</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT0_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x000c</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT1_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0010</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT1_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0014</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT1_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0018</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT2_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x001c</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT2_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0020</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT2_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0024</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Enables duty cycle correction for odd divisors</description>
              <name>DC50</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>10</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_GPOUT3_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0028</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_GPOUT3_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x002c</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_GPOUT3_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0030</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[6:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:0]</bitRange>
              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_clk_ref_aux</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>2</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SRC</name>
            </field>
          </fields>
          <name>CLK_REF_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0034</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
          </fields>
          <name>CLK_REF_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0038</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
          <name>CLK_REF_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x003c</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <description>Selects the clock source glitchlessly, can be changed on-the-fly</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_clk_sys_aux</name>
                  <value>1</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>SRC</name>
            </field>
          </fields>
          <name>CLK_SYS_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0040</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_SYS_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0044</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.</description>
          <name>CLK_SYS_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0048</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>6</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_PERI_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0050</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_PERI_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0054</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_USB_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0058</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
          </fields>
          <name>CLK_USB_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x005c</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_USB_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0060</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_ADC_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0064</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[9:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
          </fields>
          <name>CLK_ADC_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0068</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_ADC_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x006c</addressOffset>
          <description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <description>An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n
                This can be done at any time</description>
              <name>NUDGE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:16]</bitRange>
              <description>This delays the enable signal by up to 3 cycles of the input clock\n
                This must be set before the clock is enabled to have any effect</description>
              <name>PHASE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <description>Starts and stops the clock generator cleanly</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <description>Asynchronously kills the clock generator</description>
              <name>KILL</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:5]</bitRange>
              <description>Selects the auxiliary clock source, will glitch when switching</description>
              <enumeratedValues>
                <enumeratedValue>
                  <name>clksrc_pll_usb</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_pll_sys</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>5</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>AUXSRC</name>
            </field>
          </fields>
          <name>CLK_RTC_CTRL</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0070</addressOffset>
          <description>Clock divisor, can be changed on-the-fly</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:8]</bitRange>
              <description>Integer component of the divisor, 0 -&gt; divide by 2^16</description>
              <name>INT</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>Fractional component of the divisor</description>
              <name>FRAC</name>
            </field>
          </fields>
          <name>CLK_RTC_DIV</name>
          <resetValue>0x00000100</resetValue>
        </register>
        <register>
          <access>read-only</access>
          <addressOffset>0x0074</addressOffset>
          <description>Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.</description>
          <name>CLK_RTC_SELECTED</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0078</addressOffset>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <description>For clearing the resus after the fault that triggered it has been corrected</description>
              <name>CLEAR</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <description>Force a resus, for test purposes only</description>
              <name>FRCE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <description>Enable resus</description>
              <name>ENABLE</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <description>This is expressed as a number of clk_ref cycles\n
                and must be &gt;= 2x clk_ref_freq/min_clk_tst_freq</description>
              <name>TIMEOUT</name>
            </field>
          </fields>
          <name>CLK_SYS_RESUS_CTRL</name>
          <resetValue>0x000000ff</resetValue>
        </register>
        <register>
          <addressOffset>0x007c</addressOffset>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Clock has been resuscitated, correct the error then send ctrl_clear=1</description>
              <name>RESUSSED</name>
            </field>
          </fields>
          <name>CLK_SYS_RESUS_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0080</addressOffset>
          <description>Reference clock frequency in kHz</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[19:0]</bitRange>
              <name>FC0_REF_KHZ</name>
            </field>
          </fields>
          <name>FC0_REF_KHZ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0084</addressOffset>
          <description>Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:0]</bitRange>
              <name>FC0_MIN_KHZ</name>
            </field>
          </fields>
          <name>FC0_MIN_KHZ</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0088</addressOffset>
          <description>Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:0]</bitRange>
              <name>FC0_MAX_KHZ</name>
            </field>
          </fields>
          <name>FC0_MAX_KHZ</name>
          <resetValue>0x01ffffff</resetValue>
        </register>
        <register>
          <addressOffset>0x008c</addressOffset>
          <description>Delays the start of frequency counting to allow the mux to settle\n
            Delay is measured in multiples of the reference clock period</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[2:0]</bitRange>
              <name>FC0_DELAY</name>
            </field>
          </fields>
          <name>FC0_DELAY</name>
          <resetValue>0x00000001</resetValue>
        </register>
        <register>
          <addressOffset>0x0090</addressOffset>
          <description>The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n
            The default gives a test interval of 250us</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[3:0]</bitRange>
              <name>FC0_INTERVAL</name>
            </field>
          </fields>
          <name>FC0_INTERVAL</name>
          <resetValue>0x00000008</resetValue>
        </register>
        <register>
          <addressOffset>0x0094</addressOffset>
          <description>Clock sent to frequency counter, set to 0 when not required\n
            Writing to this register initiates the frequency count</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[7:0]</bitRange>
              <enumeratedValues>
                <enumeratedValue>
                  <name>NULL</name>
                  <value>0</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pll_sys_clksrc_primary</name>
                  <value>1</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>pll_usb_clksrc_primary</name>
                  <value>2</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc</name>
                  <value>3</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>rosc_clksrc_ph</name>
                  <value>4</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>xosc_clksrc</name>
                  <value>5</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin0</name>
                  <value>6</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clksrc_gpin1</name>
                  <value>7</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_ref</name>
                  <value>8</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_sys</name>
                  <value>9</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_peri</name>
                  <value>10</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_usb</name>
                  <value>11</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_adc</name>
                  <value>12</value>
                </enumeratedValue>
                <enumeratedValue>
                  <name>clk_rtc</name>
                  <value>13</value>
                </enumeratedValue>
              </enumeratedValues>
              <name>FC0_SRC</name>
            </field>
          </fields>
          <name>FC0_SRC</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x0098</addressOffset>
          <description>Frequency counter status</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <description>Test clock stopped during test</description>
              <name>DIED</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <description>Test clock faster than expected, only valid when status_done=1</description>
              <name>FAST</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <description>Test clock slower than expected, only valid when status_done=1</description>
              <name>SLOW</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <description>Test failed</description>
              <name>FAIL</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <description>Waiting for test clock to start</description>
              <name>WAITING</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <description>Test running</description>
              <name>RUNNING</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <description>Test complete</description>
              <name>DONE</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <description>Test passed</description>
              <name>PASS</name>
            </field>
          </fields>
          <name>FC0_STATUS</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x009c</addressOffset>
          <description>Result of frequency measurement, only valid when status_done=1</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[29:5]</bitRange>
              <name>KHZ</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:0]</bitRange>
              <name>FRAC</name>
            </field>
          </fields>
          <name>FC0_RESULT</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00a0</addressOffset>
          <description>enable clock in wake mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>clk_sys_sram3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>clk_sys_sram2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>clk_sys_sram1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>clk_sys_sram0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>clk_sys_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>clk_peri_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>clk_sys_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>clk_peri_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>clk_sys_sio</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>clk_sys_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>clk_rtc_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>clk_sys_rosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>clk_sys_rom</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>clk_sys_resets</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>clk_sys_pwm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>clk_sys_psm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>clk_sys_pll_usb</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_pll_sys</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_pio1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_pio0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_sys_pads</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_jtag</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_sys_io</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_i2c1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_sys_i2c0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_dma</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_busfabric</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_busctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_adc_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_clocks</name>
            </field>
          </fields>
          <name>WAKE_EN0</name>
          <resetValue>0xffffffff</resetValue>
        </register>
        <register>
          <addressOffset>0x00a4</addressOffset>
          <description>enable clock in wake mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_xosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_xip</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_watchdog</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_usb_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_peri_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_peri_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_timer</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_tbman</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_sysinfo</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_syscfg</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_sys_sram5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_sram4</name>
            </field>
          </fields>
          <name>WAKE_EN1</name>
          <resetValue>0x00007fff</resetValue>
        </register>
        <register>
          <addressOffset>0x00a8</addressOffset>
          <description>enable clock in sleep mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[31:31]</bitRange>
              <name>clk_sys_sram3</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[30:30]</bitRange>
              <name>clk_sys_sram2</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[29:29]</bitRange>
              <name>clk_sys_sram1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[28:28]</bitRange>
              <name>clk_sys_sram0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[27:27]</bitRange>
              <name>clk_sys_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[26:26]</bitRange>
              <name>clk_peri_spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[25:25]</bitRange>
              <name>clk_sys_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>clk_peri_spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>clk_sys_sio</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>clk_sys_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>clk_rtc_rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>clk_sys_rosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>clk_sys_rom</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>clk_sys_resets</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>clk_sys_pwm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>clk_sys_psm</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>clk_sys_pll_usb</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_pll_sys</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_pio1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_pio0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_sys_pads</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_jtag</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_sys_io</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_i2c1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_sys_i2c0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_dma</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_busfabric</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_busctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_adc_adc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_clocks</name>
            </field>
          </fields>
          <name>SLEEP_EN0</name>
          <resetValue>0xffffffff</resetValue>
        </register>
        <register>
          <addressOffset>0x00ac</addressOffset>
          <description>enable clock in sleep mode</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_xosc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_xip</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_watchdog</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_usb_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_peri_uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_peri_uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_timer</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_tbman</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_sysinfo</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_syscfg</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_sys_sram5</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_sram4</name>
            </field>
          </fields>
          <name>SLEEP_EN1</name>
          <resetValue>0x00007fff</resetValue>
        </register>
        <register>
          <addressOffset>0x00b0</addressOffset>
          <description>indicates the state of the clock enable</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[31:31]</bitRange>
              <name>clk_sys_sram3</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[30:30]</bitRange>
              <name>clk_sys_sram2</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[29:29]</bitRange>
              <name>clk_sys_sram1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[28:28]</bitRange>
              <name>clk_sys_sram0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[27:27]</bitRange>
              <name>clk_sys_spi1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[26:26]</bitRange>
              <name>clk_peri_spi1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[25:25]</bitRange>
              <name>clk_sys_spi0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[24:24]</bitRange>
              <name>clk_peri_spi0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[23:23]</bitRange>
              <name>clk_sys_sio</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[22:22]</bitRange>
              <name>clk_sys_rtc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[21:21]</bitRange>
              <name>clk_rtc_rtc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[20:20]</bitRange>
              <name>clk_sys_rosc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[19:19]</bitRange>
              <name>clk_sys_rom</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[18:18]</bitRange>
              <name>clk_sys_resets</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[17:17]</bitRange>
              <name>clk_sys_pwm</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[16:16]</bitRange>
              <name>clk_sys_psm</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[15:15]</bitRange>
              <name>clk_sys_pll_usb</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_pll_sys</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_pio1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_pio0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_sys_pads</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_vreg_and_chip_reset</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_jtag</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_sys_io</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_i2c1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_sys_i2c0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_dma</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_busfabric</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_busctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_adc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_adc_adc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_clocks</name>
            </field>
          </fields>
          <name>ENABLED0</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b4</addressOffset>
          <description>indicates the state of the clock enable</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[14:14]</bitRange>
              <name>clk_sys_xosc</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[13:13]</bitRange>
              <name>clk_sys_xip</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[12:12]</bitRange>
              <name>clk_sys_watchdog</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[11:11]</bitRange>
              <name>clk_usb_usbctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[10:10]</bitRange>
              <name>clk_sys_usbctrl</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[9:9]</bitRange>
              <name>clk_sys_uart1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[8:8]</bitRange>
              <name>clk_peri_uart1</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[7:7]</bitRange>
              <name>clk_sys_uart0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[6:6]</bitRange>
              <name>clk_peri_uart0</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[5:5]</bitRange>
              <name>clk_sys_timer</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[4:4]</bitRange>
              <name>clk_sys_tbman</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[3:3]</bitRange>
              <name>clk_sys_sysinfo</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[2:2]</bitRange>
              <name>clk_sys_syscfg</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[1:1]</bitRange>
              <name>clk_sys_sram5</name>
            </field>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>clk_sys_sram4</name>
            </field>
          </fields>
          <name>ENABLED1</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00b8</addressOffset>
          <description>Raw Interrupts</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTR</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00bc</addressOffset>
          <description>Interrupt Enable</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTE</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c0</addressOffset>
          <description>Interrupt Force</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTF</name>
          <resetValue>0x00000000</resetValue>
        </register>
        <register>
          <addressOffset>0x00c4</addressOffset>
          <description>Interrupt status after masking &amp; forcing</description>
          <fields>
            <field>
              <access>read-only</access>
              <bitRange>[0:0]</bitRange>
              <name>CLK_SYS_RESUS</name>
            </field>
          </fields>
          <name>INTS</name>
          <resetValue>0x00000000</resetValue>
        </register>
      </registers>
      <size>32</size>
      <version>1</version>
    </peripheral>
    <peripheral>
      <addressBlock>
        <offset>0</offset>
        <size>0x1000</size>
        <usage>registers</usage>
      </addressBlock>
      <baseAddress>0x4000c000</baseAddress>
      <name>RESETS</name>
      <registers>
        <register>
          <addressOffset>0x0000</addressOffset>
          <description>Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.</description>
          <fields>
            <field>
              <access>read-write</access>
              <bitRange>[24:24]</bitRange>
              <name>usbctrl</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[23:23]</bitRange>
              <name>uart1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[22:22]</bitRange>
              <name>uart0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[21:21]</bitRange>
              <name>timer</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[20:20]</bitRange>
              <name>tbman</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[19:19]</bitRange>
              <name>sysinfo</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[18:18]</bitRange>
              <name>syscfg</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[17:17]</bitRange>
              <name>spi1</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[16:16]</bitRange>
              <name>spi0</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[15:15]</bitRange>
              <name>rtc</name>
            </field>
            <field>
              <access>read-write</access>
              <bitRange>[14:14]</bitRange>
              <name>pwm</name>
            </field>
            <field>